2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
28 #include <drm_fourcc.h>
30 #include "intel_batchbuffer.h"
31 #include "intel_image.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_tex.h"
34 #include "intel_blit.h"
35 #include "intel_fbo.h"
37 #include "brw_blorp.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
48 #include "x86/common_x86_asm.h"
50 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
52 static void *intel_miptree_map_raw(struct brw_context
*brw
,
53 struct intel_mipmap_tree
*mt
,
56 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
59 intel_miptree_alloc_aux(struct brw_context
*brw
,
60 struct intel_mipmap_tree
*mt
);
63 intel_miptree_supports_mcs(struct brw_context
*brw
,
64 const struct intel_mipmap_tree
*mt
)
66 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
68 /* MCS compression only applies to multisampled miptrees */
69 if (mt
->surf
.samples
<= 1)
72 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
76 /* See isl_surf_get_mcs_surf for details. */
77 if (mt
->surf
.samples
== 16 && mt
->surf
.logical_level0_px
.width
> 8192)
80 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
81 switch (_mesa_get_format_base_format(mt
->format
)) {
82 case GL_DEPTH_COMPONENT
:
83 case GL_STENCIL_INDEX
:
84 case GL_DEPTH_STENCIL
:
87 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
89 * This field must be set to 0 for all SINT MSRTs when all RT channels
92 * In practice this means that we have to disable MCS for all signed
93 * integer MSAA buffers. The alternative, to disable MCS only when one
94 * of the render target channels is disabled, is impractical because it
95 * would require converting between CMS and UMS MSAA layouts on the fly,
98 if (devinfo
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
107 intel_tiling_supports_ccs(const struct brw_context
*brw
,
108 enum isl_tiling tiling
)
110 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
112 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
113 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
115 * - Support is limited to tiled render targets.
117 * Gen9 changes the restriction to Y-tile only.
119 if (devinfo
->gen
>= 9)
120 return tiling
== ISL_TILING_Y0
;
121 else if (devinfo
->gen
>= 7)
122 return tiling
!= ISL_TILING_LINEAR
;
128 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
129 * can be used. This doesn't (and should not) inspect any of the properties of
132 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
133 * beneath the "Fast Color Clear" bullet (p326):
135 * - Support is for non-mip-mapped and non-array surface types only.
137 * And then later, on p327:
139 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
142 * From the Skylake documentation, it is made clear that X-tiling is no longer
145 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
149 intel_miptree_supports_ccs(struct brw_context
*brw
,
150 const struct intel_mipmap_tree
*mt
)
152 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
154 /* MCS support does not exist prior to Gen7 */
155 if (devinfo
->gen
< 7)
158 /* This function applies only to non-multisampled render targets. */
159 if (mt
->surf
.samples
> 1)
162 /* MCS is only supported for color buffers */
163 switch (_mesa_get_format_base_format(mt
->format
)) {
164 case GL_DEPTH_COMPONENT
:
165 case GL_DEPTH_STENCIL
:
166 case GL_STENCIL_INDEX
:
170 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
173 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
174 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
175 mt
->surf
.logical_level0_px
.depth
> 1;
178 /* Multisample surfaces with the CMS layout are not layered surfaces,
179 * yet still have physical_depth0 > 1. Assert that we don't
180 * accidentally reject a multisampled surface here. We should have
181 * rejected it earlier by explicitly checking the sample count.
183 assert(mt
->surf
.samples
== 1);
186 /* Handle the hardware restrictions...
188 * All GENs have the following restriction: "MCS buffer for non-MSRT is
189 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
191 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
192 * Non-MultiSampler Render Target Restrictions) Support is for
193 * non-mip-mapped and non-array surface types only.
195 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
196 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
197 * surfaces are supported with MCS buffer layout with these alignments in
198 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
200 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
201 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
202 * surfaces are supported with MCS buffer layout with these alignments in
203 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
205 if (devinfo
->gen
< 8 && (mip_mapped
|| arrayed
))
208 /* There's no point in using an MCS buffer if the surface isn't in a
211 if (!brw
->mesa_format_supports_render
[mt
->format
])
218 intel_tiling_supports_hiz(const struct brw_context
*brw
,
219 enum isl_tiling tiling
)
221 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
223 if (devinfo
->gen
< 6)
226 return tiling
== ISL_TILING_Y0
;
230 intel_miptree_supports_hiz(const struct brw_context
*brw
,
231 const struct intel_mipmap_tree
*mt
)
236 switch (mt
->format
) {
237 case MESA_FORMAT_Z_FLOAT32
:
238 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
239 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
240 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
241 case MESA_FORMAT_Z_UNORM16
:
249 * Return true if the format that will be used to access the miptree is
250 * CCS_E-compatible with the miptree's linear/non-sRGB format.
252 * Why use the linear format? Well, although the miptree may be specified with
253 * an sRGB format, the usage of that color space/format can be toggled. Since
254 * our HW tends to support more linear formats than sRGB ones, we use this
255 * format variant for check for CCS_E compatibility.
258 format_ccs_e_compat_with_miptree(const struct gen_device_info
*devinfo
,
259 const struct intel_mipmap_tree
*mt
,
260 enum isl_format access_format
)
262 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
264 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
265 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
266 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
270 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
271 const struct intel_mipmap_tree
*mt
)
273 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
275 if (devinfo
->gen
< 9)
278 /* For now compression is only enabled for integer formats even though
279 * there exist supported floating point formats also. This is a heuristic
280 * decision based on current public benchmarks. In none of the cases these
281 * formats provided any improvement but a few cases were seen to regress.
282 * Hence these are left to to be enabled in the future when they are known
285 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
288 if (!intel_miptree_supports_ccs(brw
, mt
))
291 /* Many window system buffers are sRGB even if they are never rendered as
292 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
293 * surface is used as sRGB, we fall back to CCS_D.
295 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
296 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
297 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
301 * Determine depth format corresponding to a depth+stencil format,
302 * for separate stencil.
305 intel_depth_format_for_depthstencil_format(mesa_format format
) {
307 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
308 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
309 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
310 return MESA_FORMAT_Z_FLOAT32
;
317 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
318 unsigned depth0
, struct intel_mipmap_level
*table
)
320 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
322 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
324 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
325 if (!table
[level
].slice
)
332 for (unsigned level
= first_level
; level
<= last_level
; level
++)
333 free(table
[level
].slice
);
339 needs_separate_stencil(const struct brw_context
*brw
,
340 struct intel_mipmap_tree
*mt
,
343 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
345 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
348 if (devinfo
->must_use_separate_stencil
)
351 return brw
->has_separate_stencil
&&
352 intel_miptree_supports_hiz(brw
, mt
);
356 * Choose the aux usage for this miptree. This function must be called fairly
357 * late in the miptree create process after we have a tiling.
360 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
361 struct intel_mipmap_tree
*mt
)
363 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
365 if (intel_miptree_supports_mcs(brw
, mt
)) {
366 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
367 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
368 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
369 intel_miptree_supports_ccs(brw
, mt
)) {
370 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
371 intel_miptree_supports_ccs_e(brw
, mt
)) {
372 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
374 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
376 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
377 intel_miptree_supports_hiz(brw
, mt
)) {
378 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
381 /* We can do fast-clear on all auxiliary surface types that are
382 * allocated through the normal texture creation paths.
384 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
385 mt
->supports_fast_clear
= true;
390 * Choose an appropriate uncompressed format for a requested
391 * compressed format, if unsupported.
394 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
396 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
398 /* No need to lower ETC formats on these platforms,
399 * they are supported natively.
401 if (devinfo
->gen
>= 8 || devinfo
->is_baytrail
)
405 case MESA_FORMAT_ETC1_RGB8
:
406 return MESA_FORMAT_R8G8B8X8_UNORM
;
407 case MESA_FORMAT_ETC2_RGB8
:
408 return MESA_FORMAT_R8G8B8X8_UNORM
;
409 case MESA_FORMAT_ETC2_SRGB8
:
410 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
411 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
412 return MESA_FORMAT_B8G8R8A8_SRGB
;
413 case MESA_FORMAT_ETC2_RGBA8_EAC
:
414 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
415 return MESA_FORMAT_R8G8B8A8_UNORM
;
416 case MESA_FORMAT_ETC2_R11_EAC
:
417 return MESA_FORMAT_R_UNORM16
;
418 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
419 return MESA_FORMAT_R_SNORM16
;
420 case MESA_FORMAT_ETC2_RG11_EAC
:
421 return MESA_FORMAT_R16G16_UNORM
;
422 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
423 return MESA_FORMAT_R16G16_SNORM
;
425 /* Non ETC1 / ETC2 format */
431 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
433 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
434 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
436 return mt
->surf
.logical_level0_px
.array_len
;
439 UNUSED
static unsigned
440 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
442 /* In case of physical dimensions one needs to consider also the layout.
443 * See isl_calc_phys_level0_extent_sa().
445 if (surf
->dim
!= ISL_SURF_DIM_3D
)
446 return surf
->phys_level0_sa
.array_len
;
448 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
449 return minify(surf
->phys_level0_sa
.array_len
, level
);
451 return minify(surf
->phys_level0_sa
.depth
, level
);
454 /** \brief Assert that the level and layer are valid for the miptree. */
456 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
464 assert(level
>= mt
->first_level
);
465 assert(level
<= mt
->last_level
);
466 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
469 static enum isl_aux_state
**
470 create_aux_state_map(struct intel_mipmap_tree
*mt
,
471 enum isl_aux_state initial
)
473 const uint32_t levels
= mt
->last_level
+ 1;
475 uint32_t total_slices
= 0;
476 for (uint32_t level
= 0; level
< levels
; level
++)
477 total_slices
+= brw_get_num_logical_layers(mt
, level
);
479 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
481 /* We're going to allocate a single chunk of data for both the per-level
482 * reference array and the arrays of aux_state. This makes cleanup
483 * significantly easier.
485 const size_t total_size
= per_level_array_size
+
486 total_slices
* sizeof(enum isl_aux_state
);
487 void *data
= malloc(total_size
);
491 enum isl_aux_state
**per_level_arr
= data
;
492 enum isl_aux_state
*s
= data
+ per_level_array_size
;
493 for (uint32_t level
= 0; level
< levels
; level
++) {
494 per_level_arr
[level
] = s
;
495 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
496 for (uint32_t a
= 0; a
< level_layers
; a
++)
499 assert((void *)s
== data
+ total_size
);
501 return per_level_arr
;
505 free_aux_state_map(enum isl_aux_state
**state
)
511 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
512 enum isl_tiling tiling
, unsigned samples
)
517 if (tiling
== ISL_TILING_LINEAR
)
520 /* If the width is much smaller than a tile, don't bother tiling. */
524 if (ALIGN(row_pitch
, 512) >= 32768) {
525 perf_debug("row pitch %u too large to blit, falling back to untiled",
534 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
535 enum isl_tiling tiling
)
537 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
539 /* If the BO is too large to fit in the aperture, we need to use the
540 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
541 * handle Y-tiling, so we need to fall back to X.
543 if (devinfo
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
544 tiling
== ISL_TILING_Y0
)
550 static struct intel_mipmap_tree
*
551 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
552 unsigned first_level
, unsigned last_level
,
553 unsigned width0
, unsigned height0
, unsigned depth0
,
554 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
555 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
556 unsigned row_pitch
, struct brw_bo
*bo
)
558 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
562 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
570 if (target
== GL_TEXTURE_CUBE_MAP
||
571 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
572 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
574 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
576 _mesa_enum_to_string(target
),
577 _mesa_get_format_name(format
),
578 num_samples
, width0
, height0
, depth0
,
579 first_level
, last_level
, mt
);
581 struct isl_surf_init_info init_info
= {
582 .dim
= get_isl_surf_dim(target
),
583 .format
= translate_tex_format(brw
, format
, false),
586 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
587 .levels
= last_level
- first_level
+ 1,
588 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
589 .samples
= num_samples
,
590 .row_pitch
= row_pitch
,
591 .usage
= isl_usage_flags
,
592 .tiling_flags
= tiling_flags
,
595 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
598 /* Depth surfaces are always Y-tiled and stencil is always W-tiled, although
599 * on gen7 platforms we also need to create Y-tiled copies of stencil for
600 * texturing since the hardware can't sample from W-tiled surfaces. For
601 * everything else, check for corner cases needing special treatment.
603 bool is_depth_stencil
=
604 mt
->surf
.usage
& (ISL_SURF_USAGE_STENCIL_BIT
| ISL_SURF_USAGE_DEPTH_BIT
);
605 if (!is_depth_stencil
) {
606 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
607 mt
->surf
.tiling
, mt
->surf
.samples
)) {
608 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
609 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
611 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
612 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
613 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
618 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
619 * the size may not be multiple of row_pitch.
620 * See isl_apply_surface_padding().
622 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
623 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
626 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
628 isl_tiling_to_i915_tiling(
630 mt
->surf
.row_pitch
, alloc_flags
);
637 mt
->first_level
= first_level
;
638 mt
->last_level
= last_level
;
641 mt
->aux_state
= NULL
;
642 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
643 mt
->compressed
= _mesa_is_format_compressed(format
);
644 mt
->drm_modifier
= DRM_FORMAT_MOD_INVALID
;
649 intel_miptree_release(&mt
);
654 make_separate_stencil_surface(struct brw_context
*brw
,
655 struct intel_mipmap_tree
*mt
)
657 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
658 0, mt
->surf
.levels
- 1,
659 mt
->surf
.logical_level0_px
.width
,
660 mt
->surf
.logical_level0_px
.height
,
661 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
662 mt
->surf
.logical_level0_px
.depth
:
663 mt
->surf
.logical_level0_px
.array_len
,
664 mt
->surf
.samples
, ISL_TILING_W_BIT
,
665 ISL_SURF_USAGE_STENCIL_BIT
|
666 ISL_SURF_USAGE_TEXTURE_BIT
,
667 BO_ALLOC_BUSY
, 0, NULL
);
672 mt
->stencil_mt
->r8stencil_needs_update
= true;
677 static struct intel_mipmap_tree
*
678 miptree_create(struct brw_context
*brw
,
687 enum intel_miptree_create_flags flags
)
689 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
691 if (format
== MESA_FORMAT_S_UINT8
)
692 return make_surface(brw
, target
, format
, first_level
, last_level
,
693 width0
, height0
, depth0
, num_samples
,
695 ISL_SURF_USAGE_STENCIL_BIT
|
696 ISL_SURF_USAGE_TEXTURE_BIT
,
701 const GLenum base_format
= _mesa_get_format_base_format(format
);
702 if ((base_format
== GL_DEPTH_COMPONENT
||
703 base_format
== GL_DEPTH_STENCIL
) &&
704 !(flags
& MIPTREE_CREATE_LINEAR
)) {
705 /* Fix up the Z miptree format for how we're splitting out separate
706 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
708 const mesa_format depth_only_format
=
709 intel_depth_format_for_depthstencil_format(format
);
710 struct intel_mipmap_tree
*mt
= make_surface(
711 brw
, target
, devinfo
->gen
>= 6 ? depth_only_format
: format
,
712 first_level
, last_level
,
713 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
714 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
715 BO_ALLOC_BUSY
, 0, NULL
);
717 if (needs_separate_stencil(brw
, mt
, format
) &&
718 !make_separate_stencil_surface(brw
, mt
)) {
719 intel_miptree_release(&mt
);
723 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
724 intel_miptree_choose_aux_usage(brw
, mt
);
729 mesa_format tex_format
= format
;
730 mesa_format etc_format
= MESA_FORMAT_NONE
;
731 uint32_t alloc_flags
= 0;
733 format
= intel_lower_compressed_format(brw
, format
);
735 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
737 if (flags
& MIPTREE_CREATE_BUSY
)
738 alloc_flags
|= BO_ALLOC_BUSY
;
740 isl_tiling_flags_t tiling_flags
= (flags
& MIPTREE_CREATE_LINEAR
) ?
741 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
743 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
744 if (devinfo
->gen
< 6)
745 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
747 struct intel_mipmap_tree
*mt
= make_surface(
749 first_level
, last_level
,
750 width0
, height0
, depth0
,
751 num_samples
, tiling_flags
,
752 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
753 ISL_SURF_USAGE_TEXTURE_BIT
,
754 alloc_flags
, 0, NULL
);
758 mt
->etc_format
= etc_format
;
760 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
761 intel_miptree_choose_aux_usage(brw
, mt
);
766 struct intel_mipmap_tree
*
767 intel_miptree_create(struct brw_context
*brw
,
776 enum intel_miptree_create_flags flags
)
778 assert(num_samples
> 0);
780 struct intel_mipmap_tree
*mt
= miptree_create(
782 first_level
, last_level
,
783 width0
, height0
, depth0
, num_samples
,
790 if (!intel_miptree_alloc_aux(brw
, mt
)) {
791 intel_miptree_release(&mt
);
798 struct intel_mipmap_tree
*
799 intel_miptree_create_for_bo(struct brw_context
*brw
,
807 enum isl_tiling tiling
,
808 enum intel_miptree_create_flags flags
)
810 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
811 struct intel_mipmap_tree
*mt
;
812 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
813 const GLenum base_format
= _mesa_get_format_base_format(format
);
815 if ((base_format
== GL_DEPTH_COMPONENT
||
816 base_format
== GL_DEPTH_STENCIL
)) {
817 const mesa_format depth_only_format
=
818 intel_depth_format_for_depthstencil_format(format
);
819 mt
= make_surface(brw
, target
,
820 devinfo
->gen
>= 6 ? depth_only_format
: format
,
821 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
822 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
827 brw_bo_reference(bo
);
829 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
830 intel_miptree_choose_aux_usage(brw
, mt
);
833 } else if (format
== MESA_FORMAT_S_UINT8
) {
834 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
835 0, 0, width
, height
, depth
, 1,
837 ISL_SURF_USAGE_STENCIL_BIT
|
838 ISL_SURF_USAGE_TEXTURE_BIT
,
843 assert(bo
->size
>= mt
->surf
.size
);
845 brw_bo_reference(bo
);
849 /* Nothing will be able to use this miptree with the BO if the offset isn't
852 if (tiling
!= ISL_TILING_LINEAR
)
853 assert(offset
% 4096 == 0);
855 /* miptrees can't handle negative pitch. If you need flipping of images,
856 * that's outside of the scope of the mt.
860 /* The BO already has a tiling format and we shouldn't confuse the lower
861 * layers by making it try to find a tiling format again.
863 assert((flags
& MIPTREE_CREATE_LINEAR
) == 0);
865 mt
= make_surface(brw
, target
, format
,
866 0, 0, width
, height
, depth
, 1,
868 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
869 ISL_SURF_USAGE_TEXTURE_BIT
,
874 brw_bo_reference(bo
);
878 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
879 intel_miptree_choose_aux_usage(brw
, mt
);
881 if (!intel_miptree_alloc_aux(brw
, mt
)) {
882 intel_miptree_release(&mt
);
890 static struct intel_mipmap_tree
*
891 miptree_create_for_planar_image(struct brw_context
*brw
,
892 __DRIimage
*image
, GLenum target
,
893 enum isl_tiling tiling
)
895 const struct intel_image_format
*f
= image
->planar_format
;
896 struct intel_mipmap_tree
*planar_mt
= NULL
;
898 for (int i
= 0; i
< f
->nplanes
; i
++) {
899 const int index
= f
->planes
[i
].buffer_index
;
900 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
901 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
902 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
903 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
905 /* Disable creation of the texture's aux buffers because the driver
906 * exposes no EGL API to manage them. That is, there is no API for
907 * resolving the aux buffer's content to the main buffer nor for
908 * invalidating the aux buffer's content.
910 struct intel_mipmap_tree
*mt
=
911 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
912 image
->offsets
[index
],
914 image
->strides
[index
],
916 MIPTREE_CREATE_NO_AUX
);
925 planar_mt
->plane
[i
- 1] = mt
;
928 planar_mt
->drm_modifier
= image
->modifier
;
934 create_ccs_buf_for_image(struct brw_context
*brw
,
936 struct intel_mipmap_tree
*mt
,
937 enum isl_aux_state initial_state
)
939 struct isl_surf temp_ccs_surf
;
941 /* CCS is only supported for very simple miptrees */
942 assert(image
->aux_offset
!= 0 && image
->aux_pitch
!= 0);
943 assert(image
->tile_x
== 0 && image
->tile_y
== 0);
944 assert(mt
->surf
.samples
== 1);
945 assert(mt
->surf
.levels
== 1);
946 assert(mt
->surf
.logical_level0_px
.depth
== 1);
947 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
948 assert(mt
->first_level
== 0);
949 assert(mt
->last_level
== 0);
951 /* We shouldn't already have a CCS */
952 assert(!mt
->mcs_buf
);
954 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
,
958 assert(image
->aux_offset
< image
->bo
->size
);
959 assert(temp_ccs_surf
.size
<= image
->bo
->size
- image
->aux_offset
);
961 mt
->mcs_buf
= calloc(sizeof(*mt
->mcs_buf
), 1);
962 if (mt
->mcs_buf
== NULL
)
965 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
966 if (!mt
->aux_state
) {
972 mt
->mcs_buf
->bo
= image
->bo
;
973 brw_bo_reference(image
->bo
);
975 mt
->mcs_buf
->offset
= image
->aux_offset
;
976 mt
->mcs_buf
->size
= image
->bo
->size
- image
->aux_offset
;
977 mt
->mcs_buf
->pitch
= image
->aux_pitch
;
978 mt
->mcs_buf
->qpitch
= 0;
979 mt
->mcs_buf
->surf
= temp_ccs_surf
;
984 struct intel_mipmap_tree
*
985 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
986 __DRIimage
*image
, GLenum target
,
988 bool is_winsys_image
)
990 uint32_t bo_tiling
, bo_swizzle
;
991 brw_bo_get_tiling(image
->bo
, &bo_tiling
, &bo_swizzle
);
993 const struct isl_drm_modifier_info
*mod_info
=
994 isl_drm_modifier_get_info(image
->modifier
);
996 const enum isl_tiling tiling
=
997 mod_info
? mod_info
->tiling
: isl_tiling_from_i915_tiling(bo_tiling
);
999 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1)
1000 return miptree_create_for_planar_image(brw
, image
, target
, tiling
);
1002 if (image
->planar_format
)
1003 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
1005 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1006 /* The texture storage paths in core Mesa detect if the driver does not
1007 * support the user-requested format, and then searches for a
1008 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1009 * do the fallbacks here for important formats.
1011 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1012 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1013 * the Chrome OS compositor consumes as dma_buf EGLImages.
1015 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1018 if (!brw
->ctx
.TextureFormatSupported
[format
])
1021 enum intel_miptree_create_flags mt_create_flags
= 0;
1023 /* If this image comes in from a window system, we have different
1024 * requirements than if it comes in via an EGL import operation. Window
1025 * system images can use any form of auxiliary compression we wish because
1026 * they get "flushed" before being handed off to the window system and we
1027 * have the opportunity to do resolves. Non window-system images, on the
1028 * other hand, have no resolve point so we can't have aux without a
1031 if (!is_winsys_image
)
1032 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1034 /* If we have a modifier which specifies aux, don't create one yet */
1035 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
1036 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1038 /* Disable creation of the texture's aux buffers because the driver exposes
1039 * no EGL API to manage them. That is, there is no API for resolving the aux
1040 * buffer's content to the main buffer nor for invalidating the aux buffer's
1043 struct intel_mipmap_tree
*mt
=
1044 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1045 image
->offset
, image
->width
, image
->height
, 1,
1046 image
->pitch
, tiling
, mt_create_flags
);
1050 mt
->target
= target
;
1051 mt
->level
[0].level_x
= image
->tile_x
;
1052 mt
->level
[0].level_y
= image
->tile_y
;
1053 mt
->drm_modifier
= image
->modifier
;
1055 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1056 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1057 * trouble resolving back to destination image due to alignment issues.
1059 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1060 if (!devinfo
->has_surface_tile_offset
) {
1061 uint32_t draw_x
, draw_y
;
1062 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1064 if (draw_x
!= 0 || draw_y
!= 0) {
1065 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1066 intel_miptree_release(&mt
);
1071 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1072 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1074 mt
->aux_usage
= mod_info
->aux_usage
;
1075 /* If we are a window system buffer, then we can support fast-clears
1076 * even if the modifier doesn't support them by doing a partial resolve
1077 * as part of the flush operation.
1079 mt
->supports_fast_clear
=
1080 is_winsys_image
|| mod_info
->supports_clear_color
;
1082 /* We don't know the actual state of the surface when we get it but we
1083 * can make a pretty good guess based on the modifier. What we do know
1084 * for sure is that it isn't in the AUX_INVALID state, so we just assume
1085 * a worst case of compression.
1087 enum isl_aux_state initial_state
=
1088 isl_drm_modifier_get_default_aux_state(image
->modifier
);
1090 if (!create_ccs_buf_for_image(brw
, image
, mt
, initial_state
)) {
1091 intel_miptree_release(&mt
);
1096 /* Don't assume coherency for imported EGLimages. We don't know what
1097 * external clients are going to do with it. They may scan it out.
1099 image
->bo
->cache_coherent
= false;
1105 * For a singlesample renderbuffer, this simply wraps the given BO with a
1108 * For a multisample renderbuffer, this wraps the window system's
1109 * (singlesample) BO with a singlesample miptree attached to the
1110 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1111 * that will contain the actual rendering (which is lazily resolved to
1112 * irb->singlesample_mt).
1115 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1116 struct intel_renderbuffer
*irb
,
1117 struct intel_mipmap_tree
*singlesample_mt
,
1118 uint32_t width
, uint32_t height
,
1121 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1122 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1123 mesa_format format
= rb
->Format
;
1124 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1126 /* Only the front and back buffers, which are color buffers, are allocated
1127 * through the image loader.
1129 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1130 _mesa_get_format_base_format(format
) == GL_RGBA
);
1132 assert(singlesample_mt
);
1134 if (num_samples
== 1) {
1135 intel_miptree_release(&irb
->mt
);
1136 irb
->mt
= singlesample_mt
;
1138 assert(!irb
->singlesample_mt
);
1140 intel_miptree_release(&irb
->singlesample_mt
);
1141 irb
->singlesample_mt
= singlesample_mt
;
1144 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1145 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1146 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1151 if (!multisample_mt
)
1154 irb
->need_downsample
= false;
1155 intel_miptree_release(&irb
->mt
);
1156 irb
->mt
= multisample_mt
;
1162 intel_miptree_release(&irb
->mt
);
1166 struct intel_mipmap_tree
*
1167 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1171 uint32_t num_samples
)
1173 struct intel_mipmap_tree
*mt
;
1175 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1177 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1178 width
, height
, depth
, num_samples
,
1179 MIPTREE_CREATE_BUSY
);
1186 intel_miptree_release(&mt
);
1191 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1192 struct intel_mipmap_tree
*src
)
1197 intel_miptree_release(dst
);
1201 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1208 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1210 if (aux_buf
== NULL
)
1213 brw_bo_unreference(aux_buf
->bo
);
1214 brw_bo_unreference(aux_buf
->clear_color_bo
);
1220 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1225 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1226 if (--(*mt
)->refcount
<= 0) {
1229 DBG("%s deleting %p\n", __func__
, *mt
);
1231 brw_bo_unreference((*mt
)->bo
);
1232 intel_miptree_release(&(*mt
)->stencil_mt
);
1233 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1234 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1235 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1236 free_aux_state_map((*mt
)->aux_state
);
1238 intel_miptree_release(&(*mt
)->plane
[0]);
1239 intel_miptree_release(&(*mt
)->plane
[1]);
1241 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1242 free((*mt
)->level
[i
].slice
);
1252 intel_get_image_dims(struct gl_texture_image
*image
,
1253 int *width
, int *height
, int *depth
)
1255 switch (image
->TexObject
->Target
) {
1256 case GL_TEXTURE_1D_ARRAY
:
1257 /* For a 1D Array texture the OpenGL API will treat the image height as
1258 * the number of array slices. For Intel hardware, we treat the 1D array
1259 * as a 2D Array with a height of 1. So, here we want to swap image
1262 assert(image
->Depth
== 1);
1263 *width
= image
->Width
;
1265 *depth
= image
->Height
;
1267 case GL_TEXTURE_CUBE_MAP
:
1268 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1269 * though we really have 6 slices.
1271 assert(image
->Depth
== 1);
1272 *width
= image
->Width
;
1273 *height
= image
->Height
;
1277 *width
= image
->Width
;
1278 *height
= image
->Height
;
1279 *depth
= image
->Depth
;
1285 * Can the image be pulled into a unified mipmap tree? This mirrors
1286 * the completeness test in a lot of ways.
1288 * Not sure whether I want to pass gl_texture_image here.
1291 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1292 struct gl_texture_image
*image
)
1294 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1295 GLuint level
= intelImage
->base
.Base
.Level
;
1296 int width
, height
, depth
;
1298 /* glTexImage* choose the texture object based on the target passed in, and
1299 * objects can't change targets over their lifetimes, so this should be
1302 assert(image
->TexObject
->Target
== mt
->target
);
1304 mesa_format mt_format
= mt
->format
;
1305 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1306 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1307 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1308 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1309 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1310 mt_format
= mt
->etc_format
;
1312 if (_mesa_get_srgb_format_linear(image
->TexFormat
) !=
1313 _mesa_get_srgb_format_linear(mt_format
))
1316 intel_get_image_dims(image
, &width
, &height
, &depth
);
1318 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1321 if (level
>= mt
->surf
.levels
)
1324 const unsigned level_depth
=
1325 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1326 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1327 mt
->surf
.logical_level0_px
.array_len
;
1329 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1330 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1331 depth
== level_depth
&&
1332 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1336 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1337 GLuint level
, GLuint slice
,
1338 GLuint
*x
, GLuint
*y
)
1340 if (level
== 0 && slice
== 0) {
1341 *x
= mt
->level
[0].level_x
;
1342 *y
= mt
->level
[0].level_y
;
1346 uint32_t x_offset_sa
, y_offset_sa
;
1348 /* Miptree itself can have an offset only if it represents a single
1349 * slice in an imported buffer object.
1350 * See intel_miptree_create_for_dri_image().
1352 assert(mt
->level
[0].level_x
== 0);
1353 assert(mt
->level
[0].level_y
== 0);
1355 /* Given level is relative to level zero while the miptree may be
1356 * represent just a subset of all levels starting from 'first_level'.
1358 assert(level
>= mt
->first_level
);
1359 level
-= mt
->first_level
;
1361 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1362 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1363 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1364 &x_offset_sa
, &y_offset_sa
);
1372 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1373 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1374 * and tile_h is set to 1.
1377 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1378 uint32_t *tile_w
, uint32_t *tile_h
)
1389 case ISL_TILING_LINEAR
:
1394 unreachable("not reached");
1400 * This function computes masks that may be used to select the bits of the X
1401 * and Y coordinates that indicate the offset within a tile. If the BO is
1402 * untiled, the masks are set to 0.
1405 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1406 uint32_t *mask_x
, uint32_t *mask_y
)
1408 uint32_t tile_w_bytes
, tile_h
;
1410 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1412 *mask_x
= tile_w_bytes
/ cpp
- 1;
1413 *mask_y
= tile_h
- 1;
1417 * Compute the offset (in bytes) from the start of the BO to the given x
1418 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1419 * multiples of the tile size.
1422 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1423 uint32_t x
, uint32_t y
)
1426 uint32_t pitch
= mt
->surf
.row_pitch
;
1428 switch (mt
->surf
.tiling
) {
1430 unreachable("not reached");
1431 case ISL_TILING_LINEAR
:
1432 return y
* pitch
+ x
* cpp
;
1434 assert((x
% (512 / cpp
)) == 0);
1435 assert((y
% 8) == 0);
1436 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1438 assert((x
% (128 / cpp
)) == 0);
1439 assert((y
% 32) == 0);
1440 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1445 * Rendering with tiled buffers requires that the base address of the buffer
1446 * be aligned to a page boundary. For renderbuffers, and sometimes with
1447 * textures, we may want the surface to point at a texture image level that
1448 * isn't at a page boundary.
1450 * This function returns an appropriately-aligned base offset
1451 * according to the tiling restrictions, plus any required x/y offset
1455 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1456 GLuint level
, GLuint slice
,
1461 uint32_t mask_x
, mask_y
;
1463 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1464 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1466 *tile_x
= x
& mask_x
;
1467 *tile_y
= y
& mask_y
;
1469 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1473 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1474 struct intel_mipmap_tree
*src_mt
,
1475 unsigned src_level
, unsigned src_layer
,
1476 struct intel_mipmap_tree
*dst_mt
,
1477 unsigned dst_level
, unsigned dst_layer
,
1478 unsigned width
, unsigned height
)
1481 ptrdiff_t src_stride
, dst_stride
;
1482 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1484 intel_miptree_map(brw
, src_mt
,
1485 src_level
, src_layer
,
1488 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1491 intel_miptree_map(brw
, dst_mt
,
1492 dst_level
, dst_layer
,
1495 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1499 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1500 _mesa_get_format_name(src_mt
->format
),
1501 src_mt
, src
, src_stride
,
1502 _mesa_get_format_name(dst_mt
->format
),
1503 dst_mt
, dst
, dst_stride
,
1506 int row_size
= cpp
* width
;
1507 if (src_stride
== row_size
&&
1508 dst_stride
== row_size
) {
1509 memcpy(dst
, src
, row_size
* height
);
1511 for (int i
= 0; i
< height
; i
++) {
1512 memcpy(dst
, src
, row_size
);
1518 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1519 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1521 /* Don't forget to copy the stencil data over, too. We could have skipped
1522 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1523 * shuffling the two data sources in/out of temporary storage instead of
1524 * the direct mapping we get this way.
1526 if (dst_mt
->stencil_mt
) {
1527 assert(src_mt
->stencil_mt
);
1528 intel_miptree_copy_slice_sw(brw
,
1529 src_mt
->stencil_mt
, src_level
, src_layer
,
1530 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1536 intel_miptree_copy_slice(struct brw_context
*brw
,
1537 struct intel_mipmap_tree
*src_mt
,
1538 unsigned src_level
, unsigned src_layer
,
1539 struct intel_mipmap_tree
*dst_mt
,
1540 unsigned dst_level
, unsigned dst_layer
)
1543 mesa_format format
= src_mt
->format
;
1544 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1545 src_level
- src_mt
->first_level
);
1546 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1547 src_level
- src_mt
->first_level
);
1549 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1550 src_level
- src_mt
->first_level
));
1552 assert(_mesa_get_srgb_format_linear(src_mt
->format
) ==
1553 _mesa_get_srgb_format_linear(dst_mt
->format
));
1555 if (dst_mt
->compressed
) {
1557 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1558 height
= ALIGN_NPOT(height
, j
) / j
;
1559 width
= ALIGN_NPOT(width
, i
) / i
;
1562 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1563 * below won't apply since we can't do the depth's Y tiling or the
1564 * stencil's W tiling in the blitter.
1566 if (src_mt
->stencil_mt
) {
1567 intel_miptree_copy_slice_sw(brw
,
1568 src_mt
, src_level
, src_layer
,
1569 dst_mt
, dst_level
, dst_layer
,
1574 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1575 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1577 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1580 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1581 _mesa_get_format_name(src_mt
->format
),
1582 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1583 _mesa_get_format_name(dst_mt
->format
),
1584 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1587 if (!intel_miptree_blit(brw
,
1588 src_mt
, src_level
, src_layer
, 0, 0, false,
1589 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1590 width
, height
, COLOR_LOGICOP_COPY
)) {
1591 perf_debug("miptree validate blit for %s failed\n",
1592 _mesa_get_format_name(format
));
1594 intel_miptree_copy_slice_sw(brw
,
1595 src_mt
, src_level
, src_layer
,
1596 dst_mt
, dst_level
, dst_layer
,
1602 * Copies the image's current data to the given miptree, and associates that
1603 * miptree with the image.
1606 intel_miptree_copy_teximage(struct brw_context
*brw
,
1607 struct intel_texture_image
*intelImage
,
1608 struct intel_mipmap_tree
*dst_mt
)
1610 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1611 struct intel_texture_object
*intel_obj
=
1612 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1613 int level
= intelImage
->base
.Base
.Level
;
1614 const unsigned face
= intelImage
->base
.Base
.Face
;
1615 unsigned start_layer
, end_layer
;
1617 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1619 assert(intelImage
->base
.Base
.Height
);
1621 end_layer
= intelImage
->base
.Base
.Height
- 1;
1622 } else if (face
> 0) {
1626 assert(intelImage
->base
.Base
.Depth
);
1628 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1631 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1632 intel_miptree_copy_slice(brw
,
1637 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1638 intel_obj
->needs_validate
= true;
1642 intel_miptree_init_mcs(struct brw_context
*brw
,
1643 struct intel_mipmap_tree
*mt
,
1646 assert(mt
->mcs_buf
!= NULL
);
1648 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1650 * When MCS buffer is enabled and bound to MSRT, it is required that it
1651 * is cleared prior to any rendering.
1653 * Since we don't use the MCS buffer for any purpose other than rendering,
1654 * it makes sense to just clear it immediately upon allocation.
1656 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1658 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
| MAP_RAW
);
1659 if (unlikely(map
== NULL
)) {
1660 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1661 brw_bo_unreference(mt
->mcs_buf
->bo
);
1666 memset(data
, init_value
, mt
->mcs_buf
->size
);
1667 brw_bo_unmap(mt
->mcs_buf
->bo
);
1670 static struct intel_miptree_aux_buffer
*
1671 intel_alloc_aux_buffer(struct brw_context
*brw
,
1673 const struct isl_surf
*aux_surf
,
1674 uint32_t alloc_flags
,
1675 struct intel_mipmap_tree
*mt
)
1677 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1681 buf
->size
= aux_surf
->size
;
1683 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1684 if (devinfo
->gen
>= 10) {
1685 /* On CNL, instead of setting the clear color in the SURFACE_STATE, we
1686 * will set a pointer to a dword somewhere that contains the color. So,
1687 * allocate the space for the clear color value here on the aux buffer.
1689 buf
->clear_color_offset
= buf
->size
;
1690 buf
->size
+= brw
->isl_dev
.ss
.clear_color_state_size
;
1693 buf
->pitch
= aux_surf
->row_pitch
;
1694 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1696 /* ISL has stricter set of alignment rules then the drm allocator.
1697 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1698 * trying to recalculate based on different format block sizes.
1700 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1701 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1707 if (devinfo
->gen
>= 10) {
1708 buf
->clear_color_bo
= buf
->bo
;
1709 brw_bo_reference(buf
->clear_color_bo
);
1712 buf
->surf
= *aux_surf
;
1718 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1719 struct intel_mipmap_tree
*mt
,
1722 assert(brw
->screen
->devinfo
.gen
>= 7); /* MCS only used on Gen7+ */
1723 assert(mt
->mcs_buf
== NULL
);
1724 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1726 /* Multisampled miptrees are only supported for single level. */
1727 assert(mt
->first_level
== 0);
1728 enum isl_aux_state
**aux_state
=
1729 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1733 struct isl_surf temp_mcs_surf
;
1735 MAYBE_UNUSED
bool ok
=
1736 isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_mcs_surf
);
1739 /* Buffer needs to be initialised requiring the buffer to be immediately
1740 * mapped to cpu space for writing. Therefore do not use the gpu access
1741 * flag which can cause an unnecessary delay if the backing pages happened
1742 * to be just used by the GPU.
1744 const uint32_t alloc_flags
= 0;
1745 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1746 &temp_mcs_surf
, alloc_flags
, mt
);
1752 mt
->aux_state
= aux_state
;
1754 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1760 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1761 struct intel_mipmap_tree
*mt
)
1763 assert(mt
->mcs_buf
== NULL
);
1764 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1765 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1767 struct isl_surf temp_ccs_surf
;
1769 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
, 0))
1772 assert(temp_ccs_surf
.size
&&
1773 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1775 enum isl_aux_state
**aux_state
=
1776 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1780 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1781 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1783 * "If Software wants to enable Color Compression without Fast clear,
1784 * Software needs to initialize MCS with zeros."
1786 * A CCS value of 0 indicates that the corresponding block is in the
1787 * pass-through state which is what we want.
1789 * For CCS_D, on the other hand, we don't care as we're about to perform a
1790 * fast-clear operation. In that case, being hot in caches more useful.
1792 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1793 BO_ALLOC_ZEROED
: BO_ALLOC_BUSY
;
1794 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1795 &temp_ccs_surf
, alloc_flags
, mt
);
1801 mt
->aux_state
= aux_state
;
1807 * Helper for intel_miptree_alloc_hiz() that sets
1808 * \c mt->level[level].has_hiz. Return true if and only if
1809 * \c has_hiz was set.
1812 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1813 struct intel_mipmap_tree
*mt
,
1816 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1818 assert(mt
->hiz_buf
);
1819 assert(mt
->surf
.size
> 0);
1821 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
1822 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1823 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1825 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1826 * and the height is 4 aligned. This allows our HiZ support
1827 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1828 * we can grow the width & height to allow the HiZ op to
1829 * force the proper size alignments.
1831 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1832 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1837 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1838 mt
->level
[level
].has_hiz
= true;
1843 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1844 struct intel_mipmap_tree
*mt
)
1846 assert(mt
->hiz_buf
== NULL
);
1847 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1849 enum isl_aux_state
**aux_state
=
1850 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1854 struct isl_surf temp_hiz_surf
;
1856 MAYBE_UNUSED
bool ok
=
1857 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
1860 const uint32_t alloc_flags
= BO_ALLOC_BUSY
;
1861 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1862 &temp_hiz_surf
, alloc_flags
, mt
);
1869 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1870 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1872 mt
->aux_state
= aux_state
;
1879 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1881 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1882 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1883 * compress clear color so we wait until an actual fast-clear to allocate it.
1886 intel_miptree_alloc_aux(struct brw_context
*brw
,
1887 struct intel_mipmap_tree
*mt
)
1889 switch (mt
->aux_usage
) {
1890 case ISL_AUX_USAGE_NONE
:
1893 case ISL_AUX_USAGE_HIZ
:
1894 assert(!_mesa_is_format_color_format(mt
->format
));
1895 if (!intel_miptree_alloc_hiz(brw
, mt
))
1899 case ISL_AUX_USAGE_MCS
:
1900 assert(_mesa_is_format_color_format(mt
->format
));
1901 assert(mt
->surf
.samples
> 1);
1902 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
1906 case ISL_AUX_USAGE_CCS_D
:
1907 /* Since CCS_D can only compress clear color so we wait until an actual
1908 * fast-clear to allocate it.
1912 case ISL_AUX_USAGE_CCS_E
:
1913 assert(_mesa_is_format_color_format(mt
->format
));
1914 assert(mt
->surf
.samples
== 1);
1915 if (!intel_miptree_alloc_ccs(brw
, mt
))
1920 unreachable("Invalid aux usage");
1925 * Can the miptree sample using the hiz buffer?
1928 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1929 struct intel_mipmap_tree
*mt
)
1931 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1933 if (!devinfo
->has_sample_with_hiz
) {
1941 /* It seems the hardware won't fallback to the depth buffer if some of the
1942 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1943 * of the texture to be HiZ enabled.
1945 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1946 if (!intel_miptree_level_has_hiz(mt
, level
))
1950 /* If compressed multisampling is enabled, then we use it for the auxiliary
1953 * From the BDW PRM (Volume 2d: Command Reference: Structures
1954 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1956 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1957 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1959 * There is no such blurb for 1D textures, but there is sufficient evidence
1960 * that this is broken on SKL+.
1962 return (mt
->surf
.samples
== 1 &&
1963 mt
->target
!= GL_TEXTURE_3D
&&
1964 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1968 * Does the miptree slice have hiz enabled?
1971 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1973 intel_miptree_check_level_layer(mt
, level
, 0);
1974 return mt
->level
[level
].has_hiz
;
1977 static inline uint32_t
1978 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1979 uint32_t start_level
, uint32_t num_levels
)
1981 assert(start_level
>= mt
->first_level
);
1982 assert(start_level
<= mt
->last_level
);
1984 if (num_levels
== INTEL_REMAINING_LAYERS
)
1985 num_levels
= mt
->last_level
- start_level
+ 1;
1986 /* Check for overflow */
1987 assert(start_level
+ num_levels
>= start_level
);
1988 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
1993 static inline uint32_t
1994 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
1995 uint32_t start_layer
, uint32_t num_layers
)
1997 assert(level
<= mt
->last_level
);
1999 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
2000 assert(start_layer
< total_num_layers
);
2001 if (num_layers
== INTEL_REMAINING_LAYERS
)
2002 num_layers
= total_num_layers
- start_layer
;
2003 /* Check for overflow */
2004 assert(start_layer
+ num_layers
>= start_layer
);
2005 assert(start_layer
+ num_layers
<= total_num_layers
);
2011 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2012 unsigned start_level
, unsigned num_levels
,
2013 unsigned start_layer
, unsigned num_layers
)
2015 assert(_mesa_is_format_color_format(mt
->format
));
2020 /* Clamp the level range to fit the miptree */
2021 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2023 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2024 const uint32_t level
= start_level
+ l
;
2025 const uint32_t level_layers
=
2026 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2027 for (unsigned a
= 0; a
< level_layers
; a
++) {
2028 enum isl_aux_state aux_state
=
2029 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2030 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2031 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2040 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2041 const struct intel_mipmap_tree
*mt
,
2042 unsigned level
, unsigned layer
)
2047 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2048 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2049 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2051 /* Compression of arrayed msaa surfaces is supported. */
2052 if (mt
->surf
.samples
> 1)
2055 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2056 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2058 mt
->surf
.logical_level0_px
.depth
== 1 &&
2059 mt
->surf
.logical_level0_px
.array_len
== 1));
2065 static enum isl_aux_op
2066 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2067 enum isl_aux_usage aux_usage
,
2068 bool fast_clear_supported
)
2070 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
2072 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
2074 assert(ccs_supported
== fast_clear_supported
);
2076 switch (aux_state
) {
2077 case ISL_AUX_STATE_CLEAR
:
2078 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2080 return ISL_AUX_OP_FULL_RESOLVE
;
2082 return ISL_AUX_OP_NONE
;
2084 case ISL_AUX_STATE_PASS_THROUGH
:
2085 return ISL_AUX_OP_NONE
;
2087 case ISL_AUX_STATE_RESOLVED
:
2088 case ISL_AUX_STATE_AUX_INVALID
:
2089 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2090 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2094 unreachable("Invalid aux state for CCS_D");
2097 static enum isl_aux_op
2098 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2099 enum isl_aux_usage aux_usage
,
2100 bool fast_clear_supported
)
2102 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
2103 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2104 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2105 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2107 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
2108 assert(fast_clear_supported
);
2110 switch (aux_state
) {
2111 case ISL_AUX_STATE_CLEAR
:
2112 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2113 if (fast_clear_supported
)
2114 return ISL_AUX_OP_NONE
;
2115 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
2116 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2118 return ISL_AUX_OP_FULL_RESOLVE
;
2120 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2121 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2122 return ISL_AUX_OP_FULL_RESOLVE
;
2123 else if (!fast_clear_supported
)
2124 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2126 return ISL_AUX_OP_NONE
;
2128 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2129 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2130 return ISL_AUX_OP_FULL_RESOLVE
;
2132 return ISL_AUX_OP_NONE
;
2134 case ISL_AUX_STATE_PASS_THROUGH
:
2135 return ISL_AUX_OP_NONE
;
2137 case ISL_AUX_STATE_RESOLVED
:
2138 case ISL_AUX_STATE_AUX_INVALID
:
2142 unreachable("Invalid aux state for CCS_E");
2146 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2147 struct intel_mipmap_tree
*mt
,
2148 uint32_t level
, uint32_t layer
,
2149 enum isl_aux_usage aux_usage
,
2150 bool fast_clear_supported
)
2152 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2154 enum isl_aux_op resolve_op
;
2155 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2156 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2157 fast_clear_supported
);
2159 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2160 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2161 fast_clear_supported
);
2164 if (resolve_op
!= ISL_AUX_OP_NONE
) {
2165 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2166 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2168 switch (resolve_op
) {
2169 case ISL_AUX_OP_FULL_RESOLVE
:
2170 /* The CCS full resolve operation destroys the CCS and sets it to the
2171 * pass-through state. (You can also think of this as being both a
2172 * resolve and an ambiguate in one operation.)
2174 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2175 ISL_AUX_STATE_PASS_THROUGH
);
2178 case ISL_AUX_OP_PARTIAL_RESOLVE
:
2179 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2180 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2184 unreachable("Invalid resolve op");
2190 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2191 struct intel_mipmap_tree
*mt
,
2192 uint32_t level
, uint32_t layer
,
2193 enum isl_aux_usage aux_usage
)
2195 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2196 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2197 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2199 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2201 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2202 switch (aux_state
) {
2203 case ISL_AUX_STATE_CLEAR
:
2204 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2205 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2206 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2208 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2209 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2210 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2211 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2212 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2213 ISL_AUX_STATE_PARTIAL_CLEAR
);
2217 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2218 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2219 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2220 break; /* Nothing to do */
2222 case ISL_AUX_STATE_PASS_THROUGH
:
2223 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2224 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2225 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2231 case ISL_AUX_STATE_RESOLVED
:
2232 case ISL_AUX_STATE_AUX_INVALID
:
2233 unreachable("Invalid aux state for CCS_E");
2236 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2237 /* CCS_D is a bit simpler */
2238 switch (aux_state
) {
2239 case ISL_AUX_STATE_CLEAR
:
2240 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2241 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2242 ISL_AUX_STATE_PARTIAL_CLEAR
);
2245 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2246 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2247 break; /* Nothing to do */
2249 case ISL_AUX_STATE_PASS_THROUGH
:
2253 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2254 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2255 case ISL_AUX_STATE_RESOLVED
:
2256 case ISL_AUX_STATE_AUX_INVALID
:
2257 unreachable("Invalid aux state for CCS_D");
2263 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2264 struct intel_mipmap_tree
*mt
,
2266 enum isl_aux_usage aux_usage
,
2267 bool fast_clear_supported
)
2269 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2271 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2272 case ISL_AUX_STATE_CLEAR
:
2273 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2274 if (!fast_clear_supported
) {
2275 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2276 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2277 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2281 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2282 break; /* Nothing to do */
2284 case ISL_AUX_STATE_RESOLVED
:
2285 case ISL_AUX_STATE_PASS_THROUGH
:
2286 case ISL_AUX_STATE_AUX_INVALID
:
2287 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2288 unreachable("Invalid aux state for MCS");
2293 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2294 struct intel_mipmap_tree
*mt
,
2296 enum isl_aux_usage aux_usage
)
2298 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2300 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2301 case ISL_AUX_STATE_CLEAR
:
2302 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2303 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2306 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2307 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2308 break; /* Nothing to do */
2310 case ISL_AUX_STATE_RESOLVED
:
2311 case ISL_AUX_STATE_PASS_THROUGH
:
2312 case ISL_AUX_STATE_AUX_INVALID
:
2313 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2314 unreachable("Invalid aux state for MCS");
2319 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2320 struct intel_mipmap_tree
*mt
,
2321 uint32_t level
, uint32_t layer
,
2322 enum isl_aux_usage aux_usage
,
2323 bool fast_clear_supported
)
2325 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2327 enum isl_aux_op hiz_op
= ISL_AUX_OP_NONE
;
2328 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2329 case ISL_AUX_STATE_CLEAR
:
2330 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2331 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2332 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2335 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2336 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2337 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2340 case ISL_AUX_STATE_PASS_THROUGH
:
2341 case ISL_AUX_STATE_RESOLVED
:
2344 case ISL_AUX_STATE_AUX_INVALID
:
2345 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2346 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
2349 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2350 unreachable("Invalid HiZ state");
2353 if (hiz_op
!= ISL_AUX_OP_NONE
) {
2354 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2357 case ISL_AUX_OP_FULL_RESOLVE
:
2358 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2359 ISL_AUX_STATE_RESOLVED
);
2362 case ISL_AUX_OP_AMBIGUATE
:
2363 /* The HiZ resolve operation is actually an ambiguate */
2364 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2365 ISL_AUX_STATE_PASS_THROUGH
);
2369 unreachable("Invalid HiZ op");
2375 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2376 struct intel_mipmap_tree
*mt
,
2377 uint32_t level
, uint32_t layer
,
2378 enum isl_aux_usage aux_usage
)
2380 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2382 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2383 case ISL_AUX_STATE_CLEAR
:
2384 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2385 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2386 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2389 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2390 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2391 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2392 break; /* Nothing to do */
2394 case ISL_AUX_STATE_RESOLVED
:
2395 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2396 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2397 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2399 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2400 ISL_AUX_STATE_AUX_INVALID
);
2404 case ISL_AUX_STATE_PASS_THROUGH
:
2405 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2406 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2407 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2411 case ISL_AUX_STATE_AUX_INVALID
:
2412 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2415 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2416 unreachable("Invalid HiZ state");
2421 intel_miptree_prepare_access(struct brw_context
*brw
,
2422 struct intel_mipmap_tree
*mt
,
2423 uint32_t start_level
, uint32_t num_levels
,
2424 uint32_t start_layer
, uint32_t num_layers
,
2425 enum isl_aux_usage aux_usage
,
2426 bool fast_clear_supported
)
2428 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2430 switch (mt
->aux_usage
) {
2431 case ISL_AUX_USAGE_NONE
:
2435 case ISL_AUX_USAGE_MCS
:
2436 assert(mt
->mcs_buf
);
2437 assert(start_level
== 0 && num_levels
== 1);
2438 const uint32_t level_layers
=
2439 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2440 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2441 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2442 aux_usage
, fast_clear_supported
);
2446 case ISL_AUX_USAGE_CCS_D
:
2447 case ISL_AUX_USAGE_CCS_E
:
2451 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2452 const uint32_t level
= start_level
+ l
;
2453 const uint32_t level_layers
=
2454 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2455 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2456 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2458 aux_usage
, fast_clear_supported
);
2463 case ISL_AUX_USAGE_HIZ
:
2464 assert(mt
->hiz_buf
);
2465 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2466 const uint32_t level
= start_level
+ l
;
2467 if (!intel_miptree_level_has_hiz(mt
, level
))
2470 const uint32_t level_layers
=
2471 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2472 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2473 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2474 aux_usage
, fast_clear_supported
);
2480 unreachable("Invalid aux usage");
2485 intel_miptree_finish_write(struct brw_context
*brw
,
2486 struct intel_mipmap_tree
*mt
, uint32_t level
,
2487 uint32_t start_layer
, uint32_t num_layers
,
2488 enum isl_aux_usage aux_usage
)
2490 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2492 switch (mt
->aux_usage
) {
2493 case ISL_AUX_USAGE_NONE
:
2497 case ISL_AUX_USAGE_MCS
:
2498 assert(mt
->mcs_buf
);
2499 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2500 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2505 case ISL_AUX_USAGE_CCS_D
:
2506 case ISL_AUX_USAGE_CCS_E
:
2510 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2511 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2516 case ISL_AUX_USAGE_HIZ
:
2517 if (!intel_miptree_level_has_hiz(mt
, level
))
2520 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2521 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2527 unreachable("Invavlid aux usage");
2532 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2533 uint32_t level
, uint32_t layer
)
2535 intel_miptree_check_level_layer(mt
, level
, layer
);
2537 if (_mesa_is_format_color_format(mt
->format
)) {
2538 assert(mt
->mcs_buf
!= NULL
);
2539 assert(mt
->surf
.samples
== 1 ||
2540 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2541 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2542 unreachable("Cannot get aux state for stencil");
2544 assert(intel_miptree_level_has_hiz(mt
, level
));
2547 return mt
->aux_state
[level
][layer
];
2551 intel_miptree_set_aux_state(struct brw_context
*brw
,
2552 struct intel_mipmap_tree
*mt
, uint32_t level
,
2553 uint32_t start_layer
, uint32_t num_layers
,
2554 enum isl_aux_state aux_state
)
2556 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2558 if (_mesa_is_format_color_format(mt
->format
)) {
2559 assert(mt
->mcs_buf
!= NULL
);
2560 assert(mt
->surf
.samples
== 1 ||
2561 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2562 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2563 unreachable("Cannot get aux state for stencil");
2565 assert(intel_miptree_level_has_hiz(mt
, level
));
2568 for (unsigned a
= 0; a
< num_layers
; a
++) {
2569 if (mt
->aux_state
[level
][start_layer
+ a
] != aux_state
) {
2570 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2571 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2576 /* On Gen9 color buffers may be compressed by the hardware (lossless
2577 * compression). There are, however, format restrictions and care needs to be
2578 * taken that the sampler engine is capable for re-interpreting a buffer with
2579 * format different the buffer was originally written with.
2581 * For example, SRGB formats are not compressible and the sampler engine isn't
2582 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2583 * color buffer needs to be resolved so that the sampling surface can be
2584 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2588 can_texture_with_ccs(struct brw_context
*brw
,
2589 struct intel_mipmap_tree
*mt
,
2590 enum isl_format view_format
)
2592 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2595 if (!format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2597 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2598 isl_format_get_layout(view_format
)->name
,
2599 _mesa_get_format_name(mt
->format
));
2607 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2608 struct intel_mipmap_tree
*mt
,
2609 enum isl_format view_format
)
2611 switch (mt
->aux_usage
) {
2612 case ISL_AUX_USAGE_HIZ
:
2613 if (intel_miptree_sample_with_hiz(brw
, mt
))
2614 return ISL_AUX_USAGE_HIZ
;
2617 case ISL_AUX_USAGE_MCS
:
2618 return ISL_AUX_USAGE_MCS
;
2620 case ISL_AUX_USAGE_CCS_D
:
2621 case ISL_AUX_USAGE_CCS_E
:
2623 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2624 return ISL_AUX_USAGE_NONE
;
2627 /* If we don't have any unresolved color, report an aux usage of
2628 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
2629 * aux surface and we can save some bandwidth.
2631 if (!intel_miptree_has_color_unresolved(mt
, 0, INTEL_REMAINING_LEVELS
,
2632 0, INTEL_REMAINING_LAYERS
))
2633 return ISL_AUX_USAGE_NONE
;
2635 if (can_texture_with_ccs(brw
, mt
, view_format
))
2636 return ISL_AUX_USAGE_CCS_E
;
2643 return ISL_AUX_USAGE_NONE
;
2647 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2649 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2650 * values so sRGB curve application was a no-op for all fast-clearable
2653 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2654 * values, the hardware interprets the floats, not as what would be
2655 * returned from the sampler (or written by the shader), but as being
2656 * between format conversion and sRGB curve application. This means that
2657 * we can switch between sRGB and UNORM without having to whack the clear
2660 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2664 intel_miptree_prepare_texture(struct brw_context
*brw
,
2665 struct intel_mipmap_tree
*mt
,
2666 enum isl_format view_format
,
2667 uint32_t start_level
, uint32_t num_levels
,
2668 uint32_t start_layer
, uint32_t num_layers
)
2670 enum isl_aux_usage aux_usage
=
2671 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2672 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2674 /* Clear color is specified as ints or floats and the conversion is done by
2675 * the sampler. If we have a texture view, we would have to perform the
2676 * clear color conversion manually. Just disable clear color.
2678 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2679 clear_supported
= false;
2681 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2682 start_layer
, num_layers
,
2683 aux_usage
, clear_supported
);
2687 intel_miptree_prepare_image(struct brw_context
*brw
,
2688 struct intel_mipmap_tree
*mt
)
2690 /* The data port doesn't understand any compression */
2691 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2692 0, INTEL_REMAINING_LAYERS
,
2693 ISL_AUX_USAGE_NONE
, false);
2697 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2698 struct intel_mipmap_tree
*mt
,
2699 enum isl_format render_format
,
2701 bool draw_aux_disabled
)
2703 struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2705 if (draw_aux_disabled
)
2706 return ISL_AUX_USAGE_NONE
;
2708 switch (mt
->aux_usage
) {
2709 case ISL_AUX_USAGE_MCS
:
2710 assert(mt
->mcs_buf
);
2711 return ISL_AUX_USAGE_MCS
;
2713 case ISL_AUX_USAGE_CCS_D
:
2714 case ISL_AUX_USAGE_CCS_E
:
2716 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2717 return ISL_AUX_USAGE_NONE
;
2720 /* gen9 hardware technically supports non-0/1 clear colors with sRGB
2721 * formats. However, there are issues with blending where it doesn't
2722 * properly apply the sRGB curve to the clear color when blending.
2724 if (devinfo
->gen
== 9 && blend_enabled
&&
2725 isl_format_is_srgb(render_format
) &&
2726 !isl_color_value_is_zero_one(mt
->fast_clear_color
, render_format
))
2727 return ISL_AUX_USAGE_NONE
;
2729 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
&&
2730 format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2732 return ISL_AUX_USAGE_CCS_E
;
2734 /* Otherwise, we have to fall back to CCS_D */
2735 return ISL_AUX_USAGE_CCS_D
;
2738 return ISL_AUX_USAGE_NONE
;
2743 intel_miptree_prepare_render(struct brw_context
*brw
,
2744 struct intel_mipmap_tree
*mt
, uint32_t level
,
2745 uint32_t start_layer
, uint32_t layer_count
,
2746 enum isl_aux_usage aux_usage
)
2748 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2749 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2753 intel_miptree_finish_render(struct brw_context
*brw
,
2754 struct intel_mipmap_tree
*mt
, uint32_t level
,
2755 uint32_t start_layer
, uint32_t layer_count
,
2756 enum isl_aux_usage aux_usage
)
2758 assert(_mesa_is_format_color_format(mt
->format
));
2760 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2765 intel_miptree_prepare_depth(struct brw_context
*brw
,
2766 struct intel_mipmap_tree
*mt
, uint32_t level
,
2767 uint32_t start_layer
, uint32_t layer_count
)
2769 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2770 mt
->aux_usage
, mt
->hiz_buf
!= NULL
);
2774 intel_miptree_finish_depth(struct brw_context
*brw
,
2775 struct intel_mipmap_tree
*mt
, uint32_t level
,
2776 uint32_t start_layer
, uint32_t layer_count
,
2779 if (depth_written
) {
2780 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2781 mt
->hiz_buf
!= NULL
);
2786 intel_miptree_prepare_external(struct brw_context
*brw
,
2787 struct intel_mipmap_tree
*mt
)
2789 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
2790 bool supports_fast_clear
= false;
2792 const struct isl_drm_modifier_info
*mod_info
=
2793 isl_drm_modifier_get_info(mt
->drm_modifier
);
2795 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
2796 /* CCS_E is the only supported aux for external images and it's only
2797 * supported on very simple images.
2799 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
2800 assert(_mesa_is_format_color_format(mt
->format
));
2801 assert(mt
->first_level
== 0 && mt
->last_level
== 0);
2802 assert(mt
->surf
.logical_level0_px
.depth
== 1);
2803 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
2804 assert(mt
->surf
.samples
== 1);
2805 assert(mt
->mcs_buf
!= NULL
);
2807 aux_usage
= mod_info
->aux_usage
;
2808 supports_fast_clear
= mod_info
->supports_clear_color
;
2811 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2812 0, INTEL_REMAINING_LAYERS
,
2813 aux_usage
, supports_fast_clear
);
2817 intel_miptree_finish_external(struct brw_context
*brw
,
2818 struct intel_mipmap_tree
*mt
)
2823 /* We don't know the actual aux state of the aux surface. The previous
2824 * owner could have given it to us in a number of different states.
2825 * Because we don't know the aux state, we reset the aux state to the
2826 * least common denominator of possible valid states.
2828 enum isl_aux_state default_aux_state
=
2829 isl_drm_modifier_get_default_aux_state(mt
->drm_modifier
);
2830 assert(mt
->last_level
== mt
->first_level
);
2831 intel_miptree_set_aux_state(brw
, mt
, 0, 0, INTEL_REMAINING_LAYERS
,
2836 * Make it possible to share the BO backing the given miptree with another
2837 * process or another miptree.
2839 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2840 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2841 * ensure that no MCS buffer gets allocated in the future.
2843 * HiZ is similarly unsafe with shared buffers.
2846 intel_miptree_make_shareable(struct brw_context
*brw
,
2847 struct intel_mipmap_tree
*mt
)
2849 /* MCS buffers are also used for multisample buffers, but we can't resolve
2850 * away a multisample MCS buffer because it's an integral part of how the
2851 * pixel data is stored. Fortunately this code path should never be
2852 * reached for multisample buffers.
2854 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2855 mt
->surf
.samples
== 1);
2857 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2858 0, INTEL_REMAINING_LAYERS
,
2859 ISL_AUX_USAGE_NONE
, false);
2862 brw_bo_unreference(mt
->mcs_buf
->bo
);
2866 /* Any pending MCS/CCS operations are no longer needed. Trying to
2867 * execute any will likely crash due to the missing aux buffer. So let's
2868 * delete all pending ops.
2870 free(mt
->aux_state
);
2871 mt
->aux_state
= NULL
;
2872 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2876 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2879 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2880 mt
->level
[l
].has_hiz
= false;
2883 /* Any pending HiZ operations are no longer needed. Trying to execute
2884 * any will likely crash due to the missing aux buffer. So let's delete
2887 free(mt
->aux_state
);
2888 mt
->aux_state
= NULL
;
2889 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2892 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2893 mt
->supports_fast_clear
= false;
2898 * \brief Get pointer offset into stencil buffer.
2900 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2901 * must decode the tile's layout in software.
2904 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2906 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2908 * Even though the returned offset is always positive, the return type is
2910 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2911 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2914 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2916 uint32_t tile_size
= 4096;
2917 uint32_t tile_width
= 64;
2918 uint32_t tile_height
= 64;
2919 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2921 uint32_t tile_x
= x
/ tile_width
;
2922 uint32_t tile_y
= y
/ tile_height
;
2924 /* The byte's address relative to the tile's base addres. */
2925 uint32_t byte_x
= x
% tile_width
;
2926 uint32_t byte_y
= y
% tile_height
;
2928 uintptr_t u
= tile_y
* row_size
2929 + tile_x
* tile_size
2930 + 512 * (byte_x
/ 8)
2932 + 32 * ((byte_y
/ 4) % 2)
2933 + 16 * ((byte_x
/ 4) % 2)
2934 + 8 * ((byte_y
/ 2) % 2)
2935 + 4 * ((byte_x
/ 2) % 2)
2940 /* adjust for bit6 swizzling */
2941 if (((byte_x
/ 8) % 2) == 1) {
2942 if (((byte_y
/ 8) % 2) == 0) {
2954 intel_miptree_updownsample(struct brw_context
*brw
,
2955 struct intel_mipmap_tree
*src
,
2956 struct intel_mipmap_tree
*dst
)
2958 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2959 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2960 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2961 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2963 brw_blorp_blit_miptrees(brw
,
2964 src
, 0 /* level */, 0 /* layer */,
2965 src
->format
, SWIZZLE_XYZW
,
2966 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2969 GL_NEAREST
, false, false /*mirror x, y*/,
2972 if (src
->stencil_mt
) {
2973 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2974 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2975 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2976 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2978 brw_blorp_blit_miptrees(brw
,
2979 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2980 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2981 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2982 dst
->stencil_mt
->format
,
2985 GL_NEAREST
, false, false /*mirror x, y*/,
2986 false, false /* decode/encode srgb */);
2991 intel_update_r8stencil(struct brw_context
*brw
,
2992 struct intel_mipmap_tree
*mt
)
2994 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2996 assert(devinfo
->gen
>= 7);
2997 struct intel_mipmap_tree
*src
=
2998 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2999 if (!src
|| devinfo
->gen
>= 8 || !src
->r8stencil_needs_update
)
3002 assert(src
->surf
.size
> 0);
3004 if (!mt
->r8stencil_mt
) {
3005 assert(devinfo
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
3006 mt
->r8stencil_mt
= make_surface(
3009 MESA_FORMAT_R_UINT8
,
3010 src
->first_level
, src
->last_level
,
3011 src
->surf
.logical_level0_px
.width
,
3012 src
->surf
.logical_level0_px
.height
,
3013 src
->surf
.dim
== ISL_SURF_DIM_3D
?
3014 src
->surf
.logical_level0_px
.depth
:
3015 src
->surf
.logical_level0_px
.array_len
,
3018 ISL_SURF_USAGE_TEXTURE_BIT
,
3019 BO_ALLOC_BUSY
, 0, NULL
);
3020 assert(mt
->r8stencil_mt
);
3023 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
3025 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
3026 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
3027 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
3028 src
->surf
.phys_level0_sa
.array_len
;
3030 for (unsigned layer
= 0; layer
< depth
; layer
++) {
3031 brw_blorp_copy_miptrees(brw
,
3035 minify(src
->surf
.logical_level0_px
.width
,
3037 minify(src
->surf
.logical_level0_px
.height
,
3042 brw_cache_flush_for_read(brw
, dst
->bo
);
3043 src
->r8stencil_needs_update
= false;
3047 intel_miptree_map_raw(struct brw_context
*brw
,
3048 struct intel_mipmap_tree
*mt
,
3051 struct brw_bo
*bo
= mt
->bo
;
3053 if (brw_batch_references(&brw
->batch
, bo
))
3054 intel_batchbuffer_flush(brw
);
3056 return brw_bo_map(brw
, bo
, mode
);
3060 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3062 brw_bo_unmap(mt
->bo
);
3066 intel_miptree_map_gtt(struct brw_context
*brw
,
3067 struct intel_mipmap_tree
*mt
,
3068 struct intel_miptree_map
*map
,
3069 unsigned int level
, unsigned int slice
)
3071 unsigned int bw
, bh
;
3073 unsigned int image_x
, image_y
;
3074 intptr_t x
= map
->x
;
3075 intptr_t y
= map
->y
;
3077 /* For compressed formats, the stride is the number of bytes per
3078 * row of blocks. intel_miptree_get_image_offset() already does
3081 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3082 assert(y
% bh
== 0);
3083 assert(x
% bw
== 0);
3087 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3094 /* Note that in the case of cube maps, the caller must have passed the
3095 * slice number referencing the face.
3097 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3101 map
->stride
= mt
->surf
.row_pitch
;
3102 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3105 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3106 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3107 map
->x
, map
->y
, map
->w
, map
->h
,
3108 mt
, _mesa_get_format_name(mt
->format
),
3109 x
, y
, map
->ptr
, map
->stride
);
3113 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3115 intel_miptree_unmap_raw(mt
);
3119 intel_miptree_map_blit(struct brw_context
*brw
,
3120 struct intel_mipmap_tree
*mt
,
3121 struct intel_miptree_map
*map
,
3122 unsigned int level
, unsigned int slice
)
3124 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3125 /* first_level */ 0,
3129 MIPTREE_CREATE_LINEAR
);
3131 if (!map
->linear_mt
) {
3132 fprintf(stderr
, "Failed to allocate blit temporary\n");
3135 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3137 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3138 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3139 * invalidate is set, since we'll be writing the whole rectangle from our
3140 * temporary buffer back out.
3142 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3143 if (!intel_miptree_copy(brw
,
3144 mt
, level
, slice
, map
->x
, map
->y
,
3145 map
->linear_mt
, 0, 0, 0, 0,
3147 fprintf(stderr
, "Failed to blit\n");
3152 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3154 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3155 map
->x
, map
->y
, map
->w
, map
->h
,
3156 mt
, _mesa_get_format_name(mt
->format
),
3157 level
, slice
, map
->ptr
, map
->stride
);
3162 intel_miptree_release(&map
->linear_mt
);
3168 intel_miptree_unmap_blit(struct brw_context
*brw
,
3169 struct intel_mipmap_tree
*mt
,
3170 struct intel_miptree_map
*map
,
3174 struct gl_context
*ctx
= &brw
->ctx
;
3176 intel_miptree_unmap_raw(map
->linear_mt
);
3178 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3179 bool ok
= intel_miptree_copy(brw
,
3180 map
->linear_mt
, 0, 0, 0, 0,
3181 mt
, level
, slice
, map
->x
, map
->y
,
3183 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3186 intel_miptree_release(&map
->linear_mt
);
3190 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3192 #if defined(USE_SSE41)
3194 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3195 struct intel_mipmap_tree
*mt
,
3196 struct intel_miptree_map
*map
,
3197 unsigned int level
, unsigned int slice
)
3199 assert(map
->mode
& GL_MAP_READ_BIT
);
3200 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3202 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3203 map
->x
, map
->y
, map
->w
, map
->h
,
3204 mt
, _mesa_get_format_name(mt
->format
),
3205 level
, slice
, map
->ptr
, map
->stride
);
3207 /* Map the original image */
3210 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3214 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3220 src
+= image_y
* mt
->surf
.row_pitch
;
3221 src
+= image_x
* mt
->cpp
;
3223 /* Due to the pixel offsets for the particular image being mapped, our
3224 * src pointer may not be 16-byte aligned. However, if the pitch is
3225 * divisible by 16, then the amount by which it's misaligned will remain
3226 * consistent from row to row.
3228 assert((mt
->surf
.row_pitch
% 16) == 0);
3229 const int misalignment
= ((uintptr_t) src
) & 15;
3231 /* Create an untiled temporary buffer for the mapping. */
3232 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3234 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3236 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3237 /* Offset the destination so it has the same misalignment as src. */
3238 map
->ptr
= map
->buffer
+ misalignment
;
3240 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3242 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3243 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3244 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3246 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3249 intel_miptree_unmap_raw(mt
);
3253 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3254 struct intel_mipmap_tree
*mt
,
3255 struct intel_miptree_map
*map
,
3259 _mesa_align_free(map
->buffer
);
3266 intel_miptree_map_s8(struct brw_context
*brw
,
3267 struct intel_mipmap_tree
*mt
,
3268 struct intel_miptree_map
*map
,
3269 unsigned int level
, unsigned int slice
)
3271 map
->stride
= map
->w
;
3272 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3276 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3277 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3278 * invalidate is set, since we'll be writing the whole rectangle from our
3279 * temporary buffer back out.
3281 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3282 uint8_t *untiled_s8_map
= map
->ptr
;
3283 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3284 unsigned int image_x
, image_y
;
3286 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3288 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3289 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3290 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3291 x
+ image_x
+ map
->x
,
3292 y
+ image_y
+ map
->y
,
3293 brw
->has_swizzling
);
3294 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3298 intel_miptree_unmap_raw(mt
);
3300 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3301 map
->x
, map
->y
, map
->w
, map
->h
,
3302 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3304 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3305 map
->x
, map
->y
, map
->w
, map
->h
,
3306 mt
, map
->ptr
, map
->stride
);
3311 intel_miptree_unmap_s8(struct brw_context
*brw
,
3312 struct intel_mipmap_tree
*mt
,
3313 struct intel_miptree_map
*map
,
3317 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3318 unsigned int image_x
, image_y
;
3319 uint8_t *untiled_s8_map
= map
->ptr
;
3320 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3322 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3324 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3325 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3326 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3327 image_x
+ x
+ map
->x
,
3328 image_y
+ y
+ map
->y
,
3329 brw
->has_swizzling
);
3330 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3334 intel_miptree_unmap_raw(mt
);
3341 intel_miptree_map_etc(struct brw_context
*brw
,
3342 struct intel_mipmap_tree
*mt
,
3343 struct intel_miptree_map
*map
,
3347 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3348 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3349 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3352 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3353 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3355 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3356 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3357 map
->w
, map
->h
, 1));
3358 map
->ptr
= map
->buffer
;
3362 intel_miptree_unmap_etc(struct brw_context
*brw
,
3363 struct intel_mipmap_tree
*mt
,
3364 struct intel_miptree_map
*map
,
3370 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3375 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3376 + image_y
* mt
->surf
.row_pitch
3377 + image_x
* mt
->cpp
;
3379 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3380 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3381 map
->ptr
, map
->stride
,
3384 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3385 map
->ptr
, map
->stride
,
3386 map
->w
, map
->h
, mt
->etc_format
);
3388 intel_miptree_unmap_raw(mt
);
3393 * Mapping function for packed depth/stencil miptrees backed by real separate
3394 * miptrees for depth and stencil.
3396 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3397 * separate from the depth buffer. Yet at the GL API level, we have to expose
3398 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3399 * be able to map that memory for texture storage and glReadPixels-type
3400 * operations. We give Mesa core that access by mallocing a temporary and
3401 * copying the data between the actual backing store and the temporary.
3404 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3405 struct intel_mipmap_tree
*mt
,
3406 struct intel_miptree_map
*map
,
3407 unsigned int level
, unsigned int slice
)
3409 struct intel_mipmap_tree
*z_mt
= mt
;
3410 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3411 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3412 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3414 map
->stride
= map
->w
* packed_bpp
;
3415 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3419 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3420 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3421 * invalidate is set, since we'll be writing the whole rectangle from our
3422 * temporary buffer back out.
3424 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3425 uint32_t *packed_map
= map
->ptr
;
3426 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3427 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3428 unsigned int s_image_x
, s_image_y
;
3429 unsigned int z_image_x
, z_image_y
;
3431 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3432 &s_image_x
, &s_image_y
);
3433 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3434 &z_image_x
, &z_image_y
);
3436 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3437 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3438 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3439 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3442 brw
->has_swizzling
);
3443 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3444 (z_mt
->surf
.row_pitch
/ 4) +
3445 (map_x
+ z_image_x
));
3446 uint8_t s
= s_map
[s_offset
];
3447 uint32_t z
= z_map
[z_offset
];
3449 if (map_z32f_x24s8
) {
3450 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3451 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3453 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3458 intel_miptree_unmap_raw(s_mt
);
3459 intel_miptree_unmap_raw(z_mt
);
3461 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3463 map
->x
, map
->y
, map
->w
, map
->h
,
3464 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3465 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3466 map
->ptr
, map
->stride
);
3468 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3469 map
->x
, map
->y
, map
->w
, map
->h
,
3470 mt
, map
->ptr
, map
->stride
);
3475 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3476 struct intel_mipmap_tree
*mt
,
3477 struct intel_miptree_map
*map
,
3481 struct intel_mipmap_tree
*z_mt
= mt
;
3482 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3483 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3485 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3486 uint32_t *packed_map
= map
->ptr
;
3487 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3488 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3489 unsigned int s_image_x
, s_image_y
;
3490 unsigned int z_image_x
, z_image_y
;
3492 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3493 &s_image_x
, &s_image_y
);
3494 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3495 &z_image_x
, &z_image_y
);
3497 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3498 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3499 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3500 x
+ s_image_x
+ map
->x
,
3501 y
+ s_image_y
+ map
->y
,
3502 brw
->has_swizzling
);
3503 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3504 (z_mt
->surf
.row_pitch
/ 4) +
3505 (x
+ z_image_x
+ map
->x
));
3507 if (map_z32f_x24s8
) {
3508 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3509 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3511 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3512 s_map
[s_offset
] = packed
>> 24;
3513 z_map
[z_offset
] = packed
;
3518 intel_miptree_unmap_raw(s_mt
);
3519 intel_miptree_unmap_raw(z_mt
);
3521 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3523 map
->x
, map
->y
, map
->w
, map
->h
,
3524 z_mt
, _mesa_get_format_name(z_mt
->format
),
3525 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3526 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3527 map
->ptr
, map
->stride
);
3534 * Create and attach a map to the miptree at (level, slice). Return the
3537 static struct intel_miptree_map
*
3538 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3547 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3552 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3553 mt
->level
[level
].slice
[slice
].map
= map
;
3565 * Release the map at (level, slice).
3568 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3572 struct intel_miptree_map
**map
;
3574 map
= &mt
->level
[level
].slice
[slice
].map
;
3580 can_blit_slice(struct intel_mipmap_tree
*mt
,
3581 unsigned int level
, unsigned int slice
)
3583 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3584 if (mt
->surf
.row_pitch
>= 32768)
3591 use_intel_mipree_map_blit(struct brw_context
*brw
,
3592 struct intel_mipmap_tree
*mt
,
3597 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3599 if (devinfo
->has_llc
&&
3600 /* It's probably not worth swapping to the blit ring because of
3601 * all the overhead involved.
3603 !(mode
& GL_MAP_WRITE_BIT
) &&
3605 (mt
->surf
.tiling
== ISL_TILING_X
||
3606 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3607 (devinfo
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3608 /* Fast copy blit on skl+ supports all tiling formats. */
3609 devinfo
->gen
>= 9) &&
3610 can_blit_slice(mt
, level
, slice
))
3613 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3614 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3615 assert(can_blit_slice(mt
, level
, slice
));
3623 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3624 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3625 * arithmetic overflow.
3627 * If you call this function and use \a out_stride, then you're doing pointer
3628 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3629 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3630 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3631 * which usually have type uint32_t or GLuint.
3634 intel_miptree_map(struct brw_context
*brw
,
3635 struct intel_mipmap_tree
*mt
,
3644 ptrdiff_t *out_stride
)
3646 struct intel_miptree_map
*map
;
3648 assert(mt
->surf
.samples
== 1);
3650 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3657 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3658 map
->mode
& GL_MAP_WRITE_BIT
);
3660 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3661 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3662 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3663 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3664 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3665 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3666 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3667 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3668 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3669 #if defined(USE_SSE41)
3670 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3671 !mt
->compressed
&& cpu_has_sse4_1
&&
3672 (mt
->surf
.row_pitch
% 16 == 0)) {
3673 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3676 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3679 *out_ptr
= map
->ptr
;
3680 *out_stride
= map
->stride
;
3682 if (map
->ptr
== NULL
)
3683 intel_miptree_release_map(mt
, level
, slice
);
3687 intel_miptree_unmap(struct brw_context
*brw
,
3688 struct intel_mipmap_tree
*mt
,
3692 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3694 assert(mt
->surf
.samples
== 1);
3699 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3700 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3702 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3703 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3704 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3705 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3706 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3707 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3708 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3709 } else if (map
->linear_mt
) {
3710 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3711 #if defined(USE_SSE41)
3712 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3713 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3716 intel_miptree_unmap_gtt(mt
);
3719 intel_miptree_release_map(mt
, level
, slice
);
3723 get_isl_surf_dim(GLenum target
)
3727 case GL_TEXTURE_1D_ARRAY
:
3728 return ISL_SURF_DIM_1D
;
3731 case GL_TEXTURE_2D_ARRAY
:
3732 case GL_TEXTURE_RECTANGLE
:
3733 case GL_TEXTURE_CUBE_MAP
:
3734 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3735 case GL_TEXTURE_2D_MULTISAMPLE
:
3736 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3737 case GL_TEXTURE_EXTERNAL_OES
:
3738 return ISL_SURF_DIM_2D
;
3741 return ISL_SURF_DIM_3D
;
3744 unreachable("Invalid texture target");
3748 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3749 enum isl_tiling tiling
, GLenum target
)
3753 case GL_TEXTURE_1D_ARRAY
:
3754 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3755 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3758 case GL_TEXTURE_2D_ARRAY
:
3759 case GL_TEXTURE_RECTANGLE
:
3760 case GL_TEXTURE_2D_MULTISAMPLE
:
3761 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3762 case GL_TEXTURE_EXTERNAL_OES
:
3763 return ISL_DIM_LAYOUT_GEN4_2D
;
3765 case GL_TEXTURE_CUBE_MAP
:
3766 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3767 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3768 ISL_DIM_LAYOUT_GEN4_2D
);
3771 return (devinfo
->gen
>= 9 ?
3772 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3775 unreachable("Invalid texture target");
3779 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3780 const struct intel_mipmap_tree
*mt
)
3783 return ISL_AUX_USAGE_HIZ
;
3786 return ISL_AUX_USAGE_NONE
;
3788 return mt
->aux_usage
;