2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
28 #include <drm_fourcc.h>
30 #include "intel_batchbuffer.h"
31 #include "intel_image.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_tex.h"
34 #include "intel_blit.h"
35 #include "intel_fbo.h"
37 #include "brw_blorp.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
48 #include "x86/common_x86_asm.h"
50 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
52 static void *intel_miptree_map_raw(struct brw_context
*brw
,
53 struct intel_mipmap_tree
*mt
,
56 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
59 intel_miptree_alloc_aux(struct brw_context
*brw
,
60 struct intel_mipmap_tree
*mt
);
63 intel_miptree_supports_mcs(struct brw_context
*brw
,
64 const struct intel_mipmap_tree
*mt
)
66 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
68 /* MCS compression only applies to multisampled miptrees */
69 if (mt
->surf
.samples
<= 1)
72 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
76 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
77 switch (_mesa_get_format_base_format(mt
->format
)) {
78 case GL_DEPTH_COMPONENT
:
79 case GL_STENCIL_INDEX
:
80 case GL_DEPTH_STENCIL
:
83 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
85 * This field must be set to 0 for all SINT MSRTs when all RT channels
88 * In practice this means that we have to disable MCS for all signed
89 * integer MSAA buffers. The alternative, to disable MCS only when one
90 * of the render target channels is disabled, is impractical because it
91 * would require converting between CMS and UMS MSAA layouts on the fly,
94 if (devinfo
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
103 intel_tiling_supports_ccs(const struct brw_context
*brw
,
104 enum isl_tiling tiling
)
106 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
108 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
109 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
111 * - Support is limited to tiled render targets.
113 * Gen9 changes the restriction to Y-tile only.
115 if (devinfo
->gen
>= 9)
116 return tiling
== ISL_TILING_Y0
;
117 else if (devinfo
->gen
>= 7)
118 return tiling
!= ISL_TILING_LINEAR
;
124 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
125 * can be used. This doesn't (and should not) inspect any of the properties of
128 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
129 * beneath the "Fast Color Clear" bullet (p326):
131 * - Support is for non-mip-mapped and non-array surface types only.
133 * And then later, on p327:
135 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
138 * From the Skylake documentation, it is made clear that X-tiling is no longer
141 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
145 intel_miptree_supports_ccs(struct brw_context
*brw
,
146 const struct intel_mipmap_tree
*mt
)
148 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
150 /* MCS support does not exist prior to Gen7 */
151 if (devinfo
->gen
< 7)
154 /* This function applies only to non-multisampled render targets. */
155 if (mt
->surf
.samples
> 1)
158 /* MCS is only supported for color buffers */
159 switch (_mesa_get_format_base_format(mt
->format
)) {
160 case GL_DEPTH_COMPONENT
:
161 case GL_DEPTH_STENCIL
:
162 case GL_STENCIL_INDEX
:
166 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
169 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
170 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
171 mt
->surf
.logical_level0_px
.depth
> 1;
174 /* Multisample surfaces with the CMS layout are not layered surfaces,
175 * yet still have physical_depth0 > 1. Assert that we don't
176 * accidentally reject a multisampled surface here. We should have
177 * rejected it earlier by explicitly checking the sample count.
179 assert(mt
->surf
.samples
== 1);
182 /* Handle the hardware restrictions...
184 * All GENs have the following restriction: "MCS buffer for non-MSRT is
185 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
187 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
188 * Non-MultiSampler Render Target Restrictions) Support is for
189 * non-mip-mapped and non-array surface types only.
191 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
192 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
193 * surfaces are supported with MCS buffer layout with these alignments in
194 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
196 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
197 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
198 * surfaces are supported with MCS buffer layout with these alignments in
199 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
201 if (devinfo
->gen
< 8 && (mip_mapped
|| arrayed
))
204 /* There's no point in using an MCS buffer if the surface isn't in a
207 if (!brw
->mesa_format_supports_render
[mt
->format
])
214 intel_tiling_supports_hiz(const struct brw_context
*brw
,
215 enum isl_tiling tiling
)
217 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
219 if (devinfo
->gen
< 6)
222 return tiling
== ISL_TILING_Y0
;
226 intel_miptree_supports_hiz(const struct brw_context
*brw
,
227 const struct intel_mipmap_tree
*mt
)
232 switch (mt
->format
) {
233 case MESA_FORMAT_Z_FLOAT32
:
234 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
235 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
236 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
237 case MESA_FORMAT_Z_UNORM16
:
245 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
246 const struct intel_mipmap_tree
*mt
)
248 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
250 if (devinfo
->gen
< 9)
253 /* For now compression is only enabled for integer formats even though
254 * there exist supported floating point formats also. This is a heuristic
255 * decision based on current public benchmarks. In none of the cases these
256 * formats provided any improvement but a few cases were seen to regress.
257 * Hence these are left to to be enabled in the future when they are known
260 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
263 if (!intel_miptree_supports_ccs(brw
, mt
))
266 /* Many window system buffers are sRGB even if they are never rendered as
267 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
268 * surface is used as sRGB, we fall back to CCS_D.
270 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
271 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
272 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
276 * Determine depth format corresponding to a depth+stencil format,
277 * for separate stencil.
280 intel_depth_format_for_depthstencil_format(mesa_format format
) {
282 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
283 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
284 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
285 return MESA_FORMAT_Z_FLOAT32
;
292 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
293 unsigned depth0
, struct intel_mipmap_level
*table
)
295 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
297 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
299 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
300 if (!table
[level
].slice
)
307 for (unsigned level
= first_level
; level
<= last_level
; level
++)
308 free(table
[level
].slice
);
314 needs_separate_stencil(const struct brw_context
*brw
,
315 struct intel_mipmap_tree
*mt
,
318 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
320 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
323 if (devinfo
->must_use_separate_stencil
)
326 return brw
->has_separate_stencil
&&
327 intel_miptree_supports_hiz(brw
, mt
);
331 * Choose the aux usage for this miptree. This function must be called fairly
332 * late in the miptree create process after we have a tiling.
335 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
336 struct intel_mipmap_tree
*mt
)
338 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
340 if (intel_miptree_supports_mcs(brw
, mt
)) {
341 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
342 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
343 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
344 intel_miptree_supports_ccs(brw
, mt
)) {
345 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
346 intel_miptree_supports_ccs_e(brw
, mt
)) {
347 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
349 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
351 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
352 intel_miptree_supports_hiz(brw
, mt
)) {
353 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
356 /* We can do fast-clear on all auxiliary surface types that are
357 * allocated through the normal texture creation paths.
359 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
360 mt
->supports_fast_clear
= true;
365 * Choose an appropriate uncompressed format for a requested
366 * compressed format, if unsupported.
369 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
371 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
373 /* No need to lower ETC formats on these platforms,
374 * they are supported natively.
376 if (devinfo
->gen
>= 8 || devinfo
->is_baytrail
)
380 case MESA_FORMAT_ETC1_RGB8
:
381 return MESA_FORMAT_R8G8B8X8_UNORM
;
382 case MESA_FORMAT_ETC2_RGB8
:
383 return MESA_FORMAT_R8G8B8X8_UNORM
;
384 case MESA_FORMAT_ETC2_SRGB8
:
385 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
386 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
387 return MESA_FORMAT_B8G8R8A8_SRGB
;
388 case MESA_FORMAT_ETC2_RGBA8_EAC
:
389 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
390 return MESA_FORMAT_R8G8B8A8_UNORM
;
391 case MESA_FORMAT_ETC2_R11_EAC
:
392 return MESA_FORMAT_R_UNORM16
;
393 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
394 return MESA_FORMAT_R_SNORM16
;
395 case MESA_FORMAT_ETC2_RG11_EAC
:
396 return MESA_FORMAT_R16G16_UNORM
;
397 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
398 return MESA_FORMAT_R16G16_SNORM
;
400 /* Non ETC1 / ETC2 format */
406 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
408 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
409 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
411 return mt
->surf
.logical_level0_px
.array_len
;
414 UNUSED
static unsigned
415 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
417 /* In case of physical dimensions one needs to consider also the layout.
418 * See isl_calc_phys_level0_extent_sa().
420 if (surf
->dim
!= ISL_SURF_DIM_3D
)
421 return surf
->phys_level0_sa
.array_len
;
423 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
424 return minify(surf
->phys_level0_sa
.array_len
, level
);
426 return minify(surf
->phys_level0_sa
.depth
, level
);
429 /** \brief Assert that the level and layer are valid for the miptree. */
431 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
439 assert(level
>= mt
->first_level
);
440 assert(level
<= mt
->last_level
);
441 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
444 static enum isl_aux_state
**
445 create_aux_state_map(struct intel_mipmap_tree
*mt
,
446 enum isl_aux_state initial
)
448 const uint32_t levels
= mt
->last_level
+ 1;
450 uint32_t total_slices
= 0;
451 for (uint32_t level
= 0; level
< levels
; level
++)
452 total_slices
+= brw_get_num_logical_layers(mt
, level
);
454 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
456 /* We're going to allocate a single chunk of data for both the per-level
457 * reference array and the arrays of aux_state. This makes cleanup
458 * significantly easier.
460 const size_t total_size
= per_level_array_size
+
461 total_slices
* sizeof(enum isl_aux_state
);
462 void *data
= malloc(total_size
);
466 enum isl_aux_state
**per_level_arr
= data
;
467 enum isl_aux_state
*s
= data
+ per_level_array_size
;
468 for (uint32_t level
= 0; level
< levels
; level
++) {
469 per_level_arr
[level
] = s
;
470 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
471 for (uint32_t a
= 0; a
< level_layers
; a
++)
474 assert((void *)s
== data
+ total_size
);
476 return per_level_arr
;
480 free_aux_state_map(enum isl_aux_state
**state
)
486 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
487 enum isl_tiling tiling
, unsigned samples
)
492 if (tiling
== ISL_TILING_LINEAR
)
495 /* If the width is much smaller than a tile, don't bother tiling. */
499 if (ALIGN(row_pitch
, 512) >= 32768) {
500 perf_debug("row pitch %u too large to blit, falling back to untiled",
509 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
510 enum isl_tiling tiling
)
512 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
514 /* If the BO is too large to fit in the aperture, we need to use the
515 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
516 * handle Y-tiling, so we need to fall back to X.
518 if (devinfo
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
519 tiling
== ISL_TILING_Y0
)
525 static struct intel_mipmap_tree
*
526 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
527 unsigned first_level
, unsigned last_level
,
528 unsigned width0
, unsigned height0
, unsigned depth0
,
529 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
530 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
531 unsigned row_pitch
, struct brw_bo
*bo
)
533 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
537 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
545 if (target
== GL_TEXTURE_CUBE_MAP
||
546 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
547 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
549 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
551 _mesa_enum_to_string(target
),
552 _mesa_get_format_name(format
),
553 num_samples
, width0
, height0
, depth0
,
554 first_level
, last_level
, mt
);
556 struct isl_surf_init_info init_info
= {
557 .dim
= get_isl_surf_dim(target
),
558 .format
= translate_tex_format(brw
, format
, false),
561 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
562 .levels
= last_level
- first_level
+ 1,
563 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
564 .samples
= num_samples
,
565 .row_pitch
= row_pitch
,
566 .usage
= isl_usage_flags
,
567 .tiling_flags
= tiling_flags
,
570 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
573 /* Depth surfaces are always Y-tiled and stencil is always W-tiled, although
574 * on gen7 platforms we also need to create Y-tiled copies of stencil for
575 * texturing since the hardware can't sample from W-tiled surfaces. For
576 * everything else, check for corner cases needing special treatment.
578 bool is_depth_stencil
=
579 mt
->surf
.usage
& (ISL_SURF_USAGE_STENCIL_BIT
| ISL_SURF_USAGE_DEPTH_BIT
);
580 if (!is_depth_stencil
) {
581 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
582 mt
->surf
.tiling
, mt
->surf
.samples
)) {
583 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
584 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
586 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
587 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
588 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
593 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
594 * the size may not be multiple of row_pitch.
595 * See isl_apply_surface_padding().
597 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
598 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
601 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
603 isl_tiling_to_i915_tiling(
605 mt
->surf
.row_pitch
, alloc_flags
);
612 mt
->first_level
= first_level
;
613 mt
->last_level
= last_level
;
616 mt
->aux_state
= NULL
;
617 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
618 mt
->compressed
= _mesa_is_format_compressed(format
);
619 mt
->drm_modifier
= DRM_FORMAT_MOD_INVALID
;
624 intel_miptree_release(&mt
);
629 make_separate_stencil_surface(struct brw_context
*brw
,
630 struct intel_mipmap_tree
*mt
)
632 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
633 0, mt
->surf
.levels
- 1,
634 mt
->surf
.logical_level0_px
.width
,
635 mt
->surf
.logical_level0_px
.height
,
636 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
637 mt
->surf
.logical_level0_px
.depth
:
638 mt
->surf
.logical_level0_px
.array_len
,
639 mt
->surf
.samples
, ISL_TILING_W_BIT
,
640 ISL_SURF_USAGE_STENCIL_BIT
|
641 ISL_SURF_USAGE_TEXTURE_BIT
,
642 BO_ALLOC_BUSY
, 0, NULL
);
647 mt
->stencil_mt
->r8stencil_needs_update
= true;
652 static struct intel_mipmap_tree
*
653 miptree_create(struct brw_context
*brw
,
662 enum intel_miptree_create_flags flags
)
664 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
666 if (format
== MESA_FORMAT_S_UINT8
)
667 return make_surface(brw
, target
, format
, first_level
, last_level
,
668 width0
, height0
, depth0
, num_samples
,
670 ISL_SURF_USAGE_STENCIL_BIT
|
671 ISL_SURF_USAGE_TEXTURE_BIT
,
676 const GLenum base_format
= _mesa_get_format_base_format(format
);
677 if ((base_format
== GL_DEPTH_COMPONENT
||
678 base_format
== GL_DEPTH_STENCIL
) &&
679 !(flags
& MIPTREE_CREATE_LINEAR
)) {
680 /* Fix up the Z miptree format for how we're splitting out separate
681 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
683 const mesa_format depth_only_format
=
684 intel_depth_format_for_depthstencil_format(format
);
685 struct intel_mipmap_tree
*mt
= make_surface(
686 brw
, target
, devinfo
->gen
>= 6 ? depth_only_format
: format
,
687 first_level
, last_level
,
688 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
689 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
690 BO_ALLOC_BUSY
, 0, NULL
);
692 if (needs_separate_stencil(brw
, mt
, format
) &&
693 !make_separate_stencil_surface(brw
, mt
)) {
694 intel_miptree_release(&mt
);
698 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
699 intel_miptree_choose_aux_usage(brw
, mt
);
704 mesa_format tex_format
= format
;
705 mesa_format etc_format
= MESA_FORMAT_NONE
;
706 uint32_t alloc_flags
= 0;
708 format
= intel_lower_compressed_format(brw
, format
);
710 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
712 if (flags
& MIPTREE_CREATE_BUSY
)
713 alloc_flags
|= BO_ALLOC_BUSY
;
715 isl_tiling_flags_t tiling_flags
= (flags
& MIPTREE_CREATE_LINEAR
) ?
716 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
718 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
719 if (devinfo
->gen
< 6)
720 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
722 struct intel_mipmap_tree
*mt
= make_surface(
724 first_level
, last_level
,
725 width0
, height0
, depth0
,
726 num_samples
, tiling_flags
,
727 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
728 ISL_SURF_USAGE_TEXTURE_BIT
,
729 alloc_flags
, 0, NULL
);
733 mt
->etc_format
= etc_format
;
735 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
736 intel_miptree_choose_aux_usage(brw
, mt
);
741 struct intel_mipmap_tree
*
742 intel_miptree_create(struct brw_context
*brw
,
751 enum intel_miptree_create_flags flags
)
753 assert(num_samples
> 0);
755 struct intel_mipmap_tree
*mt
= miptree_create(
757 first_level
, last_level
,
758 width0
, height0
, depth0
, num_samples
,
765 if (!intel_miptree_alloc_aux(brw
, mt
)) {
766 intel_miptree_release(&mt
);
773 struct intel_mipmap_tree
*
774 intel_miptree_create_for_bo(struct brw_context
*brw
,
782 enum intel_miptree_create_flags flags
)
784 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
785 struct intel_mipmap_tree
*mt
;
786 uint32_t tiling
, swizzle
;
787 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
788 const GLenum base_format
= _mesa_get_format_base_format(format
);
790 if ((base_format
== GL_DEPTH_COMPONENT
||
791 base_format
== GL_DEPTH_STENCIL
)) {
792 const mesa_format depth_only_format
=
793 intel_depth_format_for_depthstencil_format(format
);
794 mt
= make_surface(brw
, target
,
795 devinfo
->gen
>= 6 ? depth_only_format
: format
,
796 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
797 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
798 BO_ALLOC_BUSY
, pitch
, bo
);
802 brw_bo_reference(bo
);
804 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
805 intel_miptree_choose_aux_usage(brw
, mt
);
808 } else if (format
== MESA_FORMAT_S_UINT8
) {
809 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
810 0, 0, width
, height
, depth
, 1,
812 ISL_SURF_USAGE_STENCIL_BIT
|
813 ISL_SURF_USAGE_TEXTURE_BIT
,
814 BO_ALLOC_BUSY
, pitch
, bo
);
818 assert(bo
->size
>= mt
->surf
.size
);
820 brw_bo_reference(bo
);
824 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
826 /* Nothing will be able to use this miptree with the BO if the offset isn't
829 if (tiling
!= I915_TILING_NONE
)
830 assert(offset
% 4096 == 0);
832 /* miptrees can't handle negative pitch. If you need flipping of images,
833 * that's outside of the scope of the mt.
837 /* The BO already has a tiling format and we shouldn't confuse the lower
838 * layers by making it try to find a tiling format again.
840 assert((flags
& MIPTREE_CREATE_LINEAR
) == 0);
842 mt
= make_surface(brw
, target
, format
,
843 0, 0, width
, height
, depth
, 1,
844 1lu << isl_tiling_from_i915_tiling(tiling
),
845 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
846 ISL_SURF_USAGE_TEXTURE_BIT
,
851 brw_bo_reference(bo
);
855 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
856 intel_miptree_choose_aux_usage(brw
, mt
);
858 if (!intel_miptree_alloc_aux(brw
, mt
)) {
859 intel_miptree_release(&mt
);
867 static struct intel_mipmap_tree
*
868 miptree_create_for_planar_image(struct brw_context
*brw
,
869 __DRIimage
*image
, GLenum target
)
871 const struct intel_image_format
*f
= image
->planar_format
;
872 struct intel_mipmap_tree
*planar_mt
= NULL
;
874 for (int i
= 0; i
< f
->nplanes
; i
++) {
875 const int index
= f
->planes
[i
].buffer_index
;
876 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
877 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
878 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
879 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
881 /* Disable creation of the texture's aux buffers because the driver
882 * exposes no EGL API to manage them. That is, there is no API for
883 * resolving the aux buffer's content to the main buffer nor for
884 * invalidating the aux buffer's content.
886 struct intel_mipmap_tree
*mt
=
887 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
888 image
->offsets
[index
],
890 image
->strides
[index
],
891 MIPTREE_CREATE_NO_AUX
);
900 planar_mt
->plane
[i
- 1] = mt
;
903 planar_mt
->drm_modifier
= image
->modifier
;
909 create_ccs_buf_for_image(struct brw_context
*brw
,
911 struct intel_mipmap_tree
*mt
,
912 enum isl_aux_state initial_state
)
914 struct isl_surf temp_ccs_surf
;
916 /* CCS is only supported for very simple miptrees */
917 assert(image
->aux_offset
!= 0 && image
->aux_pitch
!= 0);
918 assert(image
->tile_x
== 0 && image
->tile_y
== 0);
919 assert(mt
->surf
.samples
== 1);
920 assert(mt
->surf
.levels
== 1);
921 assert(mt
->surf
.logical_level0_px
.depth
== 1);
922 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
923 assert(mt
->first_level
== 0);
924 assert(mt
->last_level
== 0);
926 /* We shouldn't already have a CCS */
927 assert(!mt
->mcs_buf
);
929 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
,
933 assert(image
->aux_offset
< image
->bo
->size
);
934 assert(temp_ccs_surf
.size
<= image
->bo
->size
- image
->aux_offset
);
936 mt
->mcs_buf
= calloc(sizeof(*mt
->mcs_buf
), 1);
937 if (mt
->mcs_buf
== NULL
)
940 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
941 if (!mt
->aux_state
) {
947 mt
->mcs_buf
->bo
= image
->bo
;
948 brw_bo_reference(image
->bo
);
950 mt
->mcs_buf
->offset
= image
->aux_offset
;
951 mt
->mcs_buf
->size
= image
->bo
->size
- image
->aux_offset
;
952 mt
->mcs_buf
->pitch
= image
->aux_pitch
;
953 mt
->mcs_buf
->qpitch
= 0;
954 mt
->mcs_buf
->surf
= temp_ccs_surf
;
959 struct intel_mipmap_tree
*
960 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
961 __DRIimage
*image
, GLenum target
,
962 enum isl_colorspace colorspace
,
963 bool is_winsys_image
)
965 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1) {
966 assert(colorspace
== ISL_COLORSPACE_NONE
||
967 colorspace
== ISL_COLORSPACE_YUV
);
968 return miptree_create_for_planar_image(brw
, image
, target
);
971 if (image
->planar_format
)
972 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
974 mesa_format format
= image
->format
;
975 switch (colorspace
) {
976 case ISL_COLORSPACE_NONE
:
977 /* Keep the image format unmodified */
980 case ISL_COLORSPACE_LINEAR
:
981 format
=_mesa_get_srgb_format_linear(format
);
984 case ISL_COLORSPACE_SRGB
:
985 format
=_mesa_get_linear_format_srgb(format
);
989 unreachable("Inalid colorspace for non-planar image");
992 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
993 /* The texture storage paths in core Mesa detect if the driver does not
994 * support the user-requested format, and then searches for a
995 * fallback format. The DRIimage code bypasses core Mesa, though. So we
996 * do the fallbacks here for important formats.
998 * We must support DRM_FOURCC_XBGR8888 textures because the Android
999 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1000 * the Chrome OS compositor consumes as dma_buf EGLImages.
1002 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1005 if (!brw
->ctx
.TextureFormatSupported
[format
])
1008 const struct isl_drm_modifier_info
*mod_info
=
1009 isl_drm_modifier_get_info(image
->modifier
);
1011 enum intel_miptree_create_flags mt_create_flags
= 0;
1013 /* If this image comes in from a window system, we have different
1014 * requirements than if it comes in via an EGL import operation. Window
1015 * system images can use any form of auxiliary compression we wish because
1016 * they get "flushed" before being handed off to the window system and we
1017 * have the opportunity to do resolves. Non window-system images, on the
1018 * other hand, have no resolve point so we can't have aux without a
1021 if (!is_winsys_image
)
1022 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1024 /* If we have a modifier which specifies aux, don't create one yet */
1025 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
1026 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1028 /* Disable creation of the texture's aux buffers because the driver exposes
1029 * no EGL API to manage them. That is, there is no API for resolving the aux
1030 * buffer's content to the main buffer nor for invalidating the aux buffer's
1033 struct intel_mipmap_tree
*mt
=
1034 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1035 image
->offset
, image
->width
, image
->height
, 1,
1036 image
->pitch
, mt_create_flags
);
1040 mt
->target
= target
;
1041 mt
->level
[0].level_x
= image
->tile_x
;
1042 mt
->level
[0].level_y
= image
->tile_y
;
1043 mt
->drm_modifier
= image
->modifier
;
1045 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1046 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1047 * trouble resolving back to destination image due to alignment issues.
1049 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1050 if (!devinfo
->has_surface_tile_offset
) {
1051 uint32_t draw_x
, draw_y
;
1052 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1054 if (draw_x
!= 0 || draw_y
!= 0) {
1055 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1056 intel_miptree_release(&mt
);
1061 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1062 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1064 mt
->aux_usage
= mod_info
->aux_usage
;
1065 /* If we are a window system buffer, then we can support fast-clears
1066 * even if the modifier doesn't support them by doing a partial resolve
1067 * as part of the flush operation.
1069 mt
->supports_fast_clear
=
1070 is_winsys_image
|| mod_info
->supports_clear_color
;
1072 /* We don't know the actual state of the surface when we get it but we
1073 * can make a pretty good guess based on the modifier. What we do know
1074 * for sure is that it isn't in the AUX_INVALID state, so we just assume
1075 * a worst case of compression.
1077 enum isl_aux_state initial_state
=
1078 mod_info
->supports_clear_color
? ISL_AUX_STATE_COMPRESSED_CLEAR
:
1079 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
;
1081 if (!create_ccs_buf_for_image(brw
, image
, mt
, initial_state
)) {
1082 intel_miptree_release(&mt
);
1087 /* Don't assume coherency for imported EGLimages. We don't know what
1088 * external clients are going to do with it. They may scan it out.
1090 image
->bo
->cache_coherent
= false;
1096 * For a singlesample renderbuffer, this simply wraps the given BO with a
1099 * For a multisample renderbuffer, this wraps the window system's
1100 * (singlesample) BO with a singlesample miptree attached to the
1101 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1102 * that will contain the actual rendering (which is lazily resolved to
1103 * irb->singlesample_mt).
1106 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1107 struct intel_renderbuffer
*irb
,
1108 struct intel_mipmap_tree
*singlesample_mt
,
1109 uint32_t width
, uint32_t height
,
1112 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1113 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1114 mesa_format format
= rb
->Format
;
1115 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1117 /* Only the front and back buffers, which are color buffers, are allocated
1118 * through the image loader.
1120 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1121 _mesa_get_format_base_format(format
) == GL_RGBA
);
1123 assert(singlesample_mt
);
1125 if (num_samples
== 1) {
1126 intel_miptree_release(&irb
->mt
);
1127 irb
->mt
= singlesample_mt
;
1129 assert(!irb
->singlesample_mt
);
1131 intel_miptree_release(&irb
->singlesample_mt
);
1132 irb
->singlesample_mt
= singlesample_mt
;
1135 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1136 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1137 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1142 if (!multisample_mt
)
1145 irb
->need_downsample
= false;
1146 intel_miptree_release(&irb
->mt
);
1147 irb
->mt
= multisample_mt
;
1153 intel_miptree_release(&irb
->mt
);
1157 struct intel_mipmap_tree
*
1158 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1162 uint32_t num_samples
)
1164 struct intel_mipmap_tree
*mt
;
1166 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1168 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1169 width
, height
, depth
, num_samples
,
1170 MIPTREE_CREATE_BUSY
);
1177 intel_miptree_release(&mt
);
1182 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1183 struct intel_mipmap_tree
*src
)
1188 intel_miptree_release(dst
);
1192 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1199 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1201 if (aux_buf
== NULL
)
1204 brw_bo_unreference(aux_buf
->bo
);
1210 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1215 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1216 if (--(*mt
)->refcount
<= 0) {
1219 DBG("%s deleting %p\n", __func__
, *mt
);
1221 brw_bo_unreference((*mt
)->bo
);
1222 intel_miptree_release(&(*mt
)->stencil_mt
);
1223 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1224 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1225 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1226 free_aux_state_map((*mt
)->aux_state
);
1228 intel_miptree_release(&(*mt
)->plane
[0]);
1229 intel_miptree_release(&(*mt
)->plane
[1]);
1231 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1232 free((*mt
)->level
[i
].slice
);
1242 intel_get_image_dims(struct gl_texture_image
*image
,
1243 int *width
, int *height
, int *depth
)
1245 switch (image
->TexObject
->Target
) {
1246 case GL_TEXTURE_1D_ARRAY
:
1247 /* For a 1D Array texture the OpenGL API will treat the image height as
1248 * the number of array slices. For Intel hardware, we treat the 1D array
1249 * as a 2D Array with a height of 1. So, here we want to swap image
1252 assert(image
->Depth
== 1);
1253 *width
= image
->Width
;
1255 *depth
= image
->Height
;
1257 case GL_TEXTURE_CUBE_MAP
:
1258 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1259 * though we really have 6 slices.
1261 assert(image
->Depth
== 1);
1262 *width
= image
->Width
;
1263 *height
= image
->Height
;
1267 *width
= image
->Width
;
1268 *height
= image
->Height
;
1269 *depth
= image
->Depth
;
1275 * Can the image be pulled into a unified mipmap tree? This mirrors
1276 * the completeness test in a lot of ways.
1278 * Not sure whether I want to pass gl_texture_image here.
1281 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1282 struct gl_texture_image
*image
)
1284 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1285 GLuint level
= intelImage
->base
.Base
.Level
;
1286 int width
, height
, depth
;
1288 /* glTexImage* choose the texture object based on the target passed in, and
1289 * objects can't change targets over their lifetimes, so this should be
1292 assert(image
->TexObject
->Target
== mt
->target
);
1294 mesa_format mt_format
= mt
->format
;
1295 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1296 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1297 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1298 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1299 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1300 mt_format
= mt
->etc_format
;
1302 if (image
->TexFormat
!= mt_format
)
1305 intel_get_image_dims(image
, &width
, &height
, &depth
);
1307 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1310 if (level
>= mt
->surf
.levels
)
1313 const unsigned level_depth
=
1314 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1315 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1316 mt
->surf
.logical_level0_px
.array_len
;
1318 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1319 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1320 depth
== level_depth
&&
1321 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1325 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1326 GLuint level
, GLuint slice
,
1327 GLuint
*x
, GLuint
*y
)
1329 if (level
== 0 && slice
== 0) {
1330 *x
= mt
->level
[0].level_x
;
1331 *y
= mt
->level
[0].level_y
;
1335 uint32_t x_offset_sa
, y_offset_sa
;
1337 /* Miptree itself can have an offset only if it represents a single
1338 * slice in an imported buffer object.
1339 * See intel_miptree_create_for_dri_image().
1341 assert(mt
->level
[0].level_x
== 0);
1342 assert(mt
->level
[0].level_y
== 0);
1344 /* Given level is relative to level zero while the miptree may be
1345 * represent just a subset of all levels starting from 'first_level'.
1347 assert(level
>= mt
->first_level
);
1348 level
-= mt
->first_level
;
1350 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1351 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1352 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1353 &x_offset_sa
, &y_offset_sa
);
1361 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1362 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1363 * and tile_h is set to 1.
1366 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1367 uint32_t *tile_w
, uint32_t *tile_h
)
1378 case ISL_TILING_LINEAR
:
1383 unreachable("not reached");
1389 * This function computes masks that may be used to select the bits of the X
1390 * and Y coordinates that indicate the offset within a tile. If the BO is
1391 * untiled, the masks are set to 0.
1394 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1395 uint32_t *mask_x
, uint32_t *mask_y
)
1397 uint32_t tile_w_bytes
, tile_h
;
1399 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1401 *mask_x
= tile_w_bytes
/ cpp
- 1;
1402 *mask_y
= tile_h
- 1;
1406 * Compute the offset (in bytes) from the start of the BO to the given x
1407 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1408 * multiples of the tile size.
1411 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1412 uint32_t x
, uint32_t y
)
1415 uint32_t pitch
= mt
->surf
.row_pitch
;
1417 switch (mt
->surf
.tiling
) {
1419 unreachable("not reached");
1420 case ISL_TILING_LINEAR
:
1421 return y
* pitch
+ x
* cpp
;
1423 assert((x
% (512 / cpp
)) == 0);
1424 assert((y
% 8) == 0);
1425 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1427 assert((x
% (128 / cpp
)) == 0);
1428 assert((y
% 32) == 0);
1429 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1434 * Rendering with tiled buffers requires that the base address of the buffer
1435 * be aligned to a page boundary. For renderbuffers, and sometimes with
1436 * textures, we may want the surface to point at a texture image level that
1437 * isn't at a page boundary.
1439 * This function returns an appropriately-aligned base offset
1440 * according to the tiling restrictions, plus any required x/y offset
1444 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1445 GLuint level
, GLuint slice
,
1450 uint32_t mask_x
, mask_y
;
1452 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1453 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1455 *tile_x
= x
& mask_x
;
1456 *tile_y
= y
& mask_y
;
1458 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1462 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1463 struct intel_mipmap_tree
*src_mt
,
1464 unsigned src_level
, unsigned src_layer
,
1465 struct intel_mipmap_tree
*dst_mt
,
1466 unsigned dst_level
, unsigned dst_layer
,
1467 unsigned width
, unsigned height
)
1470 ptrdiff_t src_stride
, dst_stride
;
1471 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1473 intel_miptree_map(brw
, src_mt
,
1474 src_level
, src_layer
,
1477 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1480 intel_miptree_map(brw
, dst_mt
,
1481 dst_level
, dst_layer
,
1484 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1488 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1489 _mesa_get_format_name(src_mt
->format
),
1490 src_mt
, src
, src_stride
,
1491 _mesa_get_format_name(dst_mt
->format
),
1492 dst_mt
, dst
, dst_stride
,
1495 int row_size
= cpp
* width
;
1496 if (src_stride
== row_size
&&
1497 dst_stride
== row_size
) {
1498 memcpy(dst
, src
, row_size
* height
);
1500 for (int i
= 0; i
< height
; i
++) {
1501 memcpy(dst
, src
, row_size
);
1507 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1508 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1510 /* Don't forget to copy the stencil data over, too. We could have skipped
1511 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1512 * shuffling the two data sources in/out of temporary storage instead of
1513 * the direct mapping we get this way.
1515 if (dst_mt
->stencil_mt
) {
1516 assert(src_mt
->stencil_mt
);
1517 intel_miptree_copy_slice_sw(brw
,
1518 src_mt
->stencil_mt
, src_level
, src_layer
,
1519 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1525 intel_miptree_copy_slice(struct brw_context
*brw
,
1526 struct intel_mipmap_tree
*src_mt
,
1527 unsigned src_level
, unsigned src_layer
,
1528 struct intel_mipmap_tree
*dst_mt
,
1529 unsigned dst_level
, unsigned dst_layer
)
1532 mesa_format format
= src_mt
->format
;
1533 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1534 src_level
- src_mt
->first_level
);
1535 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1536 src_level
- src_mt
->first_level
);
1538 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1539 src_level
- src_mt
->first_level
));
1541 assert(src_mt
->format
== dst_mt
->format
);
1543 if (dst_mt
->compressed
) {
1545 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1546 height
= ALIGN_NPOT(height
, j
) / j
;
1547 width
= ALIGN_NPOT(width
, i
) / i
;
1550 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1551 * below won't apply since we can't do the depth's Y tiling or the
1552 * stencil's W tiling in the blitter.
1554 if (src_mt
->stencil_mt
) {
1555 intel_miptree_copy_slice_sw(brw
,
1556 src_mt
, src_level
, src_layer
,
1557 dst_mt
, dst_level
, dst_layer
,
1562 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1563 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1565 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1568 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1569 _mesa_get_format_name(src_mt
->format
),
1570 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1571 _mesa_get_format_name(dst_mt
->format
),
1572 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1575 if (!intel_miptree_blit(brw
,
1576 src_mt
, src_level
, src_layer
, 0, 0, false,
1577 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1578 width
, height
, GL_COPY
)) {
1579 perf_debug("miptree validate blit for %s failed\n",
1580 _mesa_get_format_name(format
));
1582 intel_miptree_copy_slice_sw(brw
,
1583 src_mt
, src_level
, src_layer
,
1584 dst_mt
, dst_level
, dst_layer
,
1590 * Copies the image's current data to the given miptree, and associates that
1591 * miptree with the image.
1593 * If \c invalidate is true, then the actual image data does not need to be
1594 * copied, but the image still needs to be associated to the new miptree (this
1595 * is set to true if we're about to clear the image).
1598 intel_miptree_copy_teximage(struct brw_context
*brw
,
1599 struct intel_texture_image
*intelImage
,
1600 struct intel_mipmap_tree
*dst_mt
,
1603 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1604 struct intel_texture_object
*intel_obj
=
1605 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1606 int level
= intelImage
->base
.Base
.Level
;
1607 const unsigned face
= intelImage
->base
.Base
.Face
;
1608 unsigned start_layer
, end_layer
;
1610 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1612 assert(intelImage
->base
.Base
.Height
);
1614 end_layer
= intelImage
->base
.Base
.Height
- 1;
1615 } else if (face
> 0) {
1619 assert(intelImage
->base
.Base
.Depth
);
1621 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1625 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1626 intel_miptree_copy_slice(brw
,
1632 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1633 intel_obj
->needs_validate
= true;
1637 intel_miptree_init_mcs(struct brw_context
*brw
,
1638 struct intel_mipmap_tree
*mt
,
1641 assert(mt
->mcs_buf
!= NULL
);
1643 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1645 * When MCS buffer is enabled and bound to MSRT, it is required that it
1646 * is cleared prior to any rendering.
1648 * Since we don't use the MCS buffer for any purpose other than rendering,
1649 * it makes sense to just clear it immediately upon allocation.
1651 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1653 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1654 if (unlikely(map
== NULL
)) {
1655 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1656 brw_bo_unreference(mt
->mcs_buf
->bo
);
1661 memset(data
, init_value
, mt
->mcs_buf
->size
);
1662 brw_bo_unmap(mt
->mcs_buf
->bo
);
1665 static struct intel_miptree_aux_buffer
*
1666 intel_alloc_aux_buffer(struct brw_context
*brw
,
1668 const struct isl_surf
*aux_surf
,
1669 uint32_t alloc_flags
,
1670 struct intel_mipmap_tree
*mt
)
1672 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1676 buf
->size
= aux_surf
->size
;
1677 buf
->pitch
= aux_surf
->row_pitch
;
1678 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1680 /* ISL has stricter set of alignment rules then the drm allocator.
1681 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1682 * trying to recalculate based on different format block sizes.
1684 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1685 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1691 buf
->surf
= *aux_surf
;
1697 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1698 struct intel_mipmap_tree
*mt
,
1701 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1703 assert(devinfo
->gen
>= 7); /* MCS only used on Gen7+ */
1704 assert(mt
->mcs_buf
== NULL
);
1705 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1707 /* Multisampled miptrees are only supported for single level. */
1708 assert(mt
->first_level
== 0);
1709 enum isl_aux_state
**aux_state
=
1710 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1714 struct isl_surf temp_mcs_surf
;
1716 MAYBE_UNUSED
bool ok
=
1717 isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_mcs_surf
);
1720 /* Buffer needs to be initialised requiring the buffer to be immediately
1721 * mapped to cpu space for writing. Therefore do not use the gpu access
1722 * flag which can cause an unnecessary delay if the backing pages happened
1723 * to be just used by the GPU.
1725 const uint32_t alloc_flags
= 0;
1726 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1727 &temp_mcs_surf
, alloc_flags
, mt
);
1733 mt
->aux_state
= aux_state
;
1735 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1741 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1742 struct intel_mipmap_tree
*mt
)
1744 assert(mt
->mcs_buf
== NULL
);
1745 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1746 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1748 struct isl_surf temp_ccs_surf
;
1750 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
, 0))
1753 assert(temp_ccs_surf
.size
&&
1754 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1756 enum isl_aux_state
**aux_state
=
1757 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1761 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1762 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1764 * "If Software wants to enable Color Compression without Fast clear,
1765 * Software needs to initialize MCS with zeros."
1767 * A CCS value of 0 indicates that the corresponding block is in the
1768 * pass-through state which is what we want.
1770 * For CCS_D, on the other hand, we don't care as we're about to perform a
1771 * fast-clear operation. In that case, being hot in caches more useful.
1773 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1774 BO_ALLOC_ZEROED
: BO_ALLOC_BUSY
;
1775 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1776 &temp_ccs_surf
, alloc_flags
, mt
);
1782 mt
->aux_state
= aux_state
;
1788 * Helper for intel_miptree_alloc_hiz() that sets
1789 * \c mt->level[level].has_hiz. Return true if and only if
1790 * \c has_hiz was set.
1793 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1794 struct intel_mipmap_tree
*mt
,
1797 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1799 assert(mt
->hiz_buf
);
1800 assert(mt
->surf
.size
> 0);
1802 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
1803 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1804 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1806 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1807 * and the height is 4 aligned. This allows our HiZ support
1808 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1809 * we can grow the width & height to allow the HiZ op to
1810 * force the proper size alignments.
1812 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1813 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1818 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1819 mt
->level
[level
].has_hiz
= true;
1824 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1825 struct intel_mipmap_tree
*mt
)
1827 assert(mt
->hiz_buf
== NULL
);
1828 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1830 enum isl_aux_state
**aux_state
=
1831 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1835 struct isl_surf temp_hiz_surf
;
1837 MAYBE_UNUSED
bool ok
=
1838 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
1841 const uint32_t alloc_flags
= BO_ALLOC_BUSY
;
1842 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1843 &temp_hiz_surf
, alloc_flags
, mt
);
1850 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1851 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1853 mt
->aux_state
= aux_state
;
1860 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1862 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1863 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1864 * compress clear color so we wait until an actual fast-clear to allocate it.
1867 intel_miptree_alloc_aux(struct brw_context
*brw
,
1868 struct intel_mipmap_tree
*mt
)
1870 switch (mt
->aux_usage
) {
1871 case ISL_AUX_USAGE_NONE
:
1874 case ISL_AUX_USAGE_HIZ
:
1875 assert(!_mesa_is_format_color_format(mt
->format
));
1876 if (!intel_miptree_alloc_hiz(brw
, mt
))
1880 case ISL_AUX_USAGE_MCS
:
1881 assert(_mesa_is_format_color_format(mt
->format
));
1882 assert(mt
->surf
.samples
> 1);
1883 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
1887 case ISL_AUX_USAGE_CCS_D
:
1888 /* Since CCS_D can only compress clear color so we wait until an actual
1889 * fast-clear to allocate it.
1893 case ISL_AUX_USAGE_CCS_E
:
1894 assert(_mesa_is_format_color_format(mt
->format
));
1895 assert(mt
->surf
.samples
== 1);
1896 if (!intel_miptree_alloc_ccs(brw
, mt
))
1901 unreachable("Invalid aux usage");
1906 * Can the miptree sample using the hiz buffer?
1909 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1910 struct intel_mipmap_tree
*mt
)
1912 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1914 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1915 * so keep things conservative for now and never enable it unless we're SKL+.
1917 if (devinfo
->gen
< 9) {
1925 /* It seems the hardware won't fallback to the depth buffer if some of the
1926 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1927 * of the texture to be HiZ enabled.
1929 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1930 if (!intel_miptree_level_has_hiz(mt
, level
))
1934 /* If compressed multisampling is enabled, then we use it for the auxiliary
1937 * From the BDW PRM (Volume 2d: Command Reference: Structures
1938 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1940 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1941 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1943 * There is no such blurb for 1D textures, but there is sufficient evidence
1944 * that this is broken on SKL+.
1946 return (mt
->surf
.samples
== 1 &&
1947 mt
->target
!= GL_TEXTURE_3D
&&
1948 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1952 * Does the miptree slice have hiz enabled?
1955 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1957 intel_miptree_check_level_layer(mt
, level
, 0);
1958 return mt
->level
[level
].has_hiz
;
1961 static inline uint32_t
1962 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1963 uint32_t start_level
, uint32_t num_levels
)
1965 assert(start_level
>= mt
->first_level
);
1966 assert(start_level
<= mt
->last_level
);
1968 if (num_levels
== INTEL_REMAINING_LAYERS
)
1969 num_levels
= mt
->last_level
- start_level
+ 1;
1970 /* Check for overflow */
1971 assert(start_level
+ num_levels
>= start_level
);
1972 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
1977 static inline uint32_t
1978 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
1979 uint32_t start_layer
, uint32_t num_layers
)
1981 assert(level
<= mt
->last_level
);
1983 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
1984 assert(start_layer
< total_num_layers
);
1985 if (num_layers
== INTEL_REMAINING_LAYERS
)
1986 num_layers
= total_num_layers
- start_layer
;
1987 /* Check for overflow */
1988 assert(start_layer
+ num_layers
>= start_layer
);
1989 assert(start_layer
+ num_layers
<= total_num_layers
);
1995 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1996 unsigned start_level
, unsigned num_levels
,
1997 unsigned start_layer
, unsigned num_layers
)
1999 assert(_mesa_is_format_color_format(mt
->format
));
2004 /* Clamp the level range to fit the miptree */
2005 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2007 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2008 const uint32_t level
= start_level
+ l
;
2009 const uint32_t level_layers
=
2010 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2011 for (unsigned a
= 0; a
< level_layers
; a
++) {
2012 enum isl_aux_state aux_state
=
2013 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2014 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2015 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2024 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2025 const struct intel_mipmap_tree
*mt
,
2026 unsigned level
, unsigned layer
)
2028 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2033 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2034 assert(devinfo
->gen
>= 8 ||
2035 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2037 /* Compression of arrayed msaa surfaces is supported. */
2038 if (mt
->surf
.samples
> 1)
2041 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2042 assert(devinfo
->gen
>= 8 ||
2044 mt
->surf
.logical_level0_px
.depth
== 1 &&
2045 mt
->surf
.logical_level0_px
.array_len
== 1));
2051 static enum blorp_fast_clear_op
2052 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2053 enum isl_aux_usage aux_usage
,
2054 bool fast_clear_supported
)
2056 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
2058 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
2060 assert(ccs_supported
== fast_clear_supported
);
2062 switch (aux_state
) {
2063 case ISL_AUX_STATE_CLEAR
:
2064 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2066 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2068 return BLORP_FAST_CLEAR_OP_NONE
;
2070 case ISL_AUX_STATE_PASS_THROUGH
:
2071 return BLORP_FAST_CLEAR_OP_NONE
;
2073 case ISL_AUX_STATE_RESOLVED
:
2074 case ISL_AUX_STATE_AUX_INVALID
:
2075 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2076 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2080 unreachable("Invalid aux state for CCS_D");
2083 static enum blorp_fast_clear_op
2084 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2085 enum isl_aux_usage aux_usage
,
2086 bool fast_clear_supported
)
2088 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
2089 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2090 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2091 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2093 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
2094 assert(fast_clear_supported
);
2096 switch (aux_state
) {
2097 case ISL_AUX_STATE_CLEAR
:
2098 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2099 if (fast_clear_supported
)
2100 return BLORP_FAST_CLEAR_OP_NONE
;
2101 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
2102 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2104 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2106 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2107 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2108 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2109 else if (!fast_clear_supported
)
2110 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2112 return BLORP_FAST_CLEAR_OP_NONE
;
2114 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2115 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2116 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2118 return BLORP_FAST_CLEAR_OP_NONE
;
2120 case ISL_AUX_STATE_PASS_THROUGH
:
2121 return BLORP_FAST_CLEAR_OP_NONE
;
2123 case ISL_AUX_STATE_RESOLVED
:
2124 case ISL_AUX_STATE_AUX_INVALID
:
2128 unreachable("Invalid aux state for CCS_E");
2132 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2133 struct intel_mipmap_tree
*mt
,
2134 uint32_t level
, uint32_t layer
,
2135 enum isl_aux_usage aux_usage
,
2136 bool fast_clear_supported
)
2138 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2140 enum blorp_fast_clear_op resolve_op
;
2141 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2142 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2143 fast_clear_supported
);
2145 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2146 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2147 fast_clear_supported
);
2150 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2151 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2152 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2154 switch (resolve_op
) {
2155 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2156 /* The CCS full resolve operation destroys the CCS and sets it to the
2157 * pass-through state. (You can also think of this as being both a
2158 * resolve and an ambiguate in one operation.)
2160 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2161 ISL_AUX_STATE_PASS_THROUGH
);
2164 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2165 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2166 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2170 unreachable("Invalid resolve op");
2176 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2177 struct intel_mipmap_tree
*mt
,
2178 uint32_t level
, uint32_t layer
,
2179 enum isl_aux_usage aux_usage
)
2181 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2182 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2183 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2185 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2187 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2188 switch (aux_state
) {
2189 case ISL_AUX_STATE_CLEAR
:
2190 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2191 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2192 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2194 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2195 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2196 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2197 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2198 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2199 ISL_AUX_STATE_PARTIAL_CLEAR
);
2203 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2204 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2205 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2206 break; /* Nothing to do */
2208 case ISL_AUX_STATE_PASS_THROUGH
:
2209 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2210 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2211 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2217 case ISL_AUX_STATE_RESOLVED
:
2218 case ISL_AUX_STATE_AUX_INVALID
:
2219 unreachable("Invalid aux state for CCS_E");
2222 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2223 /* CCS_D is a bit simpler */
2224 switch (aux_state
) {
2225 case ISL_AUX_STATE_CLEAR
:
2226 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2227 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2228 ISL_AUX_STATE_PARTIAL_CLEAR
);
2231 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2232 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2233 break; /* Nothing to do */
2235 case ISL_AUX_STATE_PASS_THROUGH
:
2239 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2240 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2241 case ISL_AUX_STATE_RESOLVED
:
2242 case ISL_AUX_STATE_AUX_INVALID
:
2243 unreachable("Invalid aux state for CCS_D");
2249 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2250 struct intel_mipmap_tree
*mt
,
2252 enum isl_aux_usage aux_usage
,
2253 bool fast_clear_supported
)
2255 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2257 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2258 case ISL_AUX_STATE_CLEAR
:
2259 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2260 if (!fast_clear_supported
) {
2261 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2262 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2263 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2267 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2268 break; /* Nothing to do */
2270 case ISL_AUX_STATE_RESOLVED
:
2271 case ISL_AUX_STATE_PASS_THROUGH
:
2272 case ISL_AUX_STATE_AUX_INVALID
:
2273 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2274 unreachable("Invalid aux state for MCS");
2279 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2280 struct intel_mipmap_tree
*mt
,
2282 enum isl_aux_usage aux_usage
)
2284 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2286 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2287 case ISL_AUX_STATE_CLEAR
:
2288 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2289 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2292 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2293 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2294 break; /* Nothing to do */
2296 case ISL_AUX_STATE_RESOLVED
:
2297 case ISL_AUX_STATE_PASS_THROUGH
:
2298 case ISL_AUX_STATE_AUX_INVALID
:
2299 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2300 unreachable("Invalid aux state for MCS");
2305 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2306 struct intel_mipmap_tree
*mt
,
2307 uint32_t level
, uint32_t layer
,
2308 enum isl_aux_usage aux_usage
,
2309 bool fast_clear_supported
)
2311 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2313 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2314 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2315 case ISL_AUX_STATE_CLEAR
:
2316 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2317 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2318 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2321 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2322 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2323 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2326 case ISL_AUX_STATE_PASS_THROUGH
:
2327 case ISL_AUX_STATE_RESOLVED
:
2330 case ISL_AUX_STATE_AUX_INVALID
:
2331 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2332 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2335 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2336 unreachable("Invalid HiZ state");
2339 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2340 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2343 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2344 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2345 ISL_AUX_STATE_RESOLVED
);
2348 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2349 /* The HiZ resolve operation is actually an ambiguate */
2350 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2351 ISL_AUX_STATE_PASS_THROUGH
);
2355 unreachable("Invalid HiZ op");
2361 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2362 struct intel_mipmap_tree
*mt
,
2363 uint32_t level
, uint32_t layer
,
2364 enum isl_aux_usage aux_usage
)
2366 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2368 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2369 case ISL_AUX_STATE_CLEAR
:
2370 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2371 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2372 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2375 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2376 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2377 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2378 break; /* Nothing to do */
2380 case ISL_AUX_STATE_RESOLVED
:
2381 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2382 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2383 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2385 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2386 ISL_AUX_STATE_AUX_INVALID
);
2390 case ISL_AUX_STATE_PASS_THROUGH
:
2391 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2392 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2393 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2397 case ISL_AUX_STATE_AUX_INVALID
:
2398 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2401 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2402 unreachable("Invalid HiZ state");
2407 intel_miptree_prepare_access(struct brw_context
*brw
,
2408 struct intel_mipmap_tree
*mt
,
2409 uint32_t start_level
, uint32_t num_levels
,
2410 uint32_t start_layer
, uint32_t num_layers
,
2411 enum isl_aux_usage aux_usage
,
2412 bool fast_clear_supported
)
2414 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2416 switch (mt
->aux_usage
) {
2417 case ISL_AUX_USAGE_NONE
:
2421 case ISL_AUX_USAGE_MCS
:
2422 assert(mt
->mcs_buf
);
2423 assert(start_level
== 0 && num_levels
== 1);
2424 const uint32_t level_layers
=
2425 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2426 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2427 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2428 aux_usage
, fast_clear_supported
);
2432 case ISL_AUX_USAGE_CCS_D
:
2433 case ISL_AUX_USAGE_CCS_E
:
2437 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2438 const uint32_t level
= start_level
+ l
;
2439 const uint32_t level_layers
=
2440 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2441 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2442 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2444 aux_usage
, fast_clear_supported
);
2449 case ISL_AUX_USAGE_HIZ
:
2450 assert(mt
->hiz_buf
);
2451 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2452 const uint32_t level
= start_level
+ l
;
2453 if (!intel_miptree_level_has_hiz(mt
, level
))
2456 const uint32_t level_layers
=
2457 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2458 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2459 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2460 aux_usage
, fast_clear_supported
);
2466 unreachable("Invalid aux usage");
2471 intel_miptree_finish_write(struct brw_context
*brw
,
2472 struct intel_mipmap_tree
*mt
, uint32_t level
,
2473 uint32_t start_layer
, uint32_t num_layers
,
2474 enum isl_aux_usage aux_usage
)
2476 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2478 switch (mt
->aux_usage
) {
2479 case ISL_AUX_USAGE_NONE
:
2483 case ISL_AUX_USAGE_MCS
:
2484 assert(mt
->mcs_buf
);
2485 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2486 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2491 case ISL_AUX_USAGE_CCS_D
:
2492 case ISL_AUX_USAGE_CCS_E
:
2496 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2497 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2502 case ISL_AUX_USAGE_HIZ
:
2503 if (!intel_miptree_level_has_hiz(mt
, level
))
2506 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2507 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2513 unreachable("Invavlid aux usage");
2518 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2519 uint32_t level
, uint32_t layer
)
2521 intel_miptree_check_level_layer(mt
, level
, layer
);
2523 if (_mesa_is_format_color_format(mt
->format
)) {
2524 assert(mt
->mcs_buf
!= NULL
);
2525 assert(mt
->surf
.samples
== 1 ||
2526 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2527 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2528 unreachable("Cannot get aux state for stencil");
2530 assert(intel_miptree_level_has_hiz(mt
, level
));
2533 return mt
->aux_state
[level
][layer
];
2537 intel_miptree_set_aux_state(struct brw_context
*brw
,
2538 struct intel_mipmap_tree
*mt
, uint32_t level
,
2539 uint32_t start_layer
, uint32_t num_layers
,
2540 enum isl_aux_state aux_state
)
2542 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2544 if (_mesa_is_format_color_format(mt
->format
)) {
2545 assert(mt
->mcs_buf
!= NULL
);
2546 assert(mt
->surf
.samples
== 1 ||
2547 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2548 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2549 unreachable("Cannot get aux state for stencil");
2551 assert(intel_miptree_level_has_hiz(mt
, level
));
2554 for (unsigned a
= 0; a
< num_layers
; a
++)
2555 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2558 /* On Gen9 color buffers may be compressed by the hardware (lossless
2559 * compression). There are, however, format restrictions and care needs to be
2560 * taken that the sampler engine is capable for re-interpreting a buffer with
2561 * format different the buffer was originally written with.
2563 * For example, SRGB formats are not compressible and the sampler engine isn't
2564 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2565 * color buffer needs to be resolved so that the sampling surface can be
2566 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2570 can_texture_with_ccs(struct brw_context
*brw
,
2571 struct intel_mipmap_tree
*mt
,
2572 enum isl_format view_format
)
2574 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2577 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2578 mt
->surf
.format
, view_format
)) {
2579 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2580 isl_format_get_layout(view_format
)->name
,
2581 _mesa_get_format_name(mt
->format
));
2589 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2590 struct intel_mipmap_tree
*mt
,
2591 enum isl_format view_format
)
2593 switch (mt
->aux_usage
) {
2594 case ISL_AUX_USAGE_HIZ
:
2595 if (intel_miptree_sample_with_hiz(brw
, mt
))
2596 return ISL_AUX_USAGE_HIZ
;
2599 case ISL_AUX_USAGE_MCS
:
2600 return ISL_AUX_USAGE_MCS
;
2602 case ISL_AUX_USAGE_CCS_D
:
2603 case ISL_AUX_USAGE_CCS_E
:
2605 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2606 return ISL_AUX_USAGE_NONE
;
2609 /* If we don't have any unresolved color, report an aux usage of
2610 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
2611 * aux surface and we can save some bandwidth.
2613 if (!intel_miptree_has_color_unresolved(mt
, 0, INTEL_REMAINING_LEVELS
,
2614 0, INTEL_REMAINING_LAYERS
))
2615 return ISL_AUX_USAGE_NONE
;
2617 if (can_texture_with_ccs(brw
, mt
, view_format
))
2618 return ISL_AUX_USAGE_CCS_E
;
2625 return ISL_AUX_USAGE_NONE
;
2629 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2631 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2632 * values so sRGB curve application was a no-op for all fast-clearable
2635 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2636 * values, the hardware interprets the floats, not as what would be
2637 * returned from the sampler (or written by the shader), but as being
2638 * between format conversion and sRGB curve application. This means that
2639 * we can switch between sRGB and UNORM without having to whack the clear
2642 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2646 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2647 struct intel_mipmap_tree
*mt
,
2648 enum isl_format view_format
,
2649 uint32_t start_level
, uint32_t num_levels
,
2650 uint32_t start_layer
, uint32_t num_layers
,
2651 bool *aux_supported_out
)
2653 enum isl_aux_usage aux_usage
=
2654 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2655 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2657 /* Clear color is specified as ints or floats and the conversion is done by
2658 * the sampler. If we have a texture view, we would have to perform the
2659 * clear color conversion manually. Just disable clear color.
2661 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2662 clear_supported
= false;
2664 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2665 start_layer
, num_layers
,
2666 aux_usage
, clear_supported
);
2667 if (aux_supported_out
)
2668 *aux_supported_out
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2672 intel_miptree_prepare_texture(struct brw_context
*brw
,
2673 struct intel_mipmap_tree
*mt
,
2674 enum isl_format view_format
,
2675 bool *aux_supported_out
)
2677 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2678 0, INTEL_REMAINING_LEVELS
,
2679 0, INTEL_REMAINING_LAYERS
,
2684 intel_miptree_prepare_image(struct brw_context
*brw
,
2685 struct intel_mipmap_tree
*mt
)
2687 /* The data port doesn't understand any compression */
2688 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2689 0, INTEL_REMAINING_LAYERS
,
2690 ISL_AUX_USAGE_NONE
, false);
2694 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2695 struct intel_mipmap_tree
*mt
, uint32_t level
,
2696 uint32_t start_layer
, uint32_t num_layers
)
2698 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->surf
.format
, level
, 1,
2699 start_layer
, num_layers
, NULL
);
2703 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2704 struct intel_mipmap_tree
*mt
,
2705 bool srgb_enabled
, bool blend_enabled
)
2707 switch (mt
->aux_usage
) {
2708 case ISL_AUX_USAGE_MCS
:
2709 assert(mt
->mcs_buf
);
2710 return ISL_AUX_USAGE_MCS
;
2712 case ISL_AUX_USAGE_CCS_D
:
2713 return mt
->mcs_buf
? ISL_AUX_USAGE_CCS_D
: ISL_AUX_USAGE_NONE
;
2715 case ISL_AUX_USAGE_CCS_E
: {
2716 mesa_format mesa_format
=
2717 srgb_enabled
? mt
->format
:_mesa_get_srgb_format_linear(mt
->format
);
2718 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
2720 /* If the format supports CCS_E, then we can just use it */
2721 if (isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
))
2722 return ISL_AUX_USAGE_CCS_E
;
2724 /* Otherwise, we have to fall back to CCS_D */
2726 /* gen9 hardware technically supports non-0/1 clear colors with sRGB
2727 * formats. However, there are issues with blending where it doesn't
2728 * properly apply the sRGB curve to the clear color when blending.
2730 if (blend_enabled
&& isl_format_is_srgb(isl_format
) &&
2731 !isl_color_value_is_zero_one(mt
->fast_clear_color
, isl_format
))
2732 return ISL_AUX_USAGE_NONE
;
2734 return ISL_AUX_USAGE_CCS_D
;
2738 return ISL_AUX_USAGE_NONE
;
2743 intel_miptree_prepare_render(struct brw_context
*brw
,
2744 struct intel_mipmap_tree
*mt
, uint32_t level
,
2745 uint32_t start_layer
, uint32_t layer_count
,
2746 bool srgb_enabled
, bool blend_enabled
)
2748 enum isl_aux_usage aux_usage
=
2749 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
, blend_enabled
);
2750 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2751 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2755 intel_miptree_finish_render(struct brw_context
*brw
,
2756 struct intel_mipmap_tree
*mt
, uint32_t level
,
2757 uint32_t start_layer
, uint32_t layer_count
,
2758 bool srgb_enabled
, bool blend_enabled
)
2760 assert(_mesa_is_format_color_format(mt
->format
));
2762 enum isl_aux_usage aux_usage
=
2763 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
, blend_enabled
);
2764 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2769 intel_miptree_prepare_depth(struct brw_context
*brw
,
2770 struct intel_mipmap_tree
*mt
, uint32_t level
,
2771 uint32_t start_layer
, uint32_t layer_count
)
2773 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2774 mt
->aux_usage
, mt
->hiz_buf
!= NULL
);
2778 intel_miptree_finish_depth(struct brw_context
*brw
,
2779 struct intel_mipmap_tree
*mt
, uint32_t level
,
2780 uint32_t start_layer
, uint32_t layer_count
,
2783 if (depth_written
) {
2784 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2785 mt
->hiz_buf
!= NULL
);
2790 intel_miptree_prepare_external(struct brw_context
*brw
,
2791 struct intel_mipmap_tree
*mt
)
2793 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
2794 bool supports_fast_clear
= false;
2796 const struct isl_drm_modifier_info
*mod_info
=
2797 isl_drm_modifier_get_info(mt
->drm_modifier
);
2799 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
2800 /* CCS_E is the only supported aux for external images and it's only
2801 * supported on very simple images.
2803 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
2804 assert(_mesa_is_format_color_format(mt
->format
));
2805 assert(mt
->first_level
== 0 && mt
->last_level
== 0);
2806 assert(mt
->surf
.logical_level0_px
.depth
== 1);
2807 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
2808 assert(mt
->surf
.samples
== 1);
2809 assert(mt
->mcs_buf
!= NULL
);
2811 aux_usage
= mod_info
->aux_usage
;
2812 supports_fast_clear
= mod_info
->supports_clear_color
;
2815 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2816 0, INTEL_REMAINING_LAYERS
,
2817 aux_usage
, supports_fast_clear
);
2821 * Make it possible to share the BO backing the given miptree with another
2822 * process or another miptree.
2824 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2825 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2826 * ensure that no MCS buffer gets allocated in the future.
2828 * HiZ is similarly unsafe with shared buffers.
2831 intel_miptree_make_shareable(struct brw_context
*brw
,
2832 struct intel_mipmap_tree
*mt
)
2834 /* MCS buffers are also used for multisample buffers, but we can't resolve
2835 * away a multisample MCS buffer because it's an integral part of how the
2836 * pixel data is stored. Fortunately this code path should never be
2837 * reached for multisample buffers.
2839 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2840 mt
->surf
.samples
== 1);
2842 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2843 0, INTEL_REMAINING_LAYERS
,
2844 ISL_AUX_USAGE_NONE
, false);
2847 brw_bo_unreference(mt
->mcs_buf
->bo
);
2851 /* Any pending MCS/CCS operations are no longer needed. Trying to
2852 * execute any will likely crash due to the missing aux buffer. So let's
2853 * delete all pending ops.
2855 free(mt
->aux_state
);
2856 mt
->aux_state
= NULL
;
2860 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2863 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2864 mt
->level
[l
].has_hiz
= false;
2867 /* Any pending HiZ operations are no longer needed. Trying to execute
2868 * any will likely crash due to the missing aux buffer. So let's delete
2871 free(mt
->aux_state
);
2872 mt
->aux_state
= NULL
;
2875 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2876 mt
->supports_fast_clear
= false;
2881 * \brief Get pointer offset into stencil buffer.
2883 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2884 * must decode the tile's layout in software.
2887 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2889 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2891 * Even though the returned offset is always positive, the return type is
2893 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2894 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2897 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2899 uint32_t tile_size
= 4096;
2900 uint32_t tile_width
= 64;
2901 uint32_t tile_height
= 64;
2902 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2904 uint32_t tile_x
= x
/ tile_width
;
2905 uint32_t tile_y
= y
/ tile_height
;
2907 /* The byte's address relative to the tile's base addres. */
2908 uint32_t byte_x
= x
% tile_width
;
2909 uint32_t byte_y
= y
% tile_height
;
2911 uintptr_t u
= tile_y
* row_size
2912 + tile_x
* tile_size
2913 + 512 * (byte_x
/ 8)
2915 + 32 * ((byte_y
/ 4) % 2)
2916 + 16 * ((byte_x
/ 4) % 2)
2917 + 8 * ((byte_y
/ 2) % 2)
2918 + 4 * ((byte_x
/ 2) % 2)
2923 /* adjust for bit6 swizzling */
2924 if (((byte_x
/ 8) % 2) == 1) {
2925 if (((byte_y
/ 8) % 2) == 0) {
2937 intel_miptree_updownsample(struct brw_context
*brw
,
2938 struct intel_mipmap_tree
*src
,
2939 struct intel_mipmap_tree
*dst
)
2941 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2942 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2943 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2944 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2946 brw_blorp_blit_miptrees(brw
,
2947 src
, 0 /* level */, 0 /* layer */,
2948 src
->format
, SWIZZLE_XYZW
,
2949 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2952 GL_NEAREST
, false, false /*mirror x, y*/,
2955 if (src
->stencil_mt
) {
2956 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2957 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2958 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2959 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2961 brw_blorp_blit_miptrees(brw
,
2962 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2963 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2964 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2965 dst
->stencil_mt
->format
,
2968 GL_NEAREST
, false, false /*mirror x, y*/,
2969 false, false /* decode/encode srgb */);
2974 intel_update_r8stencil(struct brw_context
*brw
,
2975 struct intel_mipmap_tree
*mt
)
2977 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2979 assert(devinfo
->gen
>= 7);
2980 struct intel_mipmap_tree
*src
=
2981 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2982 if (!src
|| devinfo
->gen
>= 8 || !src
->r8stencil_needs_update
)
2985 assert(src
->surf
.size
> 0);
2987 if (!mt
->r8stencil_mt
) {
2988 assert(devinfo
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2989 mt
->r8stencil_mt
= make_surface(
2992 MESA_FORMAT_R_UINT8
,
2993 src
->first_level
, src
->last_level
,
2994 src
->surf
.logical_level0_px
.width
,
2995 src
->surf
.logical_level0_px
.height
,
2996 src
->surf
.dim
== ISL_SURF_DIM_3D
?
2997 src
->surf
.logical_level0_px
.depth
:
2998 src
->surf
.logical_level0_px
.array_len
,
3001 ISL_SURF_USAGE_TEXTURE_BIT
,
3002 BO_ALLOC_BUSY
, 0, NULL
);
3003 assert(mt
->r8stencil_mt
);
3006 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
3008 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
3009 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
3010 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
3011 src
->surf
.phys_level0_sa
.array_len
;
3013 for (unsigned layer
= 0; layer
< depth
; layer
++) {
3014 brw_blorp_copy_miptrees(brw
,
3018 minify(src
->surf
.logical_level0_px
.width
,
3020 minify(src
->surf
.logical_level0_px
.height
,
3025 brw_render_cache_set_check_flush(brw
, dst
->bo
);
3026 src
->r8stencil_needs_update
= false;
3030 intel_miptree_map_raw(struct brw_context
*brw
,
3031 struct intel_mipmap_tree
*mt
,
3034 struct brw_bo
*bo
= mt
->bo
;
3036 if (brw_batch_references(&brw
->batch
, bo
))
3037 intel_batchbuffer_flush(brw
);
3039 return brw_bo_map(brw
, bo
, mode
);
3043 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3045 brw_bo_unmap(mt
->bo
);
3049 intel_miptree_map_gtt(struct brw_context
*brw
,
3050 struct intel_mipmap_tree
*mt
,
3051 struct intel_miptree_map
*map
,
3052 unsigned int level
, unsigned int slice
)
3054 unsigned int bw
, bh
;
3056 unsigned int image_x
, image_y
;
3057 intptr_t x
= map
->x
;
3058 intptr_t y
= map
->y
;
3060 /* For compressed formats, the stride is the number of bytes per
3061 * row of blocks. intel_miptree_get_image_offset() already does
3064 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3065 assert(y
% bh
== 0);
3066 assert(x
% bw
== 0);
3070 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3077 /* Note that in the case of cube maps, the caller must have passed the
3078 * slice number referencing the face.
3080 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3084 map
->stride
= mt
->surf
.row_pitch
;
3085 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3088 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3089 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3090 map
->x
, map
->y
, map
->w
, map
->h
,
3091 mt
, _mesa_get_format_name(mt
->format
),
3092 x
, y
, map
->ptr
, map
->stride
);
3096 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3098 intel_miptree_unmap_raw(mt
);
3102 intel_miptree_map_blit(struct brw_context
*brw
,
3103 struct intel_mipmap_tree
*mt
,
3104 struct intel_miptree_map
*map
,
3105 unsigned int level
, unsigned int slice
)
3107 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3108 /* first_level */ 0,
3112 MIPTREE_CREATE_LINEAR
);
3114 if (!map
->linear_mt
) {
3115 fprintf(stderr
, "Failed to allocate blit temporary\n");
3118 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3120 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3121 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3122 * invalidate is set, since we'll be writing the whole rectangle from our
3123 * temporary buffer back out.
3125 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3126 if (!intel_miptree_copy(brw
,
3127 mt
, level
, slice
, map
->x
, map
->y
,
3128 map
->linear_mt
, 0, 0, 0, 0,
3130 fprintf(stderr
, "Failed to blit\n");
3135 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3137 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3138 map
->x
, map
->y
, map
->w
, map
->h
,
3139 mt
, _mesa_get_format_name(mt
->format
),
3140 level
, slice
, map
->ptr
, map
->stride
);
3145 intel_miptree_release(&map
->linear_mt
);
3151 intel_miptree_unmap_blit(struct brw_context
*brw
,
3152 struct intel_mipmap_tree
*mt
,
3153 struct intel_miptree_map
*map
,
3157 struct gl_context
*ctx
= &brw
->ctx
;
3159 intel_miptree_unmap_raw(map
->linear_mt
);
3161 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3162 bool ok
= intel_miptree_copy(brw
,
3163 map
->linear_mt
, 0, 0, 0, 0,
3164 mt
, level
, slice
, map
->x
, map
->y
,
3166 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3169 intel_miptree_release(&map
->linear_mt
);
3173 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3175 #if defined(USE_SSE41)
3177 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3178 struct intel_mipmap_tree
*mt
,
3179 struct intel_miptree_map
*map
,
3180 unsigned int level
, unsigned int slice
)
3182 assert(map
->mode
& GL_MAP_READ_BIT
);
3183 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3185 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3186 map
->x
, map
->y
, map
->w
, map
->h
,
3187 mt
, _mesa_get_format_name(mt
->format
),
3188 level
, slice
, map
->ptr
, map
->stride
);
3190 /* Map the original image */
3193 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3197 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3203 src
+= image_y
* mt
->surf
.row_pitch
;
3204 src
+= image_x
* mt
->cpp
;
3206 /* Due to the pixel offsets for the particular image being mapped, our
3207 * src pointer may not be 16-byte aligned. However, if the pitch is
3208 * divisible by 16, then the amount by which it's misaligned will remain
3209 * consistent from row to row.
3211 assert((mt
->surf
.row_pitch
% 16) == 0);
3212 const int misalignment
= ((uintptr_t) src
) & 15;
3214 /* Create an untiled temporary buffer for the mapping. */
3215 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3217 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3219 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3220 /* Offset the destination so it has the same misalignment as src. */
3221 map
->ptr
= map
->buffer
+ misalignment
;
3223 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3225 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3226 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3227 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3229 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3232 intel_miptree_unmap_raw(mt
);
3236 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3237 struct intel_mipmap_tree
*mt
,
3238 struct intel_miptree_map
*map
,
3242 _mesa_align_free(map
->buffer
);
3249 intel_miptree_map_s8(struct brw_context
*brw
,
3250 struct intel_mipmap_tree
*mt
,
3251 struct intel_miptree_map
*map
,
3252 unsigned int level
, unsigned int slice
)
3254 map
->stride
= map
->w
;
3255 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3259 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3260 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3261 * invalidate is set, since we'll be writing the whole rectangle from our
3262 * temporary buffer back out.
3264 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3265 uint8_t *untiled_s8_map
= map
->ptr
;
3266 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3267 unsigned int image_x
, image_y
;
3269 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3271 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3272 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3273 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3274 x
+ image_x
+ map
->x
,
3275 y
+ image_y
+ map
->y
,
3276 brw
->has_swizzling
);
3277 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3281 intel_miptree_unmap_raw(mt
);
3283 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3284 map
->x
, map
->y
, map
->w
, map
->h
,
3285 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3287 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3288 map
->x
, map
->y
, map
->w
, map
->h
,
3289 mt
, map
->ptr
, map
->stride
);
3294 intel_miptree_unmap_s8(struct brw_context
*brw
,
3295 struct intel_mipmap_tree
*mt
,
3296 struct intel_miptree_map
*map
,
3300 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3301 unsigned int image_x
, image_y
;
3302 uint8_t *untiled_s8_map
= map
->ptr
;
3303 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3305 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3307 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3308 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3309 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3310 image_x
+ x
+ map
->x
,
3311 image_y
+ y
+ map
->y
,
3312 brw
->has_swizzling
);
3313 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3317 intel_miptree_unmap_raw(mt
);
3324 intel_miptree_map_etc(struct brw_context
*brw
,
3325 struct intel_mipmap_tree
*mt
,
3326 struct intel_miptree_map
*map
,
3330 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3331 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3332 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3335 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3336 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3338 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3339 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3340 map
->w
, map
->h
, 1));
3341 map
->ptr
= map
->buffer
;
3345 intel_miptree_unmap_etc(struct brw_context
*brw
,
3346 struct intel_mipmap_tree
*mt
,
3347 struct intel_miptree_map
*map
,
3353 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3358 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3359 + image_y
* mt
->surf
.row_pitch
3360 + image_x
* mt
->cpp
;
3362 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3363 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3364 map
->ptr
, map
->stride
,
3367 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3368 map
->ptr
, map
->stride
,
3369 map
->w
, map
->h
, mt
->etc_format
);
3371 intel_miptree_unmap_raw(mt
);
3376 * Mapping function for packed depth/stencil miptrees backed by real separate
3377 * miptrees for depth and stencil.
3379 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3380 * separate from the depth buffer. Yet at the GL API level, we have to expose
3381 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3382 * be able to map that memory for texture storage and glReadPixels-type
3383 * operations. We give Mesa core that access by mallocing a temporary and
3384 * copying the data between the actual backing store and the temporary.
3387 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3388 struct intel_mipmap_tree
*mt
,
3389 struct intel_miptree_map
*map
,
3390 unsigned int level
, unsigned int slice
)
3392 struct intel_mipmap_tree
*z_mt
= mt
;
3393 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3394 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3395 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3397 map
->stride
= map
->w
* packed_bpp
;
3398 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3402 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3403 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3404 * invalidate is set, since we'll be writing the whole rectangle from our
3405 * temporary buffer back out.
3407 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3408 uint32_t *packed_map
= map
->ptr
;
3409 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3410 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3411 unsigned int s_image_x
, s_image_y
;
3412 unsigned int z_image_x
, z_image_y
;
3414 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3415 &s_image_x
, &s_image_y
);
3416 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3417 &z_image_x
, &z_image_y
);
3419 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3420 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3421 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3422 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3425 brw
->has_swizzling
);
3426 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3427 (z_mt
->surf
.row_pitch
/ 4) +
3428 (map_x
+ z_image_x
));
3429 uint8_t s
= s_map
[s_offset
];
3430 uint32_t z
= z_map
[z_offset
];
3432 if (map_z32f_x24s8
) {
3433 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3434 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3436 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3441 intel_miptree_unmap_raw(s_mt
);
3442 intel_miptree_unmap_raw(z_mt
);
3444 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3446 map
->x
, map
->y
, map
->w
, map
->h
,
3447 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3448 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3449 map
->ptr
, map
->stride
);
3451 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3452 map
->x
, map
->y
, map
->w
, map
->h
,
3453 mt
, map
->ptr
, map
->stride
);
3458 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3459 struct intel_mipmap_tree
*mt
,
3460 struct intel_miptree_map
*map
,
3464 struct intel_mipmap_tree
*z_mt
= mt
;
3465 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3466 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3468 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3469 uint32_t *packed_map
= map
->ptr
;
3470 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3471 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3472 unsigned int s_image_x
, s_image_y
;
3473 unsigned int z_image_x
, z_image_y
;
3475 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3476 &s_image_x
, &s_image_y
);
3477 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3478 &z_image_x
, &z_image_y
);
3480 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3481 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3482 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3483 x
+ s_image_x
+ map
->x
,
3484 y
+ s_image_y
+ map
->y
,
3485 brw
->has_swizzling
);
3486 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3487 (z_mt
->surf
.row_pitch
/ 4) +
3488 (x
+ z_image_x
+ map
->x
));
3490 if (map_z32f_x24s8
) {
3491 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3492 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3494 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3495 s_map
[s_offset
] = packed
>> 24;
3496 z_map
[z_offset
] = packed
;
3501 intel_miptree_unmap_raw(s_mt
);
3502 intel_miptree_unmap_raw(z_mt
);
3504 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3506 map
->x
, map
->y
, map
->w
, map
->h
,
3507 z_mt
, _mesa_get_format_name(z_mt
->format
),
3508 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3509 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3510 map
->ptr
, map
->stride
);
3517 * Create and attach a map to the miptree at (level, slice). Return the
3520 static struct intel_miptree_map
*
3521 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3530 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3535 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3536 mt
->level
[level
].slice
[slice
].map
= map
;
3548 * Release the map at (level, slice).
3551 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3555 struct intel_miptree_map
**map
;
3557 map
= &mt
->level
[level
].slice
[slice
].map
;
3563 can_blit_slice(struct intel_mipmap_tree
*mt
,
3564 unsigned int level
, unsigned int slice
)
3566 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3567 if (mt
->surf
.row_pitch
>= 32768)
3574 use_intel_mipree_map_blit(struct brw_context
*brw
,
3575 struct intel_mipmap_tree
*mt
,
3580 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3582 if (devinfo
->has_llc
&&
3583 /* It's probably not worth swapping to the blit ring because of
3584 * all the overhead involved.
3586 !(mode
& GL_MAP_WRITE_BIT
) &&
3588 (mt
->surf
.tiling
== ISL_TILING_X
||
3589 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3590 (devinfo
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3591 /* Fast copy blit on skl+ supports all tiling formats. */
3592 devinfo
->gen
>= 9) &&
3593 can_blit_slice(mt
, level
, slice
))
3596 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3597 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3598 assert(can_blit_slice(mt
, level
, slice
));
3606 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3607 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3608 * arithmetic overflow.
3610 * If you call this function and use \a out_stride, then you're doing pointer
3611 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3612 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3613 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3614 * which usually have type uint32_t or GLuint.
3617 intel_miptree_map(struct brw_context
*brw
,
3618 struct intel_mipmap_tree
*mt
,
3627 ptrdiff_t *out_stride
)
3629 struct intel_miptree_map
*map
;
3631 assert(mt
->surf
.samples
== 1);
3633 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3640 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3641 map
->mode
& GL_MAP_WRITE_BIT
);
3643 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3644 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3645 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3646 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3647 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3648 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3649 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3650 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3651 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3652 #if defined(USE_SSE41)
3653 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3654 !mt
->compressed
&& cpu_has_sse4_1
&&
3655 (mt
->surf
.row_pitch
% 16 == 0)) {
3656 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3659 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3662 *out_ptr
= map
->ptr
;
3663 *out_stride
= map
->stride
;
3665 if (map
->ptr
== NULL
)
3666 intel_miptree_release_map(mt
, level
, slice
);
3670 intel_miptree_unmap(struct brw_context
*brw
,
3671 struct intel_mipmap_tree
*mt
,
3675 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3677 assert(mt
->surf
.samples
== 1);
3682 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3683 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3685 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3686 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3687 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3688 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3689 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3690 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3691 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3692 } else if (map
->linear_mt
) {
3693 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3694 #if defined(USE_SSE41)
3695 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3696 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3699 intel_miptree_unmap_gtt(mt
);
3702 intel_miptree_release_map(mt
, level
, slice
);
3706 get_isl_surf_dim(GLenum target
)
3710 case GL_TEXTURE_1D_ARRAY
:
3711 return ISL_SURF_DIM_1D
;
3714 case GL_TEXTURE_2D_ARRAY
:
3715 case GL_TEXTURE_RECTANGLE
:
3716 case GL_TEXTURE_CUBE_MAP
:
3717 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3718 case GL_TEXTURE_2D_MULTISAMPLE
:
3719 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3720 case GL_TEXTURE_EXTERNAL_OES
:
3721 return ISL_SURF_DIM_2D
;
3724 return ISL_SURF_DIM_3D
;
3727 unreachable("Invalid texture target");
3731 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3732 enum isl_tiling tiling
, GLenum target
)
3736 case GL_TEXTURE_1D_ARRAY
:
3737 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3738 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3741 case GL_TEXTURE_2D_ARRAY
:
3742 case GL_TEXTURE_RECTANGLE
:
3743 case GL_TEXTURE_2D_MULTISAMPLE
:
3744 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3745 case GL_TEXTURE_EXTERNAL_OES
:
3746 return ISL_DIM_LAYOUT_GEN4_2D
;
3748 case GL_TEXTURE_CUBE_MAP
:
3749 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3750 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3751 ISL_DIM_LAYOUT_GEN4_2D
);
3754 return (devinfo
->gen
>= 9 ?
3755 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3758 unreachable("Invalid texture target");
3762 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3763 const struct intel_mipmap_tree
*mt
)
3766 return ISL_AUX_USAGE_HIZ
;
3769 return ISL_AUX_USAGE_NONE
;
3771 return mt
->aux_usage
;