1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_chipset.h"
33 #include "intel_mipmap_tree.h"
34 #include "intel_regions.h"
35 #include "intel_resolve_map.h"
36 #include "intel_tex.h"
37 #include "intel_blit.h"
39 #include "brw_blorp.h"
40 #include "brw_context.h"
42 #include "main/enums.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
52 target_to_target(GLenum target
)
55 case GL_TEXTURE_CUBE_MAP_POSITIVE_X_ARB
:
56 case GL_TEXTURE_CUBE_MAP_NEGATIVE_X_ARB
:
57 case GL_TEXTURE_CUBE_MAP_POSITIVE_Y_ARB
:
58 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y_ARB
:
59 case GL_TEXTURE_CUBE_MAP_POSITIVE_Z_ARB
:
60 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z_ARB
:
61 return GL_TEXTURE_CUBE_MAP_ARB
;
69 * Determine which MSAA layout should be used by the MSAA surface being
70 * created, based on the chip generation and the surface type.
72 static enum intel_msaa_layout
73 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
, GLenum target
)
75 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
77 return INTEL_MSAA_LAYOUT_IMS
;
79 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
80 switch (_mesa_get_format_base_format(format
)) {
81 case GL_DEPTH_COMPONENT
:
82 case GL_STENCIL_INDEX
:
83 case GL_DEPTH_STENCIL
:
84 return INTEL_MSAA_LAYOUT_IMS
;
86 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
88 * This field must be set to 0 for all SINT MSRTs when all RT channels
91 * In practice this means that we have to disable MCS for all signed
92 * integer MSAA buffers. The alternative, to disable MCS only when one
93 * of the render target channels is disabled, is impractical because it
94 * would require converting between CMS and UMS MSAA layouts on the fly,
97 if (_mesa_get_format_datatype(format
) == GL_INT
) {
98 /* TODO: is this workaround needed for future chipsets? */
99 assert(brw
->gen
== 7);
100 return INTEL_MSAA_LAYOUT_UMS
;
102 return INTEL_MSAA_LAYOUT_CMS
;
109 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
110 * scaled-down bitfield representation of the color buffer which is capable of
111 * recording when blocks of the color buffer are equal to the clear value.
112 * This function returns the block size that will be used by the MCS buffer
113 * corresponding to a certain color miptree.
115 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
116 * beneath the "Fast Color Clear" bullet (p327):
118 * The following table describes the RT alignment
132 * This alignment has the following uses:
134 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
135 * buffer contains 128 blocks horizontally and 256 blocks vertically.
137 * - For figuring out alignment restrictions for a fast clear operation. Fast
138 * clear operations must always clear aligned multiples of 16 blocks
139 * horizontally and 32 blocks vertically.
141 * - For scaling down the coordinates sent through the render pipeline during
142 * a fast clear. X coordinates must be scaled down by 8 times the block
143 * width, and Y coordinates by 16 times the block height.
145 * - For scaling down the coordinates sent through the render pipeline during
146 * a "Render Target Resolve" operation. X coordinates must be scaled down
147 * by half the block width, and Y coordinates by half the block height.
150 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
151 struct intel_mipmap_tree
*mt
,
152 unsigned *width_px
, unsigned *height
)
154 switch (mt
->region
->tiling
) {
156 assert(!"Non-MSRT MCS requires X or Y tiling");
157 /* In release builds, fall through */
159 *width_px
= 32 / mt
->cpp
;
163 *width_px
= 64 / mt
->cpp
;
170 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
173 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
174 * beneath the "Fast Color Clear" bullet (p326):
176 * - Support is limited to tiled render targets.
177 * - Support is for non-mip-mapped and non-array surface types only.
179 * And then later, on p327:
181 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
185 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
186 struct intel_mipmap_tree
*mt
)
188 /* MCS support does not exist prior to Gen7 */
189 if (brw
->gen
< 7 || brw
->gen
>= 8)
192 /* MCS is only supported for color buffers */
193 switch (_mesa_get_format_base_format(mt
->format
)) {
194 case GL_DEPTH_COMPONENT
:
195 case GL_DEPTH_STENCIL
:
196 case GL_STENCIL_INDEX
:
200 if (mt
->region
->tiling
!= I915_TILING_X
&&
201 mt
->region
->tiling
!= I915_TILING_Y
)
203 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
205 if (mt
->first_level
!= 0 || mt
->last_level
!= 0)
207 if (mt
->physical_depth0
!= 1)
210 /* There's no point in using an MCS buffer if the surface isn't in a
213 if (!brw
->format_supported_as_render_target
[mt
->format
])
221 * @param for_bo Indicates that the caller is
222 * intel_miptree_create_for_bo(). If true, then do not create
225 struct intel_mipmap_tree
*
226 intel_miptree_create_layout(struct brw_context
*brw
,
237 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
241 DBG("%s target %s format %s level %d..%d <-- %p\n", __FUNCTION__
,
242 _mesa_lookup_enum_by_nr(target
),
243 _mesa_get_format_name(format
),
244 first_level
, last_level
, mt
);
246 mt
->target
= target_to_target(target
);
248 mt
->first_level
= first_level
;
249 mt
->last_level
= last_level
;
250 mt
->logical_width0
= width0
;
251 mt
->logical_height0
= height0
;
252 mt
->logical_depth0
= depth0
;
253 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
255 /* The cpp is bytes per (1, blockheight)-sized block for compressed
256 * textures. This is why you'll see divides by blockheight all over
259 _mesa_get_format_block_size(format
, &bw
, &bh
);
260 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
261 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
263 mt
->num_samples
= num_samples
;
264 mt
->compressed
= _mesa_is_format_compressed(format
);
265 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
268 if (num_samples
> 1) {
269 /* Adjust width/height/depth for MSAA */
270 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->target
);
271 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
272 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says:
274 * "Any of the other messages (sample*, LOD, load4) used with a
275 * (4x) multisampled surface will in-effect sample a surface with
276 * double the height and width as that indicated in the surface
277 * state. Each pixel position on the original-sized surface is
278 * replaced with a 2x2 of samples with the following arrangement:
283 * Thus, when sampling from a multisampled texture, it behaves as
284 * though the layout in memory for (x,y,sample) is:
286 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
287 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
289 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
290 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
292 * However, the actual layout of multisampled data in memory is:
294 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
295 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
297 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
298 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
300 * This pattern repeats for each 2x2 pixel block.
302 * As a result, when calculating the size of our 4-sample buffer for
303 * an odd width or height, we have to align before scaling up because
304 * sample 3 is in that bottom right 2x2 block.
306 switch (num_samples
) {
308 width0
= ALIGN(width0
, 2) * 2;
309 height0
= ALIGN(height0
, 2) * 2;
312 width0
= ALIGN(width0
, 2) * 4;
313 height0
= ALIGN(height0
, 2) * 2;
316 /* num_samples should already have been quantized to 0, 1, 4, or
322 /* Non-interleaved */
323 depth0
*= num_samples
;
327 /* array_spacing_lod0 is only used for non-IMS MSAA surfaces. TODO: can we
330 switch (mt
->msaa_layout
) {
331 case INTEL_MSAA_LAYOUT_NONE
:
332 case INTEL_MSAA_LAYOUT_IMS
:
333 mt
->array_spacing_lod0
= false;
335 case INTEL_MSAA_LAYOUT_UMS
:
336 case INTEL_MSAA_LAYOUT_CMS
:
337 mt
->array_spacing_lod0
= true;
341 if (target
== GL_TEXTURE_CUBE_MAP
) {
346 mt
->physical_width0
= width0
;
347 mt
->physical_height0
= height0
;
348 mt
->physical_depth0
= depth0
;
351 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
352 (brw
->must_use_separate_stencil
||
353 (brw
->has_separate_stencil
&& brw_is_hiz_depth_format(brw
, format
)))) {
354 mt
->stencil_mt
= intel_miptree_create(brw
,
364 INTEL_MIPTREE_TILING_ANY
);
365 if (!mt
->stencil_mt
) {
366 intel_miptree_release(&mt
);
370 /* Fix up the Z miptree format for how we're splitting out separate
371 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
373 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) {
374 mt
->format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
375 } else if (mt
->format
== MESA_FORMAT_Z32_FLOAT_S8X24_UINT
) {
376 mt
->format
= MESA_FORMAT_Z_FLOAT32
;
379 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
380 _mesa_get_format_name(mt
->format
));
384 brw_miptree_layout(brw
, mt
);
390 * \brief Helper function for intel_miptree_create().
393 intel_miptree_choose_tiling(struct brw_context
*brw
,
396 uint32_t num_samples
,
397 enum intel_miptree_tiling_mode requested
,
398 struct intel_mipmap_tree
*mt
)
400 if (format
== MESA_FORMAT_S_UINT8
) {
401 /* The stencil buffer is W tiled. However, we request from the kernel a
402 * non-tiled buffer because the GTT is incapable of W fencing.
404 return I915_TILING_NONE
;
407 /* Some usages may want only one type of tiling, like depth miptrees (Y
408 * tiled), or temporary BOs for uploading data once (linear).
411 case INTEL_MIPTREE_TILING_ANY
:
413 case INTEL_MIPTREE_TILING_Y
:
414 return I915_TILING_Y
;
415 case INTEL_MIPTREE_TILING_NONE
:
416 return I915_TILING_NONE
;
419 if (num_samples
> 1) {
420 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
423 * [DevSNB+]: For multi-sample render targets, this field must be
424 * 1. MSRTs can only be tiled.
426 * Our usual reason for preferring X tiling (fast blits using the
427 * blitting engine) doesn't apply to MSAA, since we'll generally be
428 * downsampling or upsampling when blitting between the MSAA buffer
429 * and another buffer, and the blitting engine doesn't support that.
430 * So use Y tiling, since it makes better use of the cache.
432 return I915_TILING_Y
;
435 GLenum base_format
= _mesa_get_format_base_format(format
);
436 if (base_format
== GL_DEPTH_COMPONENT
||
437 base_format
== GL_DEPTH_STENCIL_EXT
)
438 return I915_TILING_Y
;
440 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
442 /* If the width is much smaller than a tile, don't bother tiling. */
443 if (minimum_pitch
< 64)
444 return I915_TILING_NONE
;
446 if (ALIGN(minimum_pitch
, 512) >= 32768 ||
447 mt
->total_width
>= 32768 || mt
->total_height
>= 32768) {
448 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
449 mt
->total_width
, mt
->total_height
);
450 return I915_TILING_NONE
;
453 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
455 return I915_TILING_X
;
457 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
458 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
460 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
461 * all the way back to 965, but is explicitly permitted on Gen7.
463 if (brw
->gen
!= 7 && mt
->cpp
>= 16)
464 return I915_TILING_X
;
466 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
467 * messages), on p64, under the heading "Surface Vertical Alignment":
469 * This field must be set to VALIGN_4 for all tiled Y Render Target
472 * So if the surface is renderable and uses a vertical alignment of 2,
473 * force it to be X tiled. This is somewhat conservative (it's possible
474 * that the client won't ever render to this surface), but it's difficult
475 * to know that ahead of time. And besides, since we use a vertical
476 * alignment of 4 as often as we can, this shouldn't happen very often.
478 if (brw
->gen
== 7 && mt
->align_h
== 2 &&
479 brw
->format_supported_as_render_target
[format
]) {
480 return I915_TILING_X
;
483 return I915_TILING_Y
| I915_TILING_X
;
486 struct intel_mipmap_tree
*
487 intel_miptree_create(struct brw_context
*brw
,
495 bool expect_accelerated_upload
,
497 enum intel_miptree_tiling_mode requested_tiling
)
499 struct intel_mipmap_tree
*mt
;
500 mesa_format tex_format
= format
;
501 mesa_format etc_format
= MESA_FORMAT_NONE
;
502 GLuint total_width
, total_height
;
504 if (brw
->gen
< 8 && !brw
->is_baytrail
) {
506 case MESA_FORMAT_ETC1_RGB8
:
507 format
= MESA_FORMAT_R8G8B8X8_UNORM
;
509 case MESA_FORMAT_ETC2_RGB8
:
510 format
= MESA_FORMAT_R8G8B8X8_UNORM
;
512 case MESA_FORMAT_ETC2_SRGB8
:
513 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
514 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
515 format
= MESA_FORMAT_B8G8R8A8_SRGB
;
517 case MESA_FORMAT_ETC2_RGBA8_EAC
:
518 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
519 format
= MESA_FORMAT_R8G8B8A8_UNORM
;
521 case MESA_FORMAT_ETC2_R11_EAC
:
522 format
= MESA_FORMAT_R_UNORM16
;
524 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
525 format
= MESA_FORMAT_R_SNORM16
;
527 case MESA_FORMAT_ETC2_RG11_EAC
:
528 format
= MESA_FORMAT_R16G16_UNORM
;
530 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
531 format
= MESA_FORMAT_R16G16_SNORM
;
534 /* Non ETC1 / ETC2 format */
539 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
541 mt
= intel_miptree_create_layout(brw
, target
, format
,
542 first_level
, last_level
, width0
,
546 * pitch == 0 || height == 0 indicates the null texture
548 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
549 intel_miptree_release(&mt
);
553 total_width
= mt
->total_width
;
554 total_height
= mt
->total_height
;
556 if (format
== MESA_FORMAT_S_UINT8
) {
557 /* Align to size of W tile, 64x64. */
558 total_width
= ALIGN(total_width
, 64);
559 total_height
= ALIGN(total_height
, 64);
562 uint32_t tiling
= intel_miptree_choose_tiling(brw
, format
, width0
,
563 num_samples
, requested_tiling
,
565 bool y_or_x
= tiling
== (I915_TILING_Y
| I915_TILING_X
);
567 mt
->etc_format
= etc_format
;
568 mt
->region
= intel_region_alloc(brw
->intelScreen
,
569 y_or_x
? I915_TILING_Y
: tiling
,
573 expect_accelerated_upload
);
575 /* If the region is too large to fit in the aperture, we need to use the
576 * BLT engine to support it. The BLT paths can't currently handle Y-tiling,
577 * so we need to fall back to X.
579 if (y_or_x
&& mt
->region
->bo
->size
>= brw
->max_gtt_map_object_size
) {
580 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
581 mt
->total_width
, mt
->total_height
);
582 intel_region_release(&mt
->region
);
584 mt
->region
= intel_region_alloc(brw
->intelScreen
,
589 expect_accelerated_upload
);
595 intel_miptree_release(&mt
);
600 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
601 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
602 intel_miptree_release(&mt
);
607 /* If this miptree is capable of supporting fast color clears, set
608 * fast_clear_state appropriately to ensure that fast clears will occur.
609 * Allocation of the MCS miptree will be deferred until the first fast
610 * clear actually occurs.
612 if (intel_is_non_msrt_mcs_buffer_supported(brw
, mt
))
613 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
618 struct intel_mipmap_tree
*
619 intel_miptree_create_for_bo(struct brw_context
*brw
,
628 struct intel_mipmap_tree
*mt
;
630 struct intel_region
*region
= calloc(1, sizeof(*region
));
634 /* Nothing will be able to use this miptree with the BO if the offset isn't
637 if (tiling
!= I915_TILING_NONE
)
638 assert(offset
% 4096 == 0);
640 /* miptrees can't handle negative pitch. If you need flipping of images,
641 * that's outside of the scope of the mt.
645 mt
= intel_miptree_create_layout(brw
, GL_TEXTURE_2D
, format
,
648 true, 0 /* num_samples */);
654 region
->cpp
= mt
->cpp
;
655 region
->width
= width
;
656 region
->height
= height
;
657 region
->pitch
= pitch
;
658 region
->refcount
= 1;
659 drm_intel_bo_reference(bo
);
661 region
->tiling
= tiling
;
671 * For a singlesample DRI2 buffer, this simply wraps the given region with a miptree.
673 * For a multisample DRI2 buffer, this wraps the given region with
674 * a singlesample miptree, then creates a multisample miptree into which the
675 * singlesample miptree is embedded as a child.
677 struct intel_mipmap_tree
*
678 intel_miptree_create_for_dri2_buffer(struct brw_context
*brw
,
679 unsigned dri_attachment
,
681 uint32_t num_samples
,
682 struct intel_region
*region
)
684 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
685 struct intel_mipmap_tree
*multisample_mt
= NULL
;
687 /* Only the front and back buffers, which are color buffers, are shared
690 assert(dri_attachment
== __DRI_BUFFER_BACK_LEFT
||
691 dri_attachment
== __DRI_BUFFER_FRONT_LEFT
||
692 dri_attachment
== __DRI_BUFFER_FAKE_FRONT_LEFT
);
693 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
694 _mesa_get_format_base_format(format
) == GL_RGBA
);
696 singlesample_mt
= intel_miptree_create_for_bo(brw
,
704 if (!singlesample_mt
)
706 singlesample_mt
->region
->name
= region
->name
;
708 /* If this miptree is capable of supporting fast color clears, set
709 * fast_clear_state appropriately to ensure that fast clears will occur.
710 * Allocation of the MCS miptree will be deferred until the first fast
711 * clear actually occurs.
713 if (intel_is_non_msrt_mcs_buffer_supported(brw
, singlesample_mt
))
714 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
716 if (num_samples
== 0)
717 return singlesample_mt
;
719 multisample_mt
= intel_miptree_create_for_renderbuffer(brw
,
724 if (!multisample_mt
) {
725 intel_miptree_release(&singlesample_mt
);
729 multisample_mt
->singlesample_mt
= singlesample_mt
;
730 multisample_mt
->need_downsample
= false;
732 if (brw
->is_front_buffer_rendering
&&
733 (dri_attachment
== __DRI_BUFFER_FRONT_LEFT
||
734 dri_attachment
== __DRI_BUFFER_FAKE_FRONT_LEFT
)) {
735 intel_miptree_upsample(brw
, multisample_mt
);
738 return multisample_mt
;
742 * For a singlesample image buffer, this simply wraps the given region with a miptree.
744 * For a multisample image buffer, this wraps the given region with
745 * a singlesample miptree, then creates a multisample miptree into which the
746 * singlesample miptree is embedded as a child.
748 struct intel_mipmap_tree
*
749 intel_miptree_create_for_image_buffer(struct brw_context
*intel
,
750 enum __DRIimageBufferMask buffer_type
,
752 uint32_t num_samples
,
753 struct intel_region
*region
)
755 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
756 struct intel_mipmap_tree
*multisample_mt
= NULL
;
758 /* Only the front and back buffers, which are color buffers, are allocated
759 * through the image loader.
761 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
762 _mesa_get_format_base_format(format
) == GL_RGBA
);
764 singlesample_mt
= intel_miptree_create_for_bo(intel
,
772 if (!singlesample_mt
)
775 /* If this miptree is capable of supporting fast color clears, set
776 * mcs_state appropriately to ensure that fast clears will occur.
777 * Allocation of the MCS miptree will be deferred until the first fast
778 * clear actually occurs.
780 if (intel_is_non_msrt_mcs_buffer_supported(intel
, singlesample_mt
))
781 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
783 if (num_samples
== 0)
784 return singlesample_mt
;
786 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
791 if (!multisample_mt
) {
792 intel_miptree_release(&singlesample_mt
);
796 multisample_mt
->singlesample_mt
= singlesample_mt
;
797 multisample_mt
->need_downsample
= false;
799 if (intel
->is_front_buffer_rendering
&& buffer_type
== __DRI_IMAGE_BUFFER_FRONT
) {
800 intel_miptree_upsample(intel
, multisample_mt
);
803 return multisample_mt
;
806 struct intel_mipmap_tree
*
807 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
811 uint32_t num_samples
)
813 struct intel_mipmap_tree
*mt
;
817 mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, format
, 0, 0,
818 width
, height
, depth
, true, num_samples
,
819 INTEL_MIPTREE_TILING_ANY
);
823 if (brw_is_hiz_depth_format(brw
, format
)) {
824 ok
= intel_miptree_alloc_hiz(brw
, mt
);
832 intel_miptree_release(&mt
);
837 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
838 struct intel_mipmap_tree
*src
)
843 intel_miptree_release(dst
);
847 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
855 intel_miptree_release(struct intel_mipmap_tree
**mt
)
860 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
861 if (--(*mt
)->refcount
<= 0) {
864 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
866 intel_region_release(&((*mt
)->region
));
867 intel_miptree_release(&(*mt
)->stencil_mt
);
868 intel_miptree_release(&(*mt
)->hiz_mt
);
869 intel_miptree_release(&(*mt
)->mcs_mt
);
870 intel_miptree_release(&(*mt
)->singlesample_mt
);
871 intel_resolve_map_clear(&(*mt
)->hiz_map
);
873 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
874 free((*mt
)->level
[i
].slice
);
883 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
884 int *width
, int *height
, int *depth
)
886 switch (image
->TexObject
->Target
) {
887 case GL_TEXTURE_1D_ARRAY
:
888 *width
= image
->Width
;
890 *depth
= image
->Height
;
893 *width
= image
->Width
;
894 *height
= image
->Height
;
895 *depth
= image
->Depth
;
901 * Can the image be pulled into a unified mipmap tree? This mirrors
902 * the completeness test in a lot of ways.
904 * Not sure whether I want to pass gl_texture_image here.
907 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
908 struct gl_texture_image
*image
)
910 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
911 GLuint level
= intelImage
->base
.Base
.Level
;
912 int width
, height
, depth
;
914 /* glTexImage* choose the texture object based on the target passed in, and
915 * objects can't change targets over their lifetimes, so this should be
918 assert(target_to_target(image
->TexObject
->Target
) == mt
->target
);
920 mesa_format mt_format
= mt
->format
;
921 if (mt
->format
== MESA_FORMAT_Z24_UNORM_S8_UINT
&& mt
->stencil_mt
)
922 mt_format
= MESA_FORMAT_Z24_UNORM_X8_UINT
;
923 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
924 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
925 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
926 mt_format
= mt
->etc_format
;
928 if (image
->TexFormat
!= mt_format
)
931 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
933 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
936 /* Test image dimensions against the base level image adjusted for
937 * minification. This will also catch images not present in the
938 * tree, changed targets, etc.
940 if (mt
->target
== GL_TEXTURE_2D_MULTISAMPLE
||
941 mt
->target
== GL_TEXTURE_2D_MULTISAMPLE_ARRAY
) {
942 /* nonzero level here is always bogus */
945 if (width
!= mt
->logical_width0
||
946 height
!= mt
->logical_height0
||
947 depth
!= mt
->logical_depth0
) {
952 /* all normal textures, renderbuffers, etc */
953 if (width
!= mt
->level
[level
].width
||
954 height
!= mt
->level
[level
].height
||
955 depth
!= mt
->level
[level
].depth
) {
960 if (image
->NumSamples
!= mt
->num_samples
)
968 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
971 GLuint w
, GLuint h
, GLuint d
)
973 mt
->level
[level
].width
= w
;
974 mt
->level
[level
].height
= h
;
975 mt
->level
[level
].depth
= d
;
976 mt
->level
[level
].level_x
= x
;
977 mt
->level
[level
].level_y
= y
;
979 DBG("%s level %d size: %d,%d,%d offset %d,%d\n", __FUNCTION__
,
980 level
, w
, h
, d
, x
, y
);
982 assert(mt
->level
[level
].slice
== NULL
);
984 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
985 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
986 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
991 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
992 GLuint level
, GLuint img
,
995 if (img
== 0 && level
== 0)
996 assert(x
== 0 && y
== 0);
998 assert(img
< mt
->level
[level
].depth
);
1000 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1001 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1003 DBG("%s level %d img %d pos %d,%d\n",
1004 __FUNCTION__
, level
, img
,
1005 mt
->level
[level
].slice
[img
].x_offset
,
1006 mt
->level
[level
].slice
[img
].y_offset
);
1010 intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt
,
1011 GLuint level
, GLuint slice
,
1012 GLuint
*x
, GLuint
*y
)
1014 assert(slice
< mt
->level
[level
].depth
);
1016 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1017 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1021 * Rendering with tiled buffers requires that the base address of the buffer
1022 * be aligned to a page boundary. For renderbuffers, and sometimes with
1023 * textures, we may want the surface to point at a texture image level that
1024 * isn't at a page boundary.
1026 * This function returns an appropriately-aligned base offset
1027 * according to the tiling restrictions, plus any required x/y offset
1031 intel_miptree_get_tile_offsets(struct intel_mipmap_tree
*mt
,
1032 GLuint level
, GLuint slice
,
1036 struct intel_region
*region
= mt
->region
;
1038 uint32_t mask_x
, mask_y
;
1040 intel_region_get_tile_masks(region
, &mask_x
, &mask_y
, false);
1041 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1043 *tile_x
= x
& mask_x
;
1044 *tile_y
= y
& mask_y
;
1046 return intel_region_get_aligned_offset(region
, x
& ~mask_x
, y
& ~mask_y
,
1051 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1052 struct intel_mipmap_tree
*dst_mt
,
1053 struct intel_mipmap_tree
*src_mt
,
1060 int src_stride
, dst_stride
;
1061 int cpp
= dst_mt
->cpp
;
1063 intel_miptree_map(brw
, src_mt
,
1067 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1070 intel_miptree_map(brw
, dst_mt
,
1074 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1078 DBG("sw blit %s mt %p %p/%d -> %s mt %p %p/%d (%dx%d)\n",
1079 _mesa_get_format_name(src_mt
->format
),
1080 src_mt
, src
, src_stride
,
1081 _mesa_get_format_name(dst_mt
->format
),
1082 dst_mt
, dst
, dst_stride
,
1085 int row_size
= cpp
* width
;
1086 if (src_stride
== row_size
&&
1087 dst_stride
== row_size
) {
1088 memcpy(dst
, src
, row_size
* height
);
1090 for (int i
= 0; i
< height
; i
++) {
1091 memcpy(dst
, src
, row_size
);
1097 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1098 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1100 /* Don't forget to copy the stencil data over, too. We could have skipped
1101 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1102 * shuffling the two data sources in/out of temporary storage instead of
1103 * the direct mapping we get this way.
1105 if (dst_mt
->stencil_mt
) {
1106 assert(src_mt
->stencil_mt
);
1107 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1108 level
, slice
, width
, height
);
1113 intel_miptree_copy_slice(struct brw_context
*brw
,
1114 struct intel_mipmap_tree
*dst_mt
,
1115 struct intel_mipmap_tree
*src_mt
,
1121 mesa_format format
= src_mt
->format
;
1122 uint32_t width
= src_mt
->level
[level
].width
;
1123 uint32_t height
= src_mt
->level
[level
].height
;
1131 assert(depth
< src_mt
->level
[level
].depth
);
1132 assert(src_mt
->format
== dst_mt
->format
);
1134 if (dst_mt
->compressed
) {
1135 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1136 width
= ALIGN(width
, dst_mt
->align_w
);
1139 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1140 * below won't apply since we can't do the depth's Y tiling or the
1141 * stencil's W tiling in the blitter.
1143 if (src_mt
->stencil_mt
) {
1144 intel_miptree_copy_slice_sw(brw
,
1151 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1152 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1153 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1155 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1156 _mesa_get_format_name(src_mt
->format
),
1157 src_mt
, src_x
, src_y
, src_mt
->region
->pitch
,
1158 _mesa_get_format_name(dst_mt
->format
),
1159 dst_mt
, dst_x
, dst_y
, dst_mt
->region
->pitch
,
1162 if (!intel_miptree_blit(brw
,
1163 src_mt
, level
, slice
, 0, 0, false,
1164 dst_mt
, level
, slice
, 0, 0, false,
1165 width
, height
, GL_COPY
)) {
1166 perf_debug("miptree validate blit for %s failed\n",
1167 _mesa_get_format_name(format
));
1169 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1175 * Copies the image's current data to the given miptree, and associates that
1176 * miptree with the image.
1178 * If \c invalidate is true, then the actual image data does not need to be
1179 * copied, but the image still needs to be associated to the new miptree (this
1180 * is set to true if we're about to clear the image).
1183 intel_miptree_copy_teximage(struct brw_context
*brw
,
1184 struct intel_texture_image
*intelImage
,
1185 struct intel_mipmap_tree
*dst_mt
,
1188 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1189 struct intel_texture_object
*intel_obj
=
1190 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1191 int level
= intelImage
->base
.Base
.Level
;
1192 int face
= intelImage
->base
.Base
.Face
;
1193 GLuint depth
= intelImage
->base
.Base
.Depth
;
1196 for (int slice
= 0; slice
< depth
; slice
++) {
1197 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1201 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1202 intel_obj
->needs_validate
= true;
1206 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1207 struct intel_mipmap_tree
*mt
,
1210 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1211 assert(mt
->mcs_mt
== NULL
);
1213 /* Choose the correct format for the MCS buffer. All that really matters
1214 * is that we allocate the right buffer size, since we'll always be
1215 * accessing this miptree using MCS-specific hardware mechanisms, which
1216 * infer the correct format based on num_samples.
1219 switch (num_samples
) {
1221 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1224 format
= MESA_FORMAT_R_UNORM8
;
1227 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1228 * for each sample, plus 8 padding bits).
1230 format
= MESA_FORMAT_R_UINT32
;
1233 assert(!"Unrecognized sample count in intel_miptree_alloc_mcs");
1237 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1239 * "The MCS surface must be stored as Tile Y."
1241 mt
->mcs_mt
= intel_miptree_create(brw
,
1247 mt
->logical_height0
,
1250 0 /* num_samples */,
1251 INTEL_MIPTREE_TILING_Y
);
1253 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1255 * When MCS buffer is enabled and bound to MSRT, it is required that it
1256 * is cleared prior to any rendering.
1258 * Since we don't use the MCS buffer for any purpose other than rendering,
1259 * it makes sense to just clear it immediately upon allocation.
1261 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1263 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1264 memset(data
, 0xff, mt
->mcs_mt
->region
->bo
->size
);
1265 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1266 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1273 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1274 struct intel_mipmap_tree
*mt
)
1276 assert(mt
->mcs_mt
== NULL
);
1278 /* The format of the MCS buffer is opaque to the driver; all that matters
1279 * is that we get its size and pitch right. We'll pretend that the format
1280 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1281 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1282 * the block width and then a further factor of 4. Since an MCS tile
1283 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1284 * we'll need to scale the height down by the block height and then a
1285 * further factor of 8.
1287 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1288 unsigned block_width_px
;
1289 unsigned block_height
;
1290 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1291 unsigned width_divisor
= block_width_px
* 4;
1292 unsigned height_divisor
= block_height
* 8;
1293 unsigned mcs_width
=
1294 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1295 unsigned mcs_height
=
1296 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1297 assert(mt
->logical_depth0
== 1);
1298 mt
->mcs_mt
= intel_miptree_create(brw
,
1307 0 /* num_samples */,
1308 INTEL_MIPTREE_TILING_Y
);
1315 * Helper for intel_miptree_alloc_hiz() that sets
1316 * \c mt->level[level].slice[layer].has_hiz. Return true if and only if
1317 * \c has_hiz was set.
1320 intel_miptree_slice_enable_hiz(struct brw_context
*brw
,
1321 struct intel_mipmap_tree
*mt
,
1327 if (brw
->is_haswell
) {
1328 const struct intel_mipmap_level
*l
= &mt
->level
[level
];
1330 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1331 * and the height is 4 aligned. This allows our HiZ support
1332 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1333 * we can grow the width & height to allow the HiZ op to
1334 * force the proper size alignments.
1336 if (level
> 0 && ((l
->width
& 7) || (l
->height
& 3))) {
1341 mt
->level
[level
].slice
[layer
].has_hiz
= true;
1348 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1349 struct intel_mipmap_tree
*mt
)
1351 assert(mt
->hiz_mt
== NULL
);
1352 mt
->hiz_mt
= intel_miptree_create(brw
,
1358 mt
->logical_height0
,
1362 INTEL_MIPTREE_TILING_ANY
);
1367 /* Mark that all slices need a HiZ resolve. */
1368 struct intel_resolve_map
*head
= &mt
->hiz_map
;
1369 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1370 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1371 if (!intel_miptree_slice_enable_hiz(brw
, mt
, level
, layer
))
1374 head
->next
= malloc(sizeof(*head
->next
));
1375 head
->next
->prev
= head
;
1376 head
->next
->next
= NULL
;
1379 head
->level
= level
;
1380 head
->layer
= layer
;
1381 head
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1389 * Does the miptree slice have hiz enabled?
1392 intel_miptree_slice_has_hiz(struct intel_mipmap_tree
*mt
,
1396 intel_miptree_check_level_layer(mt
, level
, layer
);
1397 return mt
->level
[level
].slice
[layer
].has_hiz
;
1401 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1405 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1408 intel_resolve_map_set(&mt
->hiz_map
,
1409 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1414 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1418 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1421 intel_resolve_map_set(&mt
->hiz_map
,
1422 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1426 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1430 uint32_t end_layer
= mt
->level
[level
].depth
;
1432 for (layer
= 0; layer
< end_layer
; layer
++) {
1433 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1438 intel_miptree_slice_resolve(struct brw_context
*brw
,
1439 struct intel_mipmap_tree
*mt
,
1442 enum gen6_hiz_op need
)
1444 intel_miptree_check_level_layer(mt
, level
, layer
);
1446 struct intel_resolve_map
*item
=
1447 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1449 if (!item
|| item
->need
!= need
)
1452 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1453 intel_resolve_map_remove(item
);
1458 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1459 struct intel_mipmap_tree
*mt
,
1463 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1464 GEN6_HIZ_OP_HIZ_RESOLVE
);
1468 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1469 struct intel_mipmap_tree
*mt
,
1473 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1474 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1478 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1479 struct intel_mipmap_tree
*mt
,
1480 enum gen6_hiz_op need
)
1482 bool did_resolve
= false;
1483 struct intel_resolve_map
*i
, *next
;
1485 for (i
= mt
->hiz_map
.next
; i
; i
= next
) {
1487 if (i
->need
!= need
)
1490 intel_hiz_exec(brw
, mt
, i
->level
, i
->layer
, need
);
1491 intel_resolve_map_remove(i
);
1499 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1500 struct intel_mipmap_tree
*mt
)
1502 return intel_miptree_all_slices_resolve(brw
, mt
,
1503 GEN6_HIZ_OP_HIZ_RESOLVE
);
1507 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1508 struct intel_mipmap_tree
*mt
)
1510 return intel_miptree_all_slices_resolve(brw
, mt
,
1511 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1516 intel_miptree_resolve_color(struct brw_context
*brw
,
1517 struct intel_mipmap_tree
*mt
)
1519 switch (mt
->fast_clear_state
) {
1520 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1521 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1522 /* No resolve needed */
1524 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1525 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1526 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1527 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1528 brw_blorp_resolve_color(brw
, mt
);
1535 * Make it possible to share the region backing the given miptree with another
1536 * process or another miptree.
1538 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1539 * then discard the MCS buffer, if present. We also set the fast_clear_state
1540 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1541 * allocated in the future.
1544 intel_miptree_make_shareable(struct brw_context
*brw
,
1545 struct intel_mipmap_tree
*mt
)
1547 /* MCS buffers are also used for multisample buffers, but we can't resolve
1548 * away a multisample MCS buffer because it's an integral part of how the
1549 * pixel data is stored. Fortunately this code path should never be
1550 * reached for multisample buffers.
1552 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1555 intel_miptree_resolve_color(brw
, mt
);
1556 intel_miptree_release(&mt
->mcs_mt
);
1557 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
1563 * \brief Get pointer offset into stencil buffer.
1565 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1566 * must decode the tile's layout in software.
1569 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1571 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1573 * Even though the returned offset is always positive, the return type is
1575 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1576 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1579 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1581 uint32_t tile_size
= 4096;
1582 uint32_t tile_width
= 64;
1583 uint32_t tile_height
= 64;
1584 uint32_t row_size
= 64 * stride
;
1586 uint32_t tile_x
= x
/ tile_width
;
1587 uint32_t tile_y
= y
/ tile_height
;
1589 /* The byte's address relative to the tile's base addres. */
1590 uint32_t byte_x
= x
% tile_width
;
1591 uint32_t byte_y
= y
% tile_height
;
1593 uintptr_t u
= tile_y
* row_size
1594 + tile_x
* tile_size
1595 + 512 * (byte_x
/ 8)
1597 + 32 * ((byte_y
/ 4) % 2)
1598 + 16 * ((byte_x
/ 4) % 2)
1599 + 8 * ((byte_y
/ 2) % 2)
1600 + 4 * ((byte_x
/ 2) % 2)
1605 /* adjust for bit6 swizzling */
1606 if (((byte_x
/ 8) % 2) == 1) {
1607 if (((byte_y
/ 8) % 2) == 0) {
1619 intel_miptree_updownsample(struct brw_context
*brw
,
1620 struct intel_mipmap_tree
*src
,
1621 struct intel_mipmap_tree
*dst
,
1630 brw_blorp_blit_miptrees(brw
,
1631 src
, 0 /* level */, 0 /* layer */,
1632 dst
, 0 /* level */, 0 /* layer */,
1637 GL_NEAREST
, false, false /*mirror x, y*/);
1639 if (src
->stencil_mt
) {
1640 brw_blorp_blit_miptrees(brw
,
1641 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1642 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1647 GL_NEAREST
, false, false /*mirror x, y*/);
1652 assert_is_flat(struct intel_mipmap_tree
*mt
)
1654 assert(mt
->target
== GL_TEXTURE_2D
);
1655 assert(mt
->first_level
== 0);
1656 assert(mt
->last_level
== 0);
1660 * \brief Downsample from mt to mt->singlesample_mt.
1662 * If the miptree needs no downsample, then skip.
1665 intel_miptree_downsample(struct brw_context
*brw
,
1666 struct intel_mipmap_tree
*mt
)
1668 /* Only flat, renderbuffer-like miptrees are supported. */
1671 if (!mt
->need_downsample
)
1673 intel_miptree_updownsample(brw
,
1674 mt
, mt
->singlesample_mt
,
1676 mt
->logical_height0
);
1677 mt
->need_downsample
= false;
1681 * \brief Upsample from mt->singlesample_mt to mt.
1683 * The upsample is done unconditionally.
1686 intel_miptree_upsample(struct brw_context
*brw
,
1687 struct intel_mipmap_tree
*mt
)
1689 /* Only flat, renderbuffer-like miptrees are supported. */
1691 assert(!mt
->need_downsample
);
1693 intel_miptree_updownsample(brw
,
1694 mt
->singlesample_mt
, mt
,
1696 mt
->logical_height0
);
1700 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
1702 /* CPU accesses to color buffers don't understand fast color clears, so
1703 * resolve any pending fast color clears before we map.
1705 intel_miptree_resolve_color(brw
, mt
);
1707 drm_intel_bo
*bo
= mt
->region
->bo
;
1709 intel_batchbuffer_flush(brw
);
1711 if (mt
->region
->tiling
!= I915_TILING_NONE
)
1712 brw_bo_map_gtt(brw
, bo
, "miptree");
1714 brw_bo_map(brw
, bo
, true, "miptree");
1720 intel_miptree_unmap_raw(struct brw_context
*brw
,
1721 struct intel_mipmap_tree
*mt
)
1723 drm_intel_bo_unmap(mt
->region
->bo
);
1727 intel_miptree_map_gtt(struct brw_context
*brw
,
1728 struct intel_mipmap_tree
*mt
,
1729 struct intel_miptree_map
*map
,
1730 unsigned int level
, unsigned int slice
)
1732 unsigned int bw
, bh
;
1734 unsigned int image_x
, image_y
;
1738 /* For compressed formats, the stride is the number of bytes per
1739 * row of blocks. intel_miptree_get_image_offset() already does
1742 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1743 assert(y
% bh
== 0);
1746 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
1751 /* Note that in the case of cube maps, the caller must have passed the
1752 * slice number referencing the face.
1754 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1758 map
->stride
= mt
->region
->pitch
;
1759 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1762 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1763 map
->x
, map
->y
, map
->w
, map
->h
,
1764 mt
, _mesa_get_format_name(mt
->format
),
1765 x
, y
, map
->ptr
, map
->stride
);
1769 intel_miptree_unmap_gtt(struct brw_context
*brw
,
1770 struct intel_mipmap_tree
*mt
,
1771 struct intel_miptree_map
*map
,
1775 intel_miptree_unmap_raw(brw
, mt
);
1779 intel_miptree_map_blit(struct brw_context
*brw
,
1780 struct intel_mipmap_tree
*mt
,
1781 struct intel_miptree_map
*map
,
1782 unsigned int level
, unsigned int slice
)
1784 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
1788 INTEL_MIPTREE_TILING_NONE
);
1790 fprintf(stderr
, "Failed to allocate blit temporary\n");
1793 map
->stride
= map
->mt
->region
->pitch
;
1795 if (!intel_miptree_blit(brw
,
1797 map
->x
, map
->y
, false,
1800 map
->w
, map
->h
, GL_COPY
)) {
1801 fprintf(stderr
, "Failed to blit\n");
1805 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
1807 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1808 map
->x
, map
->y
, map
->w
, map
->h
,
1809 mt
, _mesa_get_format_name(mt
->format
),
1810 level
, slice
, map
->ptr
, map
->stride
);
1815 intel_miptree_release(&map
->mt
);
1821 intel_miptree_unmap_blit(struct brw_context
*brw
,
1822 struct intel_mipmap_tree
*mt
,
1823 struct intel_miptree_map
*map
,
1827 struct gl_context
*ctx
= &brw
->ctx
;
1829 intel_miptree_unmap_raw(brw
, map
->mt
);
1831 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1832 bool ok
= intel_miptree_blit(brw
,
1836 map
->x
, map
->y
, false,
1837 map
->w
, map
->h
, GL_COPY
);
1838 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
1841 intel_miptree_release(&map
->mt
);
1846 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
1849 intel_miptree_map_movntdqa(struct brw_context
*brw
,
1850 struct intel_mipmap_tree
*mt
,
1851 struct intel_miptree_map
*map
,
1852 unsigned int level
, unsigned int slice
)
1854 assert(map
->mode
& GL_MAP_READ_BIT
);
1855 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
1857 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1858 map
->x
, map
->y
, map
->w
, map
->h
,
1859 mt
, _mesa_get_format_name(mt
->format
),
1860 level
, slice
, map
->ptr
, map
->stride
);
1862 /* Map the original image */
1865 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1869 void *src
= intel_miptree_map_raw(brw
, mt
);
1872 src
+= image_y
* mt
->region
->pitch
;
1873 src
+= image_x
* mt
->region
->cpp
;
1875 /* Due to the pixel offsets for the particular image being mapped, our
1876 * src pointer may not be 16-byte aligned. However, if the pitch is
1877 * divisible by 16, then the amount by which it's misaligned will remain
1878 * consistent from row to row.
1880 assert((mt
->region
->pitch
% 16) == 0);
1881 const int misalignment
= ((uintptr_t) src
) & 15;
1883 /* Create an untiled temporary buffer for the mapping. */
1884 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
1886 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
1888 map
->buffer
= malloc(map
->stride
* map
->h
);
1889 /* Offset the destination so it has the same misalignment as src. */
1890 map
->ptr
= map
->buffer
+ misalignment
;
1892 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
1894 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1895 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
1896 void *src_ptr
= src
+ y
* mt
->region
->pitch
;
1898 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
1901 intel_miptree_unmap_raw(brw
, mt
);
1905 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
1906 struct intel_mipmap_tree
*mt
,
1907 struct intel_miptree_map
*map
,
1918 intel_miptree_map_s8(struct brw_context
*brw
,
1919 struct intel_mipmap_tree
*mt
,
1920 struct intel_miptree_map
*map
,
1921 unsigned int level
, unsigned int slice
)
1923 map
->stride
= map
->w
;
1924 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1928 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1929 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1930 * invalidate is set, since we'll be writing the whole rectangle from our
1931 * temporary buffer back out.
1933 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1934 uint8_t *untiled_s8_map
= map
->ptr
;
1935 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1936 unsigned int image_x
, image_y
;
1938 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1940 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1941 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1942 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1943 x
+ image_x
+ map
->x
,
1944 y
+ image_y
+ map
->y
,
1945 brw
->has_swizzling
);
1946 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
1950 intel_miptree_unmap_raw(brw
, mt
);
1952 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
1953 map
->x
, map
->y
, map
->w
, map
->h
,
1954 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
1956 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1957 map
->x
, map
->y
, map
->w
, map
->h
,
1958 mt
, map
->ptr
, map
->stride
);
1963 intel_miptree_unmap_s8(struct brw_context
*brw
,
1964 struct intel_mipmap_tree
*mt
,
1965 struct intel_miptree_map
*map
,
1969 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1970 unsigned int image_x
, image_y
;
1971 uint8_t *untiled_s8_map
= map
->ptr
;
1972 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1974 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1976 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1977 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1978 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1981 brw
->has_swizzling
);
1982 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
1986 intel_miptree_unmap_raw(brw
, mt
);
1993 intel_miptree_map_etc(struct brw_context
*brw
,
1994 struct intel_mipmap_tree
*mt
,
1995 struct intel_miptree_map
*map
,
1999 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2000 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2001 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2004 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2005 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2007 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2008 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2009 map
->w
, map
->h
, 1));
2010 map
->ptr
= map
->buffer
;
2014 intel_miptree_unmap_etc(struct brw_context
*brw
,
2015 struct intel_mipmap_tree
*mt
,
2016 struct intel_miptree_map
*map
,
2022 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2027 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2028 + image_y
* mt
->region
->pitch
2029 + image_x
* mt
->region
->cpp
;
2031 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2032 _mesa_etc1_unpack_rgba8888(dst
, mt
->region
->pitch
,
2033 map
->ptr
, map
->stride
,
2036 _mesa_unpack_etc2_format(dst
, mt
->region
->pitch
,
2037 map
->ptr
, map
->stride
,
2038 map
->w
, map
->h
, mt
->etc_format
);
2040 intel_miptree_unmap_raw(brw
, mt
);
2045 * Mapping function for packed depth/stencil miptrees backed by real separate
2046 * miptrees for depth and stencil.
2048 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2049 * separate from the depth buffer. Yet at the GL API level, we have to expose
2050 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2051 * be able to map that memory for texture storage and glReadPixels-type
2052 * operations. We give Mesa core that access by mallocing a temporary and
2053 * copying the data between the actual backing store and the temporary.
2056 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2057 struct intel_mipmap_tree
*mt
,
2058 struct intel_miptree_map
*map
,
2059 unsigned int level
, unsigned int slice
)
2061 struct intel_mipmap_tree
*z_mt
= mt
;
2062 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2063 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2064 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2066 map
->stride
= map
->w
* packed_bpp
;
2067 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2071 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2072 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2073 * invalidate is set, since we'll be writing the whole rectangle from our
2074 * temporary buffer back out.
2076 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2077 uint32_t *packed_map
= map
->ptr
;
2078 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2079 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2080 unsigned int s_image_x
, s_image_y
;
2081 unsigned int z_image_x
, z_image_y
;
2083 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2084 &s_image_x
, &s_image_y
);
2085 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2086 &z_image_x
, &z_image_y
);
2088 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2089 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2090 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2091 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
2094 brw
->has_swizzling
);
2095 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2096 (z_mt
->region
->pitch
/ 4) +
2097 (map_x
+ z_image_x
));
2098 uint8_t s
= s_map
[s_offset
];
2099 uint32_t z
= z_map
[z_offset
];
2101 if (map_z32f_x24s8
) {
2102 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2103 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2105 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2110 intel_miptree_unmap_raw(brw
, s_mt
);
2111 intel_miptree_unmap_raw(brw
, z_mt
);
2113 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2115 map
->x
, map
->y
, map
->w
, map
->h
,
2116 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2117 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2118 map
->ptr
, map
->stride
);
2120 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
2121 map
->x
, map
->y
, map
->w
, map
->h
,
2122 mt
, map
->ptr
, map
->stride
);
2127 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2128 struct intel_mipmap_tree
*mt
,
2129 struct intel_miptree_map
*map
,
2133 struct intel_mipmap_tree
*z_mt
= mt
;
2134 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2135 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2137 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2138 uint32_t *packed_map
= map
->ptr
;
2139 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2140 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2141 unsigned int s_image_x
, s_image_y
;
2142 unsigned int z_image_x
, z_image_y
;
2144 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2145 &s_image_x
, &s_image_y
);
2146 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2147 &z_image_x
, &z_image_y
);
2149 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2150 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2151 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
2152 x
+ s_image_x
+ map
->x
,
2153 y
+ s_image_y
+ map
->y
,
2154 brw
->has_swizzling
);
2155 ptrdiff_t z_offset
= ((y
+ z_image_y
) *
2156 (z_mt
->region
->pitch
/ 4) +
2159 if (map_z32f_x24s8
) {
2160 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2161 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2163 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2164 s_map
[s_offset
] = packed
>> 24;
2165 z_map
[z_offset
] = packed
;
2170 intel_miptree_unmap_raw(brw
, s_mt
);
2171 intel_miptree_unmap_raw(brw
, z_mt
);
2173 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2175 map
->x
, map
->y
, map
->w
, map
->h
,
2176 z_mt
, _mesa_get_format_name(z_mt
->format
),
2177 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2178 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2179 map
->ptr
, map
->stride
);
2186 * Create and attach a map to the miptree at (level, slice). Return the
2189 static struct intel_miptree_map
*
2190 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2199 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2204 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2205 mt
->level
[level
].slice
[slice
].map
= map
;
2217 * Release the map at (level, slice).
2220 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2224 struct intel_miptree_map
**map
;
2226 map
= &mt
->level
[level
].slice
[slice
].map
;
2232 can_blit_slice(struct intel_mipmap_tree
*mt
,
2233 unsigned int level
, unsigned int slice
)
2237 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2238 if (image_x
>= 32768 || image_y
>= 32768)
2241 if (mt
->region
->pitch
>= 32768)
2248 intel_miptree_map_singlesample(struct brw_context
*brw
,
2249 struct intel_mipmap_tree
*mt
,
2260 struct intel_miptree_map
*map
;
2262 assert(mt
->num_samples
<= 1);
2264 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2271 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2272 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2273 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2276 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2277 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2278 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2279 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2280 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2281 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2282 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2284 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2285 else if (brw
->has_llc
&&
2286 !(mode
& GL_MAP_WRITE_BIT
) &&
2288 (mt
->region
->tiling
== I915_TILING_X
||
2289 (brw
->gen
>= 6 && mt
->region
->tiling
== I915_TILING_Y
)) &&
2290 can_blit_slice(mt
, level
, slice
)) {
2291 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2292 } else if (mt
->region
->tiling
!= I915_TILING_NONE
&&
2293 mt
->region
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2294 assert(can_blit_slice(mt
, level
, slice
));
2295 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2297 } else if (!(mode
& GL_MAP_WRITE_BIT
) && !mt
->compressed
) {
2298 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2301 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2304 *out_ptr
= map
->ptr
;
2305 *out_stride
= map
->stride
;
2307 if (map
->ptr
== NULL
)
2308 intel_miptree_release_map(mt
, level
, slice
);
2312 intel_miptree_unmap_singlesample(struct brw_context
*brw
,
2313 struct intel_mipmap_tree
*mt
,
2317 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2319 assert(mt
->num_samples
<= 1);
2324 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
2325 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2327 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2328 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2329 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2330 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2331 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2332 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2333 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2334 } else if (map
->mt
) {
2335 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2337 } else if (map
->buffer
) {
2338 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2341 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2344 intel_miptree_release_map(mt
, level
, slice
);
2348 intel_miptree_map_multisample(struct brw_context
*brw
,
2349 struct intel_mipmap_tree
*mt
,
2360 struct gl_context
*ctx
= &brw
->ctx
;
2361 struct intel_miptree_map
*map
;
2363 assert(mt
->num_samples
> 1);
2365 /* Only flat, renderbuffer-like miptrees are supported. */
2366 if (mt
->target
!= GL_TEXTURE_2D
||
2367 mt
->first_level
!= 0 ||
2368 mt
->last_level
!= 0) {
2369 _mesa_problem(ctx
, "attempt to map a multisample miptree for "
2370 "which (target, first_level, last_level != "
2371 "(GL_TEXTURE_2D, 0, 0)");
2375 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2379 if (!mt
->singlesample_mt
) {
2380 mt
->singlesample_mt
=
2381 intel_miptree_create_for_renderbuffer(brw
,
2384 mt
->logical_height0
,
2386 if (!mt
->singlesample_mt
)
2389 map
->singlesample_mt_is_tmp
= true;
2390 mt
->need_downsample
= true;
2393 intel_miptree_downsample(brw
, mt
);
2394 intel_miptree_map_singlesample(brw
, mt
->singlesample_mt
,
2398 out_ptr
, out_stride
);
2402 intel_miptree_release_map(mt
, level
, slice
);
2408 intel_miptree_unmap_multisample(struct brw_context
*brw
,
2409 struct intel_mipmap_tree
*mt
,
2413 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2415 assert(mt
->num_samples
> 1);
2420 intel_miptree_unmap_singlesample(brw
, mt
->singlesample_mt
, level
, slice
);
2422 mt
->need_downsample
= false;
2423 if (map
->mode
& GL_MAP_WRITE_BIT
)
2424 intel_miptree_upsample(brw
, mt
);
2426 if (map
->singlesample_mt_is_tmp
)
2427 intel_miptree_release(&mt
->singlesample_mt
);
2429 intel_miptree_release_map(mt
, level
, slice
);
2433 intel_miptree_map(struct brw_context
*brw
,
2434 struct intel_mipmap_tree
*mt
,
2445 if (mt
->num_samples
<= 1)
2446 intel_miptree_map_singlesample(brw
, mt
,
2450 out_ptr
, out_stride
);
2452 intel_miptree_map_multisample(brw
, mt
,
2456 out_ptr
, out_stride
);
2460 intel_miptree_unmap(struct brw_context
*brw
,
2461 struct intel_mipmap_tree
*mt
,
2465 if (mt
->num_samples
<= 1)
2466 intel_miptree_unmap_singlesample(brw
, mt
, level
, slice
);
2468 intel_miptree_unmap_multisample(brw
, mt
, level
, slice
);