2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_resolve_map.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
);
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 enum intel_aux_disable aux_disable
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (aux_disable
& INTEL_AUX_DISABLE_MCS
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
105 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
108 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
109 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
111 * - Support is limited to tiled render targets.
113 * Gen9 changes the restriction to Y-tile only.
116 return tiling
== I915_TILING_Y
;
117 else if (brw
->gen
>= 7)
118 return tiling
!= I915_TILING_NONE
;
124 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
125 * can be used. This doesn't (and should not) inspect any of the properties of
128 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
129 * beneath the "Fast Color Clear" bullet (p326):
131 * - Support is for non-mip-mapped and non-array surface types only.
133 * And then later, on p327:
135 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
138 * From the Skylake documentation, it is made clear that X-tiling is no longer
141 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
145 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
146 const struct intel_mipmap_tree
*mt
)
148 /* MCS support does not exist prior to Gen7 */
152 if (mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
)
155 /* This function applies only to non-multisampled render targets. */
156 if (mt
->num_samples
> 1)
159 /* MCS is only supported for color buffers */
160 switch (_mesa_get_format_base_format(mt
->format
)) {
161 case GL_DEPTH_COMPONENT
:
162 case GL_DEPTH_STENCIL
:
163 case GL_STENCIL_INDEX
:
167 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
170 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
171 const bool arrayed
= mt
->physical_depth0
!= 1;
174 /* Multisample surfaces with the CMS layout are not layered surfaces,
175 * yet still have physical_depth0 > 1. Assert that we don't
176 * accidentally reject a multisampled surface here. We should have
177 * rejected it earlier by explicitly checking the sample count.
179 assert(mt
->num_samples
<= 1);
182 /* Handle the hardware restrictions...
184 * All GENs have the following restriction: "MCS buffer for non-MSRT is
185 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
187 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
188 * Non-MultiSampler Render Target Restrictions) Support is for
189 * non-mip-mapped and non-array surface types only.
191 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
192 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
193 * surfaces are supported with MCS buffer layout with these alignments in
194 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
196 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
197 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
198 * surfaces are supported with MCS buffer layout with these alignments in
199 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
201 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
204 /* There's no point in using an MCS buffer if the surface isn't in a
207 if (!brw
->format_supported_as_render_target
[mt
->format
])
211 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
212 const enum isl_format isl_format
=
213 brw_isl_format_for_mesa_format(linear_format
);
214 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
219 /* On Gen9 support for color buffer compression was extended to single
220 * sampled surfaces. This is a helper considering both auxiliary buffer
221 * type and number of samples telling if the given miptree represents
222 * the new single sampled case - also called lossless compression.
225 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
226 const struct intel_mipmap_tree
*mt
)
228 /* Only available from Gen9 onwards. */
232 /* Compression always requires auxiliary buffer. */
236 /* Single sample compression is represented re-using msaa compression
237 * layout type: "Compressed Multisampled Surfaces".
239 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
242 /* And finally distinguish between msaa and single sample case. */
243 return mt
->num_samples
<= 1;
247 intel_miptree_supports_lossless_compressed(struct brw_context
*brw
,
248 const struct intel_mipmap_tree
*mt
)
250 /* For now compression is only enabled for integer formats even though
251 * there exist supported floating point formats also. This is a heuristic
252 * decision based on current public benchmarks. In none of the cases these
253 * formats provided any improvement but a few cases were seen to regress.
254 * Hence these are left to to be enabled in the future when they are known
257 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
260 /* Fast clear mechanism and lossless compression go hand in hand. */
261 if (!intel_miptree_supports_non_msrt_fast_clear(brw
, mt
))
264 /* Fast clear can be also used to clear srgb surfaces by using equivalent
265 * linear format. This trick, however, can't be extended to be used with
266 * lossless compression and therefore a check is needed to see if the format
269 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
273 * Determine depth format corresponding to a depth+stencil format,
274 * for separate stencil.
277 intel_depth_format_for_depthstencil_format(mesa_format format
) {
279 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
280 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
281 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
282 return MESA_FORMAT_Z_FLOAT32
;
290 * @param for_bo Indicates that the caller is
291 * intel_miptree_create_for_bo(). If true, then do not create
294 static struct intel_mipmap_tree
*
295 intel_miptree_create_layout(struct brw_context
*brw
,
304 uint32_t layout_flags
)
306 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
310 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
311 _mesa_enum_to_string(target
),
312 _mesa_get_format_name(format
),
313 first_level
, last_level
, depth0
, mt
);
315 if (target
== GL_TEXTURE_1D_ARRAY
)
316 assert(height0
== 1);
320 mt
->first_level
= first_level
;
321 mt
->last_level
= last_level
;
322 mt
->logical_width0
= width0
;
323 mt
->logical_height0
= height0
;
324 mt
->logical_depth0
= depth0
;
325 mt
->aux_disable
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0 ?
326 INTEL_AUX_DISABLE_ALL
: INTEL_AUX_DISABLE_NONE
;
327 mt
->aux_disable
|= INTEL_AUX_DISABLE_CCS
;
328 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
329 exec_list_make_empty(&mt
->hiz_map
);
330 exec_list_make_empty(&mt
->color_resolve_map
);
331 mt
->cpp
= _mesa_get_format_bytes(format
);
332 mt
->num_samples
= num_samples
;
333 mt
->compressed
= _mesa_is_format_compressed(format
);
334 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
337 int depth_multiply
= 1;
338 if (num_samples
> 1) {
339 /* Adjust width/height/depth for MSAA */
340 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->aux_disable
);
341 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
342 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
343 * "If the surface is multisampled and it is a depth or stencil
344 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
345 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
348 * +----------------------------------------------------------------+
349 * | Num Multisamples | W_l = | H_l = |
350 * +----------------------------------------------------------------+
351 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
352 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
353 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
354 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
355 * +----------------------------------------------------------------+
358 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
359 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
360 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
362 * Another more complicated explanation for these adjustments comes
363 * from the Sandybridge PRM, volume 4, part 1, page 31:
365 * "Any of the other messages (sample*, LOD, load4) used with a
366 * (4x) multisampled surface will in-effect sample a surface with
367 * double the height and width as that indicated in the surface
368 * state. Each pixel position on the original-sized surface is
369 * replaced with a 2x2 of samples with the following arrangement:
374 * Thus, when sampling from a multisampled texture, it behaves as
375 * though the layout in memory for (x,y,sample) is:
377 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
378 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
380 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
381 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
383 * However, the actual layout of multisampled data in memory is:
385 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
386 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
388 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
389 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
391 * This pattern repeats for each 2x2 pixel block.
393 * As a result, when calculating the size of our 4-sample buffer for
394 * an odd width or height, we have to align before scaling up because
395 * sample 3 is in that bottom right 2x2 block.
397 switch (num_samples
) {
399 assert(brw
->gen
>= 8);
400 width0
= ALIGN(width0
, 2) * 2;
401 height0
= ALIGN(height0
, 2);
404 width0
= ALIGN(width0
, 2) * 2;
405 height0
= ALIGN(height0
, 2) * 2;
408 width0
= ALIGN(width0
, 2) * 4;
409 height0
= ALIGN(height0
, 2) * 2;
412 width0
= ALIGN(width0
, 2) * 4;
413 height0
= ALIGN(height0
, 2) * 4;
416 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
419 unreachable("not reached");
422 /* Non-interleaved */
423 depth_multiply
= num_samples
;
424 depth0
*= depth_multiply
;
428 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
429 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
430 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
431 * used on Gen8 to make it pick a qpitch value which doesn't include space
432 * for the mipmaps. On Gen9 this is not necessary because it will
433 * automatically pick a packed qpitch value whenever mt->first_level ==
435 * TODO: can we use it elsewhere?
436 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
439 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
441 switch (mt
->msaa_layout
) {
442 case INTEL_MSAA_LAYOUT_NONE
:
443 case INTEL_MSAA_LAYOUT_IMS
:
444 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
446 case INTEL_MSAA_LAYOUT_UMS
:
447 case INTEL_MSAA_LAYOUT_CMS
:
448 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
453 if (target
== GL_TEXTURE_CUBE_MAP
)
454 assert(depth0
== 6 * depth_multiply
);
456 mt
->physical_width0
= width0
;
457 mt
->physical_height0
= height0
;
458 mt
->physical_depth0
= depth0
;
460 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
461 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
462 (brw
->must_use_separate_stencil
||
463 (brw
->has_separate_stencil
&&
464 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
465 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
467 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
|
468 MIPTREE_LAYOUT_TILING_ANY
;
471 mt
->stencil_mt
= intel_miptree_create(brw
,
482 if (!mt
->stencil_mt
) {
483 intel_miptree_release(&mt
);
486 mt
->stencil_mt
->r8stencil_needs_update
= true;
488 /* Fix up the Z miptree format for how we're splitting out separate
489 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
491 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
494 if (format
== mt
->format
) {
495 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
496 _mesa_get_format_name(mt
->format
));
500 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
501 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
504 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
505 * multisampled or have an AUX buffer attached to it.
507 * GEN | MSRT | AUX_CCS_* or AUX_MCS
508 * -------------------------------------------
509 * 9 | HALIGN_16 | HALIGN_16
510 * 8 | HALIGN_ANY | HALIGN_16
514 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
515 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
516 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
517 } else if (brw
->gen
>= 9 && num_samples
> 1) {
518 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
520 const UNUSED
bool is_lossless_compressed_aux
=
521 brw
->gen
>= 9 && num_samples
== 1 &&
522 mt
->format
== MESA_FORMAT_R_UINT32
;
524 /* For now, nothing else has this requirement */
525 assert(is_lossless_compressed_aux
||
526 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
529 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
530 intel_miptree_release(&mt
);
534 if (mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
)
535 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
542 * Choose an appropriate uncompressed format for a requested
543 * compressed format, if unsupported.
546 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
548 /* No need to lower ETC formats on these platforms,
549 * they are supported natively.
551 if (brw
->gen
>= 8 || brw
->is_baytrail
)
555 case MESA_FORMAT_ETC1_RGB8
:
556 return MESA_FORMAT_R8G8B8X8_UNORM
;
557 case MESA_FORMAT_ETC2_RGB8
:
558 return MESA_FORMAT_R8G8B8X8_UNORM
;
559 case MESA_FORMAT_ETC2_SRGB8
:
560 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
561 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
562 return MESA_FORMAT_B8G8R8A8_SRGB
;
563 case MESA_FORMAT_ETC2_RGBA8_EAC
:
564 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
565 return MESA_FORMAT_R8G8B8A8_UNORM
;
566 case MESA_FORMAT_ETC2_R11_EAC
:
567 return MESA_FORMAT_R_UNORM16
;
568 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
569 return MESA_FORMAT_R_SNORM16
;
570 case MESA_FORMAT_ETC2_RG11_EAC
:
571 return MESA_FORMAT_R16G16_UNORM
;
572 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
573 return MESA_FORMAT_R16G16_SNORM
;
575 /* Non ETC1 / ETC2 format */
580 static struct intel_mipmap_tree
*
581 miptree_create(struct brw_context
*brw
,
590 uint32_t layout_flags
)
592 struct intel_mipmap_tree
*mt
;
593 mesa_format tex_format
= format
;
594 mesa_format etc_format
= MESA_FORMAT_NONE
;
595 uint32_t alloc_flags
= 0;
597 format
= intel_lower_compressed_format(brw
, format
);
599 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
601 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
602 mt
= intel_miptree_create_layout(brw
, target
, format
,
603 first_level
, last_level
, width0
,
604 height0
, depth0
, num_samples
,
609 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
610 mt
->tiling
= I915_TILING_Y
;
612 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
613 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
615 mt
->etc_format
= etc_format
;
617 if (format
== MESA_FORMAT_S_UINT8
) {
618 /* Align to size of W tile, 64x64. */
619 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "miptree",
620 ALIGN(mt
->total_width
, 64),
621 ALIGN(mt
->total_height
, 64),
622 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
625 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "miptree",
626 mt
->total_width
, mt
->total_height
,
627 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
634 struct intel_mipmap_tree
*
635 intel_miptree_create(struct brw_context
*brw
,
644 uint32_t layout_flags
)
646 struct intel_mipmap_tree
*mt
= miptree_create(
648 first_level
, last_level
,
649 width0
, height0
, depth0
, num_samples
,
652 /* If the BO is too large to fit in the aperture, we need to use the
653 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
654 * handle Y-tiling, so we need to fall back to X.
656 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
657 mt
->tiling
== I915_TILING_Y
) {
658 const uint32_t alloc_flags
=
659 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
660 BO_ALLOC_FOR_RENDER
: 0;
661 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
662 mt
->total_width
, mt
->total_height
);
664 mt
->tiling
= I915_TILING_X
;
665 brw_bo_unreference(mt
->bo
);
666 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "miptree",
667 mt
->total_width
, mt
->total_height
, mt
->cpp
,
668 mt
->tiling
, &mt
->pitch
, alloc_flags
);
674 intel_miptree_release(&mt
);
679 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
680 assert(mt
->num_samples
> 1);
681 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
682 intel_miptree_release(&mt
);
687 /* If this miptree is capable of supporting fast color clears, set
688 * fast_clear_state appropriately to ensure that fast clears will occur.
689 * Allocation of the MCS miptree will be deferred until the first fast
690 * clear actually occurs or when compressed single sampled buffer is
691 * written by the GPU for the first time.
693 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
694 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
695 mt
->aux_disable
&= ~INTEL_AUX_DISABLE_CCS
;
696 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
698 /* On Gen9+ clients are not currently capable of consuming compressed
699 * single-sampled buffers. Disabling compression allows us to skip
702 const bool lossless_compression_disabled
= INTEL_DEBUG
& DEBUG_NO_RBC
;
703 const bool is_lossless_compressed
=
704 unlikely(!lossless_compression_disabled
) &&
705 brw
->gen
>= 9 && !mt
->is_scanout
&&
706 intel_miptree_supports_lossless_compressed(brw
, mt
);
708 if (is_lossless_compressed
) {
709 intel_miptree_alloc_non_msrt_mcs(brw
, mt
, is_lossless_compressed
);
716 struct intel_mipmap_tree
*
717 intel_miptree_create_for_bo(struct brw_context
*brw
,
725 uint32_t layout_flags
)
727 struct intel_mipmap_tree
*mt
;
728 uint32_t tiling
, swizzle
;
731 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
733 /* Nothing will be able to use this miptree with the BO if the offset isn't
736 if (tiling
!= I915_TILING_NONE
)
737 assert(offset
% 4096 == 0);
739 /* miptrees can't handle negative pitch. If you need flipping of images,
740 * that's outside of the scope of the mt.
744 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
746 /* The BO already has a tiling format and we shouldn't confuse the lower
747 * layers by making it try to find a tiling format again.
749 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
750 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
752 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
753 mt
= intel_miptree_create_layout(brw
, target
, format
,
755 width
, height
, depth
, 0,
760 brw_bo_reference(bo
);
770 * For a singlesample renderbuffer, this simply wraps the given BO with a
773 * For a multisample renderbuffer, this wraps the window system's
774 * (singlesample) BO with a singlesample miptree attached to the
775 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
776 * that will contain the actual rendering (which is lazily resolved to
777 * irb->singlesample_mt).
780 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
781 struct intel_renderbuffer
*irb
,
783 uint32_t width
, uint32_t height
,
786 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
787 struct intel_mipmap_tree
*multisample_mt
= NULL
;
788 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
789 mesa_format format
= rb
->Format
;
790 int num_samples
= rb
->NumSamples
;
792 /* Only the front and back buffers, which are color buffers, are allocated
793 * through the image loader.
795 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
796 _mesa_get_format_base_format(format
) == GL_RGBA
);
798 singlesample_mt
= intel_miptree_create_for_bo(intel
,
806 MIPTREE_LAYOUT_FOR_SCANOUT
);
807 if (!singlesample_mt
)
810 /* If this miptree is capable of supporting fast color clears, set
811 * mcs_state appropriately to ensure that fast clears will occur.
812 * Allocation of the MCS miptree will be deferred until the first fast
813 * clear actually occurs.
815 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
816 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
817 singlesample_mt
->aux_disable
&= ~INTEL_AUX_DISABLE_CCS
;
820 if (num_samples
== 0) {
821 intel_miptree_release(&irb
->mt
);
822 irb
->mt
= singlesample_mt
;
824 assert(!irb
->singlesample_mt
);
826 intel_miptree_release(&irb
->singlesample_mt
);
827 irb
->singlesample_mt
= singlesample_mt
;
830 irb
->mt
->logical_width0
!= width
||
831 irb
->mt
->logical_height0
!= height
) {
832 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
840 irb
->need_downsample
= false;
841 intel_miptree_release(&irb
->mt
);
842 irb
->mt
= multisample_mt
;
848 intel_miptree_release(&irb
->singlesample_mt
);
849 intel_miptree_release(&irb
->mt
);
853 struct intel_mipmap_tree
*
854 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
858 uint32_t num_samples
)
860 struct intel_mipmap_tree
*mt
;
863 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
864 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
865 MIPTREE_LAYOUT_TILING_ANY
|
866 MIPTREE_LAYOUT_FOR_SCANOUT
;
868 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
869 width
, height
, depth
, num_samples
,
874 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
875 ok
= intel_miptree_alloc_hiz(brw
, mt
);
883 intel_miptree_release(&mt
);
888 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
889 struct intel_mipmap_tree
*src
)
894 intel_miptree_release(dst
);
898 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
905 intel_miptree_hiz_buffer_free(struct intel_miptree_hiz_buffer
*hiz_buf
)
911 intel_miptree_release(&hiz_buf
->mt
);
913 brw_bo_unreference(hiz_buf
->aux_base
.bo
);
919 intel_miptree_release(struct intel_mipmap_tree
**mt
)
924 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
925 if (--(*mt
)->refcount
<= 0) {
928 DBG("%s deleting %p\n", __func__
, *mt
);
930 brw_bo_unreference((*mt
)->bo
);
931 intel_miptree_release(&(*mt
)->stencil_mt
);
932 intel_miptree_release(&(*mt
)->r8stencil_mt
);
933 intel_miptree_hiz_buffer_free((*mt
)->hiz_buf
);
934 if ((*mt
)->mcs_buf
) {
935 brw_bo_unreference((*mt
)->mcs_buf
->bo
);
936 free((*mt
)->mcs_buf
);
938 intel_resolve_map_clear(&(*mt
)->hiz_map
);
939 intel_resolve_map_clear(&(*mt
)->color_resolve_map
);
941 intel_miptree_release(&(*mt
)->plane
[0]);
942 intel_miptree_release(&(*mt
)->plane
[1]);
944 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
945 free((*mt
)->level
[i
].slice
);
955 intel_get_image_dims(struct gl_texture_image
*image
,
956 int *width
, int *height
, int *depth
)
958 switch (image
->TexObject
->Target
) {
959 case GL_TEXTURE_1D_ARRAY
:
960 /* For a 1D Array texture the OpenGL API will treat the image height as
961 * the number of array slices. For Intel hardware, we treat the 1D array
962 * as a 2D Array with a height of 1. So, here we want to swap image
965 assert(image
->Depth
== 1);
966 *width
= image
->Width
;
968 *depth
= image
->Height
;
970 case GL_TEXTURE_CUBE_MAP
:
971 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
972 * though we really have 6 slices.
974 assert(image
->Depth
== 1);
975 *width
= image
->Width
;
976 *height
= image
->Height
;
980 *width
= image
->Width
;
981 *height
= image
->Height
;
982 *depth
= image
->Depth
;
988 * Can the image be pulled into a unified mipmap tree? This mirrors
989 * the completeness test in a lot of ways.
991 * Not sure whether I want to pass gl_texture_image here.
994 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
995 struct gl_texture_image
*image
)
997 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
998 GLuint level
= intelImage
->base
.Base
.Level
;
999 int width
, height
, depth
;
1001 /* glTexImage* choose the texture object based on the target passed in, and
1002 * objects can't change targets over their lifetimes, so this should be
1005 assert(image
->TexObject
->Target
== mt
->target
);
1007 mesa_format mt_format
= mt
->format
;
1008 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1009 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1010 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1011 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1012 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1013 mt_format
= mt
->etc_format
;
1015 if (image
->TexFormat
!= mt_format
)
1018 intel_get_image_dims(image
, &width
, &height
, &depth
);
1020 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1023 int level_depth
= mt
->level
[level
].depth
;
1024 if (mt
->num_samples
> 1) {
1025 switch (mt
->msaa_layout
) {
1026 case INTEL_MSAA_LAYOUT_NONE
:
1027 case INTEL_MSAA_LAYOUT_IMS
:
1029 case INTEL_MSAA_LAYOUT_UMS
:
1030 case INTEL_MSAA_LAYOUT_CMS
:
1031 level_depth
/= mt
->num_samples
;
1036 /* Test image dimensions against the base level image adjusted for
1037 * minification. This will also catch images not present in the
1038 * tree, changed targets, etc.
1040 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1041 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1042 depth
!= level_depth
) {
1046 if (image
->NumSamples
!= mt
->num_samples
)
1054 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1056 GLuint x
, GLuint y
, GLuint d
)
1058 mt
->level
[level
].depth
= d
;
1059 mt
->level
[level
].level_x
= x
;
1060 mt
->level
[level
].level_y
= y
;
1062 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1065 assert(mt
->level
[level
].slice
== NULL
);
1067 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1068 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1069 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1074 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1075 GLuint level
, GLuint img
,
1078 if (img
== 0 && level
== 0)
1079 assert(x
== 0 && y
== 0);
1081 assert(img
< mt
->level
[level
].depth
);
1083 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1084 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1086 DBG("%s level %d img %d pos %d,%d\n",
1087 __func__
, level
, img
,
1088 mt
->level
[level
].slice
[img
].x_offset
,
1089 mt
->level
[level
].slice
[img
].y_offset
);
1093 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1094 GLuint level
, GLuint slice
,
1095 GLuint
*x
, GLuint
*y
)
1097 assert(slice
< mt
->level
[level
].depth
);
1099 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1100 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1105 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1106 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1107 * and tile_h is set to 1.
1110 intel_get_tile_dims(uint32_t tiling
, uint32_t cpp
,
1111 uint32_t *tile_w
, uint32_t *tile_h
)
1122 case I915_TILING_NONE
:
1127 unreachable("not reached");
1133 * This function computes masks that may be used to select the bits of the X
1134 * and Y coordinates that indicate the offset within a tile. If the BO is
1135 * untiled, the masks are set to 0.
1138 intel_get_tile_masks(uint32_t tiling
, uint32_t cpp
,
1139 uint32_t *mask_x
, uint32_t *mask_y
)
1141 uint32_t tile_w_bytes
, tile_h
;
1143 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1145 *mask_x
= tile_w_bytes
/ cpp
- 1;
1146 *mask_y
= tile_h
- 1;
1150 * Compute the offset (in bytes) from the start of the BO to the given x
1151 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1152 * multiples of the tile size.
1155 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1156 uint32_t x
, uint32_t y
)
1159 uint32_t pitch
= mt
->pitch
;
1160 uint32_t tiling
= mt
->tiling
;
1164 unreachable("not reached");
1165 case I915_TILING_NONE
:
1166 return y
* pitch
+ x
* cpp
;
1168 assert((x
% (512 / cpp
)) == 0);
1169 assert((y
% 8) == 0);
1170 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1172 assert((x
% (128 / cpp
)) == 0);
1173 assert((y
% 32) == 0);
1174 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1179 * Rendering with tiled buffers requires that the base address of the buffer
1180 * be aligned to a page boundary. For renderbuffers, and sometimes with
1181 * textures, we may want the surface to point at a texture image level that
1182 * isn't at a page boundary.
1184 * This function returns an appropriately-aligned base offset
1185 * according to the tiling restrictions, plus any required x/y offset
1189 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1190 GLuint level
, GLuint slice
,
1195 uint32_t mask_x
, mask_y
;
1197 intel_get_tile_masks(mt
->tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1198 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1200 *tile_x
= x
& mask_x
;
1201 *tile_y
= y
& mask_y
;
1203 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1207 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1208 struct intel_mipmap_tree
*dst_mt
,
1209 struct intel_mipmap_tree
*src_mt
,
1216 ptrdiff_t src_stride
, dst_stride
;
1217 int cpp
= dst_mt
->cpp
;
1219 intel_miptree_map(brw
, src_mt
,
1223 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1226 intel_miptree_map(brw
, dst_mt
,
1230 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1234 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1235 _mesa_get_format_name(src_mt
->format
),
1236 src_mt
, src
, src_stride
,
1237 _mesa_get_format_name(dst_mt
->format
),
1238 dst_mt
, dst
, dst_stride
,
1241 int row_size
= cpp
* width
;
1242 if (src_stride
== row_size
&&
1243 dst_stride
== row_size
) {
1244 memcpy(dst
, src
, row_size
* height
);
1246 for (int i
= 0; i
< height
; i
++) {
1247 memcpy(dst
, src
, row_size
);
1253 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1254 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1256 /* Don't forget to copy the stencil data over, too. We could have skipped
1257 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1258 * shuffling the two data sources in/out of temporary storage instead of
1259 * the direct mapping we get this way.
1261 if (dst_mt
->stencil_mt
) {
1262 assert(src_mt
->stencil_mt
);
1263 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1264 level
, slice
, width
, height
);
1269 intel_miptree_copy_slice(struct brw_context
*brw
,
1270 struct intel_mipmap_tree
*dst_mt
,
1271 struct intel_mipmap_tree
*src_mt
,
1277 mesa_format format
= src_mt
->format
;
1278 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1279 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1287 assert(depth
< src_mt
->level
[level
].depth
);
1288 assert(src_mt
->format
== dst_mt
->format
);
1290 if (dst_mt
->compressed
) {
1292 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1293 height
= ALIGN_NPOT(height
, j
) / j
;
1294 width
= ALIGN_NPOT(width
, i
) / i
;
1297 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1298 * below won't apply since we can't do the depth's Y tiling or the
1299 * stencil's W tiling in the blitter.
1301 if (src_mt
->stencil_mt
) {
1302 intel_miptree_copy_slice_sw(brw
,
1309 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1310 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1311 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1313 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1314 _mesa_get_format_name(src_mt
->format
),
1315 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1316 _mesa_get_format_name(dst_mt
->format
),
1317 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1320 if (!intel_miptree_blit(brw
,
1321 src_mt
, level
, slice
, 0, 0, false,
1322 dst_mt
, level
, slice
, 0, 0, false,
1323 width
, height
, GL_COPY
)) {
1324 perf_debug("miptree validate blit for %s failed\n",
1325 _mesa_get_format_name(format
));
1327 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1333 * Copies the image's current data to the given miptree, and associates that
1334 * miptree with the image.
1336 * If \c invalidate is true, then the actual image data does not need to be
1337 * copied, but the image still needs to be associated to the new miptree (this
1338 * is set to true if we're about to clear the image).
1341 intel_miptree_copy_teximage(struct brw_context
*brw
,
1342 struct intel_texture_image
*intelImage
,
1343 struct intel_mipmap_tree
*dst_mt
,
1346 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1347 struct intel_texture_object
*intel_obj
=
1348 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1349 int level
= intelImage
->base
.Base
.Level
;
1350 int face
= intelImage
->base
.Base
.Face
;
1353 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1354 depth
= intelImage
->base
.Base
.Height
;
1356 depth
= intelImage
->base
.Base
.Depth
;
1359 for (int slice
= 0; slice
< depth
; slice
++) {
1360 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1364 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1365 intel_obj
->needs_validate
= true;
1369 intel_miptree_init_mcs(struct brw_context
*brw
,
1370 struct intel_mipmap_tree
*mt
,
1373 assert(mt
->mcs_buf
!= NULL
);
1375 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1377 * When MCS buffer is enabled and bound to MSRT, it is required that it
1378 * is cleared prior to any rendering.
1380 * Since we don't use the MCS buffer for any purpose other than rendering,
1381 * it makes sense to just clear it immediately upon allocation.
1383 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1385 const int ret
= brw_bo_map_gtt(brw
, mt
->mcs_buf
->bo
);
1386 if (unlikely(ret
)) {
1387 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1388 brw_bo_unreference(mt
->mcs_buf
->bo
);
1392 void *data
= mt
->mcs_buf
->bo
->virtual;
1393 memset(data
, init_value
, mt
->mcs_buf
->size
);
1394 brw_bo_unmap(mt
->mcs_buf
->bo
);
1397 static struct intel_miptree_aux_buffer
*
1398 intel_mcs_miptree_buf_create(struct brw_context
*brw
,
1399 struct intel_mipmap_tree
*mt
,
1402 unsigned mcs_height
,
1403 uint32_t layout_flags
)
1405 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1406 struct intel_mipmap_tree
*temp_mt
;
1411 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1413 * "The MCS surface must be stored as Tile Y."
1415 layout_flags
|= MIPTREE_LAYOUT_TILING_Y
;
1416 temp_mt
= miptree_create(brw
,
1424 0 /* num_samples */,
1431 buf
->bo
= temp_mt
->bo
;
1432 buf
->offset
= temp_mt
->offset
;
1433 buf
->size
= temp_mt
->total_height
* temp_mt
->pitch
;
1434 buf
->pitch
= temp_mt
->pitch
;
1435 buf
->qpitch
= temp_mt
->qpitch
;
1437 /* Just hang on to the BO which backs the AUX buffer; the rest of the miptree
1438 * structure should go away. We use miptree create simply as a means to make
1439 * sure all the constraints for the buffer are satisfied.
1441 brw_bo_reference(temp_mt
->bo
);
1442 intel_miptree_release(&temp_mt
);
1448 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1449 struct intel_mipmap_tree
*mt
,
1452 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1453 assert(mt
->mcs_buf
== NULL
);
1454 assert((mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
) == 0);
1456 /* Choose the correct format for the MCS buffer. All that really matters
1457 * is that we allocate the right buffer size, since we'll always be
1458 * accessing this miptree using MCS-specific hardware mechanisms, which
1459 * infer the correct format based on num_samples.
1462 switch (num_samples
) {
1465 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1468 format
= MESA_FORMAT_R_UNORM8
;
1471 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1472 * for each sample, plus 8 padding bits).
1474 format
= MESA_FORMAT_R_UINT32
;
1477 /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
1480 format
= MESA_FORMAT_RG_UINT32
;
1483 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1487 intel_mcs_miptree_buf_create(brw
, mt
,
1490 mt
->logical_height0
,
1491 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
);
1495 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1497 /* Multisampled miptrees are only supported for single level. */
1498 assert(mt
->first_level
== 0);
1499 intel_miptree_set_fast_clear_state(brw
, mt
, mt
->first_level
, 0,
1501 INTEL_FAST_CLEAR_STATE_CLEAR
);
1508 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1509 struct intel_mipmap_tree
*mt
,
1510 bool is_lossless_compressed
)
1512 assert(mt
->mcs_buf
== NULL
);
1513 assert(!(mt
->aux_disable
& (INTEL_AUX_DISABLE_MCS
| INTEL_AUX_DISABLE_CCS
)));
1515 struct isl_surf temp_main_surf
;
1516 struct isl_surf temp_ccs_surf
;
1518 /* Create first an ISL presentation for the main color surface and let ISL
1519 * calculate equivalent CCS surface against it.
1521 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1522 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_ccs_surf
))
1525 assert(temp_ccs_surf
.size
&&
1526 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1528 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1532 buf
->size
= temp_ccs_surf
.size
;
1533 buf
->pitch
= temp_ccs_surf
.row_pitch
;
1534 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(&temp_ccs_surf
);
1536 /* In case of compression mcs buffer needs to be initialised requiring the
1537 * buffer to be immediately mapped to cpu space for writing. Therefore do
1538 * not use the gpu access flag which can cause an unnecessary delay if the
1539 * backing pages happened to be just used by the GPU.
1541 const uint32_t alloc_flags
=
1542 is_lossless_compressed
? 0 : BO_ALLOC_FOR_RENDER
;
1544 /* ISL has stricter set of alignment rules then the drm allocator.
1545 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1546 * trying to recalculate based on different format block sizes.
1548 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "ccs-miptree",
1549 buf
->pitch
, buf
->size
/ buf
->pitch
,
1550 1, I915_TILING_Y
, &buf
->pitch
, alloc_flags
);
1558 /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
1559 * used for lossless compression which requires similar initialisation
1560 * as multi-sample compression.
1562 if (is_lossless_compressed
) {
1563 /* Hardware sets the auxiliary buffer to all zeroes when it does full
1564 * resolve. Initialize it accordingly in case the first renderer is
1565 * cpu (or other none compression aware party).
1567 * This is also explicitly stated in the spec (MCS Buffer for Render
1569 * "If Software wants to enable Color Compression without Fast clear,
1570 * Software needs to initialize MCS with zeros."
1572 intel_miptree_init_mcs(brw
, mt
, 0);
1573 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_CMS
;
1580 * Helper for intel_miptree_alloc_hiz() that sets
1581 * \c mt->level[level].has_hiz. Return true if and only if
1582 * \c has_hiz was set.
1585 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1586 struct intel_mipmap_tree
*mt
,
1589 assert(mt
->hiz_buf
);
1591 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1592 uint32_t width
= minify(mt
->physical_width0
, level
);
1593 uint32_t height
= minify(mt
->physical_height0
, level
);
1595 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1596 * and the height is 4 aligned. This allows our HiZ support
1597 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1598 * we can grow the width & height to allow the HiZ op to
1599 * force the proper size alignments.
1601 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1602 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1607 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1608 mt
->level
[level
].has_hiz
= true;
1614 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1615 * buffer dimensions and allocates a bo for the hiz buffer.
1617 static struct intel_miptree_hiz_buffer
*
1618 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1619 struct intel_mipmap_tree
*mt
)
1621 unsigned z_width
= mt
->logical_width0
;
1622 unsigned z_height
= mt
->logical_height0
;
1623 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1624 unsigned hz_width
, hz_height
;
1625 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1630 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1631 * adjustments required for Z_Height and Z_Width based on multisampling.
1633 switch (mt
->num_samples
) {
1647 unreachable("unsupported sample count");
1650 const unsigned vertical_align
= 8; /* 'j' in the docs */
1651 const unsigned H0
= z_height
;
1652 const unsigned h0
= ALIGN(H0
, vertical_align
);
1653 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1654 const unsigned Z0
= z_depth
;
1656 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1657 hz_width
= ALIGN(z_width
, 16);
1659 if (mt
->target
== GL_TEXTURE_3D
) {
1663 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1664 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1665 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1666 hz_height
+= h_i
* Z_i
;
1667 H_i
= minify(H_i
, 1);
1668 Z_i
= minify(Z_i
, 1);
1671 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1673 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1675 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1676 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1677 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1680 buf
->aux_base
.bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1681 hz_width
, hz_height
, 1,
1682 I915_TILING_Y
, &buf
->aux_base
.pitch
,
1683 BO_ALLOC_FOR_RENDER
);
1684 if (!buf
->aux_base
.bo
) {
1689 buf
->aux_base
.size
= hz_width
* hz_height
;
1696 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1697 * buffer dimensions and allocates a bo for the hiz buffer.
1699 static struct intel_miptree_hiz_buffer
*
1700 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1701 struct intel_mipmap_tree
*mt
)
1703 unsigned z_width
= mt
->logical_width0
;
1704 unsigned z_height
= mt
->logical_height0
;
1705 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1706 unsigned hz_width
, hz_height
;
1707 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1712 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1713 * adjustments required for Z_Height and Z_Width based on multisampling.
1716 switch (mt
->num_samples
) {
1730 unreachable("unsupported sample count");
1734 const unsigned vertical_align
= 8; /* 'j' in the docs */
1735 const unsigned H0
= z_height
;
1736 const unsigned h0
= ALIGN(H0
, vertical_align
);
1737 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1738 const unsigned Z0
= z_depth
;
1740 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1741 hz_width
= ALIGN(z_width
, 16);
1745 unsigned sum_h_i
= 0;
1746 unsigned hz_height_3d_sum
= 0;
1747 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1748 unsigned i
= level
- mt
->first_level
;
1749 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1750 /* sum(i=2 to m; h_i) */
1754 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1755 hz_height_3d_sum
+= h_i
* Z_i
;
1756 H_i
= minify(H_i
, 1);
1757 Z_i
= minify(Z_i
, 1);
1759 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1760 buf
->aux_base
.qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1762 if (mt
->target
== GL_TEXTURE_3D
) {
1763 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1764 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1766 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1767 hz_height
= DIV_ROUND_UP(buf
->aux_base
.qpitch
, 2 * 8) * 8 * Z0
;
1770 buf
->aux_base
.bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1771 hz_width
, hz_height
, 1,
1772 I915_TILING_Y
, &buf
->aux_base
.pitch
,
1773 BO_ALLOC_FOR_RENDER
);
1774 if (!buf
->aux_base
.bo
) {
1779 buf
->aux_base
.size
= hz_width
* hz_height
;
1785 static struct intel_miptree_hiz_buffer
*
1786 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1787 struct intel_mipmap_tree
*mt
)
1789 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1790 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1793 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1798 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1799 buf
->mt
= intel_miptree_create(brw
,
1805 mt
->logical_height0
,
1814 buf
->aux_base
.bo
= buf
->mt
->bo
;
1815 buf
->aux_base
.size
= buf
->mt
->total_height
* buf
->mt
->pitch
;
1816 buf
->aux_base
.pitch
= buf
->mt
->pitch
;
1818 /* On gen6 hiz is unconditionally laid out packing all slices
1819 * at each level-of-detail (LOD). This means there is no valid qpitch
1820 * setting. In fact, this is ignored when hardware is setup - there is no
1821 * hardware qpitch setting of hiz on gen6.
1823 buf
->aux_base
.qpitch
= 0;
1829 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1830 struct intel_mipmap_tree
*mt
)
1835 if (mt
->hiz_buf
!= NULL
)
1838 if (mt
->aux_disable
& INTEL_AUX_DISABLE_HIZ
)
1841 switch (mt
->format
) {
1842 case MESA_FORMAT_Z_FLOAT32
:
1843 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1844 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1845 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1846 case MESA_FORMAT_Z_UNORM16
:
1854 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1855 struct intel_mipmap_tree
*mt
)
1857 assert(mt
->hiz_buf
== NULL
);
1858 assert((mt
->aux_disable
& INTEL_AUX_DISABLE_HIZ
) == 0);
1860 if (brw
->gen
== 7) {
1861 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1862 } else if (brw
->gen
>= 8) {
1863 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1865 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1871 /* Mark that all slices need a HiZ resolve. */
1872 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1873 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1876 for (unsigned layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1877 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1878 exec_node_init(&m
->link
);
1881 m
->need
= BLORP_HIZ_OP_HIZ_RESOLVE
;
1883 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1891 * Can the miptree sample using the hiz buffer?
1894 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1895 struct intel_mipmap_tree
*mt
)
1897 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1898 * so keep things conservative for now and never enable it unless we're SKL+.
1908 /* It seems the hardware won't fallback to the depth buffer if some of the
1909 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1910 * of the texture to be HiZ enabled.
1912 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1913 if (!intel_miptree_level_has_hiz(mt
, level
))
1917 /* If compressed multisampling is enabled, then we use it for the auxiliary
1920 * From the BDW PRM (Volume 2d: Command Reference: Structures
1921 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1923 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1924 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1926 * There is no such blurb for 1D textures, but there is sufficient evidence
1927 * that this is broken on SKL+.
1929 return (mt
->num_samples
<= 1 &&
1930 mt
->target
!= GL_TEXTURE_3D
&&
1931 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1935 * Does the miptree slice have hiz enabled?
1938 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1940 intel_miptree_check_level_layer(mt
, level
, 0);
1941 return mt
->level
[level
].has_hiz
;
1945 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1949 if (!intel_miptree_level_has_hiz(mt
, level
))
1952 intel_resolve_map_set(&mt
->hiz_map
,
1953 level
, layer
, BLORP_HIZ_OP_HIZ_RESOLVE
);
1958 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1962 if (!intel_miptree_level_has_hiz(mt
, level
))
1965 intel_resolve_map_set(&mt
->hiz_map
,
1966 level
, layer
, BLORP_HIZ_OP_DEPTH_RESOLVE
);
1970 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1974 uint32_t end_layer
= mt
->level
[level
].depth
;
1976 for (layer
= 0; layer
< end_layer
; layer
++) {
1977 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1982 intel_miptree_slice_resolve(struct brw_context
*brw
,
1983 struct intel_mipmap_tree
*mt
,
1986 enum blorp_hiz_op need
)
1988 intel_miptree_check_level_layer(mt
, level
, layer
);
1990 struct intel_resolve_map
*item
=
1991 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1993 if (!item
|| item
->need
!= need
)
1996 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1997 intel_resolve_map_remove(item
);
2002 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
2003 struct intel_mipmap_tree
*mt
,
2007 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2008 BLORP_HIZ_OP_HIZ_RESOLVE
);
2012 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
2013 struct intel_mipmap_tree
*mt
,
2017 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2018 BLORP_HIZ_OP_DEPTH_RESOLVE
);
2022 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
2023 struct intel_mipmap_tree
*mt
,
2024 enum blorp_hiz_op need
)
2026 bool did_resolve
= false;
2028 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
2029 if (map
->need
!= need
)
2032 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
2033 intel_resolve_map_remove(map
);
2041 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
2042 struct intel_mipmap_tree
*mt
)
2044 return intel_miptree_all_slices_resolve(brw
, mt
,
2045 BLORP_HIZ_OP_HIZ_RESOLVE
);
2049 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
2050 struct intel_mipmap_tree
*mt
)
2052 return intel_miptree_all_slices_resolve(brw
, mt
,
2053 BLORP_HIZ_OP_DEPTH_RESOLVE
);
2056 enum intel_fast_clear_state
2057 intel_miptree_get_fast_clear_state(const struct intel_mipmap_tree
*mt
,
2058 unsigned level
, unsigned layer
)
2060 intel_miptree_check_level_layer(mt
, level
, layer
);
2062 const struct intel_resolve_map
*item
=
2063 intel_resolve_map_const_get(&mt
->color_resolve_map
, level
, layer
);
2066 return INTEL_FAST_CLEAR_STATE_RESOLVED
;
2068 return item
->fast_clear_state
;
2072 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2073 const struct intel_mipmap_tree
*mt
,
2074 unsigned level
, unsigned layer
)
2077 if ((mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) || !mt
->mcs_buf
)
2080 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2081 assert(brw
->gen
>= 8 ||
2082 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2084 /* Compression of arrayed msaa surfaces is supported. */
2085 if (mt
->num_samples
> 1)
2088 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2089 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
2096 intel_miptree_set_fast_clear_state(const struct brw_context
*brw
,
2097 struct intel_mipmap_tree
*mt
,
2099 unsigned first_layer
,
2100 unsigned num_layers
,
2101 enum intel_fast_clear_state new_state
)
2103 /* Setting the state to resolved means removing the item from the list
2106 assert(new_state
!= INTEL_FAST_CLEAR_STATE_RESOLVED
);
2108 intel_miptree_check_color_resolve(brw
, mt
, level
, first_layer
);
2110 assert(first_layer
+ num_layers
<= mt
->physical_depth0
);
2112 for (unsigned i
= 0; i
< num_layers
; i
++)
2113 intel_resolve_map_set(&mt
->color_resolve_map
, level
,
2114 first_layer
+ i
, new_state
);
2118 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2119 unsigned start_level
, unsigned num_levels
,
2120 unsigned start_layer
, unsigned num_layers
)
2122 return intel_resolve_map_find_any(&mt
->color_resolve_map
,
2123 start_level
, num_levels
,
2124 start_layer
, num_layers
) != NULL
;
2128 intel_miptree_used_for_rendering(const struct brw_context
*brw
,
2129 struct intel_mipmap_tree
*mt
, unsigned level
,
2130 unsigned start_layer
, unsigned num_layers
)
2132 const bool is_lossless_compressed
=
2133 intel_miptree_is_lossless_compressed(brw
, mt
);
2135 for (unsigned i
= 0; i
< num_layers
; ++i
) {
2136 const enum intel_fast_clear_state fast_clear_state
=
2137 intel_miptree_get_fast_clear_state(mt
, level
, start_layer
+ i
);
2139 /* If the buffer was previously in fast clear state, change it to
2140 * unresolved state, since it won't be guaranteed to be clear after
2143 if (is_lossless_compressed
||
2144 fast_clear_state
== INTEL_FAST_CLEAR_STATE_CLEAR
) {
2145 intel_miptree_set_fast_clear_state(
2146 brw
, mt
, level
, start_layer
+ i
, 1,
2147 INTEL_FAST_CLEAR_STATE_UNRESOLVED
);
2153 intel_miptree_needs_color_resolve(const struct brw_context
*brw
,
2154 const struct intel_mipmap_tree
*mt
,
2157 if (mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
)
2160 const bool is_lossless_compressed
=
2161 intel_miptree_is_lossless_compressed(brw
, mt
);
2163 /* From gen9 onwards there is new compression scheme for single sampled
2164 * surfaces called "lossless compressed". These don't need to be always
2167 if ((flags
& INTEL_MIPTREE_IGNORE_CCS_E
) && is_lossless_compressed
)
2170 /* Fast color clear resolves only make sense for non-MSAA buffers. */
2171 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_NONE
&& !is_lossless_compressed
)
2178 intel_miptree_resolve_color(struct brw_context
*brw
,
2179 struct intel_mipmap_tree
*mt
, unsigned level
,
2180 unsigned start_layer
, unsigned num_layers
,
2183 intel_miptree_check_color_resolve(brw
, mt
, level
, start_layer
);
2185 if (!intel_miptree_needs_color_resolve(brw
, mt
, flags
))
2188 /* Arrayed fast clear is only supported for gen8+. */
2189 assert(brw
->gen
>= 8 || num_layers
== 1);
2191 bool resolved
= false;
2192 for (unsigned i
= 0; i
< num_layers
; ++i
) {
2193 intel_miptree_check_level_layer(mt
, level
, start_layer
+ i
);
2195 struct intel_resolve_map
*item
=
2196 intel_resolve_map_get(&mt
->color_resolve_map
, level
,
2200 assert(item
->fast_clear_state
!= INTEL_FAST_CLEAR_STATE_RESOLVED
);
2202 brw_blorp_resolve_color(brw
, mt
, level
, start_layer
);
2203 intel_resolve_map_remove(item
);
2212 intel_miptree_all_slices_resolve_color(struct brw_context
*brw
,
2213 struct intel_mipmap_tree
*mt
,
2216 if (!intel_miptree_needs_color_resolve(brw
, mt
, flags
))
2219 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
,
2220 &mt
->color_resolve_map
) {
2221 assert(map
->fast_clear_state
!= INTEL_FAST_CLEAR_STATE_RESOLVED
);
2223 brw_blorp_resolve_color(brw
, mt
, map
->level
, map
->layer
);
2224 intel_resolve_map_remove(map
);
2229 * Make it possible to share the BO backing the given miptree with another
2230 * process or another miptree.
2232 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2233 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2234 * ensure that no MCS buffer gets allocated in the future.
2236 * HiZ is similarly unsafe with shared buffers.
2239 intel_miptree_make_shareable(struct brw_context
*brw
,
2240 struct intel_mipmap_tree
*mt
)
2242 /* MCS buffers are also used for multisample buffers, but we can't resolve
2243 * away a multisample MCS buffer because it's an integral part of how the
2244 * pixel data is stored. Fortunately this code path should never be
2245 * reached for multisample buffers.
2247 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
|| mt
->num_samples
<= 1);
2250 intel_miptree_all_slices_resolve_color(brw
, mt
, 0);
2251 mt
->aux_disable
|= (INTEL_AUX_DISABLE_CCS
| INTEL_AUX_DISABLE_MCS
);
2252 brw_bo_unreference(mt
->mcs_buf
->bo
);
2256 /* Any pending MCS/CCS operations are no longer needed. Trying to
2257 * execute any will likely crash due to the missing aux buffer. So let's
2258 * delete all pending ops.
2260 exec_list_make_empty(&mt
->color_resolve_map
);
2264 mt
->aux_disable
|= INTEL_AUX_DISABLE_HIZ
;
2265 intel_miptree_all_slices_resolve_depth(brw
, mt
);
2266 intel_miptree_hiz_buffer_free(mt
->hiz_buf
);
2269 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2270 mt
->level
[l
].has_hiz
= false;
2273 /* Any pending HiZ operations are no longer needed. Trying to execute
2274 * any will likely crash due to the missing aux buffer. So let's delete
2277 exec_list_make_empty(&mt
->hiz_map
);
2283 * \brief Get pointer offset into stencil buffer.
2285 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2286 * must decode the tile's layout in software.
2289 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2291 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2293 * Even though the returned offset is always positive, the return type is
2295 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2296 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2299 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2301 uint32_t tile_size
= 4096;
2302 uint32_t tile_width
= 64;
2303 uint32_t tile_height
= 64;
2304 uint32_t row_size
= 64 * stride
;
2306 uint32_t tile_x
= x
/ tile_width
;
2307 uint32_t tile_y
= y
/ tile_height
;
2309 /* The byte's address relative to the tile's base addres. */
2310 uint32_t byte_x
= x
% tile_width
;
2311 uint32_t byte_y
= y
% tile_height
;
2313 uintptr_t u
= tile_y
* row_size
2314 + tile_x
* tile_size
2315 + 512 * (byte_x
/ 8)
2317 + 32 * ((byte_y
/ 4) % 2)
2318 + 16 * ((byte_x
/ 4) % 2)
2319 + 8 * ((byte_y
/ 2) % 2)
2320 + 4 * ((byte_x
/ 2) % 2)
2325 /* adjust for bit6 swizzling */
2326 if (((byte_x
/ 8) % 2) == 1) {
2327 if (((byte_y
/ 8) % 2) == 0) {
2339 intel_miptree_updownsample(struct brw_context
*brw
,
2340 struct intel_mipmap_tree
*src
,
2341 struct intel_mipmap_tree
*dst
)
2343 brw_blorp_blit_miptrees(brw
,
2344 src
, 0 /* level */, 0 /* layer */,
2345 src
->format
, SWIZZLE_XYZW
,
2346 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2348 src
->logical_width0
, src
->logical_height0
,
2350 dst
->logical_width0
, dst
->logical_height0
,
2351 GL_NEAREST
, false, false /*mirror x, y*/,
2354 if (src
->stencil_mt
) {
2355 brw_blorp_blit_miptrees(brw
,
2356 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2357 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2358 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2359 dst
->stencil_mt
->format
,
2361 src
->logical_width0
, src
->logical_height0
,
2363 dst
->logical_width0
, dst
->logical_height0
,
2364 GL_NEAREST
, false, false /*mirror x, y*/,
2365 false, false /* decode/encode srgb */);
2370 intel_update_r8stencil(struct brw_context
*brw
,
2371 struct intel_mipmap_tree
*mt
)
2373 assert(brw
->gen
>= 7);
2374 struct intel_mipmap_tree
*src
=
2375 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2376 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2379 if (!mt
->r8stencil_mt
) {
2380 const uint32_t r8stencil_flags
=
2381 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2382 MIPTREE_LAYOUT_DISABLE_AUX
;
2383 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD */
2384 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2386 MESA_FORMAT_R_UINT8
,
2389 src
->logical_width0
,
2390 src
->logical_height0
,
2391 src
->logical_depth0
,
2394 assert(mt
->r8stencil_mt
);
2397 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2399 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2400 const unsigned depth
= src
->level
[level
].depth
;
2402 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2403 brw_blorp_copy_miptrees(brw
,
2407 minify(src
->logical_width0
, level
),
2408 minify(src
->logical_height0
, level
));
2412 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2413 src
->r8stencil_needs_update
= false;
2417 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2419 /* CPU accesses to color buffers don't understand fast color clears, so
2420 * resolve any pending fast color clears before we map.
2422 intel_miptree_all_slices_resolve_color(brw
, mt
, 0);
2424 struct brw_bo
*bo
= mt
->bo
;
2426 if (brw_batch_references(&brw
->batch
, bo
))
2427 intel_batchbuffer_flush(brw
);
2429 /* brw_bo_map() uses a WB mmaping of the buffer's backing storage. It
2430 * will utilize the CPU cache even if the buffer is incoherent with the
2431 * GPU (i.e. any writes will be stored in the cache and not flushed to
2432 * memory and so will be invisible to the GPU or display engine). This
2433 * is the majority of buffers on a !llc machine, but even on a llc
2434 * almost all scanouts are incoherent with the CPU. A WB write into the
2435 * backing storage of the current scanout will not be immediately
2436 * visible on the screen. The transfer from cache to screen is slow and
2437 * indeterministic causing visible glitching on the screen. Never use
2438 * this WB mapping for writes to an active scanout (reads are fine, so
2439 * long as cache consistency is maintained).
2441 if (mt
->tiling
!= I915_TILING_NONE
|| mt
->is_scanout
)
2442 brw_bo_map_gtt(brw
, bo
);
2444 brw_bo_map(brw
, bo
, true);
2450 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2452 brw_bo_unmap(mt
->bo
);
2456 intel_miptree_map_gtt(struct brw_context
*brw
,
2457 struct intel_mipmap_tree
*mt
,
2458 struct intel_miptree_map
*map
,
2459 unsigned int level
, unsigned int slice
)
2461 unsigned int bw
, bh
;
2463 unsigned int image_x
, image_y
;
2464 intptr_t x
= map
->x
;
2465 intptr_t y
= map
->y
;
2467 /* For compressed formats, the stride is the number of bytes per
2468 * row of blocks. intel_miptree_get_image_offset() already does
2471 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2472 assert(y
% bh
== 0);
2473 assert(x
% bw
== 0);
2477 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2482 /* Note that in the case of cube maps, the caller must have passed the
2483 * slice number referencing the face.
2485 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2489 map
->stride
= mt
->pitch
;
2490 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2493 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2494 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2495 map
->x
, map
->y
, map
->w
, map
->h
,
2496 mt
, _mesa_get_format_name(mt
->format
),
2497 x
, y
, map
->ptr
, map
->stride
);
2501 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2503 intel_miptree_unmap_raw(mt
);
2507 intel_miptree_map_blit(struct brw_context
*brw
,
2508 struct intel_mipmap_tree
*mt
,
2509 struct intel_miptree_map
*map
,
2510 unsigned int level
, unsigned int slice
)
2512 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2513 /* first_level */ 0,
2517 MIPTREE_LAYOUT_TILING_NONE
);
2519 if (!map
->linear_mt
) {
2520 fprintf(stderr
, "Failed to allocate blit temporary\n");
2523 map
->stride
= map
->linear_mt
->pitch
;
2525 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2526 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2527 * invalidate is set, since we'll be writing the whole rectangle from our
2528 * temporary buffer back out.
2530 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2531 if (!intel_miptree_copy(brw
,
2532 mt
, level
, slice
, map
->x
, map
->y
,
2533 map
->linear_mt
, 0, 0, 0, 0,
2535 fprintf(stderr
, "Failed to blit\n");
2540 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
);
2542 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2543 map
->x
, map
->y
, map
->w
, map
->h
,
2544 mt
, _mesa_get_format_name(mt
->format
),
2545 level
, slice
, map
->ptr
, map
->stride
);
2550 intel_miptree_release(&map
->linear_mt
);
2556 intel_miptree_unmap_blit(struct brw_context
*brw
,
2557 struct intel_mipmap_tree
*mt
,
2558 struct intel_miptree_map
*map
,
2562 struct gl_context
*ctx
= &brw
->ctx
;
2564 intel_miptree_unmap_raw(map
->linear_mt
);
2566 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2567 bool ok
= intel_miptree_copy(brw
,
2568 map
->linear_mt
, 0, 0, 0, 0,
2569 mt
, level
, slice
, map
->x
, map
->y
,
2571 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2574 intel_miptree_release(&map
->linear_mt
);
2578 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2580 #if defined(USE_SSE41)
2582 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2583 struct intel_mipmap_tree
*mt
,
2584 struct intel_miptree_map
*map
,
2585 unsigned int level
, unsigned int slice
)
2587 assert(map
->mode
& GL_MAP_READ_BIT
);
2588 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2590 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2591 map
->x
, map
->y
, map
->w
, map
->h
,
2592 mt
, _mesa_get_format_name(mt
->format
),
2593 level
, slice
, map
->ptr
, map
->stride
);
2595 /* Map the original image */
2598 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2602 void *src
= intel_miptree_map_raw(brw
, mt
);
2608 src
+= image_y
* mt
->pitch
;
2609 src
+= image_x
* mt
->cpp
;
2611 /* Due to the pixel offsets for the particular image being mapped, our
2612 * src pointer may not be 16-byte aligned. However, if the pitch is
2613 * divisible by 16, then the amount by which it's misaligned will remain
2614 * consistent from row to row.
2616 assert((mt
->pitch
% 16) == 0);
2617 const int misalignment
= ((uintptr_t) src
) & 15;
2619 /* Create an untiled temporary buffer for the mapping. */
2620 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2622 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2624 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2625 /* Offset the destination so it has the same misalignment as src. */
2626 map
->ptr
= map
->buffer
+ misalignment
;
2628 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2630 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2631 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2632 void *src_ptr
= src
+ y
* mt
->pitch
;
2634 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2637 intel_miptree_unmap_raw(mt
);
2641 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2642 struct intel_mipmap_tree
*mt
,
2643 struct intel_miptree_map
*map
,
2647 _mesa_align_free(map
->buffer
);
2654 intel_miptree_map_s8(struct brw_context
*brw
,
2655 struct intel_mipmap_tree
*mt
,
2656 struct intel_miptree_map
*map
,
2657 unsigned int level
, unsigned int slice
)
2659 map
->stride
= map
->w
;
2660 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2664 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2665 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2666 * invalidate is set, since we'll be writing the whole rectangle from our
2667 * temporary buffer back out.
2669 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2670 uint8_t *untiled_s8_map
= map
->ptr
;
2671 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2672 unsigned int image_x
, image_y
;
2674 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2676 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2677 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2678 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2679 x
+ image_x
+ map
->x
,
2680 y
+ image_y
+ map
->y
,
2681 brw
->has_swizzling
);
2682 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2686 intel_miptree_unmap_raw(mt
);
2688 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2689 map
->x
, map
->y
, map
->w
, map
->h
,
2690 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2692 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2693 map
->x
, map
->y
, map
->w
, map
->h
,
2694 mt
, map
->ptr
, map
->stride
);
2699 intel_miptree_unmap_s8(struct brw_context
*brw
,
2700 struct intel_mipmap_tree
*mt
,
2701 struct intel_miptree_map
*map
,
2705 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2706 unsigned int image_x
, image_y
;
2707 uint8_t *untiled_s8_map
= map
->ptr
;
2708 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2710 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2712 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2713 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2714 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2715 image_x
+ x
+ map
->x
,
2716 image_y
+ y
+ map
->y
,
2717 brw
->has_swizzling
);
2718 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2722 intel_miptree_unmap_raw(mt
);
2729 intel_miptree_map_etc(struct brw_context
*brw
,
2730 struct intel_mipmap_tree
*mt
,
2731 struct intel_miptree_map
*map
,
2735 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2736 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2737 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2740 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2741 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2743 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2744 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2745 map
->w
, map
->h
, 1));
2746 map
->ptr
= map
->buffer
;
2750 intel_miptree_unmap_etc(struct brw_context
*brw
,
2751 struct intel_mipmap_tree
*mt
,
2752 struct intel_miptree_map
*map
,
2758 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2763 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2764 + image_y
* mt
->pitch
2765 + image_x
* mt
->cpp
;
2767 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2768 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2769 map
->ptr
, map
->stride
,
2772 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2773 map
->ptr
, map
->stride
,
2774 map
->w
, map
->h
, mt
->etc_format
);
2776 intel_miptree_unmap_raw(mt
);
2781 * Mapping function for packed depth/stencil miptrees backed by real separate
2782 * miptrees for depth and stencil.
2784 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2785 * separate from the depth buffer. Yet at the GL API level, we have to expose
2786 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2787 * be able to map that memory for texture storage and glReadPixels-type
2788 * operations. We give Mesa core that access by mallocing a temporary and
2789 * copying the data between the actual backing store and the temporary.
2792 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2793 struct intel_mipmap_tree
*mt
,
2794 struct intel_miptree_map
*map
,
2795 unsigned int level
, unsigned int slice
)
2797 struct intel_mipmap_tree
*z_mt
= mt
;
2798 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2799 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2800 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2802 map
->stride
= map
->w
* packed_bpp
;
2803 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2807 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2808 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2809 * invalidate is set, since we'll be writing the whole rectangle from our
2810 * temporary buffer back out.
2812 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2813 uint32_t *packed_map
= map
->ptr
;
2814 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2815 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2816 unsigned int s_image_x
, s_image_y
;
2817 unsigned int z_image_x
, z_image_y
;
2819 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2820 &s_image_x
, &s_image_y
);
2821 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2822 &z_image_x
, &z_image_y
);
2824 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2825 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2826 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2827 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2830 brw
->has_swizzling
);
2831 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2833 (map_x
+ z_image_x
));
2834 uint8_t s
= s_map
[s_offset
];
2835 uint32_t z
= z_map
[z_offset
];
2837 if (map_z32f_x24s8
) {
2838 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2839 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2841 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2846 intel_miptree_unmap_raw(s_mt
);
2847 intel_miptree_unmap_raw(z_mt
);
2849 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2851 map
->x
, map
->y
, map
->w
, map
->h
,
2852 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2853 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2854 map
->ptr
, map
->stride
);
2856 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2857 map
->x
, map
->y
, map
->w
, map
->h
,
2858 mt
, map
->ptr
, map
->stride
);
2863 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2864 struct intel_mipmap_tree
*mt
,
2865 struct intel_miptree_map
*map
,
2869 struct intel_mipmap_tree
*z_mt
= mt
;
2870 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2871 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2873 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2874 uint32_t *packed_map
= map
->ptr
;
2875 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2876 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2877 unsigned int s_image_x
, s_image_y
;
2878 unsigned int z_image_x
, z_image_y
;
2880 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2881 &s_image_x
, &s_image_y
);
2882 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2883 &z_image_x
, &z_image_y
);
2885 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2886 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2887 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2888 x
+ s_image_x
+ map
->x
,
2889 y
+ s_image_y
+ map
->y
,
2890 brw
->has_swizzling
);
2891 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2893 (x
+ z_image_x
+ map
->x
));
2895 if (map_z32f_x24s8
) {
2896 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2897 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2899 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2900 s_map
[s_offset
] = packed
>> 24;
2901 z_map
[z_offset
] = packed
;
2906 intel_miptree_unmap_raw(s_mt
);
2907 intel_miptree_unmap_raw(z_mt
);
2909 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2911 map
->x
, map
->y
, map
->w
, map
->h
,
2912 z_mt
, _mesa_get_format_name(z_mt
->format
),
2913 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2914 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2915 map
->ptr
, map
->stride
);
2922 * Create and attach a map to the miptree at (level, slice). Return the
2925 static struct intel_miptree_map
*
2926 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2935 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2940 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2941 mt
->level
[level
].slice
[slice
].map
= map
;
2953 * Release the map at (level, slice).
2956 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2960 struct intel_miptree_map
**map
;
2962 map
= &mt
->level
[level
].slice
[slice
].map
;
2968 can_blit_slice(struct intel_mipmap_tree
*mt
,
2969 unsigned int level
, unsigned int slice
)
2971 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2972 if (mt
->pitch
>= 32768)
2979 use_intel_mipree_map_blit(struct brw_context
*brw
,
2980 struct intel_mipmap_tree
*mt
,
2986 /* It's probably not worth swapping to the blit ring because of
2987 * all the overhead involved.
2989 !(mode
& GL_MAP_WRITE_BIT
) &&
2991 (mt
->tiling
== I915_TILING_X
||
2992 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2993 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
2994 /* Fast copy blit on skl+ supports all tiling formats. */
2996 can_blit_slice(mt
, level
, slice
))
2999 if (mt
->tiling
!= I915_TILING_NONE
&&
3000 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3001 assert(can_blit_slice(mt
, level
, slice
));
3009 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3010 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3011 * arithmetic overflow.
3013 * If you call this function and use \a out_stride, then you're doing pointer
3014 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3015 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3016 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3017 * which usually have type uint32_t or GLuint.
3020 intel_miptree_map(struct brw_context
*brw
,
3021 struct intel_mipmap_tree
*mt
,
3030 ptrdiff_t *out_stride
)
3032 struct intel_miptree_map
*map
;
3034 assert(mt
->num_samples
<= 1);
3036 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3043 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
3044 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3045 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
3048 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3049 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3050 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3051 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3052 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3053 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3054 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3055 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3056 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3057 #if defined(USE_SSE41)
3058 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3059 !mt
->compressed
&& cpu_has_sse4_1
&&
3060 (mt
->pitch
% 16 == 0)) {
3061 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3064 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3067 *out_ptr
= map
->ptr
;
3068 *out_stride
= map
->stride
;
3070 if (map
->ptr
== NULL
)
3071 intel_miptree_release_map(mt
, level
, slice
);
3075 intel_miptree_unmap(struct brw_context
*brw
,
3076 struct intel_mipmap_tree
*mt
,
3080 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3082 assert(mt
->num_samples
<= 1);
3087 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3088 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3090 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3091 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3092 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3093 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3094 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3095 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3096 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3097 } else if (map
->linear_mt
) {
3098 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3099 #if defined(USE_SSE41)
3100 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3101 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3104 intel_miptree_unmap_gtt(mt
);
3107 intel_miptree_release_map(mt
, level
, slice
);
3111 get_isl_surf_dim(GLenum target
)
3115 case GL_TEXTURE_1D_ARRAY
:
3116 return ISL_SURF_DIM_1D
;
3119 case GL_TEXTURE_2D_ARRAY
:
3120 case GL_TEXTURE_RECTANGLE
:
3121 case GL_TEXTURE_CUBE_MAP
:
3122 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3123 case GL_TEXTURE_2D_MULTISAMPLE
:
3124 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3125 case GL_TEXTURE_EXTERNAL_OES
:
3126 return ISL_SURF_DIM_2D
;
3129 return ISL_SURF_DIM_3D
;
3132 unreachable("Invalid texture target");
3136 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3141 case GL_TEXTURE_1D_ARRAY
:
3142 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3143 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3146 case GL_TEXTURE_2D_ARRAY
:
3147 case GL_TEXTURE_RECTANGLE
:
3148 case GL_TEXTURE_2D_MULTISAMPLE
:
3149 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3150 case GL_TEXTURE_EXTERNAL_OES
:
3151 return ISL_DIM_LAYOUT_GEN4_2D
;
3153 case GL_TEXTURE_CUBE_MAP
:
3154 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3155 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3156 ISL_DIM_LAYOUT_GEN4_2D
);
3159 return (devinfo
->gen
>= 9 ?
3160 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3163 unreachable("Invalid texture target");
3167 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3169 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3170 return ISL_TILING_W
;
3172 switch (mt
->tiling
) {
3173 case I915_TILING_NONE
:
3174 return ISL_TILING_LINEAR
;
3176 return ISL_TILING_X
;
3178 return ISL_TILING_Y0
;
3180 unreachable("Invalid tiling mode");
3186 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3187 const struct intel_mipmap_tree
*mt
,
3188 struct isl_surf
*surf
)
3190 surf
->dim
= get_isl_surf_dim(mt
->target
);
3191 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3192 mt
->tiling
, mt
->target
);
3194 if (mt
->num_samples
> 1) {
3195 switch (mt
->msaa_layout
) {
3196 case INTEL_MSAA_LAYOUT_IMS
:
3197 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3199 case INTEL_MSAA_LAYOUT_UMS
:
3200 case INTEL_MSAA_LAYOUT_CMS
:
3201 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3204 unreachable("Invalid MSAA layout");
3207 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3210 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3212 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3213 /* The ISL definition of row_pitch matches the surface state pitch field
3214 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3215 * the factor of 2 for W-tiling in row_pitch.
3217 surf
->row_pitch
= 2 * mt
->pitch
;
3219 surf
->row_pitch
= mt
->pitch
;
3222 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3224 if (brw
->gen
>= 9) {
3225 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3226 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3227 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3229 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3230 * alignment in terms of surface elements like we want.
3232 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3235 /* On earlier gens it's stored in pixels. */
3237 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3238 surf
->image_alignment_el
=
3239 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3242 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3243 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3244 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3245 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3246 surf
->logical_level0_px
.array_len
= 1;
3248 surf
->logical_level0_px
.depth
= 1;
3249 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3252 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3253 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3254 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3255 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3256 surf
->phys_level0_sa
.array_len
= 1;
3258 surf
->phys_level0_sa
.depth
= 1;
3259 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3262 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3263 surf
->samples
= MAX2(mt
->num_samples
, 1);
3265 surf
->size
= 0; /* TODO */
3266 surf
->alignment
= 0; /* TODO */
3268 switch (surf
->dim_layout
) {
3269 case ISL_DIM_LAYOUT_GEN4_2D
:
3270 case ISL_DIM_LAYOUT_GEN4_3D
:
3271 if (brw
->gen
>= 9) {
3272 surf
->array_pitch_el_rows
= mt
->qpitch
;
3275 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3276 assert(mt
->qpitch
% bh
== 0);
3277 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3280 case ISL_DIM_LAYOUT_GEN9_1D
:
3281 surf
->array_pitch_el_rows
= 1;
3285 switch (mt
->array_layout
) {
3286 case ALL_LOD_IN_EACH_SLICE
:
3287 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3289 case ALL_SLICES_AT_EACH_LOD
:
3290 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3293 unreachable("Invalid array layout");
3296 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3297 switch (base_format
) {
3298 case GL_DEPTH_COMPONENT
:
3299 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3301 case GL_STENCIL_INDEX
:
3302 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3304 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3306 case GL_DEPTH_STENCIL
:
3307 /* In this case we only texture from the depth part */
3308 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3309 ISL_SURF_USAGE_TEXTURE_BIT
;
3312 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3313 if (brw
->format_supported_as_render_target
[mt
->format
])
3314 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3318 if (_mesa_is_cube_map_texture(mt
->target
))
3319 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3322 /* WARNING: THE SURFACE CREATED BY THIS FUNCTION IS NOT COMPLETE AND CANNOT BE
3323 * USED FOR ANY REAL CALCULATIONS. THE ONLY VALID USE OF SUCH A SURFACE IS TO
3324 * PASS IT INTO isl_surf_fill_state.
3327 intel_miptree_get_aux_isl_surf(struct brw_context
*brw
,
3328 const struct intel_mipmap_tree
*mt
,
3329 struct isl_surf
*surf
,
3330 enum isl_aux_usage
*usage
)
3332 uint32_t aux_pitch
, aux_qpitch
;
3334 aux_pitch
= mt
->mcs_buf
->pitch
;
3335 aux_qpitch
= mt
->mcs_buf
->qpitch
;
3337 if (mt
->num_samples
> 1) {
3338 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
3339 *usage
= ISL_AUX_USAGE_MCS
;
3340 } else if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
3341 assert(brw
->gen
>= 9);
3342 *usage
= ISL_AUX_USAGE_CCS_E
;
3343 } else if ((mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) == 0) {
3344 *usage
= ISL_AUX_USAGE_CCS_D
;
3346 unreachable("Invalid MCS miptree");
3348 } else if (mt
->hiz_buf
) {
3349 aux_pitch
= mt
->hiz_buf
->aux_base
.pitch
;
3350 aux_qpitch
= mt
->hiz_buf
->aux_base
.qpitch
;
3352 *usage
= ISL_AUX_USAGE_HIZ
;
3354 *usage
= ISL_AUX_USAGE_NONE
;
3358 /* Start with a copy of the original surface. */
3359 intel_miptree_get_isl_surf(brw
, mt
, surf
);
3361 /* Figure out the format and tiling of the auxiliary surface */
3363 case ISL_AUX_USAGE_NONE
:
3364 unreachable("Invalid auxiliary usage");
3366 case ISL_AUX_USAGE_HIZ
:
3367 isl_surf_get_hiz_surf(&brw
->isl_dev
, surf
, surf
);
3370 case ISL_AUX_USAGE_MCS
:
3373 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3374 * HALIGN 16 must be used."
3377 assert(mt
->halign
== 16);
3379 isl_surf_get_mcs_surf(&brw
->isl_dev
, surf
, surf
);
3382 case ISL_AUX_USAGE_CCS_D
:
3383 case ISL_AUX_USAGE_CCS_E
:
3385 * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
3387 * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
3389 * From the hardware spec for GEN9:
3391 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3392 * HALIGN 16 must be used."
3394 assert(mt
->num_samples
<= 1);
3396 assert(mt
->halign
== 16);
3398 isl_surf_get_ccs_surf(&brw
->isl_dev
, surf
, surf
);
3402 /* We want the pitch of the actual aux buffer. */
3403 surf
->row_pitch
= aux_pitch
;
3405 /* Auxiliary surfaces in ISL have compressed formats and array_pitch_el_rows
3406 * is in elements. This doesn't match intel_mipmap_tree::qpitch which is
3407 * in elements of the primary color surface so we have to divide by the
3408 * compression block height.
3410 surf
->array_pitch_el_rows
=
3411 aux_qpitch
/ isl_format_get_layout(surf
->format
)->bh
;
3414 union isl_color_value
3415 intel_miptree_get_isl_clear_color(struct brw_context
*brw
,
3416 const struct intel_mipmap_tree
*mt
)
3418 union isl_color_value clear_color
;
3420 if (_mesa_get_format_base_format(mt
->format
) == GL_DEPTH_COMPONENT
) {
3421 clear_color
.i32
[0] = mt
->depth_clear_value
;
3422 clear_color
.i32
[1] = 0;
3423 clear_color
.i32
[2] = 0;
3424 clear_color
.i32
[3] = 0;
3425 } else if (brw
->gen
>= 9) {
3426 clear_color
.i32
[0] = mt
->gen9_fast_clear_color
.i
[0];
3427 clear_color
.i32
[1] = mt
->gen9_fast_clear_color
.i
[1];
3428 clear_color
.i32
[2] = mt
->gen9_fast_clear_color
.i
[2];
3429 clear_color
.i32
[3] = mt
->gen9_fast_clear_color
.i
[3];
3430 } else if (_mesa_is_format_integer(mt
->format
)) {
3431 clear_color
.i32
[0] = (mt
->fast_clear_color_value
& (1u << 31)) != 0;
3432 clear_color
.i32
[1] = (mt
->fast_clear_color_value
& (1u << 30)) != 0;
3433 clear_color
.i32
[2] = (mt
->fast_clear_color_value
& (1u << 29)) != 0;
3434 clear_color
.i32
[3] = (mt
->fast_clear_color_value
& (1u << 28)) != 0;
3436 clear_color
.f32
[0] = (mt
->fast_clear_color_value
& (1u << 31)) != 0;
3437 clear_color
.f32
[1] = (mt
->fast_clear_color_value
& (1u << 30)) != 0;
3438 clear_color
.f32
[2] = (mt
->fast_clear_color_value
& (1u << 29)) != 0;
3439 clear_color
.f32
[3] = (mt
->fast_clear_color_value
& (1u << 28)) != 0;