2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_image.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
,
55 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
58 intel_miptree_alloc_mcs(struct brw_context
*brw
,
59 struct intel_mipmap_tree
*mt
,
63 * Determine which MSAA layout should be used by the MSAA surface being
64 * created, based on the chip generation and the surface type.
66 static enum intel_msaa_layout
67 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
68 uint32_t layout_flags
)
70 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
72 return INTEL_MSAA_LAYOUT_IMS
;
74 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
75 switch (_mesa_get_format_base_format(format
)) {
76 case GL_DEPTH_COMPONENT
:
77 case GL_STENCIL_INDEX
:
78 case GL_DEPTH_STENCIL
:
79 return INTEL_MSAA_LAYOUT_IMS
;
81 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
83 * This field must be set to 0 for all SINT MSRTs when all RT channels
86 * In practice this means that we have to disable MCS for all signed
87 * integer MSAA buffers. The alternative, to disable MCS only when one
88 * of the render target channels is disabled, is impractical because it
89 * would require converting between CMS and UMS MSAA layouts on the fly,
92 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
93 return INTEL_MSAA_LAYOUT_UMS
;
94 } else if (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) {
95 /* We can't use the CMS layout because it uses an aux buffer, the MCS
96 * buffer. So fallback to UMS, which is identical to CMS without the
98 return INTEL_MSAA_LAYOUT_UMS
;
100 return INTEL_MSAA_LAYOUT_CMS
;
106 intel_tiling_supports_ccs(const struct brw_context
*brw
, unsigned tiling
)
108 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
109 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
111 * - Support is limited to tiled render targets.
113 * Gen9 changes the restriction to Y-tile only.
116 return tiling
== I915_TILING_Y
;
117 else if (brw
->gen
>= 7)
118 return tiling
!= I915_TILING_NONE
;
124 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
125 * can be used. This doesn't (and should not) inspect any of the properties of
128 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
129 * beneath the "Fast Color Clear" bullet (p326):
131 * - Support is for non-mip-mapped and non-array surface types only.
133 * And then later, on p327:
135 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
138 * From the Skylake documentation, it is made clear that X-tiling is no longer
141 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
145 intel_miptree_supports_ccs(struct brw_context
*brw
,
146 const struct intel_mipmap_tree
*mt
)
148 /* MCS support does not exist prior to Gen7 */
152 /* This function applies only to non-multisampled render targets. */
153 if (mt
->num_samples
> 1)
156 /* MCS is only supported for color buffers */
157 switch (_mesa_get_format_base_format(mt
->format
)) {
158 case GL_DEPTH_COMPONENT
:
159 case GL_DEPTH_STENCIL
:
160 case GL_STENCIL_INDEX
:
164 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
167 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
168 const bool arrayed
= mt
->physical_depth0
!= 1;
171 /* Multisample surfaces with the CMS layout are not layered surfaces,
172 * yet still have physical_depth0 > 1. Assert that we don't
173 * accidentally reject a multisampled surface here. We should have
174 * rejected it earlier by explicitly checking the sample count.
176 assert(mt
->num_samples
<= 1);
179 /* Handle the hardware restrictions...
181 * All GENs have the following restriction: "MCS buffer for non-MSRT is
182 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
184 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
185 * Non-MultiSampler Render Target Restrictions) Support is for
186 * non-mip-mapped and non-array surface types only.
188 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
189 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
190 * surfaces are supported with MCS buffer layout with these alignments in
191 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
193 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
194 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
195 * surfaces are supported with MCS buffer layout with these alignments in
196 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
198 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
201 /* There's no point in using an MCS buffer if the surface isn't in a
204 if (!brw
->mesa_format_supports_render
[mt
->format
])
208 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
209 const enum isl_format isl_format
=
210 brw_isl_format_for_mesa_format(linear_format
);
211 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
217 intel_miptree_supports_hiz(struct brw_context
*brw
,
218 struct intel_mipmap_tree
*mt
)
223 switch (mt
->format
) {
224 case MESA_FORMAT_Z_FLOAT32
:
225 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
226 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
227 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
228 case MESA_FORMAT_Z_UNORM16
:
236 /* On Gen9 support for color buffer compression was extended to single
237 * sampled surfaces. This is a helper considering both auxiliary buffer
238 * type and number of samples telling if the given miptree represents
239 * the new single sampled case - also called lossless compression.
242 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
243 const struct intel_mipmap_tree
*mt
)
245 /* Only available from Gen9 onwards. */
249 /* Compression always requires auxiliary buffer. */
253 /* Single sample compression is represented re-using msaa compression
254 * layout type: "Compressed Multisampled Surfaces".
256 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
259 /* And finally distinguish between msaa and single sample case. */
260 return mt
->num_samples
<= 1;
264 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
265 const struct intel_mipmap_tree
*mt
)
267 /* For now compression is only enabled for integer formats even though
268 * there exist supported floating point formats also. This is a heuristic
269 * decision based on current public benchmarks. In none of the cases these
270 * formats provided any improvement but a few cases were seen to regress.
271 * Hence these are left to to be enabled in the future when they are known
274 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
277 if (!intel_miptree_supports_ccs(brw
, mt
))
280 /* Fast clear can be also used to clear srgb surfaces by using equivalent
281 * linear format. This trick, however, can't be extended to be used with
282 * lossless compression and therefore a check is needed to see if the format
285 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
289 * Determine depth format corresponding to a depth+stencil format,
290 * for separate stencil.
293 intel_depth_format_for_depthstencil_format(mesa_format format
) {
295 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
296 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
297 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
298 return MESA_FORMAT_Z_FLOAT32
;
305 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
306 unsigned depth0
, struct intel_mipmap_level
*table
)
308 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
310 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
312 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
313 if (!table
[level
].slice
)
320 for (unsigned level
= first_level
; level
<= last_level
; level
++)
321 free(table
[level
].slice
);
327 * @param for_bo Indicates that the caller is
328 * intel_miptree_create_for_bo(). If true, then do not create
331 static struct intel_mipmap_tree
*
332 intel_miptree_create_layout(struct brw_context
*brw
,
341 uint32_t layout_flags
)
343 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
347 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
348 _mesa_enum_to_string(target
),
349 _mesa_get_format_name(format
),
350 first_level
, last_level
, depth0
, mt
);
352 if (target
== GL_TEXTURE_1D_ARRAY
)
353 assert(height0
== 1);
357 mt
->first_level
= first_level
;
358 mt
->last_level
= last_level
;
359 mt
->logical_width0
= width0
;
360 mt
->logical_height0
= height0
;
361 mt
->logical_depth0
= depth0
;
362 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
363 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
364 mt
->supports_fast_clear
= false;
365 mt
->aux_state
= NULL
;
366 mt
->cpp
= _mesa_get_format_bytes(format
);
367 mt
->num_samples
= num_samples
;
368 mt
->compressed
= _mesa_is_format_compressed(format
);
369 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
372 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
373 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
375 int depth_multiply
= 1;
376 if (num_samples
> 1) {
377 /* Adjust width/height/depth for MSAA */
378 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, layout_flags
);
379 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
380 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
381 * "If the surface is multisampled and it is a depth or stencil
382 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
383 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
386 * +----------------------------------------------------------------+
387 * | Num Multisamples | W_l = | H_l = |
388 * +----------------------------------------------------------------+
389 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
390 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
391 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
392 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
393 * +----------------------------------------------------------------+
396 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
397 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
398 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
400 * Another more complicated explanation for these adjustments comes
401 * from the Sandybridge PRM, volume 4, part 1, page 31:
403 * "Any of the other messages (sample*, LOD, load4) used with a
404 * (4x) multisampled surface will in-effect sample a surface with
405 * double the height and width as that indicated in the surface
406 * state. Each pixel position on the original-sized surface is
407 * replaced with a 2x2 of samples with the following arrangement:
412 * Thus, when sampling from a multisampled texture, it behaves as
413 * though the layout in memory for (x,y,sample) is:
415 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
416 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
418 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
419 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
421 * However, the actual layout of multisampled data in memory is:
423 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
424 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
426 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
427 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
429 * This pattern repeats for each 2x2 pixel block.
431 * As a result, when calculating the size of our 4-sample buffer for
432 * an odd width or height, we have to align before scaling up because
433 * sample 3 is in that bottom right 2x2 block.
435 switch (num_samples
) {
437 assert(brw
->gen
>= 8);
438 width0
= ALIGN(width0
, 2) * 2;
439 height0
= ALIGN(height0
, 2);
442 width0
= ALIGN(width0
, 2) * 2;
443 height0
= ALIGN(height0
, 2) * 2;
446 width0
= ALIGN(width0
, 2) * 4;
447 height0
= ALIGN(height0
, 2) * 2;
450 width0
= ALIGN(width0
, 2) * 4;
451 height0
= ALIGN(height0
, 2) * 4;
454 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
457 unreachable("not reached");
460 /* Non-interleaved */
461 depth_multiply
= num_samples
;
462 depth0
*= depth_multiply
;
466 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
472 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
473 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
474 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
475 * used on Gen8 to make it pick a qpitch value which doesn't include space
476 * for the mipmaps. On Gen9 this is not necessary because it will
477 * automatically pick a packed qpitch value whenever mt->first_level ==
479 * TODO: can we use it elsewhere?
480 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
483 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
485 switch (mt
->msaa_layout
) {
486 case INTEL_MSAA_LAYOUT_NONE
:
487 case INTEL_MSAA_LAYOUT_IMS
:
488 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
490 case INTEL_MSAA_LAYOUT_UMS
:
491 case INTEL_MSAA_LAYOUT_CMS
:
492 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
497 if (target
== GL_TEXTURE_CUBE_MAP
)
498 assert(depth0
== 6 * depth_multiply
);
500 mt
->physical_width0
= width0
;
501 mt
->physical_height0
= height0
;
502 mt
->physical_depth0
= depth0
;
504 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
505 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
506 (brw
->must_use_separate_stencil
||
507 (brw
->has_separate_stencil
&& intel_miptree_supports_hiz(brw
, mt
)))) {
508 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
510 stencil_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
513 mt
->stencil_mt
= intel_miptree_create(brw
,
524 if (!mt
->stencil_mt
) {
525 intel_miptree_release(&mt
);
528 mt
->stencil_mt
->r8stencil_needs_update
= true;
530 /* Fix up the Z miptree format for how we're splitting out separate
531 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
533 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
536 if (format
== mt
->format
) {
537 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
538 _mesa_get_format_name(mt
->format
));
542 if (layout_flags
& MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
)
543 mt
->array_layout
= GEN6_HIZ_STENCIL
;
546 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
547 * multisampled or have an AUX buffer attached to it.
549 * GEN | MSRT | AUX_CCS_* or AUX_MCS
550 * -------------------------------------------
551 * 9 | HALIGN_16 | HALIGN_16
552 * 8 | HALIGN_ANY | HALIGN_16
556 if (intel_miptree_supports_ccs(brw
, mt
)) {
557 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
558 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
559 } else if (brw
->gen
>= 9 && num_samples
> 1) {
560 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
562 const UNUSED
bool is_lossless_compressed_aux
=
563 brw
->gen
>= 9 && num_samples
== 1 &&
564 mt
->format
== MESA_FORMAT_R_UINT32
;
566 /* For now, nothing else has this requirement */
567 assert(is_lossless_compressed_aux
||
568 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
571 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
572 intel_miptree_release(&mt
);
581 * Choose the aux usage for this miptree. This function must be called fairly
582 * late in the miptree create process after we have a tiling.
585 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
586 struct intel_mipmap_tree
*mt
)
588 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
590 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
591 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
592 } else if (intel_tiling_supports_ccs(brw
, mt
->tiling
) &&
593 intel_miptree_supports_ccs(brw
, mt
)) {
594 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
595 brw
->gen
>= 9 && !mt
->is_scanout
&&
596 intel_miptree_supports_ccs_e(brw
, mt
)) {
597 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
599 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
601 } else if (intel_miptree_supports_hiz(brw
, mt
)) {
602 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
605 /* We can do fast-clear on all auxiliary surface types that are
606 * allocated through the normal texture creation paths.
608 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
609 mt
->supports_fast_clear
= true;
614 * Choose an appropriate uncompressed format for a requested
615 * compressed format, if unsupported.
618 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
620 /* No need to lower ETC formats on these platforms,
621 * they are supported natively.
623 if (brw
->gen
>= 8 || brw
->is_baytrail
)
627 case MESA_FORMAT_ETC1_RGB8
:
628 return MESA_FORMAT_R8G8B8X8_UNORM
;
629 case MESA_FORMAT_ETC2_RGB8
:
630 return MESA_FORMAT_R8G8B8X8_UNORM
;
631 case MESA_FORMAT_ETC2_SRGB8
:
632 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
633 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
634 return MESA_FORMAT_B8G8R8A8_SRGB
;
635 case MESA_FORMAT_ETC2_RGBA8_EAC
:
636 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
637 return MESA_FORMAT_R8G8B8A8_UNORM
;
638 case MESA_FORMAT_ETC2_R11_EAC
:
639 return MESA_FORMAT_R_UNORM16
;
640 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
641 return MESA_FORMAT_R_SNORM16
;
642 case MESA_FORMAT_ETC2_RG11_EAC
:
643 return MESA_FORMAT_R16G16_UNORM
;
644 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
645 return MESA_FORMAT_R16G16_SNORM
;
647 /* Non ETC1 / ETC2 format */
652 /** \brief Assert that the level and layer are valid for the miptree. */
654 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
662 assert(level
>= mt
->first_level
);
663 assert(level
<= mt
->last_level
);
665 if (mt
->surf
.size
> 0)
666 assert(layer
< (mt
->surf
.dim
== ISL_SURF_DIM_3D
?
667 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
668 mt
->surf
.phys_level0_sa
.array_len
));
670 assert(layer
< mt
->level
[level
].depth
);
673 static enum isl_aux_state
**
674 create_aux_state_map(struct intel_mipmap_tree
*mt
,
675 enum isl_aux_state initial
)
677 const uint32_t levels
= mt
->last_level
+ 1;
679 uint32_t total_slices
= 0;
680 for (uint32_t level
= 0; level
< levels
; level
++)
681 total_slices
+= mt
->level
[level
].depth
;
683 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
685 /* We're going to allocate a single chunk of data for both the per-level
686 * reference array and the arrays of aux_state. This makes cleanup
687 * significantly easier.
689 const size_t total_size
= per_level_array_size
+
690 total_slices
* sizeof(enum isl_aux_state
);
691 void *data
= malloc(total_size
);
695 enum isl_aux_state
**per_level_arr
= data
;
696 enum isl_aux_state
*s
= data
+ per_level_array_size
;
697 for (uint32_t level
= 0; level
< levels
; level
++) {
698 per_level_arr
[level
] = s
;
699 for (uint32_t a
= 0; a
< mt
->level
[level
].depth
; a
++)
702 assert((void *)s
== data
+ total_size
);
704 return per_level_arr
;
708 free_aux_state_map(enum isl_aux_state
**state
)
713 static struct intel_mipmap_tree
*
714 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
715 unsigned first_level
, unsigned last_level
,
716 unsigned width0
, unsigned height0
, unsigned depth0
,
717 unsigned num_samples
, enum isl_tiling isl_tiling
,
718 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
721 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
725 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
731 if (target
== GL_TEXTURE_CUBE_MAP
||
732 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
733 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
735 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
737 _mesa_enum_to_string(target
),
738 _mesa_get_format_name(format
),
739 num_samples
, width0
, height0
, depth0
,
740 first_level
, last_level
, mt
);
742 struct isl_surf_init_info init_info
= {
743 .dim
= get_isl_surf_dim(target
),
744 .format
= translate_tex_format(brw
, format
, false),
747 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
748 .levels
= last_level
- first_level
+ 1,
749 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
750 .samples
= MAX2(num_samples
, 1),
751 .usage
= isl_usage_flags
,
752 .tiling_flags
= 1u << isl_tiling
755 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
758 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
761 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
763 isl_tiling_to_bufmgr_tiling(isl_tiling
),
764 mt
->surf
.row_pitch
, alloc_flags
);
771 mt
->first_level
= first_level
;
772 mt
->last_level
= last_level
;
776 mt
->aux_state
= NULL
;
781 intel_miptree_release(&mt
);
785 static struct intel_mipmap_tree
*
786 miptree_create(struct brw_context
*brw
,
795 uint32_t layout_flags
)
797 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
798 return make_surface(brw
, target
, format
, first_level
, last_level
,
799 width0
, height0
, depth0
, num_samples
, ISL_TILING_W
,
800 ISL_SURF_USAGE_STENCIL_BIT
|
801 ISL_SURF_USAGE_TEXTURE_BIT
,
802 BO_ALLOC_FOR_RENDER
, NULL
);
804 struct intel_mipmap_tree
*mt
;
805 mesa_format tex_format
= format
;
806 mesa_format etc_format
= MESA_FORMAT_NONE
;
807 uint32_t alloc_flags
= 0;
809 format
= intel_lower_compressed_format(brw
, format
);
811 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
813 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
814 mt
= intel_miptree_create_layout(brw
, target
, format
,
815 first_level
, last_level
, width0
,
816 height0
, depth0
, num_samples
,
821 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
822 mt
->tiling
= I915_TILING_Y
;
824 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
825 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
827 mt
->etc_format
= etc_format
;
829 if (format
== MESA_FORMAT_S_UINT8
) {
830 /* Align to size of W tile, 64x64. */
831 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
832 ALIGN(mt
->total_width
, 64),
833 ALIGN(mt
->total_height
, 64),
834 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
837 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
838 mt
->total_width
, mt
->total_height
,
839 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
843 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
844 mt
->bo
->cache_coherent
= false;
846 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
847 intel_miptree_choose_aux_usage(brw
, mt
);
852 struct intel_mipmap_tree
*
853 intel_miptree_create(struct brw_context
*brw
,
862 uint32_t layout_flags
)
864 struct intel_mipmap_tree
*mt
= miptree_create(
866 first_level
, last_level
,
867 width0
, height0
, depth0
, num_samples
,
870 /* If the BO is too large to fit in the aperture, we need to use the
871 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
872 * handle Y-tiling, so we need to fall back to X.
874 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
875 mt
->tiling
== I915_TILING_Y
) {
876 const uint32_t alloc_flags
=
877 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
878 BO_ALLOC_FOR_RENDER
: 0;
879 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
880 mt
->total_width
, mt
->total_height
);
882 mt
->tiling
= I915_TILING_X
;
883 brw_bo_unreference(mt
->bo
);
884 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
885 mt
->total_width
, mt
->total_height
, mt
->cpp
,
886 mt
->tiling
, &mt
->pitch
, alloc_flags
);
892 intel_miptree_release(&mt
);
897 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
898 assert(mt
->num_samples
> 1);
899 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
900 intel_miptree_release(&mt
);
905 /* Since CCS_E can compress more than just clear color, we create the CCS
906 * for it up-front. For CCS_D which only compresses clears, we create the
907 * CCS on-demand when a clear occurs that wants one.
909 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
910 if (!intel_miptree_alloc_ccs(brw
, mt
)) {
911 intel_miptree_release(&mt
);
919 struct intel_mipmap_tree
*
920 intel_miptree_create_for_bo(struct brw_context
*brw
,
928 uint32_t layout_flags
)
930 struct intel_mipmap_tree
*mt
;
931 uint32_t tiling
, swizzle
;
932 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
934 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
) {
935 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
936 0, 0, width
, height
, depth
, 1, ISL_TILING_W
,
937 ISL_SURF_USAGE_STENCIL_BIT
|
938 ISL_SURF_USAGE_TEXTURE_BIT
,
939 BO_ALLOC_FOR_RENDER
, bo
);
943 assert(bo
->size
>= mt
->surf
.size
);
945 brw_bo_reference(bo
);
949 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
951 /* Nothing will be able to use this miptree with the BO if the offset isn't
954 if (tiling
!= I915_TILING_NONE
)
955 assert(offset
% 4096 == 0);
957 /* miptrees can't handle negative pitch. If you need flipping of images,
958 * that's outside of the scope of the mt.
962 /* The BO already has a tiling format and we shouldn't confuse the lower
963 * layers by making it try to find a tiling format again.
965 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
966 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
968 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
969 mt
= intel_miptree_create_layout(brw
, target
, format
,
971 width
, height
, depth
, 0,
976 brw_bo_reference(bo
);
982 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
983 intel_miptree_choose_aux_usage(brw
, mt
);
988 static struct intel_mipmap_tree
*
989 miptree_create_for_planar_image(struct brw_context
*brw
,
990 __DRIimage
*image
, GLenum target
)
992 struct intel_image_format
*f
= image
->planar_format
;
993 struct intel_mipmap_tree
*planar_mt
;
995 for (int i
= 0; i
< f
->nplanes
; i
++) {
996 const int index
= f
->planes
[i
].buffer_index
;
997 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
998 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
999 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
1000 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
1002 /* Disable creation of the texture's aux buffers because the driver
1003 * exposes no EGL API to manage them. That is, there is no API for
1004 * resolving the aux buffer's content to the main buffer nor for
1005 * invalidating the aux buffer's content.
1007 struct intel_mipmap_tree
*mt
=
1008 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1009 image
->offsets
[index
],
1011 image
->strides
[index
],
1012 MIPTREE_LAYOUT_DISABLE_AUX
);
1016 mt
->target
= target
;
1017 mt
->total_width
= width
;
1018 mt
->total_height
= height
;
1023 planar_mt
->plane
[i
- 1] = mt
;
1029 struct intel_mipmap_tree
*
1030 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
1031 __DRIimage
*image
, GLenum target
,
1032 enum isl_colorspace colorspace
,
1033 bool is_winsys_image
)
1035 if (image
->planar_format
&& image
->planar_format
->nplanes
> 0) {
1036 assert(colorspace
== ISL_COLORSPACE_NONE
||
1037 colorspace
== ISL_COLORSPACE_YUV
);
1038 return miptree_create_for_planar_image(brw
, image
, target
);
1041 mesa_format format
= image
->format
;
1042 switch (colorspace
) {
1043 case ISL_COLORSPACE_NONE
:
1044 /* Keep the image format unmodified */
1047 case ISL_COLORSPACE_LINEAR
:
1048 format
=_mesa_get_srgb_format_linear(format
);
1051 case ISL_COLORSPACE_SRGB
:
1052 format
=_mesa_get_linear_format_srgb(format
);
1056 unreachable("Inalid colorspace for non-planar image");
1059 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1060 /* The texture storage paths in core Mesa detect if the driver does not
1061 * support the user-requested format, and then searches for a
1062 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1063 * do the fallbacks here for important formats.
1065 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1066 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1067 * the Chrome OS compositor consumes as dma_buf EGLImages.
1069 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1072 if (!brw
->ctx
.TextureFormatSupported
[format
])
1075 /* If this image comes in from a window system, we have different
1076 * requirements than if it comes in via an EGL import operation. Window
1077 * system images can use any form of auxiliary compression we wish because
1078 * they get "flushed" before being handed off to the window system and we
1079 * have the opportunity to do resolves. Window system buffers also may be
1080 * used for scanout so we need to flag that appropriately.
1082 const uint32_t mt_layout_flags
=
1083 is_winsys_image
? MIPTREE_LAYOUT_FOR_SCANOUT
: MIPTREE_LAYOUT_DISABLE_AUX
;
1085 /* Disable creation of the texture's aux buffers because the driver exposes
1086 * no EGL API to manage them. That is, there is no API for resolving the aux
1087 * buffer's content to the main buffer nor for invalidating the aux buffer's
1090 struct intel_mipmap_tree
*mt
=
1091 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1092 image
->offset
, image
->width
, image
->height
, 1,
1093 image
->pitch
, mt_layout_flags
);
1097 mt
->target
= target
;
1098 mt
->level
[0].level_x
= image
->tile_x
;
1099 mt
->level
[0].level_y
= image
->tile_y
;
1100 mt
->level
[0].slice
[0].x_offset
= image
->tile_x
;
1101 mt
->level
[0].slice
[0].y_offset
= image
->tile_y
;
1102 mt
->total_width
+= image
->tile_x
;
1103 mt
->total_height
+= image
->tile_y
;
1105 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1106 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1107 * trouble resolving back to destination image due to alignment issues.
1109 if (!brw
->has_surface_tile_offset
) {
1110 uint32_t draw_x
, draw_y
;
1111 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1113 if (draw_x
!= 0 || draw_y
!= 0) {
1114 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1115 intel_miptree_release(&mt
);
1120 /* Since CCS_E can compress more than just clear color, we create the CCS
1121 * for it up-front. For CCS_D which only compresses clears, we create the
1122 * CCS on-demand when a clear occurs that wants one.
1124 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1125 if (!intel_miptree_alloc_ccs(brw
, mt
)) {
1126 intel_miptree_release(&mt
);
1135 * For a singlesample renderbuffer, this simply wraps the given BO with a
1138 * For a multisample renderbuffer, this wraps the window system's
1139 * (singlesample) BO with a singlesample miptree attached to the
1140 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1141 * that will contain the actual rendering (which is lazily resolved to
1142 * irb->singlesample_mt).
1145 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1146 struct intel_renderbuffer
*irb
,
1147 struct intel_mipmap_tree
*singlesample_mt
,
1148 uint32_t width
, uint32_t height
,
1151 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1152 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1153 mesa_format format
= rb
->Format
;
1154 int num_samples
= rb
->NumSamples
;
1156 /* Only the front and back buffers, which are color buffers, are allocated
1157 * through the image loader.
1159 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1160 _mesa_get_format_base_format(format
) == GL_RGBA
);
1162 assert(singlesample_mt
);
1164 if (num_samples
== 0) {
1165 intel_miptree_release(&irb
->mt
);
1166 irb
->mt
= singlesample_mt
;
1168 assert(!irb
->singlesample_mt
);
1170 intel_miptree_release(&irb
->singlesample_mt
);
1171 irb
->singlesample_mt
= singlesample_mt
;
1174 irb
->mt
->logical_width0
!= width
||
1175 irb
->mt
->logical_height0
!= height
) {
1176 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1181 if (!multisample_mt
)
1184 irb
->need_downsample
= false;
1185 intel_miptree_release(&irb
->mt
);
1186 irb
->mt
= multisample_mt
;
1192 intel_miptree_release(&irb
->mt
);
1196 struct intel_mipmap_tree
*
1197 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1201 uint32_t num_samples
)
1203 struct intel_mipmap_tree
*mt
;
1206 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1207 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1208 MIPTREE_LAYOUT_TILING_ANY
|
1209 MIPTREE_LAYOUT_FOR_SCANOUT
;
1211 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1212 width
, height
, depth
, num_samples
,
1217 if (mt
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
1218 ok
= intel_miptree_alloc_hiz(brw
, mt
);
1226 intel_miptree_release(&mt
);
1231 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1232 struct intel_mipmap_tree
*src
)
1237 intel_miptree_release(dst
);
1241 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1248 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1250 if (aux_buf
== NULL
)
1253 brw_bo_unreference(aux_buf
->bo
);
1259 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1264 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1265 if (--(*mt
)->refcount
<= 0) {
1268 DBG("%s deleting %p\n", __func__
, *mt
);
1270 brw_bo_unreference((*mt
)->bo
);
1271 intel_miptree_release(&(*mt
)->stencil_mt
);
1272 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1273 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1274 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1275 free_aux_state_map((*mt
)->aux_state
);
1277 intel_miptree_release(&(*mt
)->plane
[0]);
1278 intel_miptree_release(&(*mt
)->plane
[1]);
1280 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1281 free((*mt
)->level
[i
].slice
);
1291 intel_get_image_dims(struct gl_texture_image
*image
,
1292 int *width
, int *height
, int *depth
)
1294 switch (image
->TexObject
->Target
) {
1295 case GL_TEXTURE_1D_ARRAY
:
1296 /* For a 1D Array texture the OpenGL API will treat the image height as
1297 * the number of array slices. For Intel hardware, we treat the 1D array
1298 * as a 2D Array with a height of 1. So, here we want to swap image
1301 assert(image
->Depth
== 1);
1302 *width
= image
->Width
;
1304 *depth
= image
->Height
;
1306 case GL_TEXTURE_CUBE_MAP
:
1307 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1308 * though we really have 6 slices.
1310 assert(image
->Depth
== 1);
1311 *width
= image
->Width
;
1312 *height
= image
->Height
;
1316 *width
= image
->Width
;
1317 *height
= image
->Height
;
1318 *depth
= image
->Depth
;
1324 * Can the image be pulled into a unified mipmap tree? This mirrors
1325 * the completeness test in a lot of ways.
1327 * Not sure whether I want to pass gl_texture_image here.
1330 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1331 struct gl_texture_image
*image
)
1333 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1334 GLuint level
= intelImage
->base
.Base
.Level
;
1335 int width
, height
, depth
;
1337 /* glTexImage* choose the texture object based on the target passed in, and
1338 * objects can't change targets over their lifetimes, so this should be
1341 assert(image
->TexObject
->Target
== mt
->target
);
1343 mesa_format mt_format
= mt
->format
;
1344 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1345 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1346 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1347 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1348 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1349 mt_format
= mt
->etc_format
;
1351 if (image
->TexFormat
!= mt_format
)
1354 intel_get_image_dims(image
, &width
, &height
, &depth
);
1356 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1359 if (mt
->surf
.size
> 0) {
1360 if (level
>= mt
->surf
.levels
)
1363 const unsigned level_depth
=
1364 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1365 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1366 mt
->surf
.logical_level0_px
.array_len
;
1368 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1369 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1370 depth
== level_depth
&&
1371 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1374 int level_depth
= mt
->level
[level
].depth
;
1375 if (mt
->num_samples
> 1) {
1376 switch (mt
->msaa_layout
) {
1377 case INTEL_MSAA_LAYOUT_NONE
:
1378 case INTEL_MSAA_LAYOUT_IMS
:
1380 case INTEL_MSAA_LAYOUT_UMS
:
1381 case INTEL_MSAA_LAYOUT_CMS
:
1382 level_depth
/= mt
->num_samples
;
1387 /* Test image dimensions against the base level image adjusted for
1388 * minification. This will also catch images not present in the
1389 * tree, changed targets, etc.
1391 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1392 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1393 depth
!= level_depth
) {
1397 if (image
->NumSamples
!= mt
->num_samples
)
1405 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1407 GLuint x
, GLuint y
, GLuint d
)
1409 mt
->level
[level
].depth
= d
;
1410 mt
->level
[level
].level_x
= x
;
1411 mt
->level
[level
].level_y
= y
;
1413 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1416 assert(mt
->level
[level
].slice
);
1418 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1419 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1424 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1425 GLuint level
, GLuint img
,
1428 if (img
== 0 && level
== 0)
1429 assert(x
== 0 && y
== 0);
1431 assert(img
< mt
->level
[level
].depth
);
1433 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1434 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1436 DBG("%s level %d img %d pos %d,%d\n",
1437 __func__
, level
, img
,
1438 mt
->level
[level
].slice
[img
].x_offset
,
1439 mt
->level
[level
].slice
[img
].y_offset
);
1443 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1444 GLuint level
, GLuint slice
,
1445 GLuint
*x
, GLuint
*y
)
1447 if (mt
->surf
.size
> 0) {
1448 uint32_t x_offset_sa
, y_offset_sa
;
1450 /* Given level is relative to level zero while the miptree may be
1451 * represent just a subset of all levels starting from 'first_level'.
1453 assert(level
>= mt
->first_level
);
1454 level
-= mt
->first_level
;
1456 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1457 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1458 isl_surf_get_image_offset_sa(&mt
->surf
, level
, slice
, z
,
1459 &x_offset_sa
, &y_offset_sa
);
1466 assert(slice
< mt
->level
[level
].depth
);
1468 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1469 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1474 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1475 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1476 * and tile_h is set to 1.
1479 intel_get_tile_dims(uint32_t tiling
, uint32_t cpp
,
1480 uint32_t *tile_w
, uint32_t *tile_h
)
1491 case I915_TILING_NONE
:
1496 unreachable("not reached");
1502 * This function computes masks that may be used to select the bits of the X
1503 * and Y coordinates that indicate the offset within a tile. If the BO is
1504 * untiled, the masks are set to 0.
1507 intel_get_tile_masks(uint32_t tiling
, uint32_t cpp
,
1508 uint32_t *mask_x
, uint32_t *mask_y
)
1510 uint32_t tile_w_bytes
, tile_h
;
1512 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1514 *mask_x
= tile_w_bytes
/ cpp
- 1;
1515 *mask_y
= tile_h
- 1;
1519 * Compute the offset (in bytes) from the start of the BO to the given x
1520 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1521 * multiples of the tile size.
1524 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1525 uint32_t x
, uint32_t y
)
1528 uint32_t pitch
= mt
->pitch
;
1529 uint32_t tiling
= mt
->tiling
;
1533 unreachable("not reached");
1534 case I915_TILING_NONE
:
1535 return y
* pitch
+ x
* cpp
;
1537 assert((x
% (512 / cpp
)) == 0);
1538 assert((y
% 8) == 0);
1539 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1541 assert((x
% (128 / cpp
)) == 0);
1542 assert((y
% 32) == 0);
1543 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1548 * Rendering with tiled buffers requires that the base address of the buffer
1549 * be aligned to a page boundary. For renderbuffers, and sometimes with
1550 * textures, we may want the surface to point at a texture image level that
1551 * isn't at a page boundary.
1553 * This function returns an appropriately-aligned base offset
1554 * according to the tiling restrictions, plus any required x/y offset
1558 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1559 GLuint level
, GLuint slice
,
1564 uint32_t mask_x
, mask_y
;
1566 intel_get_tile_masks(mt
->tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1567 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1569 *tile_x
= x
& mask_x
;
1570 *tile_y
= y
& mask_y
;
1572 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1576 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1577 struct intel_mipmap_tree
*src_mt
,
1578 unsigned src_level
, unsigned src_layer
,
1579 struct intel_mipmap_tree
*dst_mt
,
1580 unsigned dst_level
, unsigned dst_layer
,
1581 unsigned width
, unsigned height
)
1584 ptrdiff_t src_stride
, dst_stride
;
1585 const unsigned cpp
= dst_mt
->surf
.size
> 0 ?
1586 (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8) : dst_mt
->cpp
;
1588 intel_miptree_map(brw
, src_mt
,
1589 src_level
, src_layer
,
1592 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1595 intel_miptree_map(brw
, dst_mt
,
1596 dst_level
, dst_layer
,
1599 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1603 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1604 _mesa_get_format_name(src_mt
->format
),
1605 src_mt
, src
, src_stride
,
1606 _mesa_get_format_name(dst_mt
->format
),
1607 dst_mt
, dst
, dst_stride
,
1610 int row_size
= cpp
* width
;
1611 if (src_stride
== row_size
&&
1612 dst_stride
== row_size
) {
1613 memcpy(dst
, src
, row_size
* height
);
1615 for (int i
= 0; i
< height
; i
++) {
1616 memcpy(dst
, src
, row_size
);
1622 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1623 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1625 /* Don't forget to copy the stencil data over, too. We could have skipped
1626 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1627 * shuffling the two data sources in/out of temporary storage instead of
1628 * the direct mapping we get this way.
1630 if (dst_mt
->stencil_mt
) {
1631 assert(src_mt
->stencil_mt
);
1632 intel_miptree_copy_slice_sw(brw
,
1633 src_mt
->stencil_mt
, src_level
, src_layer
,
1634 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1640 intel_miptree_copy_slice(struct brw_context
*brw
,
1641 struct intel_mipmap_tree
*src_mt
,
1642 unsigned src_level
, unsigned src_layer
,
1643 struct intel_mipmap_tree
*dst_mt
,
1644 unsigned dst_level
, unsigned dst_layer
)
1647 mesa_format format
= src_mt
->format
;
1648 uint32_t width
, height
;
1650 if (src_mt
->surf
.size
> 0) {
1651 width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1652 src_level
- src_mt
->first_level
);
1653 height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1654 src_level
- src_mt
->first_level
);
1656 if (src_mt
->surf
.dim
== ISL_SURF_DIM_3D
)
1657 assert(src_layer
< minify(src_mt
->surf
.phys_level0_sa
.depth
,
1658 src_level
- src_mt
->first_level
));
1660 assert(src_layer
< src_mt
->surf
.phys_level0_sa
.array_len
);
1662 width
= minify(src_mt
->physical_width0
,
1663 src_level
- src_mt
->first_level
);
1664 height
= minify(src_mt
->physical_height0
,
1665 src_level
- src_mt
->first_level
);
1666 assert(src_layer
< src_mt
->level
[src_level
].depth
);
1669 assert(src_mt
->format
== dst_mt
->format
);
1671 if (dst_mt
->compressed
) {
1673 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1674 height
= ALIGN_NPOT(height
, j
) / j
;
1675 width
= ALIGN_NPOT(width
, i
) / i
;
1678 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1679 * below won't apply since we can't do the depth's Y tiling or the
1680 * stencil's W tiling in the blitter.
1682 if (src_mt
->stencil_mt
) {
1683 intel_miptree_copy_slice_sw(brw
,
1684 src_mt
, src_level
, src_layer
,
1685 dst_mt
, dst_level
, dst_layer
,
1690 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1691 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1693 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1696 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1697 _mesa_get_format_name(src_mt
->format
),
1698 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1699 _mesa_get_format_name(dst_mt
->format
),
1700 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1703 if (!intel_miptree_blit(brw
,
1704 src_mt
, src_level
, src_layer
, 0, 0, false,
1705 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1706 width
, height
, GL_COPY
)) {
1707 perf_debug("miptree validate blit for %s failed\n",
1708 _mesa_get_format_name(format
));
1710 intel_miptree_copy_slice_sw(brw
,
1711 src_mt
, src_level
, src_layer
,
1712 dst_mt
, dst_level
, dst_layer
,
1718 * Copies the image's current data to the given miptree, and associates that
1719 * miptree with the image.
1721 * If \c invalidate is true, then the actual image data does not need to be
1722 * copied, but the image still needs to be associated to the new miptree (this
1723 * is set to true if we're about to clear the image).
1726 intel_miptree_copy_teximage(struct brw_context
*brw
,
1727 struct intel_texture_image
*intelImage
,
1728 struct intel_mipmap_tree
*dst_mt
,
1731 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1732 struct intel_texture_object
*intel_obj
=
1733 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1734 int level
= intelImage
->base
.Base
.Level
;
1735 const unsigned face
= intelImage
->base
.Base
.Face
;
1736 unsigned start_layer
, end_layer
;
1738 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1740 assert(intelImage
->base
.Base
.Height
);
1742 end_layer
= intelImage
->base
.Base
.Height
- 1;
1743 } else if (face
> 0) {
1747 assert(intelImage
->base
.Base
.Depth
);
1749 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1753 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1754 intel_miptree_copy_slice(brw
,
1760 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1761 intel_obj
->needs_validate
= true;
1765 intel_miptree_init_mcs(struct brw_context
*brw
,
1766 struct intel_mipmap_tree
*mt
,
1769 assert(mt
->mcs_buf
!= NULL
);
1771 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1773 * When MCS buffer is enabled and bound to MSRT, it is required that it
1774 * is cleared prior to any rendering.
1776 * Since we don't use the MCS buffer for any purpose other than rendering,
1777 * it makes sense to just clear it immediately upon allocation.
1779 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1781 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1782 if (unlikely(map
== NULL
)) {
1783 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1784 brw_bo_unreference(mt
->mcs_buf
->bo
);
1789 memset(data
, init_value
, mt
->mcs_buf
->size
);
1790 brw_bo_unmap(mt
->mcs_buf
->bo
);
1793 static struct intel_miptree_aux_buffer
*
1794 intel_alloc_aux_buffer(struct brw_context
*brw
,
1796 const struct isl_surf
*aux_surf
,
1797 uint32_t alloc_flags
,
1798 struct intel_mipmap_tree
*mt
)
1800 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1804 buf
->size
= aux_surf
->size
;
1805 buf
->pitch
= aux_surf
->row_pitch
;
1806 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1808 /* ISL has stricter set of alignment rules then the drm allocator.
1809 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1810 * trying to recalculate based on different format block sizes.
1812 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1813 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1819 buf
->surf
= *aux_surf
;
1825 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1826 struct intel_mipmap_tree
*mt
,
1829 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1830 assert(mt
->mcs_buf
== NULL
);
1831 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1833 /* Multisampled miptrees are only supported for single level. */
1834 assert(mt
->first_level
== 0);
1835 enum isl_aux_state
**aux_state
=
1836 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1840 struct isl_surf temp_main_surf
;
1841 struct isl_surf temp_mcs_surf
;
1843 /* Create first an ISL presentation for the main color surface and let ISL
1844 * calculate equivalent MCS surface against it.
1846 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1847 MAYBE_UNUSED
bool ok
=
1848 isl_surf_get_mcs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_mcs_surf
);
1851 /* Buffer needs to be initialised requiring the buffer to be immediately
1852 * mapped to cpu space for writing. Therefore do not use the gpu access
1853 * flag which can cause an unnecessary delay if the backing pages happened
1854 * to be just used by the GPU.
1856 const uint32_t alloc_flags
= 0;
1857 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1858 &temp_mcs_surf
, alloc_flags
, mt
);
1864 mt
->aux_state
= aux_state
;
1866 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1872 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1873 struct intel_mipmap_tree
*mt
)
1875 assert(mt
->mcs_buf
== NULL
);
1876 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1877 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1879 struct isl_surf temp_main_surf
;
1880 struct isl_surf temp_ccs_surf
;
1882 /* Create first an ISL presentation for the main color surface and let ISL
1883 * calculate equivalent CCS surface against it.
1885 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1886 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_ccs_surf
))
1889 assert(temp_ccs_surf
.size
&&
1890 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1892 enum isl_aux_state
**aux_state
=
1893 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1897 /* In case of compression mcs buffer needs to be initialised requiring the
1898 * buffer to be immediately mapped to cpu space for writing. Therefore do
1899 * not use the gpu access flag which can cause an unnecessary delay if the
1900 * backing pages happened to be just used by the GPU.
1902 const uint32_t alloc_flags
=
1903 mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
? 0 : BO_ALLOC_FOR_RENDER
;
1904 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1905 &temp_ccs_surf
, alloc_flags
, mt
);
1911 mt
->aux_state
= aux_state
;
1913 /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
1914 * used for lossless compression which requires similar initialisation
1915 * as multi-sample compression.
1917 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1918 /* Hardware sets the auxiliary buffer to all zeroes when it does full
1919 * resolve. Initialize it accordingly in case the first renderer is
1920 * cpu (or other none compression aware party).
1922 * This is also explicitly stated in the spec (MCS Buffer for Render
1924 * "If Software wants to enable Color Compression without Fast clear,
1925 * Software needs to initialize MCS with zeros."
1927 intel_miptree_init_mcs(brw
, mt
, 0);
1928 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_CMS
;
1935 * Helper for intel_miptree_alloc_hiz() that sets
1936 * \c mt->level[level].has_hiz. Return true if and only if
1937 * \c has_hiz was set.
1940 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1941 struct intel_mipmap_tree
*mt
,
1944 assert(mt
->hiz_buf
);
1946 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1947 uint32_t width
= minify(mt
->physical_width0
, level
);
1948 uint32_t height
= minify(mt
->physical_height0
, level
);
1950 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1951 * and the height is 4 aligned. This allows our HiZ support
1952 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1953 * we can grow the width & height to allow the HiZ op to
1954 * force the proper size alignments.
1956 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1957 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1962 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1963 mt
->level
[level
].has_hiz
= true;
1968 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1969 struct intel_mipmap_tree
*mt
)
1971 assert(mt
->hiz_buf
== NULL
);
1972 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1974 enum isl_aux_state
**aux_state
=
1975 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1979 struct isl_surf temp_main_surf
;
1980 struct isl_surf temp_hiz_surf
;
1982 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1983 MAYBE_UNUSED
bool ok
=
1984 isl_surf_get_hiz_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_hiz_surf
);
1987 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
1988 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1989 &temp_hiz_surf
, alloc_flags
, mt
);
1996 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1997 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1999 mt
->aux_state
= aux_state
;
2005 * Can the miptree sample using the hiz buffer?
2008 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
2009 struct intel_mipmap_tree
*mt
)
2011 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
2012 * so keep things conservative for now and never enable it unless we're SKL+.
2022 /* It seems the hardware won't fallback to the depth buffer if some of the
2023 * mipmap levels aren't available in the HiZ buffer. So we need all levels
2024 * of the texture to be HiZ enabled.
2026 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
2027 if (!intel_miptree_level_has_hiz(mt
, level
))
2031 /* If compressed multisampling is enabled, then we use it for the auxiliary
2034 * From the BDW PRM (Volume 2d: Command Reference: Structures
2035 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
2037 * "If this field is set to AUX_HIZ, Number of Multisamples must be
2038 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
2040 * There is no such blurb for 1D textures, but there is sufficient evidence
2041 * that this is broken on SKL+.
2043 return (mt
->num_samples
<= 1 &&
2044 mt
->target
!= GL_TEXTURE_3D
&&
2045 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
2049 * Does the miptree slice have hiz enabled?
2052 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
2054 intel_miptree_check_level_layer(mt
, level
, 0);
2055 return mt
->level
[level
].has_hiz
;
2059 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2060 unsigned start_level
, unsigned num_levels
,
2061 unsigned start_layer
, unsigned num_layers
)
2063 assert(_mesa_is_format_color_format(mt
->format
));
2068 /* Clamp the level range to fit the miptree */
2069 assert(start_level
+ num_levels
>= start_level
);
2070 const uint32_t last_level
=
2071 MIN2(mt
->last_level
, start_level
+ num_levels
- 1);
2072 start_level
= MAX2(mt
->first_level
, start_level
);
2073 num_levels
= last_level
- start_level
+ 1;
2075 for (uint32_t level
= start_level
; level
<= last_level
; level
++) {
2076 const uint32_t level_layers
= MIN2(num_layers
, mt
->level
[level
].depth
);
2077 for (unsigned a
= 0; a
< level_layers
; a
++) {
2078 enum isl_aux_state aux_state
=
2079 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2080 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2081 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2090 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2091 const struct intel_mipmap_tree
*mt
,
2092 unsigned level
, unsigned layer
)
2098 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2099 assert(brw
->gen
>= 8 ||
2100 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2102 /* Compression of arrayed msaa surfaces is supported. */
2103 if (mt
->num_samples
> 1)
2106 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2107 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
2113 static enum blorp_fast_clear_op
2114 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2115 bool ccs_supported
, bool fast_clear_supported
)
2117 assert(ccs_supported
== fast_clear_supported
);
2119 switch (aux_state
) {
2120 case ISL_AUX_STATE_CLEAR
:
2121 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2123 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2125 return BLORP_FAST_CLEAR_OP_NONE
;
2127 case ISL_AUX_STATE_PASS_THROUGH
:
2128 return BLORP_FAST_CLEAR_OP_NONE
;
2130 case ISL_AUX_STATE_RESOLVED
:
2131 case ISL_AUX_STATE_AUX_INVALID
:
2132 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2136 unreachable("Invalid aux state for CCS_D");
2139 static enum blorp_fast_clear_op
2140 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2141 bool ccs_supported
, bool fast_clear_supported
)
2143 switch (aux_state
) {
2144 case ISL_AUX_STATE_CLEAR
:
2145 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2147 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2148 else if (!fast_clear_supported
)
2149 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2151 return BLORP_FAST_CLEAR_OP_NONE
;
2153 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2155 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2157 return BLORP_FAST_CLEAR_OP_NONE
;
2159 case ISL_AUX_STATE_PASS_THROUGH
:
2160 return BLORP_FAST_CLEAR_OP_NONE
;
2162 case ISL_AUX_STATE_RESOLVED
:
2163 case ISL_AUX_STATE_AUX_INVALID
:
2167 unreachable("Invalid aux state for CCS_E");
2171 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2172 struct intel_mipmap_tree
*mt
,
2173 uint32_t level
, uint32_t layer
,
2175 bool fast_clear_supported
)
2177 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2179 enum blorp_fast_clear_op resolve_op
;
2180 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
2181 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_supported
,
2182 fast_clear_supported
);
2184 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_supported
,
2185 fast_clear_supported
);
2188 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2189 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2190 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2192 switch (resolve_op
) {
2193 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2194 /* The CCS full resolve operation destroys the CCS and sets it to the
2195 * pass-through state. (You can also think of this as being both a
2196 * resolve and an ambiguate in one operation.)
2198 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2199 ISL_AUX_STATE_PASS_THROUGH
);
2202 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2203 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2204 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2208 unreachable("Invalid resolve op");
2214 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2215 struct intel_mipmap_tree
*mt
,
2216 uint32_t level
, uint32_t layer
,
2217 bool written_with_ccs
)
2219 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2221 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
2222 switch (aux_state
) {
2223 case ISL_AUX_STATE_CLEAR
:
2224 assert(written_with_ccs
);
2225 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2226 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2229 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2230 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2231 assert(written_with_ccs
);
2232 break; /* Nothing to do */
2234 case ISL_AUX_STATE_PASS_THROUGH
:
2235 if (written_with_ccs
) {
2236 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2237 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2243 case ISL_AUX_STATE_RESOLVED
:
2244 case ISL_AUX_STATE_AUX_INVALID
:
2245 unreachable("Invalid aux state for CCS_E");
2248 /* CCS_D is a bit simpler */
2249 switch (aux_state
) {
2250 case ISL_AUX_STATE_CLEAR
:
2251 assert(written_with_ccs
);
2252 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2253 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2256 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2257 assert(written_with_ccs
);
2258 break; /* Nothing to do */
2260 case ISL_AUX_STATE_PASS_THROUGH
:
2264 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2265 case ISL_AUX_STATE_RESOLVED
:
2266 case ISL_AUX_STATE_AUX_INVALID
:
2267 unreachable("Invalid aux state for CCS_D");
2273 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2274 struct intel_mipmap_tree
*mt
,
2275 uint32_t level
, uint32_t layer
,
2276 bool written_with_aux
)
2278 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2279 case ISL_AUX_STATE_CLEAR
:
2280 assert(written_with_aux
);
2281 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2282 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2285 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2286 assert(written_with_aux
);
2287 break; /* Nothing to do */
2289 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2290 case ISL_AUX_STATE_RESOLVED
:
2291 case ISL_AUX_STATE_PASS_THROUGH
:
2292 case ISL_AUX_STATE_AUX_INVALID
:
2293 unreachable("Invalid aux state for MCS");
2298 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2299 struct intel_mipmap_tree
*mt
,
2300 uint32_t level
, uint32_t layer
,
2301 bool hiz_supported
, bool fast_clear_supported
)
2303 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2304 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2305 case ISL_AUX_STATE_CLEAR
:
2306 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2307 if (!hiz_supported
|| !fast_clear_supported
)
2308 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2311 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2313 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2316 case ISL_AUX_STATE_PASS_THROUGH
:
2317 case ISL_AUX_STATE_RESOLVED
:
2320 case ISL_AUX_STATE_AUX_INVALID
:
2322 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2326 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2327 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2330 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2331 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2332 ISL_AUX_STATE_RESOLVED
);
2335 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2336 /* The HiZ resolve operation is actually an ambiguate */
2337 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2338 ISL_AUX_STATE_PASS_THROUGH
);
2342 unreachable("Invalid HiZ op");
2348 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2349 struct intel_mipmap_tree
*mt
,
2350 uint32_t level
, uint32_t layer
,
2351 bool written_with_hiz
)
2353 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2354 case ISL_AUX_STATE_CLEAR
:
2355 assert(written_with_hiz
);
2356 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2357 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2360 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2361 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2362 assert(written_with_hiz
);
2363 break; /* Nothing to do */
2365 case ISL_AUX_STATE_RESOLVED
:
2366 if (written_with_hiz
) {
2367 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2368 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2370 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2371 ISL_AUX_STATE_AUX_INVALID
);
2375 case ISL_AUX_STATE_PASS_THROUGH
:
2376 if (written_with_hiz
) {
2377 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2378 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2382 case ISL_AUX_STATE_AUX_INVALID
:
2383 assert(!written_with_hiz
);
2388 static inline uint32_t
2389 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
2390 uint32_t start_level
, uint32_t num_levels
)
2392 assert(start_level
>= mt
->first_level
);
2393 assert(start_level
<= mt
->last_level
);
2395 if (num_levels
== INTEL_REMAINING_LAYERS
)
2396 num_levels
= mt
->last_level
- start_level
+ 1;
2397 /* Check for overflow */
2398 assert(start_level
+ num_levels
>= start_level
);
2399 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2404 static inline uint32_t
2405 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2406 uint32_t start_layer
, uint32_t num_layers
)
2408 assert(level
<= mt
->last_level
);
2409 uint32_t total_num_layers
;
2411 if (mt
->surf
.size
> 0)
2412 total_num_layers
= mt
->surf
.dim
== ISL_SURF_DIM_3D
?
2413 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
2414 mt
->surf
.phys_level0_sa
.array_len
;
2416 total_num_layers
= mt
->level
[level
].depth
;
2418 assert(start_layer
< total_num_layers
);
2419 if (num_layers
== INTEL_REMAINING_LAYERS
)
2420 num_layers
= total_num_layers
- start_layer
;
2421 /* Check for overflow */
2422 assert(start_layer
+ num_layers
>= start_layer
);
2423 assert(start_layer
+ num_layers
<= total_num_layers
);
2429 intel_miptree_prepare_access(struct brw_context
*brw
,
2430 struct intel_mipmap_tree
*mt
,
2431 uint32_t start_level
, uint32_t num_levels
,
2432 uint32_t start_layer
, uint32_t num_layers
,
2433 bool aux_supported
, bool fast_clear_supported
)
2435 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2437 if (_mesa_is_format_color_format(mt
->format
)) {
2441 if (mt
->num_samples
> 1) {
2442 /* Nothing to do for MSAA */
2443 assert(aux_supported
&& fast_clear_supported
);
2445 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2446 const uint32_t level
= start_level
+ l
;
2447 const uint32_t level_layers
=
2448 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2449 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2450 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2451 start_layer
+ a
, aux_supported
,
2452 fast_clear_supported
);
2456 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2457 /* Nothing to do for stencil */
2462 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2463 const uint32_t level
= start_level
+ l
;
2464 if (!intel_miptree_level_has_hiz(mt
, level
))
2467 const uint32_t level_layers
=
2468 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2469 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2470 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2472 fast_clear_supported
);
2479 intel_miptree_finish_write(struct brw_context
*brw
,
2480 struct intel_mipmap_tree
*mt
, uint32_t level
,
2481 uint32_t start_layer
, uint32_t num_layers
,
2482 bool written_with_aux
)
2484 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2486 if (_mesa_is_format_color_format(mt
->format
)) {
2490 if (mt
->num_samples
> 1) {
2491 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2492 intel_miptree_finish_mcs_write(brw
, mt
, level
, start_layer
+ a
,
2496 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2497 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2501 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2502 /* Nothing to do for stencil */
2504 if (!intel_miptree_level_has_hiz(mt
, level
))
2507 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2508 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2515 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2516 uint32_t level
, uint32_t layer
)
2518 intel_miptree_check_level_layer(mt
, level
, layer
);
2520 if (_mesa_is_format_color_format(mt
->format
)) {
2521 assert(mt
->mcs_buf
!= NULL
);
2522 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2523 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2524 unreachable("Cannot get aux state for stencil");
2526 assert(intel_miptree_level_has_hiz(mt
, level
));
2529 return mt
->aux_state
[level
][layer
];
2533 intel_miptree_set_aux_state(struct brw_context
*brw
,
2534 struct intel_mipmap_tree
*mt
, uint32_t level
,
2535 uint32_t start_layer
, uint32_t num_layers
,
2536 enum isl_aux_state aux_state
)
2538 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2540 if (_mesa_is_format_color_format(mt
->format
)) {
2541 assert(mt
->mcs_buf
!= NULL
);
2542 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2543 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2544 unreachable("Cannot get aux state for stencil");
2546 assert(intel_miptree_level_has_hiz(mt
, level
));
2549 for (unsigned a
= 0; a
< num_layers
; a
++)
2550 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2553 /* On Gen9 color buffers may be compressed by the hardware (lossless
2554 * compression). There are, however, format restrictions and care needs to be
2555 * taken that the sampler engine is capable for re-interpreting a buffer with
2556 * format different the buffer was originally written with.
2558 * For example, SRGB formats are not compressible and the sampler engine isn't
2559 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2560 * color buffer needs to be resolved so that the sampling surface can be
2561 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2565 can_texture_with_ccs(struct brw_context
*brw
,
2566 struct intel_mipmap_tree
*mt
,
2567 mesa_format view_format
)
2569 if (!intel_miptree_is_lossless_compressed(brw
, mt
))
2572 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2573 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2575 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2576 isl_mt_format
, isl_view_format
)) {
2577 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2578 _mesa_get_format_name(view_format
),
2579 _mesa_get_format_name(mt
->format
));
2587 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2588 struct intel_mipmap_tree
*mt
,
2589 mesa_format view_format
,
2590 uint32_t start_level
, uint32_t num_levels
,
2591 uint32_t start_layer
, uint32_t num_layers
,
2592 bool *aux_supported_out
)
2594 bool aux_supported
, clear_supported
;
2595 if (_mesa_is_format_color_format(mt
->format
)) {
2596 if (mt
->num_samples
> 1) {
2597 aux_supported
= clear_supported
= true;
2599 aux_supported
= can_texture_with_ccs(brw
, mt
, view_format
);
2601 /* Clear color is specified as ints or floats and the conversion is
2602 * done by the sampler. If we have a texture view, we would have to
2603 * perform the clear color conversion manually. Just disable clear
2606 clear_supported
= aux_supported
&& (mt
->format
== view_format
);
2608 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2609 aux_supported
= clear_supported
= false;
2611 aux_supported
= clear_supported
= intel_miptree_sample_with_hiz(brw
, mt
);
2614 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2615 start_layer
, num_layers
,
2616 aux_supported
, clear_supported
);
2617 if (aux_supported_out
)
2618 *aux_supported_out
= aux_supported
;
2622 intel_miptree_prepare_texture(struct brw_context
*brw
,
2623 struct intel_mipmap_tree
*mt
,
2624 mesa_format view_format
,
2625 bool *aux_supported_out
)
2627 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2628 0, INTEL_REMAINING_LEVELS
,
2629 0, INTEL_REMAINING_LAYERS
,
2634 intel_miptree_prepare_image(struct brw_context
*brw
,
2635 struct intel_mipmap_tree
*mt
)
2637 /* The data port doesn't understand any compression */
2638 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2639 0, INTEL_REMAINING_LAYERS
, false, false);
2643 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2644 struct intel_mipmap_tree
*mt
, uint32_t level
,
2645 uint32_t start_layer
, uint32_t num_layers
)
2647 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2648 start_layer
, num_layers
, NULL
);
2652 intel_miptree_prepare_render(struct brw_context
*brw
,
2653 struct intel_mipmap_tree
*mt
, uint32_t level
,
2654 uint32_t start_layer
, uint32_t layer_count
,
2657 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2658 * the single-sampled color renderbuffers because the CCS buffer isn't
2659 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2660 * enabled because otherwise the surface state will be programmed with
2661 * the linear equivalent format anyway.
2663 if (brw
->gen
== 9 && srgb_enabled
&& mt
->num_samples
<= 1 &&
2664 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2666 /* Lossless compression is not supported for SRGB formats, it
2667 * should be impossible to get here with such surfaces.
2669 assert(!intel_miptree_is_lossless_compressed(brw
, mt
));
2670 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2676 intel_miptree_finish_render(struct brw_context
*brw
,
2677 struct intel_mipmap_tree
*mt
, uint32_t level
,
2678 uint32_t start_layer
, uint32_t layer_count
)
2680 assert(_mesa_is_format_color_format(mt
->format
));
2681 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2682 mt
->mcs_buf
!= NULL
);
2686 intel_miptree_prepare_depth(struct brw_context
*brw
,
2687 struct intel_mipmap_tree
*mt
, uint32_t level
,
2688 uint32_t start_layer
, uint32_t layer_count
)
2690 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2691 mt
->hiz_buf
!= NULL
, mt
->hiz_buf
!= NULL
);
2695 intel_miptree_finish_depth(struct brw_context
*brw
,
2696 struct intel_mipmap_tree
*mt
, uint32_t level
,
2697 uint32_t start_layer
, uint32_t layer_count
,
2700 if (depth_written
) {
2701 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2702 mt
->hiz_buf
!= NULL
);
2707 * Make it possible to share the BO backing the given miptree with another
2708 * process or another miptree.
2710 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2711 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2712 * ensure that no MCS buffer gets allocated in the future.
2714 * HiZ is similarly unsafe with shared buffers.
2717 intel_miptree_make_shareable(struct brw_context
*brw
,
2718 struct intel_mipmap_tree
*mt
)
2720 /* MCS buffers are also used for multisample buffers, but we can't resolve
2721 * away a multisample MCS buffer because it's an integral part of how the
2722 * pixel data is stored. Fortunately this code path should never be
2723 * reached for multisample buffers.
2725 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
|| mt
->num_samples
<= 1);
2727 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2728 0, INTEL_REMAINING_LAYERS
, false, false);
2731 brw_bo_unreference(mt
->mcs_buf
->bo
);
2735 /* Any pending MCS/CCS operations are no longer needed. Trying to
2736 * execute any will likely crash due to the missing aux buffer. So let's
2737 * delete all pending ops.
2739 free(mt
->aux_state
);
2740 mt
->aux_state
= NULL
;
2744 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2747 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2748 mt
->level
[l
].has_hiz
= false;
2751 /* Any pending HiZ operations are no longer needed. Trying to execute
2752 * any will likely crash due to the missing aux buffer. So let's delete
2755 free(mt
->aux_state
);
2756 mt
->aux_state
= NULL
;
2759 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2764 * \brief Get pointer offset into stencil buffer.
2766 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2767 * must decode the tile's layout in software.
2770 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2772 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2774 * Even though the returned offset is always positive, the return type is
2776 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2777 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2780 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2782 uint32_t tile_size
= 4096;
2783 uint32_t tile_width
= 64;
2784 uint32_t tile_height
= 64;
2785 uint32_t row_size
= 64 * stride
;
2787 uint32_t tile_x
= x
/ tile_width
;
2788 uint32_t tile_y
= y
/ tile_height
;
2790 /* The byte's address relative to the tile's base addres. */
2791 uint32_t byte_x
= x
% tile_width
;
2792 uint32_t byte_y
= y
% tile_height
;
2794 uintptr_t u
= tile_y
* row_size
2795 + tile_x
* tile_size
2796 + 512 * (byte_x
/ 8)
2798 + 32 * ((byte_y
/ 4) % 2)
2799 + 16 * ((byte_x
/ 4) % 2)
2800 + 8 * ((byte_y
/ 2) % 2)
2801 + 4 * ((byte_x
/ 2) % 2)
2806 /* adjust for bit6 swizzling */
2807 if (((byte_x
/ 8) % 2) == 1) {
2808 if (((byte_y
/ 8) % 2) == 0) {
2820 intel_miptree_updownsample(struct brw_context
*brw
,
2821 struct intel_mipmap_tree
*src
,
2822 struct intel_mipmap_tree
*dst
)
2824 unsigned src_w
, src_h
, dst_w
, dst_h
;
2826 if (src
->surf
.size
> 0) {
2827 src_w
= src
->surf
.logical_level0_px
.width
;
2828 src_h
= src
->surf
.logical_level0_px
.height
;
2830 src_w
= src
->logical_width0
;
2831 src_h
= src
->logical_height0
;
2834 if (dst
->surf
.size
> 0) {
2835 dst_w
= dst
->surf
.logical_level0_px
.width
;
2836 dst_h
= dst
->surf
.logical_level0_px
.height
;
2838 dst_w
= dst
->logical_width0
;
2839 dst_h
= dst
->logical_height0
;
2842 brw_blorp_blit_miptrees(brw
,
2843 src
, 0 /* level */, 0 /* layer */,
2844 src
->format
, SWIZZLE_XYZW
,
2845 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2848 GL_NEAREST
, false, false /*mirror x, y*/,
2851 if (src
->stencil_mt
) {
2852 if (src
->stencil_mt
->surf
.size
> 0) {
2853 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2854 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2856 src_w
= src
->stencil_mt
->logical_width0
;
2857 src_h
= src
->stencil_mt
->logical_height0
;
2860 if (dst
->stencil_mt
->surf
.size
> 0) {
2861 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2862 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2864 dst_w
= dst
->stencil_mt
->logical_width0
;
2865 dst_h
= dst
->stencil_mt
->logical_height0
;
2868 brw_blorp_blit_miptrees(brw
,
2869 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2870 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2871 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2872 dst
->stencil_mt
->format
,
2875 GL_NEAREST
, false, false /*mirror x, y*/,
2876 false, false /* decode/encode srgb */);
2881 intel_update_r8stencil(struct brw_context
*brw
,
2882 struct intel_mipmap_tree
*mt
)
2884 assert(brw
->gen
>= 7);
2885 struct intel_mipmap_tree
*src
=
2886 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2887 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2890 if (!mt
->r8stencil_mt
) {
2891 const uint32_t r8stencil_flags
=
2892 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2893 MIPTREE_LAYOUT_DISABLE_AUX
;
2894 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2895 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2897 MESA_FORMAT_R_UINT8
,
2900 src
->logical_width0
,
2901 src
->logical_height0
,
2902 src
->logical_depth0
,
2905 assert(mt
->r8stencil_mt
);
2908 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2910 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2911 const unsigned depth
= src
->level
[level
].depth
;
2913 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2914 brw_blorp_copy_miptrees(brw
,
2918 minify(src
->logical_width0
, level
),
2919 minify(src
->logical_height0
, level
));
2923 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2924 src
->r8stencil_needs_update
= false;
2928 intel_miptree_map_raw(struct brw_context
*brw
,
2929 struct intel_mipmap_tree
*mt
,
2932 struct brw_bo
*bo
= mt
->bo
;
2934 if (brw_batch_references(&brw
->batch
, bo
))
2935 intel_batchbuffer_flush(brw
);
2937 return brw_bo_map(brw
, bo
, mode
);
2941 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2943 brw_bo_unmap(mt
->bo
);
2947 intel_miptree_map_gtt(struct brw_context
*brw
,
2948 struct intel_mipmap_tree
*mt
,
2949 struct intel_miptree_map
*map
,
2950 unsigned int level
, unsigned int slice
)
2952 unsigned int bw
, bh
;
2954 unsigned int image_x
, image_y
;
2955 intptr_t x
= map
->x
;
2956 intptr_t y
= map
->y
;
2958 /* For compressed formats, the stride is the number of bytes per
2959 * row of blocks. intel_miptree_get_image_offset() already does
2962 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2963 assert(y
% bh
== 0);
2964 assert(x
% bw
== 0);
2968 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
2975 /* Note that in the case of cube maps, the caller must have passed the
2976 * slice number referencing the face.
2978 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2982 map
->stride
= mt
->pitch
;
2983 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2986 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2987 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2988 map
->x
, map
->y
, map
->w
, map
->h
,
2989 mt
, _mesa_get_format_name(mt
->format
),
2990 x
, y
, map
->ptr
, map
->stride
);
2994 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2996 intel_miptree_unmap_raw(mt
);
3000 intel_miptree_map_blit(struct brw_context
*brw
,
3001 struct intel_mipmap_tree
*mt
,
3002 struct intel_miptree_map
*map
,
3003 unsigned int level
, unsigned int slice
)
3005 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3006 /* first_level */ 0,
3010 MIPTREE_LAYOUT_TILING_NONE
);
3012 if (!map
->linear_mt
) {
3013 fprintf(stderr
, "Failed to allocate blit temporary\n");
3016 map
->stride
= map
->linear_mt
->pitch
;
3018 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3019 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3020 * invalidate is set, since we'll be writing the whole rectangle from our
3021 * temporary buffer back out.
3023 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3024 if (!intel_miptree_copy(brw
,
3025 mt
, level
, slice
, map
->x
, map
->y
,
3026 map
->linear_mt
, 0, 0, 0, 0,
3028 fprintf(stderr
, "Failed to blit\n");
3033 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3035 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3036 map
->x
, map
->y
, map
->w
, map
->h
,
3037 mt
, _mesa_get_format_name(mt
->format
),
3038 level
, slice
, map
->ptr
, map
->stride
);
3043 intel_miptree_release(&map
->linear_mt
);
3049 intel_miptree_unmap_blit(struct brw_context
*brw
,
3050 struct intel_mipmap_tree
*mt
,
3051 struct intel_miptree_map
*map
,
3055 struct gl_context
*ctx
= &brw
->ctx
;
3057 intel_miptree_unmap_raw(map
->linear_mt
);
3059 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3060 bool ok
= intel_miptree_copy(brw
,
3061 map
->linear_mt
, 0, 0, 0, 0,
3062 mt
, level
, slice
, map
->x
, map
->y
,
3064 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3067 intel_miptree_release(&map
->linear_mt
);
3071 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3073 #if defined(USE_SSE41)
3075 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3076 struct intel_mipmap_tree
*mt
,
3077 struct intel_miptree_map
*map
,
3078 unsigned int level
, unsigned int slice
)
3080 assert(map
->mode
& GL_MAP_READ_BIT
);
3081 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3083 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3084 map
->x
, map
->y
, map
->w
, map
->h
,
3085 mt
, _mesa_get_format_name(mt
->format
),
3086 level
, slice
, map
->ptr
, map
->stride
);
3088 /* Map the original image */
3091 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3095 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3101 src
+= image_y
* mt
->pitch
;
3102 src
+= image_x
* mt
->cpp
;
3104 /* Due to the pixel offsets for the particular image being mapped, our
3105 * src pointer may not be 16-byte aligned. However, if the pitch is
3106 * divisible by 16, then the amount by which it's misaligned will remain
3107 * consistent from row to row.
3109 assert((mt
->pitch
% 16) == 0);
3110 const int misalignment
= ((uintptr_t) src
) & 15;
3112 /* Create an untiled temporary buffer for the mapping. */
3113 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3115 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3117 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3118 /* Offset the destination so it has the same misalignment as src. */
3119 map
->ptr
= map
->buffer
+ misalignment
;
3121 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3123 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3124 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3125 void *src_ptr
= src
+ y
* mt
->pitch
;
3127 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3130 intel_miptree_unmap_raw(mt
);
3134 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3135 struct intel_mipmap_tree
*mt
,
3136 struct intel_miptree_map
*map
,
3140 _mesa_align_free(map
->buffer
);
3147 intel_miptree_map_s8(struct brw_context
*brw
,
3148 struct intel_mipmap_tree
*mt
,
3149 struct intel_miptree_map
*map
,
3150 unsigned int level
, unsigned int slice
)
3152 map
->stride
= map
->w
;
3153 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3157 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3158 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3159 * invalidate is set, since we'll be writing the whole rectangle from our
3160 * temporary buffer back out.
3162 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3163 /* ISL uses a stencil pitch value that is expected by hardware whereas
3164 * traditional miptree uses half of that. Below the value gets supplied
3165 * to intel_offset_S8() which expects the legacy interpretation.
3167 const unsigned pitch
= mt
->surf
.size
> 0 ?
3168 mt
->surf
.row_pitch
/ 2 : mt
->pitch
;
3169 uint8_t *untiled_s8_map
= map
->ptr
;
3170 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3171 unsigned int image_x
, image_y
;
3173 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3175 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3176 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3177 ptrdiff_t offset
= intel_offset_S8(pitch
,
3178 x
+ image_x
+ map
->x
,
3179 y
+ image_y
+ map
->y
,
3180 brw
->has_swizzling
);
3181 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3185 intel_miptree_unmap_raw(mt
);
3187 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3188 map
->x
, map
->y
, map
->w
, map
->h
,
3189 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3191 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3192 map
->x
, map
->y
, map
->w
, map
->h
,
3193 mt
, map
->ptr
, map
->stride
);
3198 intel_miptree_unmap_s8(struct brw_context
*brw
,
3199 struct intel_mipmap_tree
*mt
,
3200 struct intel_miptree_map
*map
,
3204 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3205 /* ISL uses a stencil pitch value that is expected by hardware whereas
3206 * traditional miptree uses half of that. Below the value gets supplied
3207 * to intel_offset_S8() which expects the legacy interpretation.
3209 const unsigned pitch
= mt
->surf
.size
> 0 ?
3210 mt
->surf
.row_pitch
/ 2: mt
->pitch
;
3211 unsigned int image_x
, image_y
;
3212 uint8_t *untiled_s8_map
= map
->ptr
;
3213 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3215 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3217 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3218 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3219 ptrdiff_t offset
= intel_offset_S8(pitch
,
3220 image_x
+ x
+ map
->x
,
3221 image_y
+ y
+ map
->y
,
3222 brw
->has_swizzling
);
3223 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3227 intel_miptree_unmap_raw(mt
);
3234 intel_miptree_map_etc(struct brw_context
*brw
,
3235 struct intel_mipmap_tree
*mt
,
3236 struct intel_miptree_map
*map
,
3240 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3241 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3242 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3245 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3246 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3248 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3249 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3250 map
->w
, map
->h
, 1));
3251 map
->ptr
= map
->buffer
;
3255 intel_miptree_unmap_etc(struct brw_context
*brw
,
3256 struct intel_mipmap_tree
*mt
,
3257 struct intel_miptree_map
*map
,
3263 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3268 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3269 + image_y
* mt
->pitch
3270 + image_x
* mt
->cpp
;
3272 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3273 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
3274 map
->ptr
, map
->stride
,
3277 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
3278 map
->ptr
, map
->stride
,
3279 map
->w
, map
->h
, mt
->etc_format
);
3281 intel_miptree_unmap_raw(mt
);
3286 * Mapping function for packed depth/stencil miptrees backed by real separate
3287 * miptrees for depth and stencil.
3289 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3290 * separate from the depth buffer. Yet at the GL API level, we have to expose
3291 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3292 * be able to map that memory for texture storage and glReadPixels-type
3293 * operations. We give Mesa core that access by mallocing a temporary and
3294 * copying the data between the actual backing store and the temporary.
3297 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3298 struct intel_mipmap_tree
*mt
,
3299 struct intel_miptree_map
*map
,
3300 unsigned int level
, unsigned int slice
)
3302 struct intel_mipmap_tree
*z_mt
= mt
;
3303 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3304 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3305 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3307 map
->stride
= map
->w
* packed_bpp
;
3308 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3312 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3313 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3314 * invalidate is set, since we'll be writing the whole rectangle from our
3315 * temporary buffer back out.
3317 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3318 /* ISL uses a stencil pitch value that is expected by hardware whereas
3319 * traditional miptree uses half of that. Below the value gets supplied
3320 * to intel_offset_S8() which expects the legacy interpretation.
3322 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3323 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3324 uint32_t *packed_map
= map
->ptr
;
3325 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3326 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3327 unsigned int s_image_x
, s_image_y
;
3328 unsigned int z_image_x
, z_image_y
;
3330 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3331 &s_image_x
, &s_image_y
);
3332 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3333 &z_image_x
, &z_image_y
);
3335 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3336 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3337 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3338 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3341 brw
->has_swizzling
);
3342 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3344 (map_x
+ z_image_x
));
3345 uint8_t s
= s_map
[s_offset
];
3346 uint32_t z
= z_map
[z_offset
];
3348 if (map_z32f_x24s8
) {
3349 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3350 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3352 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3357 intel_miptree_unmap_raw(s_mt
);
3358 intel_miptree_unmap_raw(z_mt
);
3360 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3362 map
->x
, map
->y
, map
->w
, map
->h
,
3363 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3364 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3365 map
->ptr
, map
->stride
);
3367 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3368 map
->x
, map
->y
, map
->w
, map
->h
,
3369 mt
, map
->ptr
, map
->stride
);
3374 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3375 struct intel_mipmap_tree
*mt
,
3376 struct intel_miptree_map
*map
,
3380 struct intel_mipmap_tree
*z_mt
= mt
;
3381 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3382 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3384 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3385 /* ISL uses a stencil pitch value that is expected by hardware whereas
3386 * traditional miptree uses half of that. Below the value gets supplied
3387 * to intel_offset_S8() which expects the legacy interpretation.
3389 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3390 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3391 uint32_t *packed_map
= map
->ptr
;
3392 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3393 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3394 unsigned int s_image_x
, s_image_y
;
3395 unsigned int z_image_x
, z_image_y
;
3397 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3398 &s_image_x
, &s_image_y
);
3399 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3400 &z_image_x
, &z_image_y
);
3402 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3403 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3404 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3405 x
+ s_image_x
+ map
->x
,
3406 y
+ s_image_y
+ map
->y
,
3407 brw
->has_swizzling
);
3408 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3410 (x
+ z_image_x
+ map
->x
));
3412 if (map_z32f_x24s8
) {
3413 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3414 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3416 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3417 s_map
[s_offset
] = packed
>> 24;
3418 z_map
[z_offset
] = packed
;
3423 intel_miptree_unmap_raw(s_mt
);
3424 intel_miptree_unmap_raw(z_mt
);
3426 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3428 map
->x
, map
->y
, map
->w
, map
->h
,
3429 z_mt
, _mesa_get_format_name(z_mt
->format
),
3430 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3431 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3432 map
->ptr
, map
->stride
);
3439 * Create and attach a map to the miptree at (level, slice). Return the
3442 static struct intel_miptree_map
*
3443 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3452 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3457 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3458 mt
->level
[level
].slice
[slice
].map
= map
;
3470 * Release the map at (level, slice).
3473 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3477 struct intel_miptree_map
**map
;
3479 map
= &mt
->level
[level
].slice
[slice
].map
;
3485 can_blit_slice(struct intel_mipmap_tree
*mt
,
3486 unsigned int level
, unsigned int slice
)
3488 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3489 if (mt
->pitch
>= 32768)
3496 use_intel_mipree_map_blit(struct brw_context
*brw
,
3497 struct intel_mipmap_tree
*mt
,
3503 /* It's probably not worth swapping to the blit ring because of
3504 * all the overhead involved.
3506 !(mode
& GL_MAP_WRITE_BIT
) &&
3508 (mt
->tiling
== I915_TILING_X
||
3509 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3510 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
3511 /* Fast copy blit on skl+ supports all tiling formats. */
3513 can_blit_slice(mt
, level
, slice
))
3516 if (mt
->tiling
!= I915_TILING_NONE
&&
3517 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3518 assert(can_blit_slice(mt
, level
, slice
));
3526 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3527 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3528 * arithmetic overflow.
3530 * If you call this function and use \a out_stride, then you're doing pointer
3531 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3532 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3533 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3534 * which usually have type uint32_t or GLuint.
3537 intel_miptree_map(struct brw_context
*brw
,
3538 struct intel_mipmap_tree
*mt
,
3547 ptrdiff_t *out_stride
)
3549 struct intel_miptree_map
*map
;
3551 assert(mt
->num_samples
<= 1);
3553 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3560 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3561 map
->mode
& GL_MAP_WRITE_BIT
);
3563 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3564 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3565 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3566 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3567 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3568 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3569 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3570 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3571 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3572 #if defined(USE_SSE41)
3573 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3574 !mt
->compressed
&& cpu_has_sse4_1
&&
3575 (mt
->pitch
% 16 == 0)) {
3576 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3579 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3582 *out_ptr
= map
->ptr
;
3583 *out_stride
= map
->stride
;
3585 if (map
->ptr
== NULL
)
3586 intel_miptree_release_map(mt
, level
, slice
);
3590 intel_miptree_unmap(struct brw_context
*brw
,
3591 struct intel_mipmap_tree
*mt
,
3595 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3597 assert(mt
->num_samples
<= 1);
3602 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3603 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3605 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3606 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3607 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3608 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3609 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3610 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3611 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3612 } else if (map
->linear_mt
) {
3613 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3614 #if defined(USE_SSE41)
3615 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3616 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3619 intel_miptree_unmap_gtt(mt
);
3622 intel_miptree_release_map(mt
, level
, slice
);
3626 get_isl_surf_dim(GLenum target
)
3630 case GL_TEXTURE_1D_ARRAY
:
3631 return ISL_SURF_DIM_1D
;
3634 case GL_TEXTURE_2D_ARRAY
:
3635 case GL_TEXTURE_RECTANGLE
:
3636 case GL_TEXTURE_CUBE_MAP
:
3637 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3638 case GL_TEXTURE_2D_MULTISAMPLE
:
3639 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3640 case GL_TEXTURE_EXTERNAL_OES
:
3641 return ISL_SURF_DIM_2D
;
3644 return ISL_SURF_DIM_3D
;
3647 unreachable("Invalid texture target");
3651 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3652 GLenum target
, enum miptree_array_layout array_layout
)
3654 if (array_layout
== GEN6_HIZ_STENCIL
)
3655 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
3659 case GL_TEXTURE_1D_ARRAY
:
3660 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3661 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3664 case GL_TEXTURE_2D_ARRAY
:
3665 case GL_TEXTURE_RECTANGLE
:
3666 case GL_TEXTURE_2D_MULTISAMPLE
:
3667 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3668 case GL_TEXTURE_EXTERNAL_OES
:
3669 return ISL_DIM_LAYOUT_GEN4_2D
;
3671 case GL_TEXTURE_CUBE_MAP
:
3672 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3673 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3674 ISL_DIM_LAYOUT_GEN4_2D
);
3677 return (devinfo
->gen
>= 9 ?
3678 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3681 unreachable("Invalid texture target");
3685 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3687 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3688 return ISL_TILING_W
;
3690 switch (mt
->tiling
) {
3691 case I915_TILING_NONE
:
3692 return ISL_TILING_LINEAR
;
3694 return ISL_TILING_X
;
3696 return ISL_TILING_Y0
;
3698 unreachable("Invalid tiling mode");
3704 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3705 const struct intel_mipmap_tree
*mt
,
3706 struct isl_surf
*surf
)
3708 surf
->dim
= get_isl_surf_dim(mt
->target
);
3709 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3710 mt
->tiling
, mt
->target
,
3713 if (mt
->num_samples
> 1) {
3714 switch (mt
->msaa_layout
) {
3715 case INTEL_MSAA_LAYOUT_IMS
:
3716 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3718 case INTEL_MSAA_LAYOUT_UMS
:
3719 case INTEL_MSAA_LAYOUT_CMS
:
3720 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3723 unreachable("Invalid MSAA layout");
3726 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3729 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3731 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3732 /* The ISL definition of row_pitch matches the surface state pitch field
3733 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3734 * the factor of 2 for W-tiling in row_pitch.
3736 surf
->row_pitch
= 2 * mt
->pitch
;
3738 surf
->row_pitch
= mt
->pitch
;
3741 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3743 if (brw
->gen
>= 9) {
3744 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3745 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3746 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3748 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3749 * alignment in terms of surface elements like we want.
3751 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3754 /* On earlier gens it's stored in pixels. */
3756 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3757 surf
->image_alignment_el
=
3758 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3761 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3762 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3763 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3764 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3765 surf
->logical_level0_px
.array_len
= 1;
3767 surf
->logical_level0_px
.depth
= 1;
3768 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3771 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3772 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3773 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3774 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3775 surf
->phys_level0_sa
.array_len
= 1;
3777 surf
->phys_level0_sa
.depth
= 1;
3778 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3781 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3782 surf
->samples
= MAX2(mt
->num_samples
, 1);
3784 surf
->size
= 0; /* TODO */
3785 surf
->alignment
= 0; /* TODO */
3787 switch (surf
->dim_layout
) {
3788 case ISL_DIM_LAYOUT_GEN4_2D
:
3789 case ISL_DIM_LAYOUT_GEN4_3D
:
3790 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
3791 if (brw
->gen
>= 9) {
3792 surf
->array_pitch_el_rows
= mt
->qpitch
;
3795 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3796 assert(mt
->qpitch
% bh
== 0);
3797 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3800 case ISL_DIM_LAYOUT_GEN9_1D
:
3801 surf
->array_pitch_el_rows
= 1;
3805 switch (mt
->array_layout
) {
3806 case ALL_LOD_IN_EACH_SLICE
:
3807 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3809 case ALL_SLICES_AT_EACH_LOD
:
3810 case GEN6_HIZ_STENCIL
:
3811 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3814 unreachable("Invalid array layout");
3817 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3818 switch (base_format
) {
3819 case GL_DEPTH_COMPONENT
:
3820 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3822 case GL_STENCIL_INDEX
:
3823 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3825 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3827 case GL_DEPTH_STENCIL
:
3828 /* In this case we only texture from the depth part */
3829 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3830 ISL_SURF_USAGE_TEXTURE_BIT
;
3833 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3834 if (brw
->mesa_format_supports_render
[mt
->format
])
3835 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3839 if (_mesa_is_cube_map_texture(mt
->target
))
3840 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3844 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3845 const struct intel_mipmap_tree
*mt
)
3848 return ISL_AUX_USAGE_HIZ
;
3851 return ISL_AUX_USAGE_NONE
;
3853 return mt
->aux_usage
;