2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
28 #include <drm_fourcc.h>
30 #include "intel_batchbuffer.h"
31 #include "intel_image.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_tex.h"
34 #include "intel_blit.h"
35 #include "intel_fbo.h"
37 #include "brw_blorp.h"
38 #include "brw_context.h"
39 #include "brw_meta_util.h"
40 #include "brw_state.h"
42 #include "main/enums.h"
43 #include "main/fbobject.h"
44 #include "main/formats.h"
45 #include "main/glformats.h"
46 #include "main/texcompress_etc.h"
47 #include "main/teximage.h"
48 #include "main/streaming-load-memcpy.h"
50 #include "util/format_srgb.h"
52 #include "x86/common_x86_asm.h"
54 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
56 static void *intel_miptree_map_raw(struct brw_context
*brw
,
57 struct intel_mipmap_tree
*mt
,
60 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
63 intel_miptree_alloc_aux(struct brw_context
*brw
,
64 struct intel_mipmap_tree
*mt
);
67 intel_miptree_supports_mcs(struct brw_context
*brw
,
68 const struct intel_mipmap_tree
*mt
)
70 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
72 /* MCS compression only applies to multisampled miptrees */
73 if (mt
->surf
.samples
<= 1)
76 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
80 /* See isl_surf_get_mcs_surf for details. */
81 if (mt
->surf
.samples
== 16 && mt
->surf
.logical_level0_px
.width
> 8192)
84 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
85 switch (_mesa_get_format_base_format(mt
->format
)) {
86 case GL_DEPTH_COMPONENT
:
87 case GL_STENCIL_INDEX
:
88 case GL_DEPTH_STENCIL
:
91 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
93 * This field must be set to 0 for all SINT MSRTs when all RT channels
96 * In practice this means that we have to disable MCS for all signed
97 * integer MSAA buffers. The alternative, to disable MCS only when one
98 * of the render target channels is disabled, is impractical because it
99 * would require converting between CMS and UMS MSAA layouts on the fly,
100 * which is expensive.
102 if (devinfo
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
111 intel_tiling_supports_ccs(const struct brw_context
*brw
,
112 enum isl_tiling tiling
)
114 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
116 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
117 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
119 * - Support is limited to tiled render targets.
121 * Gen9 changes the restriction to Y-tile only.
123 if (devinfo
->gen
>= 9)
124 return tiling
== ISL_TILING_Y0
;
125 else if (devinfo
->gen
>= 7)
126 return tiling
!= ISL_TILING_LINEAR
;
132 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
133 * can be used. This doesn't (and should not) inspect any of the properties of
136 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
137 * beneath the "Fast Color Clear" bullet (p326):
139 * - Support is for non-mip-mapped and non-array surface types only.
141 * And then later, on p327:
143 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
146 * From the Skylake documentation, it is made clear that X-tiling is no longer
149 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
153 intel_miptree_supports_ccs(struct brw_context
*brw
,
154 const struct intel_mipmap_tree
*mt
)
156 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
158 /* MCS support does not exist prior to Gen7 */
159 if (devinfo
->gen
< 7)
162 /* This function applies only to non-multisampled render targets. */
163 if (mt
->surf
.samples
> 1)
166 /* MCS is only supported for color buffers */
167 switch (_mesa_get_format_base_format(mt
->format
)) {
168 case GL_DEPTH_COMPONENT
:
169 case GL_DEPTH_STENCIL
:
170 case GL_STENCIL_INDEX
:
174 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
177 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
178 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
179 mt
->surf
.logical_level0_px
.depth
> 1;
182 /* Multisample surfaces with the CMS layout are not layered surfaces,
183 * yet still have physical_depth0 > 1. Assert that we don't
184 * accidentally reject a multisampled surface here. We should have
185 * rejected it earlier by explicitly checking the sample count.
187 assert(mt
->surf
.samples
== 1);
190 /* Handle the hardware restrictions...
192 * All GENs have the following restriction: "MCS buffer for non-MSRT is
193 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
195 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
196 * Non-MultiSampler Render Target Restrictions) Support is for
197 * non-mip-mapped and non-array surface types only.
199 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
200 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
201 * surfaces are supported with MCS buffer layout with these alignments in
202 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
204 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
205 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
206 * surfaces are supported with MCS buffer layout with these alignments in
207 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
209 if (devinfo
->gen
< 8 && (mip_mapped
|| arrayed
))
212 /* There's no point in using an MCS buffer if the surface isn't in a
215 if (!brw
->mesa_format_supports_render
[mt
->format
])
222 intel_tiling_supports_hiz(const struct brw_context
*brw
,
223 enum isl_tiling tiling
)
225 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
227 if (devinfo
->gen
< 6)
230 return tiling
== ISL_TILING_Y0
;
234 intel_miptree_supports_hiz(const struct brw_context
*brw
,
235 const struct intel_mipmap_tree
*mt
)
240 switch (mt
->format
) {
241 case MESA_FORMAT_Z_FLOAT32
:
242 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
243 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
244 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
245 case MESA_FORMAT_Z_UNORM16
:
253 * Return true if the format that will be used to access the miptree is
254 * CCS_E-compatible with the miptree's linear/non-sRGB format.
256 * Why use the linear format? Well, although the miptree may be specified with
257 * an sRGB format, the usage of that color space/format can be toggled. Since
258 * our HW tends to support more linear formats than sRGB ones, we use this
259 * format variant for check for CCS_E compatibility.
262 format_ccs_e_compat_with_miptree(const struct gen_device_info
*devinfo
,
263 const struct intel_mipmap_tree
*mt
,
264 enum isl_format access_format
)
266 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
268 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
269 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
270 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
274 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
275 const struct intel_mipmap_tree
*mt
)
277 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
279 if (devinfo
->gen
< 9)
282 /* For now compression is only enabled for integer formats even though
283 * there exist supported floating point formats also. This is a heuristic
284 * decision based on current public benchmarks. In none of the cases these
285 * formats provided any improvement but a few cases were seen to regress.
286 * Hence these are left to to be enabled in the future when they are known
289 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
292 if (!intel_miptree_supports_ccs(brw
, mt
))
295 /* Many window system buffers are sRGB even if they are never rendered as
296 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
297 * surface is used as sRGB, we fall back to CCS_D.
299 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
300 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
301 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
305 * Determine depth format corresponding to a depth+stencil format,
306 * for separate stencil.
309 intel_depth_format_for_depthstencil_format(mesa_format format
) {
311 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
312 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
313 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
314 return MESA_FORMAT_Z_FLOAT32
;
321 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
322 unsigned depth0
, struct intel_mipmap_level
*table
)
324 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
326 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
328 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
329 if (!table
[level
].slice
)
336 for (unsigned level
= first_level
; level
<= last_level
; level
++)
337 free(table
[level
].slice
);
343 needs_separate_stencil(const struct brw_context
*brw
,
344 struct intel_mipmap_tree
*mt
,
347 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
349 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
352 if (devinfo
->must_use_separate_stencil
)
355 return brw
->has_separate_stencil
&&
356 intel_miptree_supports_hiz(brw
, mt
);
360 * Choose the aux usage for this miptree. This function must be called fairly
361 * late in the miptree create process after we have a tiling.
364 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
365 struct intel_mipmap_tree
*mt
)
367 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
369 if (intel_miptree_supports_mcs(brw
, mt
)) {
370 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
371 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
372 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
373 intel_miptree_supports_ccs(brw
, mt
)) {
374 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
375 intel_miptree_supports_ccs_e(brw
, mt
)) {
376 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
378 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
380 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
381 intel_miptree_supports_hiz(brw
, mt
)) {
382 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
385 /* We can do fast-clear on all auxiliary surface types that are
386 * allocated through the normal texture creation paths.
388 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
389 mt
->supports_fast_clear
= true;
394 * Choose an appropriate uncompressed format for a requested
395 * compressed format, if unsupported.
398 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
400 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
402 /* No need to lower ETC formats on these platforms,
403 * they are supported natively.
405 if (devinfo
->gen
>= 8 || devinfo
->is_baytrail
)
409 case MESA_FORMAT_ETC1_RGB8
:
410 return MESA_FORMAT_R8G8B8X8_UNORM
;
411 case MESA_FORMAT_ETC2_RGB8
:
412 return MESA_FORMAT_R8G8B8X8_UNORM
;
413 case MESA_FORMAT_ETC2_SRGB8
:
414 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
415 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
416 return MESA_FORMAT_B8G8R8A8_SRGB
;
417 case MESA_FORMAT_ETC2_RGBA8_EAC
:
418 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
419 return MESA_FORMAT_R8G8B8A8_UNORM
;
420 case MESA_FORMAT_ETC2_R11_EAC
:
421 return MESA_FORMAT_R_UNORM16
;
422 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
423 return MESA_FORMAT_R_SNORM16
;
424 case MESA_FORMAT_ETC2_RG11_EAC
:
425 return MESA_FORMAT_R16G16_UNORM
;
426 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
427 return MESA_FORMAT_R16G16_SNORM
;
429 /* Non ETC1 / ETC2 format */
435 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
437 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
438 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
440 return mt
->surf
.logical_level0_px
.array_len
;
443 UNUSED
static unsigned
444 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
446 /* In case of physical dimensions one needs to consider also the layout.
447 * See isl_calc_phys_level0_extent_sa().
449 if (surf
->dim
!= ISL_SURF_DIM_3D
)
450 return surf
->phys_level0_sa
.array_len
;
452 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
453 return minify(surf
->phys_level0_sa
.array_len
, level
);
455 return minify(surf
->phys_level0_sa
.depth
, level
);
458 /** \brief Assert that the level and layer are valid for the miptree. */
460 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
468 assert(level
>= mt
->first_level
);
469 assert(level
<= mt
->last_level
);
470 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
473 static enum isl_aux_state
**
474 create_aux_state_map(struct intel_mipmap_tree
*mt
,
475 enum isl_aux_state initial
)
477 const uint32_t levels
= mt
->last_level
+ 1;
479 uint32_t total_slices
= 0;
480 for (uint32_t level
= 0; level
< levels
; level
++)
481 total_slices
+= brw_get_num_logical_layers(mt
, level
);
483 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
485 /* We're going to allocate a single chunk of data for both the per-level
486 * reference array and the arrays of aux_state. This makes cleanup
487 * significantly easier.
489 const size_t total_size
= per_level_array_size
+
490 total_slices
* sizeof(enum isl_aux_state
);
491 void *data
= malloc(total_size
);
495 enum isl_aux_state
**per_level_arr
= data
;
496 enum isl_aux_state
*s
= data
+ per_level_array_size
;
497 for (uint32_t level
= 0; level
< levels
; level
++) {
498 per_level_arr
[level
] = s
;
499 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
500 for (uint32_t a
= 0; a
< level_layers
; a
++)
503 assert((void *)s
== data
+ total_size
);
505 return per_level_arr
;
509 free_aux_state_map(enum isl_aux_state
**state
)
515 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
516 enum isl_tiling tiling
, unsigned samples
)
521 if (tiling
== ISL_TILING_LINEAR
)
524 /* If the width is much smaller than a tile, don't bother tiling. */
528 if (ALIGN(row_pitch
, 512) >= 32768) {
529 perf_debug("row pitch %u too large to blit, falling back to untiled",
538 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
539 enum isl_tiling tiling
)
541 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
543 /* If the BO is too large to fit in the aperture, we need to use the
544 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
545 * handle Y-tiling, so we need to fall back to X.
547 if (devinfo
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
548 tiling
== ISL_TILING_Y0
)
554 static struct intel_mipmap_tree
*
555 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
556 unsigned first_level
, unsigned last_level
,
557 unsigned width0
, unsigned height0
, unsigned depth0
,
558 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
559 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
560 unsigned row_pitch
, struct brw_bo
*bo
)
562 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
566 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
574 if (target
== GL_TEXTURE_CUBE_MAP
||
575 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
576 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
578 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
580 _mesa_enum_to_string(target
),
581 _mesa_get_format_name(format
),
582 num_samples
, width0
, height0
, depth0
,
583 first_level
, last_level
, mt
);
585 struct isl_surf_init_info init_info
= {
586 .dim
= get_isl_surf_dim(target
),
587 .format
= translate_tex_format(brw
, format
, false),
590 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
591 .levels
= last_level
- first_level
+ 1,
592 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
593 .samples
= num_samples
,
594 .row_pitch
= row_pitch
,
595 .usage
= isl_usage_flags
,
596 .tiling_flags
= tiling_flags
,
599 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
602 /* Depth surfaces are always Y-tiled and stencil is always W-tiled, although
603 * on gen7 platforms we also need to create Y-tiled copies of stencil for
604 * texturing since the hardware can't sample from W-tiled surfaces. For
605 * everything else, check for corner cases needing special treatment.
607 bool is_depth_stencil
=
608 mt
->surf
.usage
& (ISL_SURF_USAGE_STENCIL_BIT
| ISL_SURF_USAGE_DEPTH_BIT
);
609 if (!is_depth_stencil
) {
610 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
611 mt
->surf
.tiling
, mt
->surf
.samples
)) {
612 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
613 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
615 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
616 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
617 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
622 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
623 * the size may not be multiple of row_pitch.
624 * See isl_apply_surface_padding().
626 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
627 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
630 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
632 isl_tiling_to_i915_tiling(
634 mt
->surf
.row_pitch
, alloc_flags
);
641 mt
->first_level
= first_level
;
642 mt
->last_level
= last_level
;
645 mt
->aux_state
= NULL
;
646 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
647 mt
->compressed
= _mesa_is_format_compressed(format
);
648 mt
->drm_modifier
= DRM_FORMAT_MOD_INVALID
;
653 intel_miptree_release(&mt
);
658 make_separate_stencil_surface(struct brw_context
*brw
,
659 struct intel_mipmap_tree
*mt
)
661 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
662 0, mt
->surf
.levels
- 1,
663 mt
->surf
.logical_level0_px
.width
,
664 mt
->surf
.logical_level0_px
.height
,
665 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
666 mt
->surf
.logical_level0_px
.depth
:
667 mt
->surf
.logical_level0_px
.array_len
,
668 mt
->surf
.samples
, ISL_TILING_W_BIT
,
669 ISL_SURF_USAGE_STENCIL_BIT
|
670 ISL_SURF_USAGE_TEXTURE_BIT
,
671 BO_ALLOC_BUSY
, 0, NULL
);
676 mt
->stencil_mt
->r8stencil_needs_update
= true;
681 static struct intel_mipmap_tree
*
682 miptree_create(struct brw_context
*brw
,
691 enum intel_miptree_create_flags flags
)
693 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
695 if (format
== MESA_FORMAT_S_UINT8
)
696 return make_surface(brw
, target
, format
, first_level
, last_level
,
697 width0
, height0
, depth0
, num_samples
,
699 ISL_SURF_USAGE_STENCIL_BIT
|
700 ISL_SURF_USAGE_TEXTURE_BIT
,
705 const GLenum base_format
= _mesa_get_format_base_format(format
);
706 if ((base_format
== GL_DEPTH_COMPONENT
||
707 base_format
== GL_DEPTH_STENCIL
) &&
708 !(flags
& MIPTREE_CREATE_LINEAR
)) {
709 /* Fix up the Z miptree format for how we're splitting out separate
710 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
712 const mesa_format depth_only_format
=
713 intel_depth_format_for_depthstencil_format(format
);
714 struct intel_mipmap_tree
*mt
= make_surface(
715 brw
, target
, devinfo
->gen
>= 6 ? depth_only_format
: format
,
716 first_level
, last_level
,
717 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
718 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
719 BO_ALLOC_BUSY
, 0, NULL
);
721 if (needs_separate_stencil(brw
, mt
, format
) &&
722 !make_separate_stencil_surface(brw
, mt
)) {
723 intel_miptree_release(&mt
);
727 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
728 intel_miptree_choose_aux_usage(brw
, mt
);
733 mesa_format tex_format
= format
;
734 mesa_format etc_format
= MESA_FORMAT_NONE
;
735 uint32_t alloc_flags
= 0;
737 format
= intel_lower_compressed_format(brw
, format
);
739 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
741 if (flags
& MIPTREE_CREATE_BUSY
)
742 alloc_flags
|= BO_ALLOC_BUSY
;
744 isl_tiling_flags_t tiling_flags
= (flags
& MIPTREE_CREATE_LINEAR
) ?
745 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
747 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
748 if (devinfo
->gen
< 6)
749 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
751 struct intel_mipmap_tree
*mt
= make_surface(
753 first_level
, last_level
,
754 width0
, height0
, depth0
,
755 num_samples
, tiling_flags
,
756 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
757 ISL_SURF_USAGE_TEXTURE_BIT
,
758 alloc_flags
, 0, NULL
);
762 mt
->etc_format
= etc_format
;
764 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
765 intel_miptree_choose_aux_usage(brw
, mt
);
770 struct intel_mipmap_tree
*
771 intel_miptree_create(struct brw_context
*brw
,
780 enum intel_miptree_create_flags flags
)
782 assert(num_samples
> 0);
784 struct intel_mipmap_tree
*mt
= miptree_create(
786 first_level
, last_level
,
787 width0
, height0
, depth0
, num_samples
,
794 if (!intel_miptree_alloc_aux(brw
, mt
)) {
795 intel_miptree_release(&mt
);
802 struct intel_mipmap_tree
*
803 intel_miptree_create_for_bo(struct brw_context
*brw
,
811 enum isl_tiling tiling
,
812 enum intel_miptree_create_flags flags
)
814 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
815 struct intel_mipmap_tree
*mt
;
816 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
817 const GLenum base_format
= _mesa_get_format_base_format(format
);
819 if ((base_format
== GL_DEPTH_COMPONENT
||
820 base_format
== GL_DEPTH_STENCIL
)) {
821 const mesa_format depth_only_format
=
822 intel_depth_format_for_depthstencil_format(format
);
823 mt
= make_surface(brw
, target
,
824 devinfo
->gen
>= 6 ? depth_only_format
: format
,
825 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
826 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
831 brw_bo_reference(bo
);
833 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
834 intel_miptree_choose_aux_usage(brw
, mt
);
837 } else if (format
== MESA_FORMAT_S_UINT8
) {
838 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
839 0, 0, width
, height
, depth
, 1,
841 ISL_SURF_USAGE_STENCIL_BIT
|
842 ISL_SURF_USAGE_TEXTURE_BIT
,
847 assert(bo
->size
>= mt
->surf
.size
);
849 brw_bo_reference(bo
);
853 /* Nothing will be able to use this miptree with the BO if the offset isn't
856 if (tiling
!= ISL_TILING_LINEAR
)
857 assert(offset
% 4096 == 0);
859 /* miptrees can't handle negative pitch. If you need flipping of images,
860 * that's outside of the scope of the mt.
864 /* The BO already has a tiling format and we shouldn't confuse the lower
865 * layers by making it try to find a tiling format again.
867 assert((flags
& MIPTREE_CREATE_LINEAR
) == 0);
869 mt
= make_surface(brw
, target
, format
,
870 0, 0, width
, height
, depth
, 1,
872 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
873 ISL_SURF_USAGE_TEXTURE_BIT
,
878 brw_bo_reference(bo
);
882 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
883 intel_miptree_choose_aux_usage(brw
, mt
);
885 if (!intel_miptree_alloc_aux(brw
, mt
)) {
886 intel_miptree_release(&mt
);
894 static struct intel_mipmap_tree
*
895 miptree_create_for_planar_image(struct brw_context
*brw
,
896 __DRIimage
*image
, GLenum target
,
897 enum isl_tiling tiling
)
899 const struct intel_image_format
*f
= image
->planar_format
;
900 struct intel_mipmap_tree
*planar_mt
= NULL
;
902 for (int i
= 0; i
< f
->nplanes
; i
++) {
903 const int index
= f
->planes
[i
].buffer_index
;
904 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
905 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
906 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
907 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
909 /* Disable creation of the texture's aux buffers because the driver
910 * exposes no EGL API to manage them. That is, there is no API for
911 * resolving the aux buffer's content to the main buffer nor for
912 * invalidating the aux buffer's content.
914 struct intel_mipmap_tree
*mt
=
915 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
916 image
->offsets
[index
],
918 image
->strides
[index
],
920 MIPTREE_CREATE_NO_AUX
);
929 planar_mt
->plane
[i
- 1] = mt
;
932 planar_mt
->drm_modifier
= image
->modifier
;
938 create_ccs_buf_for_image(struct brw_context
*brw
,
940 struct intel_mipmap_tree
*mt
,
941 enum isl_aux_state initial_state
)
943 struct isl_surf temp_ccs_surf
;
945 /* CCS is only supported for very simple miptrees */
946 assert(image
->aux_offset
!= 0 && image
->aux_pitch
!= 0);
947 assert(image
->tile_x
== 0 && image
->tile_y
== 0);
948 assert(mt
->surf
.samples
== 1);
949 assert(mt
->surf
.levels
== 1);
950 assert(mt
->surf
.logical_level0_px
.depth
== 1);
951 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
952 assert(mt
->first_level
== 0);
953 assert(mt
->last_level
== 0);
955 /* We shouldn't already have a CCS */
956 assert(!mt
->aux_buf
);
958 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
,
962 assert(image
->aux_offset
< image
->bo
->size
);
963 assert(temp_ccs_surf
.size
<= image
->bo
->size
- image
->aux_offset
);
965 mt
->aux_buf
= calloc(sizeof(*mt
->aux_buf
), 1);
966 if (mt
->aux_buf
== NULL
)
969 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
970 if (!mt
->aux_state
) {
976 /* On gen10+ we start using an extra space in the aux buffer to store the
977 * indirect clear color. However, if we imported an image from the window
978 * system with CCS, we don't have the extra space at the end of the aux
979 * buffer. So create a new bo here that will store that clear color.
981 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
982 if (devinfo
->gen
>= 10) {
983 mt
->aux_buf
->clear_color_bo
=
984 brw_bo_alloc(brw
->bufmgr
, "clear_color_bo",
985 brw
->isl_dev
.ss
.clear_color_state_size
);
986 if (!mt
->aux_buf
->clear_color_bo
) {
993 mt
->aux_buf
->bo
= image
->bo
;
994 brw_bo_reference(image
->bo
);
996 mt
->aux_buf
->offset
= image
->aux_offset
;
997 mt
->aux_buf
->surf
= temp_ccs_surf
;
1002 struct intel_mipmap_tree
*
1003 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
1004 __DRIimage
*image
, GLenum target
,
1006 bool is_winsys_image
)
1008 uint32_t bo_tiling
, bo_swizzle
;
1009 brw_bo_get_tiling(image
->bo
, &bo_tiling
, &bo_swizzle
);
1011 const struct isl_drm_modifier_info
*mod_info
=
1012 isl_drm_modifier_get_info(image
->modifier
);
1014 const enum isl_tiling tiling
=
1015 mod_info
? mod_info
->tiling
: isl_tiling_from_i915_tiling(bo_tiling
);
1017 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1)
1018 return miptree_create_for_planar_image(brw
, image
, target
, tiling
);
1020 if (image
->planar_format
)
1021 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
1023 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1024 /* The texture storage paths in core Mesa detect if the driver does not
1025 * support the user-requested format, and then searches for a
1026 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1027 * do the fallbacks here for important formats.
1029 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1030 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1031 * the Chrome OS compositor consumes as dma_buf EGLImages.
1033 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1036 if (!brw
->ctx
.TextureFormatSupported
[format
])
1039 enum intel_miptree_create_flags mt_create_flags
= 0;
1041 /* If this image comes in from a window system, we have different
1042 * requirements than if it comes in via an EGL import operation. Window
1043 * system images can use any form of auxiliary compression we wish because
1044 * they get "flushed" before being handed off to the window system and we
1045 * have the opportunity to do resolves. Non window-system images, on the
1046 * other hand, have no resolve point so we can't have aux without a
1049 if (!is_winsys_image
)
1050 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1052 /* If we have a modifier which specifies aux, don't create one yet */
1053 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
1054 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1056 /* Disable creation of the texture's aux buffers because the driver exposes
1057 * no EGL API to manage them. That is, there is no API for resolving the aux
1058 * buffer's content to the main buffer nor for invalidating the aux buffer's
1061 struct intel_mipmap_tree
*mt
=
1062 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1063 image
->offset
, image
->width
, image
->height
, 1,
1064 image
->pitch
, tiling
, mt_create_flags
);
1068 mt
->target
= target
;
1069 mt
->level
[0].level_x
= image
->tile_x
;
1070 mt
->level
[0].level_y
= image
->tile_y
;
1071 mt
->drm_modifier
= image
->modifier
;
1073 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1074 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1075 * trouble resolving back to destination image due to alignment issues.
1077 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1078 if (!devinfo
->has_surface_tile_offset
) {
1079 uint32_t draw_x
, draw_y
;
1080 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1082 if (draw_x
!= 0 || draw_y
!= 0) {
1083 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1084 intel_miptree_release(&mt
);
1089 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1090 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1092 mt
->aux_usage
= mod_info
->aux_usage
;
1093 /* If we are a window system buffer, then we can support fast-clears
1094 * even if the modifier doesn't support them by doing a partial resolve
1095 * as part of the flush operation.
1097 mt
->supports_fast_clear
=
1098 is_winsys_image
|| mod_info
->supports_clear_color
;
1100 /* We don't know the actual state of the surface when we get it but we
1101 * can make a pretty good guess based on the modifier. What we do know
1102 * for sure is that it isn't in the AUX_INVALID state, so we just assume
1103 * a worst case of compression.
1105 enum isl_aux_state initial_state
=
1106 isl_drm_modifier_get_default_aux_state(image
->modifier
);
1108 if (!create_ccs_buf_for_image(brw
, image
, mt
, initial_state
)) {
1109 intel_miptree_release(&mt
);
1114 /* Don't assume coherency for imported EGLimages. We don't know what
1115 * external clients are going to do with it. They may scan it out.
1117 image
->bo
->cache_coherent
= false;
1123 * For a singlesample renderbuffer, this simply wraps the given BO with a
1126 * For a multisample renderbuffer, this wraps the window system's
1127 * (singlesample) BO with a singlesample miptree attached to the
1128 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1129 * that will contain the actual rendering (which is lazily resolved to
1130 * irb->singlesample_mt).
1133 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1134 struct intel_renderbuffer
*irb
,
1135 struct intel_mipmap_tree
*singlesample_mt
,
1136 uint32_t width
, uint32_t height
,
1139 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1140 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1141 mesa_format format
= rb
->Format
;
1142 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1144 /* Only the front and back buffers, which are color buffers, are allocated
1145 * through the image loader.
1147 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1148 _mesa_get_format_base_format(format
) == GL_RGBA
);
1150 assert(singlesample_mt
);
1152 if (num_samples
== 1) {
1153 intel_miptree_release(&irb
->mt
);
1154 irb
->mt
= singlesample_mt
;
1156 assert(!irb
->singlesample_mt
);
1158 intel_miptree_release(&irb
->singlesample_mt
);
1159 irb
->singlesample_mt
= singlesample_mt
;
1162 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1163 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1164 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1169 if (!multisample_mt
)
1172 irb
->need_downsample
= false;
1173 intel_miptree_release(&irb
->mt
);
1174 irb
->mt
= multisample_mt
;
1180 intel_miptree_release(&irb
->mt
);
1184 struct intel_mipmap_tree
*
1185 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1189 uint32_t num_samples
)
1191 struct intel_mipmap_tree
*mt
;
1193 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1195 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1196 width
, height
, depth
, num_samples
,
1197 MIPTREE_CREATE_BUSY
);
1204 intel_miptree_release(&mt
);
1209 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1210 struct intel_mipmap_tree
*src
)
1215 intel_miptree_release(dst
);
1219 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1226 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1228 if (aux_buf
== NULL
)
1231 brw_bo_unreference(aux_buf
->bo
);
1232 brw_bo_unreference(aux_buf
->clear_color_bo
);
1238 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1243 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1244 if (--(*mt
)->refcount
<= 0) {
1247 DBG("%s deleting %p\n", __func__
, *mt
);
1249 brw_bo_unreference((*mt
)->bo
);
1250 intel_miptree_release(&(*mt
)->stencil_mt
);
1251 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1252 intel_miptree_aux_buffer_free((*mt
)->aux_buf
);
1253 free_aux_state_map((*mt
)->aux_state
);
1255 intel_miptree_release(&(*mt
)->plane
[0]);
1256 intel_miptree_release(&(*mt
)->plane
[1]);
1258 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1259 free((*mt
)->level
[i
].slice
);
1269 intel_get_image_dims(struct gl_texture_image
*image
,
1270 int *width
, int *height
, int *depth
)
1272 switch (image
->TexObject
->Target
) {
1273 case GL_TEXTURE_1D_ARRAY
:
1274 /* For a 1D Array texture the OpenGL API will treat the image height as
1275 * the number of array slices. For Intel hardware, we treat the 1D array
1276 * as a 2D Array with a height of 1. So, here we want to swap image
1279 assert(image
->Depth
== 1);
1280 *width
= image
->Width
;
1282 *depth
= image
->Height
;
1284 case GL_TEXTURE_CUBE_MAP
:
1285 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1286 * though we really have 6 slices.
1288 assert(image
->Depth
== 1);
1289 *width
= image
->Width
;
1290 *height
= image
->Height
;
1294 *width
= image
->Width
;
1295 *height
= image
->Height
;
1296 *depth
= image
->Depth
;
1302 * Can the image be pulled into a unified mipmap tree? This mirrors
1303 * the completeness test in a lot of ways.
1305 * Not sure whether I want to pass gl_texture_image here.
1308 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1309 struct gl_texture_image
*image
)
1311 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1312 GLuint level
= intelImage
->base
.Base
.Level
;
1313 int width
, height
, depth
;
1315 /* glTexImage* choose the texture object based on the target passed in, and
1316 * objects can't change targets over their lifetimes, so this should be
1319 assert(image
->TexObject
->Target
== mt
->target
);
1321 mesa_format mt_format
= mt
->format
;
1322 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1323 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1324 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1325 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1326 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1327 mt_format
= mt
->etc_format
;
1329 if (_mesa_get_srgb_format_linear(image
->TexFormat
) !=
1330 _mesa_get_srgb_format_linear(mt_format
))
1333 intel_get_image_dims(image
, &width
, &height
, &depth
);
1335 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1338 if (level
>= mt
->surf
.levels
)
1341 const unsigned level_depth
=
1342 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1343 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1344 mt
->surf
.logical_level0_px
.array_len
;
1346 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1347 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1348 depth
== level_depth
&&
1349 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1353 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1354 GLuint level
, GLuint slice
,
1355 GLuint
*x
, GLuint
*y
)
1357 if (level
== 0 && slice
== 0) {
1358 *x
= mt
->level
[0].level_x
;
1359 *y
= mt
->level
[0].level_y
;
1363 uint32_t x_offset_sa
, y_offset_sa
;
1365 /* Miptree itself can have an offset only if it represents a single
1366 * slice in an imported buffer object.
1367 * See intel_miptree_create_for_dri_image().
1369 assert(mt
->level
[0].level_x
== 0);
1370 assert(mt
->level
[0].level_y
== 0);
1372 /* Given level is relative to level zero while the miptree may be
1373 * represent just a subset of all levels starting from 'first_level'.
1375 assert(level
>= mt
->first_level
);
1376 level
-= mt
->first_level
;
1378 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1379 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1380 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1381 &x_offset_sa
, &y_offset_sa
);
1389 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1390 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1391 * and tile_h is set to 1.
1394 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1395 uint32_t *tile_w
, uint32_t *tile_h
)
1406 case ISL_TILING_LINEAR
:
1411 unreachable("not reached");
1417 * This function computes masks that may be used to select the bits of the X
1418 * and Y coordinates that indicate the offset within a tile. If the BO is
1419 * untiled, the masks are set to 0.
1422 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1423 uint32_t *mask_x
, uint32_t *mask_y
)
1425 uint32_t tile_w_bytes
, tile_h
;
1427 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1429 *mask_x
= tile_w_bytes
/ cpp
- 1;
1430 *mask_y
= tile_h
- 1;
1434 * Compute the offset (in bytes) from the start of the BO to the given x
1435 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1436 * multiples of the tile size.
1439 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1440 uint32_t x
, uint32_t y
)
1443 uint32_t pitch
= mt
->surf
.row_pitch
;
1445 switch (mt
->surf
.tiling
) {
1447 unreachable("not reached");
1448 case ISL_TILING_LINEAR
:
1449 return y
* pitch
+ x
* cpp
;
1451 assert((x
% (512 / cpp
)) == 0);
1452 assert((y
% 8) == 0);
1453 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1455 assert((x
% (128 / cpp
)) == 0);
1456 assert((y
% 32) == 0);
1457 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1462 * Rendering with tiled buffers requires that the base address of the buffer
1463 * be aligned to a page boundary. For renderbuffers, and sometimes with
1464 * textures, we may want the surface to point at a texture image level that
1465 * isn't at a page boundary.
1467 * This function returns an appropriately-aligned base offset
1468 * according to the tiling restrictions, plus any required x/y offset
1472 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1473 GLuint level
, GLuint slice
,
1478 uint32_t mask_x
, mask_y
;
1480 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1481 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1483 *tile_x
= x
& mask_x
;
1484 *tile_y
= y
& mask_y
;
1486 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1490 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1491 struct intel_mipmap_tree
*src_mt
,
1492 unsigned src_level
, unsigned src_layer
,
1493 struct intel_mipmap_tree
*dst_mt
,
1494 unsigned dst_level
, unsigned dst_layer
,
1495 unsigned width
, unsigned height
)
1498 ptrdiff_t src_stride
, dst_stride
;
1499 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1501 intel_miptree_map(brw
, src_mt
,
1502 src_level
, src_layer
,
1505 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1508 intel_miptree_map(brw
, dst_mt
,
1509 dst_level
, dst_layer
,
1512 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1516 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1517 _mesa_get_format_name(src_mt
->format
),
1518 src_mt
, src
, src_stride
,
1519 _mesa_get_format_name(dst_mt
->format
),
1520 dst_mt
, dst
, dst_stride
,
1523 int row_size
= cpp
* width
;
1524 if (src_stride
== row_size
&&
1525 dst_stride
== row_size
) {
1526 memcpy(dst
, src
, row_size
* height
);
1528 for (int i
= 0; i
< height
; i
++) {
1529 memcpy(dst
, src
, row_size
);
1535 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1536 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1538 /* Don't forget to copy the stencil data over, too. We could have skipped
1539 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1540 * shuffling the two data sources in/out of temporary storage instead of
1541 * the direct mapping we get this way.
1543 if (dst_mt
->stencil_mt
) {
1544 assert(src_mt
->stencil_mt
);
1545 intel_miptree_copy_slice_sw(brw
,
1546 src_mt
->stencil_mt
, src_level
, src_layer
,
1547 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1553 intel_miptree_copy_slice(struct brw_context
*brw
,
1554 struct intel_mipmap_tree
*src_mt
,
1555 unsigned src_level
, unsigned src_layer
,
1556 struct intel_mipmap_tree
*dst_mt
,
1557 unsigned dst_level
, unsigned dst_layer
)
1560 mesa_format format
= src_mt
->format
;
1561 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1562 src_level
- src_mt
->first_level
);
1563 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1564 src_level
- src_mt
->first_level
);
1566 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1567 src_level
- src_mt
->first_level
));
1569 assert(_mesa_get_srgb_format_linear(src_mt
->format
) ==
1570 _mesa_get_srgb_format_linear(dst_mt
->format
));
1572 if (dst_mt
->compressed
) {
1574 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1575 height
= ALIGN_NPOT(height
, j
) / j
;
1576 width
= ALIGN_NPOT(width
, i
) / i
;
1579 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1580 * below won't apply since we can't do the depth's Y tiling or the
1581 * stencil's W tiling in the blitter.
1583 if (src_mt
->stencil_mt
) {
1584 intel_miptree_copy_slice_sw(brw
,
1585 src_mt
, src_level
, src_layer
,
1586 dst_mt
, dst_level
, dst_layer
,
1591 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1592 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1594 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1597 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1598 _mesa_get_format_name(src_mt
->format
),
1599 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1600 _mesa_get_format_name(dst_mt
->format
),
1601 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1604 if (!intel_miptree_blit(brw
,
1605 src_mt
, src_level
, src_layer
, 0, 0, false,
1606 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1607 width
, height
, COLOR_LOGICOP_COPY
)) {
1608 perf_debug("miptree validate blit for %s failed\n",
1609 _mesa_get_format_name(format
));
1611 intel_miptree_copy_slice_sw(brw
,
1612 src_mt
, src_level
, src_layer
,
1613 dst_mt
, dst_level
, dst_layer
,
1619 * Copies the image's current data to the given miptree, and associates that
1620 * miptree with the image.
1623 intel_miptree_copy_teximage(struct brw_context
*brw
,
1624 struct intel_texture_image
*intelImage
,
1625 struct intel_mipmap_tree
*dst_mt
)
1627 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1628 struct intel_texture_object
*intel_obj
=
1629 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1630 int level
= intelImage
->base
.Base
.Level
;
1631 const unsigned face
= intelImage
->base
.Base
.Face
;
1632 unsigned start_layer
, end_layer
;
1634 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1636 assert(intelImage
->base
.Base
.Height
);
1638 end_layer
= intelImage
->base
.Base
.Height
- 1;
1639 } else if (face
> 0) {
1643 assert(intelImage
->base
.Base
.Depth
);
1645 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1648 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1649 intel_miptree_copy_slice(brw
,
1654 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1655 intel_obj
->needs_validate
= true;
1658 static struct intel_miptree_aux_buffer
*
1659 intel_alloc_aux_buffer(struct brw_context
*brw
,
1661 const struct isl_surf
*aux_surf
,
1662 uint32_t alloc_flags
,
1664 uint8_t memset_value
,
1665 struct intel_mipmap_tree
*mt
)
1667 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1671 uint64_t size
= aux_surf
->size
;
1673 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1674 if (devinfo
->gen
>= 10) {
1675 /* On CNL, instead of setting the clear color in the SURFACE_STATE, we
1676 * will set a pointer to a dword somewhere that contains the color. So,
1677 * allocate the space for the clear color value here on the aux buffer.
1679 buf
->clear_color_offset
= size
;
1680 size
+= brw
->isl_dev
.ss
.clear_color_state_size
;
1683 /* ISL has stricter set of alignment rules then the drm allocator.
1684 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1685 * trying to recalculate based on different format block sizes.
1687 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, size
,
1688 I915_TILING_Y
, aux_surf
->row_pitch
,
1695 /* Initialize the bo to the desired value */
1697 assert(!(alloc_flags
& BO_ALLOC_BUSY
));
1699 void *map
= brw_bo_map(brw
, buf
->bo
, MAP_WRITE
| MAP_RAW
);
1701 intel_miptree_aux_buffer_free(buf
);
1704 memset(map
, memset_value
, aux_surf
->size
);
1705 brw_bo_unmap(buf
->bo
);
1708 if (devinfo
->gen
>= 10) {
1709 buf
->clear_color_bo
= buf
->bo
;
1710 brw_bo_reference(buf
->clear_color_bo
);
1713 buf
->surf
= *aux_surf
;
1719 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1720 struct intel_mipmap_tree
*mt
,
1723 assert(brw
->screen
->devinfo
.gen
>= 7); /* MCS only used on Gen7+ */
1724 assert(mt
->aux_buf
== NULL
);
1725 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1727 /* Multisampled miptrees are only supported for single level. */
1728 assert(mt
->first_level
== 0);
1729 enum isl_aux_state
**aux_state
=
1730 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1734 struct isl_surf temp_mcs_surf
;
1736 MAYBE_UNUSED
bool ok
=
1737 isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_mcs_surf
);
1740 /* Buffer needs to be initialised requiring the buffer to be immediately
1741 * mapped to cpu space for writing. Therefore do not use the gpu access
1742 * flag which can cause an unnecessary delay if the backing pages happened
1743 * to be just used by the GPU.
1745 const uint32_t alloc_flags
= 0;
1746 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1748 * When MCS buffer is enabled and bound to MSRT, it is required that it
1749 * is cleared prior to any rendering.
1751 * Since we don't use the MCS buffer for any purpose other than rendering,
1752 * it makes sense to just clear it immediately upon allocation.
1754 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1756 mt
->aux_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree", &temp_mcs_surf
,
1757 alloc_flags
, true, 0xFF, mt
);
1763 mt
->aux_state
= aux_state
;
1769 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1770 struct intel_mipmap_tree
*mt
)
1772 assert(mt
->aux_buf
== NULL
);
1773 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1774 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1776 struct isl_surf temp_ccs_surf
;
1778 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
, 0))
1781 assert(temp_ccs_surf
.size
&&
1782 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1784 enum isl_aux_state
**aux_state
=
1785 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1789 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1790 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1792 * "If Software wants to enable Color Compression without Fast clear,
1793 * Software needs to initialize MCS with zeros."
1795 * A CCS value of 0 indicates that the corresponding block is in the
1796 * pass-through state which is what we want.
1798 * For CCS_D, do the same thing. On gen9+, this avoids having any undefined
1799 * bits in the aux buffer.
1801 mt
->aux_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree", &temp_ccs_surf
,
1802 BO_ALLOC_ZEROED
, false, 0, mt
);
1808 mt
->aux_state
= aux_state
;
1814 * Helper for intel_miptree_alloc_hiz() that sets
1815 * \c mt->level[level].has_hiz. Return true if and only if
1816 * \c has_hiz was set.
1819 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1820 struct intel_mipmap_tree
*mt
,
1823 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1825 assert(mt
->aux_buf
);
1826 assert(mt
->surf
.size
> 0);
1828 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
1829 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1830 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1832 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1833 * and the height is 4 aligned. This allows our HiZ support
1834 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1835 * we can grow the width & height to allow the HiZ op to
1836 * force the proper size alignments.
1838 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1839 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1844 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1845 mt
->level
[level
].has_hiz
= true;
1850 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1851 struct intel_mipmap_tree
*mt
)
1853 assert(mt
->aux_buf
== NULL
);
1854 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1856 enum isl_aux_state
**aux_state
=
1857 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1861 struct isl_surf temp_hiz_surf
;
1863 MAYBE_UNUSED
bool ok
=
1864 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
1867 const uint32_t alloc_flags
= BO_ALLOC_BUSY
;
1868 mt
->aux_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree", &temp_hiz_surf
,
1869 alloc_flags
, false, 0, mt
);
1876 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1877 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1879 mt
->aux_state
= aux_state
;
1886 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1888 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1889 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1890 * compress clear color so we wait until an actual fast-clear to allocate it.
1893 intel_miptree_alloc_aux(struct brw_context
*brw
,
1894 struct intel_mipmap_tree
*mt
)
1896 switch (mt
->aux_usage
) {
1897 case ISL_AUX_USAGE_NONE
:
1900 case ISL_AUX_USAGE_HIZ
:
1901 assert(!_mesa_is_format_color_format(mt
->format
));
1902 if (!intel_miptree_alloc_hiz(brw
, mt
))
1906 case ISL_AUX_USAGE_MCS
:
1907 assert(_mesa_is_format_color_format(mt
->format
));
1908 assert(mt
->surf
.samples
> 1);
1909 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
1913 case ISL_AUX_USAGE_CCS_D
:
1914 /* Since CCS_D can only compress clear color so we wait until an actual
1915 * fast-clear to allocate it.
1919 case ISL_AUX_USAGE_CCS_E
:
1920 assert(_mesa_is_format_color_format(mt
->format
));
1921 assert(mt
->surf
.samples
== 1);
1922 if (!intel_miptree_alloc_ccs(brw
, mt
))
1927 unreachable("Invalid aux usage");
1932 * Can the miptree sample using the hiz buffer?
1935 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1936 struct intel_mipmap_tree
*mt
)
1938 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1940 if (!devinfo
->has_sample_with_hiz
) {
1948 /* It seems the hardware won't fallback to the depth buffer if some of the
1949 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1950 * of the texture to be HiZ enabled.
1952 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1953 if (!intel_miptree_level_has_hiz(mt
, level
))
1957 /* If compressed multisampling is enabled, then we use it for the auxiliary
1960 * From the BDW PRM (Volume 2d: Command Reference: Structures
1961 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1963 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1964 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1966 * There is no such blurb for 1D textures, but there is sufficient evidence
1967 * that this is broken on SKL+.
1969 return (mt
->surf
.samples
== 1 &&
1970 mt
->target
!= GL_TEXTURE_3D
&&
1971 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1975 * Does the miptree slice have hiz enabled?
1978 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1980 intel_miptree_check_level_layer(mt
, level
, 0);
1981 return mt
->level
[level
].has_hiz
;
1984 static inline uint32_t
1985 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1986 uint32_t start_level
, uint32_t num_levels
)
1988 assert(start_level
>= mt
->first_level
);
1989 assert(start_level
<= mt
->last_level
);
1991 if (num_levels
== INTEL_REMAINING_LAYERS
)
1992 num_levels
= mt
->last_level
- start_level
+ 1;
1993 /* Check for overflow */
1994 assert(start_level
+ num_levels
>= start_level
);
1995 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2000 static inline uint32_t
2001 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2002 uint32_t start_layer
, uint32_t num_layers
)
2004 assert(level
<= mt
->last_level
);
2006 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
2007 assert(start_layer
< total_num_layers
);
2008 if (num_layers
== INTEL_REMAINING_LAYERS
)
2009 num_layers
= total_num_layers
- start_layer
;
2010 /* Check for overflow */
2011 assert(start_layer
+ num_layers
>= start_layer
);
2012 assert(start_layer
+ num_layers
<= total_num_layers
);
2018 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2019 unsigned start_level
, unsigned num_levels
,
2020 unsigned start_layer
, unsigned num_layers
)
2022 assert(_mesa_is_format_color_format(mt
->format
));
2027 /* Clamp the level range to fit the miptree */
2028 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2030 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2031 const uint32_t level
= start_level
+ l
;
2032 const uint32_t level_layers
=
2033 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2034 for (unsigned a
= 0; a
< level_layers
; a
++) {
2035 enum isl_aux_state aux_state
=
2036 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2037 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2038 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2047 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2048 const struct intel_mipmap_tree
*mt
,
2049 unsigned level
, unsigned layer
)
2054 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2055 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2056 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2058 /* Compression of arrayed msaa surfaces is supported. */
2059 if (mt
->surf
.samples
> 1)
2062 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2063 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2065 mt
->surf
.logical_level0_px
.depth
== 1 &&
2066 mt
->surf
.logical_level0_px
.array_len
== 1));
2072 static enum isl_aux_op
2073 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2074 enum isl_aux_usage aux_usage
,
2075 bool fast_clear_supported
)
2077 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
2079 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
2081 assert(ccs_supported
== fast_clear_supported
);
2083 switch (aux_state
) {
2084 case ISL_AUX_STATE_CLEAR
:
2085 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2087 return ISL_AUX_OP_FULL_RESOLVE
;
2089 return ISL_AUX_OP_NONE
;
2091 case ISL_AUX_STATE_PASS_THROUGH
:
2092 return ISL_AUX_OP_NONE
;
2094 case ISL_AUX_STATE_RESOLVED
:
2095 case ISL_AUX_STATE_AUX_INVALID
:
2096 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2097 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2101 unreachable("Invalid aux state for CCS_D");
2104 static enum isl_aux_op
2105 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2106 enum isl_aux_usage aux_usage
,
2107 bool fast_clear_supported
)
2109 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
2110 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2111 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2112 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2114 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
2115 assert(fast_clear_supported
);
2117 switch (aux_state
) {
2118 case ISL_AUX_STATE_CLEAR
:
2119 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2120 if (fast_clear_supported
)
2121 return ISL_AUX_OP_NONE
;
2122 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
2123 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2125 return ISL_AUX_OP_FULL_RESOLVE
;
2127 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2128 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2129 return ISL_AUX_OP_FULL_RESOLVE
;
2130 else if (!fast_clear_supported
)
2131 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2133 return ISL_AUX_OP_NONE
;
2135 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2136 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2137 return ISL_AUX_OP_FULL_RESOLVE
;
2139 return ISL_AUX_OP_NONE
;
2141 case ISL_AUX_STATE_PASS_THROUGH
:
2142 return ISL_AUX_OP_NONE
;
2144 case ISL_AUX_STATE_RESOLVED
:
2145 case ISL_AUX_STATE_AUX_INVALID
:
2149 unreachable("Invalid aux state for CCS_E");
2153 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2154 struct intel_mipmap_tree
*mt
,
2155 uint32_t level
, uint32_t layer
,
2156 enum isl_aux_usage aux_usage
,
2157 bool fast_clear_supported
)
2159 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2161 enum isl_aux_op resolve_op
;
2162 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2163 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2164 fast_clear_supported
);
2166 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2167 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2168 fast_clear_supported
);
2171 if (resolve_op
!= ISL_AUX_OP_NONE
) {
2172 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2173 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2175 switch (resolve_op
) {
2176 case ISL_AUX_OP_FULL_RESOLVE
:
2177 /* The CCS full resolve operation destroys the CCS and sets it to the
2178 * pass-through state. (You can also think of this as being both a
2179 * resolve and an ambiguate in one operation.)
2181 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2182 ISL_AUX_STATE_PASS_THROUGH
);
2185 case ISL_AUX_OP_PARTIAL_RESOLVE
:
2186 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2187 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2191 unreachable("Invalid resolve op");
2197 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2198 struct intel_mipmap_tree
*mt
,
2199 uint32_t level
, uint32_t layer
,
2200 enum isl_aux_usage aux_usage
)
2202 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2203 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2204 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2206 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2208 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2209 switch (aux_state
) {
2210 case ISL_AUX_STATE_CLEAR
:
2211 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2212 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2213 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2215 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2216 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2217 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2218 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2219 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2220 ISL_AUX_STATE_PARTIAL_CLEAR
);
2224 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2225 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2226 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2227 break; /* Nothing to do */
2229 case ISL_AUX_STATE_PASS_THROUGH
:
2230 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2231 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2232 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2238 case ISL_AUX_STATE_RESOLVED
:
2239 case ISL_AUX_STATE_AUX_INVALID
:
2240 unreachable("Invalid aux state for CCS_E");
2243 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2244 /* CCS_D is a bit simpler */
2245 switch (aux_state
) {
2246 case ISL_AUX_STATE_CLEAR
:
2247 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2248 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2249 ISL_AUX_STATE_PARTIAL_CLEAR
);
2252 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2253 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2254 break; /* Nothing to do */
2256 case ISL_AUX_STATE_PASS_THROUGH
:
2260 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2261 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2262 case ISL_AUX_STATE_RESOLVED
:
2263 case ISL_AUX_STATE_AUX_INVALID
:
2264 unreachable("Invalid aux state for CCS_D");
2270 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2271 struct intel_mipmap_tree
*mt
,
2273 enum isl_aux_usage aux_usage
,
2274 bool fast_clear_supported
)
2276 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2278 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2279 case ISL_AUX_STATE_CLEAR
:
2280 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2281 if (!fast_clear_supported
) {
2282 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2283 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2284 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2288 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2289 break; /* Nothing to do */
2291 case ISL_AUX_STATE_RESOLVED
:
2292 case ISL_AUX_STATE_PASS_THROUGH
:
2293 case ISL_AUX_STATE_AUX_INVALID
:
2294 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2295 unreachable("Invalid aux state for MCS");
2300 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2301 struct intel_mipmap_tree
*mt
,
2303 enum isl_aux_usage aux_usage
)
2305 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2307 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2308 case ISL_AUX_STATE_CLEAR
:
2309 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2310 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2313 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2314 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2315 break; /* Nothing to do */
2317 case ISL_AUX_STATE_RESOLVED
:
2318 case ISL_AUX_STATE_PASS_THROUGH
:
2319 case ISL_AUX_STATE_AUX_INVALID
:
2320 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2321 unreachable("Invalid aux state for MCS");
2326 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2327 struct intel_mipmap_tree
*mt
,
2328 uint32_t level
, uint32_t layer
,
2329 enum isl_aux_usage aux_usage
,
2330 bool fast_clear_supported
)
2332 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2334 enum isl_aux_op hiz_op
= ISL_AUX_OP_NONE
;
2335 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2336 case ISL_AUX_STATE_CLEAR
:
2337 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2338 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2339 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2342 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2343 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2344 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2347 case ISL_AUX_STATE_PASS_THROUGH
:
2348 case ISL_AUX_STATE_RESOLVED
:
2351 case ISL_AUX_STATE_AUX_INVALID
:
2352 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2353 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
2356 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2357 unreachable("Invalid HiZ state");
2360 if (hiz_op
!= ISL_AUX_OP_NONE
) {
2361 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2364 case ISL_AUX_OP_FULL_RESOLVE
:
2365 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2366 ISL_AUX_STATE_RESOLVED
);
2369 case ISL_AUX_OP_AMBIGUATE
:
2370 /* The HiZ resolve operation is actually an ambiguate */
2371 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2372 ISL_AUX_STATE_PASS_THROUGH
);
2376 unreachable("Invalid HiZ op");
2382 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2383 struct intel_mipmap_tree
*mt
,
2384 uint32_t level
, uint32_t layer
,
2385 enum isl_aux_usage aux_usage
)
2387 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2389 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2390 case ISL_AUX_STATE_CLEAR
:
2391 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2392 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2393 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2396 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2397 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2398 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2399 break; /* Nothing to do */
2401 case ISL_AUX_STATE_RESOLVED
:
2402 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2403 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2404 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2406 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2407 ISL_AUX_STATE_AUX_INVALID
);
2411 case ISL_AUX_STATE_PASS_THROUGH
:
2412 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2413 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2414 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2418 case ISL_AUX_STATE_AUX_INVALID
:
2419 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2422 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2423 unreachable("Invalid HiZ state");
2428 intel_miptree_prepare_access(struct brw_context
*brw
,
2429 struct intel_mipmap_tree
*mt
,
2430 uint32_t start_level
, uint32_t num_levels
,
2431 uint32_t start_layer
, uint32_t num_layers
,
2432 enum isl_aux_usage aux_usage
,
2433 bool fast_clear_supported
)
2435 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2437 switch (mt
->aux_usage
) {
2438 case ISL_AUX_USAGE_NONE
:
2442 case ISL_AUX_USAGE_MCS
:
2443 assert(mt
->aux_buf
);
2444 assert(start_level
== 0 && num_levels
== 1);
2445 const uint32_t level_layers
=
2446 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2447 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2448 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2449 aux_usage
, fast_clear_supported
);
2453 case ISL_AUX_USAGE_CCS_D
:
2454 case ISL_AUX_USAGE_CCS_E
:
2458 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2459 const uint32_t level
= start_level
+ l
;
2460 const uint32_t level_layers
=
2461 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2462 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2463 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2465 aux_usage
, fast_clear_supported
);
2470 case ISL_AUX_USAGE_HIZ
:
2471 assert(mt
->aux_buf
);
2472 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2473 const uint32_t level
= start_level
+ l
;
2474 if (!intel_miptree_level_has_hiz(mt
, level
))
2477 const uint32_t level_layers
=
2478 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2479 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2480 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2481 aux_usage
, fast_clear_supported
);
2487 unreachable("Invalid aux usage");
2492 intel_miptree_finish_write(struct brw_context
*brw
,
2493 struct intel_mipmap_tree
*mt
, uint32_t level
,
2494 uint32_t start_layer
, uint32_t num_layers
,
2495 enum isl_aux_usage aux_usage
)
2497 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2499 switch (mt
->aux_usage
) {
2500 case ISL_AUX_USAGE_NONE
:
2504 case ISL_AUX_USAGE_MCS
:
2505 assert(mt
->aux_buf
);
2506 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2507 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2512 case ISL_AUX_USAGE_CCS_D
:
2513 case ISL_AUX_USAGE_CCS_E
:
2517 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2518 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2523 case ISL_AUX_USAGE_HIZ
:
2524 if (!intel_miptree_level_has_hiz(mt
, level
))
2527 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2528 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2534 unreachable("Invavlid aux usage");
2539 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2540 uint32_t level
, uint32_t layer
)
2542 intel_miptree_check_level_layer(mt
, level
, layer
);
2544 if (_mesa_is_format_color_format(mt
->format
)) {
2545 assert(mt
->aux_buf
!= NULL
);
2546 assert(mt
->surf
.samples
== 1 ||
2547 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2548 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2549 unreachable("Cannot get aux state for stencil");
2551 assert(intel_miptree_level_has_hiz(mt
, level
));
2554 return mt
->aux_state
[level
][layer
];
2558 intel_miptree_set_aux_state(struct brw_context
*brw
,
2559 struct intel_mipmap_tree
*mt
, uint32_t level
,
2560 uint32_t start_layer
, uint32_t num_layers
,
2561 enum isl_aux_state aux_state
)
2563 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2565 if (_mesa_is_format_color_format(mt
->format
)) {
2566 assert(mt
->aux_buf
!= NULL
);
2567 assert(mt
->surf
.samples
== 1 ||
2568 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2569 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2570 unreachable("Cannot get aux state for stencil");
2572 assert(intel_miptree_level_has_hiz(mt
, level
));
2575 for (unsigned a
= 0; a
< num_layers
; a
++) {
2576 if (mt
->aux_state
[level
][start_layer
+ a
] != aux_state
) {
2577 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2578 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2583 /* On Gen9 color buffers may be compressed by the hardware (lossless
2584 * compression). There are, however, format restrictions and care needs to be
2585 * taken that the sampler engine is capable for re-interpreting a buffer with
2586 * format different the buffer was originally written with.
2588 * For example, SRGB formats are not compressible and the sampler engine isn't
2589 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2590 * color buffer needs to be resolved so that the sampling surface can be
2591 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2595 can_texture_with_ccs(struct brw_context
*brw
,
2596 struct intel_mipmap_tree
*mt
,
2597 enum isl_format view_format
)
2599 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2602 if (!format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2604 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2605 isl_format_get_layout(view_format
)->name
,
2606 _mesa_get_format_name(mt
->format
));
2614 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2615 struct intel_mipmap_tree
*mt
,
2616 enum isl_format view_format
)
2618 switch (mt
->aux_usage
) {
2619 case ISL_AUX_USAGE_HIZ
:
2620 if (intel_miptree_sample_with_hiz(brw
, mt
))
2621 return ISL_AUX_USAGE_HIZ
;
2624 case ISL_AUX_USAGE_MCS
:
2625 return ISL_AUX_USAGE_MCS
;
2627 case ISL_AUX_USAGE_CCS_D
:
2628 case ISL_AUX_USAGE_CCS_E
:
2630 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2631 return ISL_AUX_USAGE_NONE
;
2634 /* If we don't have any unresolved color, report an aux usage of
2635 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
2636 * aux surface and we can save some bandwidth.
2638 if (!intel_miptree_has_color_unresolved(mt
, 0, INTEL_REMAINING_LEVELS
,
2639 0, INTEL_REMAINING_LAYERS
))
2640 return ISL_AUX_USAGE_NONE
;
2642 if (can_texture_with_ccs(brw
, mt
, view_format
))
2643 return ISL_AUX_USAGE_CCS_E
;
2650 return ISL_AUX_USAGE_NONE
;
2654 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2656 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2657 * values so sRGB curve application was a no-op for all fast-clearable
2660 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2661 * values, the hardware interprets the floats, not as what would be
2662 * returned from the sampler (or written by the shader), but as being
2663 * between format conversion and sRGB curve application. This means that
2664 * we can switch between sRGB and UNORM without having to whack the clear
2667 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2671 intel_miptree_prepare_texture(struct brw_context
*brw
,
2672 struct intel_mipmap_tree
*mt
,
2673 enum isl_format view_format
,
2674 uint32_t start_level
, uint32_t num_levels
,
2675 uint32_t start_layer
, uint32_t num_layers
)
2677 enum isl_aux_usage aux_usage
=
2678 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2679 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2681 /* Clear color is specified as ints or floats and the conversion is done by
2682 * the sampler. If we have a texture view, we would have to perform the
2683 * clear color conversion manually. Just disable clear color.
2685 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2686 clear_supported
= false;
2688 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2689 start_layer
, num_layers
,
2690 aux_usage
, clear_supported
);
2694 intel_miptree_prepare_image(struct brw_context
*brw
,
2695 struct intel_mipmap_tree
*mt
)
2697 /* The data port doesn't understand any compression */
2698 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2699 0, INTEL_REMAINING_LAYERS
,
2700 ISL_AUX_USAGE_NONE
, false);
2704 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2705 struct intel_mipmap_tree
*mt
,
2706 enum isl_format render_format
,
2708 bool draw_aux_disabled
)
2710 struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2712 if (draw_aux_disabled
)
2713 return ISL_AUX_USAGE_NONE
;
2715 switch (mt
->aux_usage
) {
2716 case ISL_AUX_USAGE_MCS
:
2717 assert(mt
->aux_buf
);
2718 return ISL_AUX_USAGE_MCS
;
2720 case ISL_AUX_USAGE_CCS_D
:
2721 case ISL_AUX_USAGE_CCS_E
:
2723 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2724 return ISL_AUX_USAGE_NONE
;
2727 /* gen9+ hardware technically supports non-0/1 clear colors with sRGB
2728 * formats. However, there are issues with blending where it doesn't
2729 * properly apply the sRGB curve to the clear color when blending.
2731 if (devinfo
->gen
>= 9 && blend_enabled
&&
2732 isl_format_is_srgb(render_format
) &&
2733 !isl_color_value_is_zero_one(mt
->fast_clear_color
, render_format
))
2734 return ISL_AUX_USAGE_NONE
;
2736 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
&&
2737 format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2739 return ISL_AUX_USAGE_CCS_E
;
2741 /* Otherwise, we have to fall back to CCS_D */
2742 return ISL_AUX_USAGE_CCS_D
;
2745 return ISL_AUX_USAGE_NONE
;
2750 intel_miptree_prepare_render(struct brw_context
*brw
,
2751 struct intel_mipmap_tree
*mt
, uint32_t level
,
2752 uint32_t start_layer
, uint32_t layer_count
,
2753 enum isl_aux_usage aux_usage
)
2755 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2756 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2760 intel_miptree_finish_render(struct brw_context
*brw
,
2761 struct intel_mipmap_tree
*mt
, uint32_t level
,
2762 uint32_t start_layer
, uint32_t layer_count
,
2763 enum isl_aux_usage aux_usage
)
2765 assert(_mesa_is_format_color_format(mt
->format
));
2767 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2772 intel_miptree_prepare_depth(struct brw_context
*brw
,
2773 struct intel_mipmap_tree
*mt
, uint32_t level
,
2774 uint32_t start_layer
, uint32_t layer_count
)
2776 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2777 mt
->aux_usage
, mt
->aux_buf
!= NULL
);
2781 intel_miptree_finish_depth(struct brw_context
*brw
,
2782 struct intel_mipmap_tree
*mt
, uint32_t level
,
2783 uint32_t start_layer
, uint32_t layer_count
,
2786 if (depth_written
) {
2787 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2788 mt
->aux_buf
!= NULL
);
2793 intel_miptree_prepare_external(struct brw_context
*brw
,
2794 struct intel_mipmap_tree
*mt
)
2796 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
2797 bool supports_fast_clear
= false;
2799 const struct isl_drm_modifier_info
*mod_info
=
2800 isl_drm_modifier_get_info(mt
->drm_modifier
);
2802 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
2803 /* CCS_E is the only supported aux for external images and it's only
2804 * supported on very simple images.
2806 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
2807 assert(_mesa_is_format_color_format(mt
->format
));
2808 assert(mt
->first_level
== 0 && mt
->last_level
== 0);
2809 assert(mt
->surf
.logical_level0_px
.depth
== 1);
2810 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
2811 assert(mt
->surf
.samples
== 1);
2812 assert(mt
->aux_buf
!= NULL
);
2814 aux_usage
= mod_info
->aux_usage
;
2815 supports_fast_clear
= mod_info
->supports_clear_color
;
2818 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2819 0, INTEL_REMAINING_LAYERS
,
2820 aux_usage
, supports_fast_clear
);
2824 intel_miptree_finish_external(struct brw_context
*brw
,
2825 struct intel_mipmap_tree
*mt
)
2830 /* We don't know the actual aux state of the aux surface. The previous
2831 * owner could have given it to us in a number of different states.
2832 * Because we don't know the aux state, we reset the aux state to the
2833 * least common denominator of possible valid states.
2835 enum isl_aux_state default_aux_state
=
2836 isl_drm_modifier_get_default_aux_state(mt
->drm_modifier
);
2837 assert(mt
->last_level
== mt
->first_level
);
2838 intel_miptree_set_aux_state(brw
, mt
, 0, 0, INTEL_REMAINING_LAYERS
,
2843 * Make it possible to share the BO backing the given miptree with another
2844 * process or another miptree.
2846 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2847 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2848 * ensure that no MCS buffer gets allocated in the future.
2850 * HiZ is similarly unsafe with shared buffers.
2853 intel_miptree_make_shareable(struct brw_context
*brw
,
2854 struct intel_mipmap_tree
*mt
)
2856 /* MCS buffers are also used for multisample buffers, but we can't resolve
2857 * away a multisample MCS buffer because it's an integral part of how the
2858 * pixel data is stored. Fortunately this code path should never be
2859 * reached for multisample buffers.
2861 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2862 mt
->surf
.samples
== 1);
2864 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2865 0, INTEL_REMAINING_LAYERS
,
2866 ISL_AUX_USAGE_NONE
, false);
2869 intel_miptree_aux_buffer_free(mt
->aux_buf
);
2872 /* Make future calls of intel_miptree_level_has_hiz() return false. */
2873 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2874 mt
->level
[l
].has_hiz
= false;
2877 free(mt
->aux_state
);
2878 mt
->aux_state
= NULL
;
2879 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2882 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2883 mt
->supports_fast_clear
= false;
2888 * \brief Get pointer offset into stencil buffer.
2890 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2891 * must decode the tile's layout in software.
2894 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2896 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2898 * Even though the returned offset is always positive, the return type is
2900 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2901 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2904 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2906 uint32_t tile_size
= 4096;
2907 uint32_t tile_width
= 64;
2908 uint32_t tile_height
= 64;
2909 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2911 uint32_t tile_x
= x
/ tile_width
;
2912 uint32_t tile_y
= y
/ tile_height
;
2914 /* The byte's address relative to the tile's base addres. */
2915 uint32_t byte_x
= x
% tile_width
;
2916 uint32_t byte_y
= y
% tile_height
;
2918 uintptr_t u
= tile_y
* row_size
2919 + tile_x
* tile_size
2920 + 512 * (byte_x
/ 8)
2922 + 32 * ((byte_y
/ 4) % 2)
2923 + 16 * ((byte_x
/ 4) % 2)
2924 + 8 * ((byte_y
/ 2) % 2)
2925 + 4 * ((byte_x
/ 2) % 2)
2930 /* adjust for bit6 swizzling */
2931 if (((byte_x
/ 8) % 2) == 1) {
2932 if (((byte_y
/ 8) % 2) == 0) {
2944 intel_miptree_updownsample(struct brw_context
*brw
,
2945 struct intel_mipmap_tree
*src
,
2946 struct intel_mipmap_tree
*dst
)
2948 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2949 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2950 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2951 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2953 brw_blorp_blit_miptrees(brw
,
2954 src
, 0 /* level */, 0 /* layer */,
2955 src
->format
, SWIZZLE_XYZW
,
2956 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2959 GL_NEAREST
, false, false /*mirror x, y*/,
2962 if (src
->stencil_mt
) {
2963 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2964 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2965 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2966 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2968 brw_blorp_blit_miptrees(brw
,
2969 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2970 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2971 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2972 dst
->stencil_mt
->format
,
2975 GL_NEAREST
, false, false /*mirror x, y*/,
2976 false, false /* decode/encode srgb */);
2981 intel_update_r8stencil(struct brw_context
*brw
,
2982 struct intel_mipmap_tree
*mt
)
2984 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2986 assert(devinfo
->gen
>= 7);
2987 struct intel_mipmap_tree
*src
=
2988 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2989 if (!src
|| devinfo
->gen
>= 8 || !src
->r8stencil_needs_update
)
2992 assert(src
->surf
.size
> 0);
2994 if (!mt
->r8stencil_mt
) {
2995 assert(devinfo
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2996 mt
->r8stencil_mt
= make_surface(
2999 MESA_FORMAT_R_UINT8
,
3000 src
->first_level
, src
->last_level
,
3001 src
->surf
.logical_level0_px
.width
,
3002 src
->surf
.logical_level0_px
.height
,
3003 src
->surf
.dim
== ISL_SURF_DIM_3D
?
3004 src
->surf
.logical_level0_px
.depth
:
3005 src
->surf
.logical_level0_px
.array_len
,
3008 ISL_SURF_USAGE_TEXTURE_BIT
,
3009 BO_ALLOC_BUSY
, 0, NULL
);
3010 assert(mt
->r8stencil_mt
);
3013 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
3015 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
3016 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
3017 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
3018 src
->surf
.phys_level0_sa
.array_len
;
3020 for (unsigned layer
= 0; layer
< depth
; layer
++) {
3021 brw_blorp_copy_miptrees(brw
,
3025 minify(src
->surf
.logical_level0_px
.width
,
3027 minify(src
->surf
.logical_level0_px
.height
,
3032 brw_cache_flush_for_read(brw
, dst
->bo
);
3033 src
->r8stencil_needs_update
= false;
3037 intel_miptree_map_raw(struct brw_context
*brw
,
3038 struct intel_mipmap_tree
*mt
,
3041 struct brw_bo
*bo
= mt
->bo
;
3043 if (brw_batch_references(&brw
->batch
, bo
))
3044 intel_batchbuffer_flush(brw
);
3046 return brw_bo_map(brw
, bo
, mode
);
3050 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3052 brw_bo_unmap(mt
->bo
);
3056 intel_miptree_unmap_gtt(struct brw_context
*brw
,
3057 struct intel_mipmap_tree
*mt
,
3058 struct intel_miptree_map
*map
,
3059 unsigned int level
, unsigned int slice
)
3061 intel_miptree_unmap_raw(mt
);
3065 intel_miptree_map_gtt(struct brw_context
*brw
,
3066 struct intel_mipmap_tree
*mt
,
3067 struct intel_miptree_map
*map
,
3068 unsigned int level
, unsigned int slice
)
3070 unsigned int bw
, bh
;
3072 unsigned int image_x
, image_y
;
3073 intptr_t x
= map
->x
;
3074 intptr_t y
= map
->y
;
3076 /* For compressed formats, the stride is the number of bytes per
3077 * row of blocks. intel_miptree_get_image_offset() already does
3080 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3081 assert(y
% bh
== 0);
3082 assert(x
% bw
== 0);
3086 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3093 /* Note that in the case of cube maps, the caller must have passed the
3094 * slice number referencing the face.
3096 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3100 map
->stride
= mt
->surf
.row_pitch
;
3101 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3104 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3105 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3106 map
->x
, map
->y
, map
->w
, map
->h
,
3107 mt
, _mesa_get_format_name(mt
->format
),
3108 x
, y
, map
->ptr
, map
->stride
);
3110 map
->unmap
= intel_miptree_unmap_gtt
;
3114 intel_miptree_unmap_blit(struct brw_context
*brw
,
3115 struct intel_mipmap_tree
*mt
,
3116 struct intel_miptree_map
*map
,
3120 struct gl_context
*ctx
= &brw
->ctx
;
3122 intel_miptree_unmap_raw(map
->linear_mt
);
3124 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3125 bool ok
= intel_miptree_copy(brw
,
3126 map
->linear_mt
, 0, 0, 0, 0,
3127 mt
, level
, slice
, map
->x
, map
->y
,
3129 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3132 intel_miptree_release(&map
->linear_mt
);
3136 intel_miptree_map_blit(struct brw_context
*brw
,
3137 struct intel_mipmap_tree
*mt
,
3138 struct intel_miptree_map
*map
,
3139 unsigned int level
, unsigned int slice
)
3141 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3142 /* first_level */ 0,
3146 MIPTREE_CREATE_LINEAR
);
3148 if (!map
->linear_mt
) {
3149 fprintf(stderr
, "Failed to allocate blit temporary\n");
3152 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3154 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3155 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3156 * invalidate is set, since we'll be writing the whole rectangle from our
3157 * temporary buffer back out.
3159 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3160 if (!intel_miptree_copy(brw
,
3161 mt
, level
, slice
, map
->x
, map
->y
,
3162 map
->linear_mt
, 0, 0, 0, 0,
3164 fprintf(stderr
, "Failed to blit\n");
3169 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3171 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3172 map
->x
, map
->y
, map
->w
, map
->h
,
3173 mt
, _mesa_get_format_name(mt
->format
),
3174 level
, slice
, map
->ptr
, map
->stride
);
3176 map
->unmap
= intel_miptree_unmap_blit
;
3180 intel_miptree_release(&map
->linear_mt
);
3186 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3188 #if defined(USE_SSE41)
3190 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3191 struct intel_mipmap_tree
*mt
,
3192 struct intel_miptree_map
*map
,
3196 _mesa_align_free(map
->buffer
);
3202 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3203 struct intel_mipmap_tree
*mt
,
3204 struct intel_miptree_map
*map
,
3205 unsigned int level
, unsigned int slice
)
3207 assert(map
->mode
& GL_MAP_READ_BIT
);
3208 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3210 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3211 map
->x
, map
->y
, map
->w
, map
->h
,
3212 mt
, _mesa_get_format_name(mt
->format
),
3213 level
, slice
, map
->ptr
, map
->stride
);
3215 /* Map the original image */
3218 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3222 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3228 src
+= image_y
* mt
->surf
.row_pitch
;
3229 src
+= image_x
* mt
->cpp
;
3231 /* Due to the pixel offsets for the particular image being mapped, our
3232 * src pointer may not be 16-byte aligned. However, if the pitch is
3233 * divisible by 16, then the amount by which it's misaligned will remain
3234 * consistent from row to row.
3236 assert((mt
->surf
.row_pitch
% 16) == 0);
3237 const int misalignment
= ((uintptr_t) src
) & 15;
3239 /* Create an untiled temporary buffer for the mapping. */
3240 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3242 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3244 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3245 /* Offset the destination so it has the same misalignment as src. */
3246 map
->ptr
= map
->buffer
+ misalignment
;
3248 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3250 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3251 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3252 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3254 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3257 intel_miptree_unmap_raw(mt
);
3259 map
->unmap
= intel_miptree_unmap_movntdqa
;
3264 intel_miptree_unmap_s8(struct brw_context
*brw
,
3265 struct intel_mipmap_tree
*mt
,
3266 struct intel_miptree_map
*map
,
3270 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3271 unsigned int image_x
, image_y
;
3272 uint8_t *untiled_s8_map
= map
->ptr
;
3273 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3275 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3277 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3278 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3279 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3280 image_x
+ x
+ map
->x
,
3281 image_y
+ y
+ map
->y
,
3282 brw
->has_swizzling
);
3283 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3287 intel_miptree_unmap_raw(mt
);
3294 intel_miptree_map_s8(struct brw_context
*brw
,
3295 struct intel_mipmap_tree
*mt
,
3296 struct intel_miptree_map
*map
,
3297 unsigned int level
, unsigned int slice
)
3299 map
->stride
= map
->w
;
3300 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3304 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3305 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3306 * invalidate is set, since we'll be writing the whole rectangle from our
3307 * temporary buffer back out.
3309 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3310 uint8_t *untiled_s8_map
= map
->ptr
;
3311 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3312 unsigned int image_x
, image_y
;
3314 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3316 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3317 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3318 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3319 x
+ image_x
+ map
->x
,
3320 y
+ image_y
+ map
->y
,
3321 brw
->has_swizzling
);
3322 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3326 intel_miptree_unmap_raw(mt
);
3328 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3329 map
->x
, map
->y
, map
->w
, map
->h
,
3330 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3332 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3333 map
->x
, map
->y
, map
->w
, map
->h
,
3334 mt
, map
->ptr
, map
->stride
);
3337 map
->unmap
= intel_miptree_unmap_s8
;
3341 intel_miptree_unmap_etc(struct brw_context
*brw
,
3342 struct intel_mipmap_tree
*mt
,
3343 struct intel_miptree_map
*map
,
3349 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3354 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3355 + image_y
* mt
->surf
.row_pitch
3356 + image_x
* mt
->cpp
;
3358 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3359 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3360 map
->ptr
, map
->stride
,
3363 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3364 map
->ptr
, map
->stride
,
3365 map
->w
, map
->h
, mt
->etc_format
);
3367 intel_miptree_unmap_raw(mt
);
3372 intel_miptree_map_etc(struct brw_context
*brw
,
3373 struct intel_mipmap_tree
*mt
,
3374 struct intel_miptree_map
*map
,
3378 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3379 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3380 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3383 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3384 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3386 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3387 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3388 map
->w
, map
->h
, 1));
3389 map
->ptr
= map
->buffer
;
3390 map
->unmap
= intel_miptree_unmap_etc
;
3394 * Mapping functions for packed depth/stencil miptrees backed by real separate
3395 * miptrees for depth and stencil.
3397 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3398 * separate from the depth buffer. Yet at the GL API level, we have to expose
3399 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3400 * be able to map that memory for texture storage and glReadPixels-type
3401 * operations. We give Mesa core that access by mallocing a temporary and
3402 * copying the data between the actual backing store and the temporary.
3405 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3406 struct intel_mipmap_tree
*mt
,
3407 struct intel_miptree_map
*map
,
3411 struct intel_mipmap_tree
*z_mt
= mt
;
3412 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3413 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3415 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3416 uint32_t *packed_map
= map
->ptr
;
3417 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3418 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3419 unsigned int s_image_x
, s_image_y
;
3420 unsigned int z_image_x
, z_image_y
;
3422 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3423 &s_image_x
, &s_image_y
);
3424 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3425 &z_image_x
, &z_image_y
);
3427 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3428 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3429 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3430 x
+ s_image_x
+ map
->x
,
3431 y
+ s_image_y
+ map
->y
,
3432 brw
->has_swizzling
);
3433 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3434 (z_mt
->surf
.row_pitch
/ 4) +
3435 (x
+ z_image_x
+ map
->x
));
3437 if (map_z32f_x24s8
) {
3438 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3439 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3441 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3442 s_map
[s_offset
] = packed
>> 24;
3443 z_map
[z_offset
] = packed
;
3448 intel_miptree_unmap_raw(s_mt
);
3449 intel_miptree_unmap_raw(z_mt
);
3451 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3453 map
->x
, map
->y
, map
->w
, map
->h
,
3454 z_mt
, _mesa_get_format_name(z_mt
->format
),
3455 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3456 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3457 map
->ptr
, map
->stride
);
3464 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3465 struct intel_mipmap_tree
*mt
,
3466 struct intel_miptree_map
*map
,
3467 unsigned int level
, unsigned int slice
)
3469 struct intel_mipmap_tree
*z_mt
= mt
;
3470 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3471 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3472 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3474 map
->stride
= map
->w
* packed_bpp
;
3475 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3479 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3480 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3481 * invalidate is set, since we'll be writing the whole rectangle from our
3482 * temporary buffer back out.
3484 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3485 uint32_t *packed_map
= map
->ptr
;
3486 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3487 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3488 unsigned int s_image_x
, s_image_y
;
3489 unsigned int z_image_x
, z_image_y
;
3491 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3492 &s_image_x
, &s_image_y
);
3493 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3494 &z_image_x
, &z_image_y
);
3496 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3497 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3498 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3499 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3502 brw
->has_swizzling
);
3503 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3504 (z_mt
->surf
.row_pitch
/ 4) +
3505 (map_x
+ z_image_x
));
3506 uint8_t s
= s_map
[s_offset
];
3507 uint32_t z
= z_map
[z_offset
];
3509 if (map_z32f_x24s8
) {
3510 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3511 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3513 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3518 intel_miptree_unmap_raw(s_mt
);
3519 intel_miptree_unmap_raw(z_mt
);
3521 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3523 map
->x
, map
->y
, map
->w
, map
->h
,
3524 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3525 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3526 map
->ptr
, map
->stride
);
3528 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3529 map
->x
, map
->y
, map
->w
, map
->h
,
3530 mt
, map
->ptr
, map
->stride
);
3533 map
->unmap
= intel_miptree_unmap_depthstencil
;
3537 * Create and attach a map to the miptree at (level, slice). Return the
3540 static struct intel_miptree_map
*
3541 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3550 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3555 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3556 mt
->level
[level
].slice
[slice
].map
= map
;
3568 * Release the map at (level, slice).
3571 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3575 struct intel_miptree_map
**map
;
3577 map
= &mt
->level
[level
].slice
[slice
].map
;
3583 can_blit_slice(struct intel_mipmap_tree
*mt
,
3584 unsigned int level
, unsigned int slice
)
3586 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3587 if (mt
->surf
.row_pitch
>= 32768)
3594 use_intel_mipree_map_blit(struct brw_context
*brw
,
3595 struct intel_mipmap_tree
*mt
,
3600 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3602 if (devinfo
->has_llc
&&
3603 /* It's probably not worth swapping to the blit ring because of
3604 * all the overhead involved.
3606 !(mode
& GL_MAP_WRITE_BIT
) &&
3608 (mt
->surf
.tiling
== ISL_TILING_X
||
3609 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3610 (devinfo
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3611 /* Fast copy blit on skl+ supports all tiling formats. */
3612 devinfo
->gen
>= 9) &&
3613 can_blit_slice(mt
, level
, slice
))
3616 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3617 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3618 assert(can_blit_slice(mt
, level
, slice
));
3626 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3627 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3628 * arithmetic overflow.
3630 * If you call this function and use \a out_stride, then you're doing pointer
3631 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3632 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3633 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3634 * which usually have type uint32_t or GLuint.
3637 intel_miptree_map(struct brw_context
*brw
,
3638 struct intel_mipmap_tree
*mt
,
3647 ptrdiff_t *out_stride
)
3649 struct intel_miptree_map
*map
;
3651 assert(mt
->surf
.samples
== 1);
3653 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3660 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3661 map
->mode
& GL_MAP_WRITE_BIT
);
3663 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3664 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3665 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3666 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3667 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3668 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3669 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3670 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3671 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3672 #if defined(USE_SSE41)
3673 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3674 !mt
->compressed
&& cpu_has_sse4_1
&&
3675 (mt
->surf
.row_pitch
% 16 == 0)) {
3676 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3679 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3682 *out_ptr
= map
->ptr
;
3683 *out_stride
= map
->stride
;
3685 if (map
->ptr
== NULL
)
3686 intel_miptree_release_map(mt
, level
, slice
);
3690 intel_miptree_unmap(struct brw_context
*brw
,
3691 struct intel_mipmap_tree
*mt
,
3695 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3697 assert(mt
->surf
.samples
== 1);
3702 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3703 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3706 map
->unmap(brw
, mt
, map
, level
, slice
);
3708 intel_miptree_release_map(mt
, level
, slice
);
3712 get_isl_surf_dim(GLenum target
)
3716 case GL_TEXTURE_1D_ARRAY
:
3717 return ISL_SURF_DIM_1D
;
3720 case GL_TEXTURE_2D_ARRAY
:
3721 case GL_TEXTURE_RECTANGLE
:
3722 case GL_TEXTURE_CUBE_MAP
:
3723 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3724 case GL_TEXTURE_2D_MULTISAMPLE
:
3725 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3726 case GL_TEXTURE_EXTERNAL_OES
:
3727 return ISL_SURF_DIM_2D
;
3730 return ISL_SURF_DIM_3D
;
3733 unreachable("Invalid texture target");
3737 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3738 enum isl_tiling tiling
, GLenum target
)
3742 case GL_TEXTURE_1D_ARRAY
:
3743 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3744 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3747 case GL_TEXTURE_2D_ARRAY
:
3748 case GL_TEXTURE_RECTANGLE
:
3749 case GL_TEXTURE_2D_MULTISAMPLE
:
3750 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3751 case GL_TEXTURE_EXTERNAL_OES
:
3752 return ISL_DIM_LAYOUT_GEN4_2D
;
3754 case GL_TEXTURE_CUBE_MAP
:
3755 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3756 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3757 ISL_DIM_LAYOUT_GEN4_2D
);
3760 return (devinfo
->gen
>= 9 ?
3761 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3764 unreachable("Invalid texture target");
3768 intel_miptree_set_clear_color(struct brw_context
*brw
,
3769 struct intel_mipmap_tree
*mt
,
3770 const union gl_color_union
*color
)
3772 const union isl_color_value clear_color
=
3773 brw_meta_convert_fast_clear_color(brw
, mt
, color
);
3775 if (memcmp(&mt
->fast_clear_color
, &clear_color
, sizeof(clear_color
)) != 0) {
3776 mt
->fast_clear_color
= clear_color
;
3777 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
3784 intel_miptree_set_depth_clear_value(struct brw_context
*brw
,
3785 struct intel_mipmap_tree
*mt
,
3788 if (mt
->fast_clear_color
.f32
[0] != clear_value
) {
3789 mt
->fast_clear_color
.f32
[0] = clear_value
;
3790 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
3796 union isl_color_value
3797 intel_miptree_get_clear_color(const struct gen_device_info
*devinfo
,
3798 const struct intel_mipmap_tree
*mt
,
3799 enum isl_format view_format
, bool sampling
,
3800 struct brw_bo
**clear_color_bo
,
3801 uint32_t *clear_color_offset
)
3803 assert(mt
->aux_buf
);
3805 if (devinfo
->gen
== 10 && isl_format_is_srgb(view_format
) && sampling
) {
3806 /* The gen10 sampler doesn't gamma-correct the clear color. In this case,
3807 * we switch to using the inline clear color and do the sRGB color
3808 * conversion process defined in the OpenGL spec. The red, green, and
3809 * blue channels take part in gamma correction, while the alpha channel
3812 union isl_color_value srgb_decoded_value
= mt
->fast_clear_color
;
3813 for (unsigned i
= 0; i
< 3; i
++) {
3814 srgb_decoded_value
.f32
[i
] =
3815 util_format_srgb_to_linear_float(mt
->fast_clear_color
.f32
[i
]);
3817 *clear_color_bo
= 0;
3818 *clear_color_offset
= 0;
3819 return srgb_decoded_value
;
3821 *clear_color_bo
= mt
->aux_buf
->clear_color_bo
;
3822 *clear_color_offset
= mt
->aux_buf
->clear_color_offset
;
3823 return mt
->fast_clear_color
;