2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_image.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
,
55 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
58 intel_miptree_alloc_aux(struct brw_context
*brw
,
59 struct intel_mipmap_tree
*mt
);
62 is_mcs_supported(const struct brw_context
*brw
, mesa_format format
,
63 uint32_t layout_flags
)
65 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
69 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
70 switch (_mesa_get_format_base_format(format
)) {
71 case GL_DEPTH_COMPONENT
:
72 case GL_STENCIL_INDEX
:
73 case GL_DEPTH_STENCIL
:
76 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
78 * This field must be set to 0 for all SINT MSRTs when all RT channels
81 * In practice this means that we have to disable MCS for all signed
82 * integer MSAA buffers. The alternative, to disable MCS only when one
83 * of the render target channels is disabled, is impractical because it
84 * would require converting between CMS and UMS MSAA layouts on the fly,
87 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
89 } else if (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) {
90 /* We can't use the CMS layout because it uses an aux buffer, the MCS
91 * buffer. So fallback to UMS, which is identical to CMS without the
101 * Determine which MSAA layout should be used by the MSAA surface being
102 * created, based on the chip generation and the surface type.
104 static enum intel_msaa_layout
105 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
106 uint32_t layout_flags
)
108 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
110 return INTEL_MSAA_LAYOUT_IMS
;
112 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
113 switch (_mesa_get_format_base_format(format
)) {
114 case GL_DEPTH_COMPONENT
:
115 case GL_STENCIL_INDEX
:
116 case GL_DEPTH_STENCIL
:
117 return INTEL_MSAA_LAYOUT_IMS
;
119 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
121 * This field must be set to 0 for all SINT MSRTs when all RT channels
124 * In practice this means that we have to disable MCS for all signed
125 * integer MSAA buffers. The alternative, to disable MCS only when one
126 * of the render target channels is disabled, is impractical because it
127 * would require converting between CMS and UMS MSAA layouts on the fly,
128 * which is expensive.
130 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
131 return INTEL_MSAA_LAYOUT_UMS
;
132 } else if (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) {
133 /* We can't use the CMS layout because it uses an aux buffer, the MCS
134 * buffer. So fallback to UMS, which is identical to CMS without the
136 return INTEL_MSAA_LAYOUT_UMS
;
138 return INTEL_MSAA_LAYOUT_CMS
;
144 intel_tiling_supports_ccs(const struct brw_context
*brw
, unsigned tiling
)
146 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
147 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
149 * - Support is limited to tiled render targets.
151 * Gen9 changes the restriction to Y-tile only.
154 return tiling
== I915_TILING_Y
;
155 else if (brw
->gen
>= 7)
156 return tiling
!= I915_TILING_NONE
;
162 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
163 * can be used. This doesn't (and should not) inspect any of the properties of
166 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
167 * beneath the "Fast Color Clear" bullet (p326):
169 * - Support is for non-mip-mapped and non-array surface types only.
171 * And then later, on p327:
173 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
176 * From the Skylake documentation, it is made clear that X-tiling is no longer
179 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
183 intel_miptree_supports_ccs(struct brw_context
*brw
,
184 const struct intel_mipmap_tree
*mt
)
186 /* MCS support does not exist prior to Gen7 */
190 /* This function applies only to non-multisampled render targets. */
191 if (mt
->num_samples
> 1)
194 /* MCS is only supported for color buffers */
195 switch (_mesa_get_format_base_format(mt
->format
)) {
196 case GL_DEPTH_COMPONENT
:
197 case GL_DEPTH_STENCIL
:
198 case GL_STENCIL_INDEX
:
202 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
205 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
206 const bool arrayed
= mt
->physical_depth0
!= 1;
209 /* Multisample surfaces with the CMS layout are not layered surfaces,
210 * yet still have physical_depth0 > 1. Assert that we don't
211 * accidentally reject a multisampled surface here. We should have
212 * rejected it earlier by explicitly checking the sample count.
214 assert(mt
->num_samples
<= 1);
217 /* Handle the hardware restrictions...
219 * All GENs have the following restriction: "MCS buffer for non-MSRT is
220 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
222 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
223 * Non-MultiSampler Render Target Restrictions) Support is for
224 * non-mip-mapped and non-array surface types only.
226 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
227 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
228 * surfaces are supported with MCS buffer layout with these alignments in
229 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
231 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
232 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
233 * surfaces are supported with MCS buffer layout with these alignments in
234 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
236 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
239 /* There's no point in using an MCS buffer if the surface isn't in a
242 if (!brw
->mesa_format_supports_render
[mt
->format
])
246 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
247 const enum isl_format isl_format
=
248 brw_isl_format_for_mesa_format(linear_format
);
249 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
255 intel_tiling_supports_hiz(const struct brw_context
*brw
, unsigned tiling
)
260 return tiling
== I915_TILING_Y
;
264 intel_miptree_supports_hiz(const struct brw_context
*brw
,
265 const struct intel_mipmap_tree
*mt
)
270 switch (mt
->format
) {
271 case MESA_FORMAT_Z_FLOAT32
:
272 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
273 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
274 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
275 case MESA_FORMAT_Z_UNORM16
:
283 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
284 const struct intel_mipmap_tree
*mt
)
286 /* For now compression is only enabled for integer formats even though
287 * there exist supported floating point formats also. This is a heuristic
288 * decision based on current public benchmarks. In none of the cases these
289 * formats provided any improvement but a few cases were seen to regress.
290 * Hence these are left to to be enabled in the future when they are known
293 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
296 if (!intel_miptree_supports_ccs(brw
, mt
))
299 /* Fast clear can be also used to clear srgb surfaces by using equivalent
300 * linear format. This trick, however, can't be extended to be used with
301 * lossless compression and therefore a check is needed to see if the format
304 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
308 * Determine depth format corresponding to a depth+stencil format,
309 * for separate stencil.
312 intel_depth_format_for_depthstencil_format(mesa_format format
) {
314 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
315 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
316 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
317 return MESA_FORMAT_Z_FLOAT32
;
324 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
325 unsigned depth0
, struct intel_mipmap_level
*table
)
327 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
329 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
331 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
332 if (!table
[level
].slice
)
339 for (unsigned level
= first_level
; level
<= last_level
; level
++)
340 free(table
[level
].slice
);
346 * @param for_bo Indicates that the caller is
347 * intel_miptree_create_for_bo(). If true, then do not create
350 static struct intel_mipmap_tree
*
351 intel_miptree_create_layout(struct brw_context
*brw
,
360 uint32_t layout_flags
)
362 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
366 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
367 _mesa_enum_to_string(target
),
368 _mesa_get_format_name(format
),
369 first_level
, last_level
, depth0
, mt
);
371 if (target
== GL_TEXTURE_1D_ARRAY
)
372 assert(height0
== 1);
376 mt
->first_level
= first_level
;
377 mt
->last_level
= last_level
;
378 mt
->logical_width0
= width0
;
379 mt
->logical_height0
= height0
;
380 mt
->logical_depth0
= depth0
;
381 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
382 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
383 mt
->supports_fast_clear
= false;
384 mt
->aux_state
= NULL
;
385 mt
->cpp
= _mesa_get_format_bytes(format
);
386 mt
->num_samples
= num_samples
;
387 mt
->compressed
= _mesa_is_format_compressed(format
);
388 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
391 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
392 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
394 int depth_multiply
= 1;
395 if (num_samples
> 1) {
396 /* Adjust width/height/depth for MSAA */
397 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, layout_flags
);
398 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
399 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
400 * "If the surface is multisampled and it is a depth or stencil
401 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
402 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
405 * +----------------------------------------------------------------+
406 * | Num Multisamples | W_l = | H_l = |
407 * +----------------------------------------------------------------+
408 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
409 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
410 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
411 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
412 * +----------------------------------------------------------------+
415 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
416 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
417 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
419 * Another more complicated explanation for these adjustments comes
420 * from the Sandybridge PRM, volume 4, part 1, page 31:
422 * "Any of the other messages (sample*, LOD, load4) used with a
423 * (4x) multisampled surface will in-effect sample a surface with
424 * double the height and width as that indicated in the surface
425 * state. Each pixel position on the original-sized surface is
426 * replaced with a 2x2 of samples with the following arrangement:
431 * Thus, when sampling from a multisampled texture, it behaves as
432 * though the layout in memory for (x,y,sample) is:
434 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
435 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
437 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
438 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
440 * However, the actual layout of multisampled data in memory is:
442 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
443 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
445 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
446 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
448 * This pattern repeats for each 2x2 pixel block.
450 * As a result, when calculating the size of our 4-sample buffer for
451 * an odd width or height, we have to align before scaling up because
452 * sample 3 is in that bottom right 2x2 block.
454 switch (num_samples
) {
456 assert(brw
->gen
>= 8);
457 width0
= ALIGN(width0
, 2) * 2;
458 height0
= ALIGN(height0
, 2);
461 width0
= ALIGN(width0
, 2) * 2;
462 height0
= ALIGN(height0
, 2) * 2;
465 width0
= ALIGN(width0
, 2) * 4;
466 height0
= ALIGN(height0
, 2) * 2;
469 width0
= ALIGN(width0
, 2) * 4;
470 height0
= ALIGN(height0
, 2) * 4;
473 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
476 unreachable("not reached");
479 /* Non-interleaved */
480 depth_multiply
= num_samples
;
481 depth0
*= depth_multiply
;
485 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
491 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
492 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
493 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
494 * used on Gen8 to make it pick a qpitch value which doesn't include space
495 * for the mipmaps. On Gen9 this is not necessary because it will
496 * automatically pick a packed qpitch value whenever mt->first_level ==
498 * TODO: can we use it elsewhere?
499 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
502 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
504 switch (mt
->msaa_layout
) {
505 case INTEL_MSAA_LAYOUT_NONE
:
506 case INTEL_MSAA_LAYOUT_IMS
:
507 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
509 case INTEL_MSAA_LAYOUT_UMS
:
510 case INTEL_MSAA_LAYOUT_CMS
:
511 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
516 if (target
== GL_TEXTURE_CUBE_MAP
)
517 assert(depth0
== 6 * depth_multiply
);
519 mt
->physical_width0
= width0
;
520 mt
->physical_height0
= height0
;
521 mt
->physical_depth0
= depth0
;
523 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
524 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
525 (brw
->must_use_separate_stencil
||
526 (brw
->has_separate_stencil
&& intel_miptree_supports_hiz(brw
, mt
)))) {
527 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
529 stencil_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
532 mt
->stencil_mt
= intel_miptree_create(brw
,
543 if (!mt
->stencil_mt
) {
544 intel_miptree_release(&mt
);
547 mt
->stencil_mt
->r8stencil_needs_update
= true;
549 /* Fix up the Z miptree format for how we're splitting out separate
550 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
552 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
555 if (format
== mt
->format
) {
556 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
557 _mesa_get_format_name(mt
->format
));
561 if (layout_flags
& MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
)
562 mt
->array_layout
= GEN6_HIZ_STENCIL
;
565 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
566 * multisampled or have an AUX buffer attached to it.
568 * GEN | MSRT | AUX_CCS_* or AUX_MCS
569 * -------------------------------------------
570 * 9 | HALIGN_16 | HALIGN_16
571 * 8 | HALIGN_ANY | HALIGN_16
575 if (intel_miptree_supports_ccs(brw
, mt
)) {
576 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
577 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
578 } else if (brw
->gen
>= 9 && num_samples
> 1) {
579 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
581 const UNUSED
bool is_lossless_compressed_aux
=
582 brw
->gen
>= 9 && num_samples
== 1 &&
583 mt
->format
== MESA_FORMAT_R_UINT32
;
585 /* For now, nothing else has this requirement */
586 assert(is_lossless_compressed_aux
||
587 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
590 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
591 intel_miptree_release(&mt
);
600 * Choose the aux usage for this miptree. This function must be called fairly
601 * late in the miptree create process after we have a tiling.
604 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
605 struct intel_mipmap_tree
*mt
)
607 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
609 const unsigned no_flags
= 0;
610 if (mt
->num_samples
> 1 && is_mcs_supported(brw
, mt
->format
, no_flags
)) {
611 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
612 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
613 } else if (intel_tiling_supports_ccs(brw
, mt
->tiling
) &&
614 intel_miptree_supports_ccs(brw
, mt
)) {
615 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
616 brw
->gen
>= 9 && !mt
->is_scanout
&&
617 intel_miptree_supports_ccs_e(brw
, mt
)) {
618 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
620 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
622 } else if (intel_tiling_supports_hiz(brw
, mt
->tiling
) &&
623 intel_miptree_supports_hiz(brw
, mt
)) {
624 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
627 /* We can do fast-clear on all auxiliary surface types that are
628 * allocated through the normal texture creation paths.
630 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
631 mt
->supports_fast_clear
= true;
636 * Choose an appropriate uncompressed format for a requested
637 * compressed format, if unsupported.
640 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
642 /* No need to lower ETC formats on these platforms,
643 * they are supported natively.
645 if (brw
->gen
>= 8 || brw
->is_baytrail
)
649 case MESA_FORMAT_ETC1_RGB8
:
650 return MESA_FORMAT_R8G8B8X8_UNORM
;
651 case MESA_FORMAT_ETC2_RGB8
:
652 return MESA_FORMAT_R8G8B8X8_UNORM
;
653 case MESA_FORMAT_ETC2_SRGB8
:
654 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
655 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
656 return MESA_FORMAT_B8G8R8A8_SRGB
;
657 case MESA_FORMAT_ETC2_RGBA8_EAC
:
658 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
659 return MESA_FORMAT_R8G8B8A8_UNORM
;
660 case MESA_FORMAT_ETC2_R11_EAC
:
661 return MESA_FORMAT_R_UNORM16
;
662 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
663 return MESA_FORMAT_R_SNORM16
;
664 case MESA_FORMAT_ETC2_RG11_EAC
:
665 return MESA_FORMAT_R16G16_UNORM
;
666 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
667 return MESA_FORMAT_R16G16_SNORM
;
669 /* Non ETC1 / ETC2 format */
674 /** \brief Assert that the level and layer are valid for the miptree. */
676 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
684 assert(level
>= mt
->first_level
);
685 assert(level
<= mt
->last_level
);
687 if (mt
->surf
.size
> 0)
688 assert(layer
< (mt
->surf
.dim
== ISL_SURF_DIM_3D
?
689 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
690 mt
->surf
.phys_level0_sa
.array_len
));
692 assert(layer
< mt
->level
[level
].depth
);
695 static enum isl_aux_state
**
696 create_aux_state_map(struct intel_mipmap_tree
*mt
,
697 enum isl_aux_state initial
)
699 const uint32_t levels
= mt
->last_level
+ 1;
701 uint32_t total_slices
= 0;
702 for (uint32_t level
= 0; level
< levels
; level
++)
703 total_slices
+= mt
->level
[level
].depth
;
705 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
707 /* We're going to allocate a single chunk of data for both the per-level
708 * reference array and the arrays of aux_state. This makes cleanup
709 * significantly easier.
711 const size_t total_size
= per_level_array_size
+
712 total_slices
* sizeof(enum isl_aux_state
);
713 void *data
= malloc(total_size
);
717 enum isl_aux_state
**per_level_arr
= data
;
718 enum isl_aux_state
*s
= data
+ per_level_array_size
;
719 for (uint32_t level
= 0; level
< levels
; level
++) {
720 per_level_arr
[level
] = s
;
721 for (uint32_t a
= 0; a
< mt
->level
[level
].depth
; a
++)
724 assert((void *)s
== data
+ total_size
);
726 return per_level_arr
;
730 free_aux_state_map(enum isl_aux_state
**state
)
735 static struct intel_mipmap_tree
*
736 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
737 unsigned first_level
, unsigned last_level
,
738 unsigned width0
, unsigned height0
, unsigned depth0
,
739 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
740 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
741 unsigned row_pitch
, struct brw_bo
*bo
)
743 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
747 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
755 if (target
== GL_TEXTURE_CUBE_MAP
||
756 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
757 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
759 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
761 _mesa_enum_to_string(target
),
762 _mesa_get_format_name(format
),
763 num_samples
, width0
, height0
, depth0
,
764 first_level
, last_level
, mt
);
766 struct isl_surf_init_info init_info
= {
767 .dim
= get_isl_surf_dim(target
),
768 .format
= translate_tex_format(brw
, format
, false),
771 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
772 .levels
= last_level
- first_level
+ 1,
773 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
774 .samples
= MAX2(num_samples
, 1),
775 .row_pitch
= row_pitch
,
776 .usage
= isl_usage_flags
,
777 .tiling_flags
= tiling_flags
,
780 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
783 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
786 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
788 isl_tiling_to_bufmgr_tiling(
790 mt
->surf
.row_pitch
, alloc_flags
);
797 mt
->first_level
= first_level
;
798 mt
->last_level
= last_level
;
801 mt
->aux_state
= NULL
;
806 intel_miptree_release(&mt
);
810 static struct intel_mipmap_tree
*
811 miptree_create(struct brw_context
*brw
,
820 uint32_t layout_flags
)
822 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
823 return make_surface(brw
, target
, format
, first_level
, last_level
,
824 width0
, height0
, depth0
, num_samples
,
826 ISL_SURF_USAGE_STENCIL_BIT
|
827 ISL_SURF_USAGE_TEXTURE_BIT
,
828 BO_ALLOC_FOR_RENDER
, 0, NULL
);
830 struct intel_mipmap_tree
*mt
;
831 mesa_format tex_format
= format
;
832 mesa_format etc_format
= MESA_FORMAT_NONE
;
833 uint32_t alloc_flags
= 0;
835 format
= intel_lower_compressed_format(brw
, format
);
837 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
839 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
840 mt
= intel_miptree_create_layout(brw
, target
, format
,
841 first_level
, last_level
, width0
,
842 height0
, depth0
, num_samples
,
847 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
848 mt
->tiling
= I915_TILING_Y
;
850 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
851 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
853 mt
->etc_format
= etc_format
;
855 if (format
== MESA_FORMAT_S_UINT8
) {
856 /* Align to size of W tile, 64x64. */
857 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
858 ALIGN(mt
->total_width
, 64),
859 ALIGN(mt
->total_height
, 64),
860 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
863 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
864 mt
->total_width
, mt
->total_height
,
865 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
869 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
870 mt
->bo
->cache_coherent
= false;
872 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
873 intel_miptree_choose_aux_usage(brw
, mt
);
878 struct intel_mipmap_tree
*
879 intel_miptree_create(struct brw_context
*brw
,
888 uint32_t layout_flags
)
890 struct intel_mipmap_tree
*mt
= miptree_create(
892 first_level
, last_level
,
893 width0
, height0
, depth0
, num_samples
,
898 /* If the BO is too large to fit in the aperture, we need to use the
899 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
900 * handle Y-tiling, so we need to fall back to X.
902 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
903 mt
->tiling
== I915_TILING_Y
) {
904 const uint32_t alloc_flags
=
905 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
906 BO_ALLOC_FOR_RENDER
: 0;
907 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
908 mt
->total_width
, mt
->total_height
);
910 mt
->tiling
= I915_TILING_X
;
911 brw_bo_unreference(mt
->bo
);
912 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
913 mt
->total_width
, mt
->total_height
, mt
->cpp
,
914 mt
->tiling
, &mt
->pitch
, alloc_flags
);
920 intel_miptree_release(&mt
);
924 if (!intel_miptree_alloc_aux(brw
, mt
)) {
925 intel_miptree_release(&mt
);
932 struct intel_mipmap_tree
*
933 intel_miptree_create_for_bo(struct brw_context
*brw
,
941 uint32_t layout_flags
)
943 struct intel_mipmap_tree
*mt
;
944 uint32_t tiling
, swizzle
;
945 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
947 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
) {
948 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
949 0, 0, width
, height
, depth
, 1,
951 ISL_SURF_USAGE_STENCIL_BIT
|
952 ISL_SURF_USAGE_TEXTURE_BIT
,
953 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
957 assert(bo
->size
>= mt
->surf
.size
);
959 brw_bo_reference(bo
);
963 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
965 /* Nothing will be able to use this miptree with the BO if the offset isn't
968 if (tiling
!= I915_TILING_NONE
)
969 assert(offset
% 4096 == 0);
971 /* miptrees can't handle negative pitch. If you need flipping of images,
972 * that's outside of the scope of the mt.
976 /* The BO already has a tiling format and we shouldn't confuse the lower
977 * layers by making it try to find a tiling format again.
979 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
980 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
982 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
983 mt
= intel_miptree_create_layout(brw
, target
, format
,
985 width
, height
, depth
, 0,
990 brw_bo_reference(bo
);
996 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
997 intel_miptree_choose_aux_usage(brw
, mt
);
1002 static struct intel_mipmap_tree
*
1003 miptree_create_for_planar_image(struct brw_context
*brw
,
1004 __DRIimage
*image
, GLenum target
)
1006 struct intel_image_format
*f
= image
->planar_format
;
1007 struct intel_mipmap_tree
*planar_mt
= NULL
;
1009 for (int i
= 0; i
< f
->nplanes
; i
++) {
1010 const int index
= f
->planes
[i
].buffer_index
;
1011 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
1012 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
1013 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
1014 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
1016 /* Disable creation of the texture's aux buffers because the driver
1017 * exposes no EGL API to manage them. That is, there is no API for
1018 * resolving the aux buffer's content to the main buffer nor for
1019 * invalidating the aux buffer's content.
1021 struct intel_mipmap_tree
*mt
=
1022 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1023 image
->offsets
[index
],
1025 image
->strides
[index
],
1026 MIPTREE_LAYOUT_DISABLE_AUX
);
1030 mt
->target
= target
;
1035 planar_mt
->plane
[i
- 1] = mt
;
1041 struct intel_mipmap_tree
*
1042 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
1043 __DRIimage
*image
, GLenum target
,
1044 enum isl_colorspace colorspace
,
1045 bool is_winsys_image
)
1047 if (image
->planar_format
&& image
->planar_format
->nplanes
> 0) {
1048 assert(colorspace
== ISL_COLORSPACE_NONE
||
1049 colorspace
== ISL_COLORSPACE_YUV
);
1050 return miptree_create_for_planar_image(brw
, image
, target
);
1053 mesa_format format
= image
->format
;
1054 switch (colorspace
) {
1055 case ISL_COLORSPACE_NONE
:
1056 /* Keep the image format unmodified */
1059 case ISL_COLORSPACE_LINEAR
:
1060 format
=_mesa_get_srgb_format_linear(format
);
1063 case ISL_COLORSPACE_SRGB
:
1064 format
=_mesa_get_linear_format_srgb(format
);
1068 unreachable("Inalid colorspace for non-planar image");
1071 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1072 /* The texture storage paths in core Mesa detect if the driver does not
1073 * support the user-requested format, and then searches for a
1074 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1075 * do the fallbacks here for important formats.
1077 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1078 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1079 * the Chrome OS compositor consumes as dma_buf EGLImages.
1081 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1084 if (!brw
->ctx
.TextureFormatSupported
[format
])
1087 /* If this image comes in from a window system, we have different
1088 * requirements than if it comes in via an EGL import operation. Window
1089 * system images can use any form of auxiliary compression we wish because
1090 * they get "flushed" before being handed off to the window system and we
1091 * have the opportunity to do resolves. Window system buffers also may be
1092 * used for scanout so we need to flag that appropriately.
1094 const uint32_t mt_layout_flags
=
1095 is_winsys_image
? MIPTREE_LAYOUT_FOR_SCANOUT
: MIPTREE_LAYOUT_DISABLE_AUX
;
1097 /* Disable creation of the texture's aux buffers because the driver exposes
1098 * no EGL API to manage them. That is, there is no API for resolving the aux
1099 * buffer's content to the main buffer nor for invalidating the aux buffer's
1102 struct intel_mipmap_tree
*mt
=
1103 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1104 image
->offset
, image
->width
, image
->height
, 1,
1105 image
->pitch
, mt_layout_flags
);
1109 mt
->target
= target
;
1110 mt
->level
[0].level_x
= image
->tile_x
;
1111 mt
->level
[0].level_y
= image
->tile_y
;
1112 mt
->level
[0].slice
[0].x_offset
= image
->tile_x
;
1113 mt
->level
[0].slice
[0].y_offset
= image
->tile_y
;
1115 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1116 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1117 * trouble resolving back to destination image due to alignment issues.
1119 if (!brw
->has_surface_tile_offset
) {
1120 uint32_t draw_x
, draw_y
;
1121 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1123 if (draw_x
!= 0 || draw_y
!= 0) {
1124 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1125 intel_miptree_release(&mt
);
1130 if (!intel_miptree_alloc_aux(brw
, mt
)) {
1131 intel_miptree_release(&mt
);
1139 * For a singlesample renderbuffer, this simply wraps the given BO with a
1142 * For a multisample renderbuffer, this wraps the window system's
1143 * (singlesample) BO with a singlesample miptree attached to the
1144 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1145 * that will contain the actual rendering (which is lazily resolved to
1146 * irb->singlesample_mt).
1149 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1150 struct intel_renderbuffer
*irb
,
1151 struct intel_mipmap_tree
*singlesample_mt
,
1152 uint32_t width
, uint32_t height
,
1155 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1156 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1157 mesa_format format
= rb
->Format
;
1158 int num_samples
= rb
->NumSamples
;
1160 /* Only the front and back buffers, which are color buffers, are allocated
1161 * through the image loader.
1163 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1164 _mesa_get_format_base_format(format
) == GL_RGBA
);
1166 assert(singlesample_mt
);
1168 if (num_samples
== 0) {
1169 intel_miptree_release(&irb
->mt
);
1170 irb
->mt
= singlesample_mt
;
1172 assert(!irb
->singlesample_mt
);
1174 intel_miptree_release(&irb
->singlesample_mt
);
1175 irb
->singlesample_mt
= singlesample_mt
;
1178 irb
->mt
->logical_width0
!= width
||
1179 irb
->mt
->logical_height0
!= height
) {
1180 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1185 if (!multisample_mt
)
1188 irb
->need_downsample
= false;
1189 intel_miptree_release(&irb
->mt
);
1190 irb
->mt
= multisample_mt
;
1196 intel_miptree_release(&irb
->mt
);
1200 struct intel_mipmap_tree
*
1201 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1205 uint32_t num_samples
)
1207 struct intel_mipmap_tree
*mt
;
1209 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1210 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1211 MIPTREE_LAYOUT_TILING_ANY
|
1212 MIPTREE_LAYOUT_FOR_SCANOUT
;
1214 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1215 width
, height
, depth
, num_samples
,
1223 intel_miptree_release(&mt
);
1228 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1229 struct intel_mipmap_tree
*src
)
1234 intel_miptree_release(dst
);
1238 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1245 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1247 if (aux_buf
== NULL
)
1250 brw_bo_unreference(aux_buf
->bo
);
1256 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1261 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1262 if (--(*mt
)->refcount
<= 0) {
1265 DBG("%s deleting %p\n", __func__
, *mt
);
1267 brw_bo_unreference((*mt
)->bo
);
1268 intel_miptree_release(&(*mt
)->stencil_mt
);
1269 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1270 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1271 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1272 free_aux_state_map((*mt
)->aux_state
);
1274 intel_miptree_release(&(*mt
)->plane
[0]);
1275 intel_miptree_release(&(*mt
)->plane
[1]);
1277 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1278 free((*mt
)->level
[i
].slice
);
1288 intel_get_image_dims(struct gl_texture_image
*image
,
1289 int *width
, int *height
, int *depth
)
1291 switch (image
->TexObject
->Target
) {
1292 case GL_TEXTURE_1D_ARRAY
:
1293 /* For a 1D Array texture the OpenGL API will treat the image height as
1294 * the number of array slices. For Intel hardware, we treat the 1D array
1295 * as a 2D Array with a height of 1. So, here we want to swap image
1298 assert(image
->Depth
== 1);
1299 *width
= image
->Width
;
1301 *depth
= image
->Height
;
1303 case GL_TEXTURE_CUBE_MAP
:
1304 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1305 * though we really have 6 slices.
1307 assert(image
->Depth
== 1);
1308 *width
= image
->Width
;
1309 *height
= image
->Height
;
1313 *width
= image
->Width
;
1314 *height
= image
->Height
;
1315 *depth
= image
->Depth
;
1321 * Can the image be pulled into a unified mipmap tree? This mirrors
1322 * the completeness test in a lot of ways.
1324 * Not sure whether I want to pass gl_texture_image here.
1327 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1328 struct gl_texture_image
*image
)
1330 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1331 GLuint level
= intelImage
->base
.Base
.Level
;
1332 int width
, height
, depth
;
1334 /* glTexImage* choose the texture object based on the target passed in, and
1335 * objects can't change targets over their lifetimes, so this should be
1338 assert(image
->TexObject
->Target
== mt
->target
);
1340 mesa_format mt_format
= mt
->format
;
1341 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1342 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1343 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1344 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1345 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1346 mt_format
= mt
->etc_format
;
1348 if (image
->TexFormat
!= mt_format
)
1351 intel_get_image_dims(image
, &width
, &height
, &depth
);
1353 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1356 if (mt
->surf
.size
> 0) {
1357 if (level
>= mt
->surf
.levels
)
1360 const unsigned level_depth
=
1361 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1362 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1363 mt
->surf
.logical_level0_px
.array_len
;
1365 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1366 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1367 depth
== level_depth
&&
1368 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1371 int level_depth
= mt
->level
[level
].depth
;
1372 if (mt
->num_samples
> 1) {
1373 switch (mt
->msaa_layout
) {
1374 case INTEL_MSAA_LAYOUT_NONE
:
1375 case INTEL_MSAA_LAYOUT_IMS
:
1377 case INTEL_MSAA_LAYOUT_UMS
:
1378 case INTEL_MSAA_LAYOUT_CMS
:
1379 level_depth
/= mt
->num_samples
;
1384 /* Test image dimensions against the base level image adjusted for
1385 * minification. This will also catch images not present in the
1386 * tree, changed targets, etc.
1388 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1389 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1390 depth
!= level_depth
) {
1394 if (image
->NumSamples
!= mt
->num_samples
)
1402 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1404 GLuint x
, GLuint y
, GLuint d
)
1406 mt
->level
[level
].depth
= d
;
1407 mt
->level
[level
].level_x
= x
;
1408 mt
->level
[level
].level_y
= y
;
1410 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1413 assert(mt
->level
[level
].slice
);
1415 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1416 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1421 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1422 GLuint level
, GLuint img
,
1425 if (img
== 0 && level
== 0)
1426 assert(x
== 0 && y
== 0);
1428 assert(img
< mt
->level
[level
].depth
);
1430 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1431 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1433 DBG("%s level %d img %d pos %d,%d\n",
1434 __func__
, level
, img
,
1435 mt
->level
[level
].slice
[img
].x_offset
,
1436 mt
->level
[level
].slice
[img
].y_offset
);
1440 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1441 GLuint level
, GLuint slice
,
1442 GLuint
*x
, GLuint
*y
)
1444 if (mt
->surf
.size
> 0) {
1445 uint32_t x_offset_sa
, y_offset_sa
;
1447 /* Given level is relative to level zero while the miptree may be
1448 * represent just a subset of all levels starting from 'first_level'.
1450 assert(level
>= mt
->first_level
);
1451 level
-= mt
->first_level
;
1453 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1454 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1455 isl_surf_get_image_offset_sa(&mt
->surf
, level
, slice
, z
,
1456 &x_offset_sa
, &y_offset_sa
);
1463 assert(slice
< mt
->level
[level
].depth
);
1465 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1466 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1471 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1472 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1473 * and tile_h is set to 1.
1476 intel_get_tile_dims(uint32_t tiling
, uint32_t cpp
,
1477 uint32_t *tile_w
, uint32_t *tile_h
)
1488 case I915_TILING_NONE
:
1493 unreachable("not reached");
1499 * This function computes masks that may be used to select the bits of the X
1500 * and Y coordinates that indicate the offset within a tile. If the BO is
1501 * untiled, the masks are set to 0.
1504 intel_get_tile_masks(uint32_t tiling
, uint32_t cpp
,
1505 uint32_t *mask_x
, uint32_t *mask_y
)
1507 uint32_t tile_w_bytes
, tile_h
;
1509 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1511 *mask_x
= tile_w_bytes
/ cpp
- 1;
1512 *mask_y
= tile_h
- 1;
1516 * Compute the offset (in bytes) from the start of the BO to the given x
1517 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1518 * multiples of the tile size.
1521 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1522 uint32_t x
, uint32_t y
)
1525 uint32_t pitch
= mt
->pitch
;
1526 uint32_t tiling
= mt
->tiling
;
1530 unreachable("not reached");
1531 case I915_TILING_NONE
:
1532 return y
* pitch
+ x
* cpp
;
1534 assert((x
% (512 / cpp
)) == 0);
1535 assert((y
% 8) == 0);
1536 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1538 assert((x
% (128 / cpp
)) == 0);
1539 assert((y
% 32) == 0);
1540 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1545 * Rendering with tiled buffers requires that the base address of the buffer
1546 * be aligned to a page boundary. For renderbuffers, and sometimes with
1547 * textures, we may want the surface to point at a texture image level that
1548 * isn't at a page boundary.
1550 * This function returns an appropriately-aligned base offset
1551 * according to the tiling restrictions, plus any required x/y offset
1555 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1556 GLuint level
, GLuint slice
,
1561 uint32_t mask_x
, mask_y
;
1563 intel_get_tile_masks(mt
->tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1564 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1566 *tile_x
= x
& mask_x
;
1567 *tile_y
= y
& mask_y
;
1569 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1573 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1574 struct intel_mipmap_tree
*src_mt
,
1575 unsigned src_level
, unsigned src_layer
,
1576 struct intel_mipmap_tree
*dst_mt
,
1577 unsigned dst_level
, unsigned dst_layer
,
1578 unsigned width
, unsigned height
)
1581 ptrdiff_t src_stride
, dst_stride
;
1582 const unsigned cpp
= dst_mt
->surf
.size
> 0 ?
1583 (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8) : dst_mt
->cpp
;
1585 intel_miptree_map(brw
, src_mt
,
1586 src_level
, src_layer
,
1589 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1592 intel_miptree_map(brw
, dst_mt
,
1593 dst_level
, dst_layer
,
1596 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1600 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1601 _mesa_get_format_name(src_mt
->format
),
1602 src_mt
, src
, src_stride
,
1603 _mesa_get_format_name(dst_mt
->format
),
1604 dst_mt
, dst
, dst_stride
,
1607 int row_size
= cpp
* width
;
1608 if (src_stride
== row_size
&&
1609 dst_stride
== row_size
) {
1610 memcpy(dst
, src
, row_size
* height
);
1612 for (int i
= 0; i
< height
; i
++) {
1613 memcpy(dst
, src
, row_size
);
1619 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1620 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1622 /* Don't forget to copy the stencil data over, too. We could have skipped
1623 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1624 * shuffling the two data sources in/out of temporary storage instead of
1625 * the direct mapping we get this way.
1627 if (dst_mt
->stencil_mt
) {
1628 assert(src_mt
->stencil_mt
);
1629 intel_miptree_copy_slice_sw(brw
,
1630 src_mt
->stencil_mt
, src_level
, src_layer
,
1631 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1637 intel_miptree_copy_slice(struct brw_context
*brw
,
1638 struct intel_mipmap_tree
*src_mt
,
1639 unsigned src_level
, unsigned src_layer
,
1640 struct intel_mipmap_tree
*dst_mt
,
1641 unsigned dst_level
, unsigned dst_layer
)
1644 mesa_format format
= src_mt
->format
;
1645 uint32_t width
, height
;
1647 if (src_mt
->surf
.size
> 0) {
1648 width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1649 src_level
- src_mt
->first_level
);
1650 height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1651 src_level
- src_mt
->first_level
);
1653 if (src_mt
->surf
.dim
== ISL_SURF_DIM_3D
)
1654 assert(src_layer
< minify(src_mt
->surf
.phys_level0_sa
.depth
,
1655 src_level
- src_mt
->first_level
));
1657 assert(src_layer
< src_mt
->surf
.phys_level0_sa
.array_len
);
1659 width
= minify(src_mt
->physical_width0
,
1660 src_level
- src_mt
->first_level
);
1661 height
= minify(src_mt
->physical_height0
,
1662 src_level
- src_mt
->first_level
);
1663 assert(src_layer
< src_mt
->level
[src_level
].depth
);
1666 assert(src_mt
->format
== dst_mt
->format
);
1668 if (dst_mt
->compressed
) {
1670 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1671 height
= ALIGN_NPOT(height
, j
) / j
;
1672 width
= ALIGN_NPOT(width
, i
) / i
;
1675 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1676 * below won't apply since we can't do the depth's Y tiling or the
1677 * stencil's W tiling in the blitter.
1679 if (src_mt
->stencil_mt
) {
1680 intel_miptree_copy_slice_sw(brw
,
1681 src_mt
, src_level
, src_layer
,
1682 dst_mt
, dst_level
, dst_layer
,
1687 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1688 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1690 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1693 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1694 _mesa_get_format_name(src_mt
->format
),
1695 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1696 _mesa_get_format_name(dst_mt
->format
),
1697 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1700 if (!intel_miptree_blit(brw
,
1701 src_mt
, src_level
, src_layer
, 0, 0, false,
1702 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1703 width
, height
, GL_COPY
)) {
1704 perf_debug("miptree validate blit for %s failed\n",
1705 _mesa_get_format_name(format
));
1707 intel_miptree_copy_slice_sw(brw
,
1708 src_mt
, src_level
, src_layer
,
1709 dst_mt
, dst_level
, dst_layer
,
1715 * Copies the image's current data to the given miptree, and associates that
1716 * miptree with the image.
1718 * If \c invalidate is true, then the actual image data does not need to be
1719 * copied, but the image still needs to be associated to the new miptree (this
1720 * is set to true if we're about to clear the image).
1723 intel_miptree_copy_teximage(struct brw_context
*brw
,
1724 struct intel_texture_image
*intelImage
,
1725 struct intel_mipmap_tree
*dst_mt
,
1728 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1729 struct intel_texture_object
*intel_obj
=
1730 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1731 int level
= intelImage
->base
.Base
.Level
;
1732 const unsigned face
= intelImage
->base
.Base
.Face
;
1733 unsigned start_layer
, end_layer
;
1735 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1737 assert(intelImage
->base
.Base
.Height
);
1739 end_layer
= intelImage
->base
.Base
.Height
- 1;
1740 } else if (face
> 0) {
1744 assert(intelImage
->base
.Base
.Depth
);
1746 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1750 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1751 intel_miptree_copy_slice(brw
,
1757 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1758 intel_obj
->needs_validate
= true;
1762 intel_miptree_init_mcs(struct brw_context
*brw
,
1763 struct intel_mipmap_tree
*mt
,
1766 assert(mt
->mcs_buf
!= NULL
);
1768 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1770 * When MCS buffer is enabled and bound to MSRT, it is required that it
1771 * is cleared prior to any rendering.
1773 * Since we don't use the MCS buffer for any purpose other than rendering,
1774 * it makes sense to just clear it immediately upon allocation.
1776 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1778 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1779 if (unlikely(map
== NULL
)) {
1780 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1781 brw_bo_unreference(mt
->mcs_buf
->bo
);
1786 memset(data
, init_value
, mt
->mcs_buf
->size
);
1787 brw_bo_unmap(mt
->mcs_buf
->bo
);
1790 static struct intel_miptree_aux_buffer
*
1791 intel_alloc_aux_buffer(struct brw_context
*brw
,
1793 const struct isl_surf
*aux_surf
,
1794 uint32_t alloc_flags
,
1795 struct intel_mipmap_tree
*mt
)
1797 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1801 buf
->size
= aux_surf
->size
;
1802 buf
->pitch
= aux_surf
->row_pitch
;
1803 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1805 /* ISL has stricter set of alignment rules then the drm allocator.
1806 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1807 * trying to recalculate based on different format block sizes.
1809 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1810 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1816 buf
->surf
= *aux_surf
;
1822 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1823 struct intel_mipmap_tree
*mt
,
1826 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1827 assert(mt
->mcs_buf
== NULL
);
1828 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1830 /* Multisampled miptrees are only supported for single level. */
1831 assert(mt
->first_level
== 0);
1832 enum isl_aux_state
**aux_state
=
1833 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1837 struct isl_surf temp_main_surf
;
1838 struct isl_surf temp_mcs_surf
;
1840 /* Create first an ISL presentation for the main color surface and let ISL
1841 * calculate equivalent MCS surface against it.
1843 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1844 MAYBE_UNUSED
bool ok
=
1845 isl_surf_get_mcs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_mcs_surf
);
1848 /* Buffer needs to be initialised requiring the buffer to be immediately
1849 * mapped to cpu space for writing. Therefore do not use the gpu access
1850 * flag which can cause an unnecessary delay if the backing pages happened
1851 * to be just used by the GPU.
1853 const uint32_t alloc_flags
= 0;
1854 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1855 &temp_mcs_surf
, alloc_flags
, mt
);
1861 mt
->aux_state
= aux_state
;
1863 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1869 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1870 struct intel_mipmap_tree
*mt
)
1872 assert(mt
->mcs_buf
== NULL
);
1873 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1874 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1876 struct isl_surf temp_main_surf
;
1877 struct isl_surf temp_ccs_surf
;
1879 /* Create first an ISL presentation for the main color surface and let ISL
1880 * calculate equivalent CCS surface against it.
1882 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1883 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
,
1887 assert(temp_ccs_surf
.size
&&
1888 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1890 enum isl_aux_state
**aux_state
=
1891 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1895 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1896 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1898 * "If Software wants to enable Color Compression without Fast clear,
1899 * Software needs to initialize MCS with zeros."
1901 * A CCS value of 0 indicates that the corresponding block is in the
1902 * pass-through state which is what we want.
1904 * For CCS_D, on the other hand, we don't care as we're about to perform a
1905 * fast-clear operation. In that case, being hot in caches more useful.
1907 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1908 BO_ALLOC_ZEROED
: BO_ALLOC_FOR_RENDER
;
1909 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1910 &temp_ccs_surf
, alloc_flags
, mt
);
1916 mt
->aux_state
= aux_state
;
1922 * Helper for intel_miptree_alloc_hiz() that sets
1923 * \c mt->level[level].has_hiz. Return true if and only if
1924 * \c has_hiz was set.
1927 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1928 struct intel_mipmap_tree
*mt
,
1931 assert(mt
->hiz_buf
);
1933 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1934 uint32_t width
= minify(mt
->physical_width0
, level
);
1935 uint32_t height
= minify(mt
->physical_height0
, level
);
1937 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1938 * and the height is 4 aligned. This allows our HiZ support
1939 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1940 * we can grow the width & height to allow the HiZ op to
1941 * force the proper size alignments.
1943 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1944 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1949 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1950 mt
->level
[level
].has_hiz
= true;
1955 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1956 struct intel_mipmap_tree
*mt
)
1958 assert(mt
->hiz_buf
== NULL
);
1959 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1961 enum isl_aux_state
**aux_state
=
1962 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1966 struct isl_surf temp_main_surf
;
1967 struct isl_surf temp_hiz_surf
;
1969 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1970 MAYBE_UNUSED
bool ok
=
1971 isl_surf_get_hiz_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_hiz_surf
);
1974 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
1975 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1976 &temp_hiz_surf
, alloc_flags
, mt
);
1983 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1984 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1986 mt
->aux_state
= aux_state
;
1993 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1995 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1996 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1997 * compress clear color so we wait until an actual fast-clear to allocate it.
2000 intel_miptree_alloc_aux(struct brw_context
*brw
,
2001 struct intel_mipmap_tree
*mt
)
2003 switch (mt
->aux_usage
) {
2004 case ISL_AUX_USAGE_NONE
:
2007 case ISL_AUX_USAGE_HIZ
:
2008 assert(!_mesa_is_format_color_format(mt
->format
));
2009 if (!intel_miptree_alloc_hiz(brw
, mt
))
2013 case ISL_AUX_USAGE_MCS
:
2014 assert(_mesa_is_format_color_format(mt
->format
));
2015 assert(mt
->num_samples
> 1);
2016 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->num_samples
))
2020 case ISL_AUX_USAGE_CCS_D
:
2021 /* Since CCS_D can only compress clear color so we wait until an actual
2022 * fast-clear to allocate it.
2026 case ISL_AUX_USAGE_CCS_E
:
2027 assert(_mesa_is_format_color_format(mt
->format
));
2028 assert(mt
->num_samples
<= 1);
2029 if (!intel_miptree_alloc_ccs(brw
, mt
))
2034 unreachable("Invalid aux usage");
2039 * Can the miptree sample using the hiz buffer?
2042 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
2043 struct intel_mipmap_tree
*mt
)
2045 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
2046 * so keep things conservative for now and never enable it unless we're SKL+.
2056 /* It seems the hardware won't fallback to the depth buffer if some of the
2057 * mipmap levels aren't available in the HiZ buffer. So we need all levels
2058 * of the texture to be HiZ enabled.
2060 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
2061 if (!intel_miptree_level_has_hiz(mt
, level
))
2065 /* If compressed multisampling is enabled, then we use it for the auxiliary
2068 * From the BDW PRM (Volume 2d: Command Reference: Structures
2069 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
2071 * "If this field is set to AUX_HIZ, Number of Multisamples must be
2072 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
2074 * There is no such blurb for 1D textures, but there is sufficient evidence
2075 * that this is broken on SKL+.
2077 return (mt
->num_samples
<= 1 &&
2078 mt
->target
!= GL_TEXTURE_3D
&&
2079 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
2083 * Does the miptree slice have hiz enabled?
2086 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
2088 intel_miptree_check_level_layer(mt
, level
, 0);
2089 return mt
->level
[level
].has_hiz
;
2093 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2094 unsigned start_level
, unsigned num_levels
,
2095 unsigned start_layer
, unsigned num_layers
)
2097 assert(_mesa_is_format_color_format(mt
->format
));
2102 /* Clamp the level range to fit the miptree */
2103 assert(start_level
+ num_levels
>= start_level
);
2104 const uint32_t last_level
=
2105 MIN2(mt
->last_level
, start_level
+ num_levels
- 1);
2106 start_level
= MAX2(mt
->first_level
, start_level
);
2107 num_levels
= last_level
- start_level
+ 1;
2109 for (uint32_t level
= start_level
; level
<= last_level
; level
++) {
2110 const uint32_t level_layers
= MIN2(num_layers
, mt
->level
[level
].depth
);
2111 for (unsigned a
= 0; a
< level_layers
; a
++) {
2112 enum isl_aux_state aux_state
=
2113 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2114 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2115 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2124 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2125 const struct intel_mipmap_tree
*mt
,
2126 unsigned level
, unsigned layer
)
2132 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2133 assert(brw
->gen
>= 8 ||
2134 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2136 /* Compression of arrayed msaa surfaces is supported. */
2137 if (mt
->num_samples
> 1)
2140 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2141 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
2147 static enum blorp_fast_clear_op
2148 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2149 bool ccs_supported
, bool fast_clear_supported
)
2151 assert(ccs_supported
== fast_clear_supported
);
2153 switch (aux_state
) {
2154 case ISL_AUX_STATE_CLEAR
:
2155 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2157 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2159 return BLORP_FAST_CLEAR_OP_NONE
;
2161 case ISL_AUX_STATE_PASS_THROUGH
:
2162 return BLORP_FAST_CLEAR_OP_NONE
;
2164 case ISL_AUX_STATE_RESOLVED
:
2165 case ISL_AUX_STATE_AUX_INVALID
:
2166 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2170 unreachable("Invalid aux state for CCS_D");
2173 static enum blorp_fast_clear_op
2174 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2175 bool ccs_supported
, bool fast_clear_supported
)
2177 switch (aux_state
) {
2178 case ISL_AUX_STATE_CLEAR
:
2179 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2181 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2182 else if (!fast_clear_supported
)
2183 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2185 return BLORP_FAST_CLEAR_OP_NONE
;
2187 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2189 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2191 return BLORP_FAST_CLEAR_OP_NONE
;
2193 case ISL_AUX_STATE_PASS_THROUGH
:
2194 return BLORP_FAST_CLEAR_OP_NONE
;
2196 case ISL_AUX_STATE_RESOLVED
:
2197 case ISL_AUX_STATE_AUX_INVALID
:
2201 unreachable("Invalid aux state for CCS_E");
2205 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2206 struct intel_mipmap_tree
*mt
,
2207 uint32_t level
, uint32_t layer
,
2209 bool fast_clear_supported
)
2211 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2213 enum blorp_fast_clear_op resolve_op
;
2214 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2215 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_supported
,
2216 fast_clear_supported
);
2218 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2219 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_supported
,
2220 fast_clear_supported
);
2223 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2224 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2225 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2227 switch (resolve_op
) {
2228 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2229 /* The CCS full resolve operation destroys the CCS and sets it to the
2230 * pass-through state. (You can also think of this as being both a
2231 * resolve and an ambiguate in one operation.)
2233 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2234 ISL_AUX_STATE_PASS_THROUGH
);
2237 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2238 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2239 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2243 unreachable("Invalid resolve op");
2249 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2250 struct intel_mipmap_tree
*mt
,
2251 uint32_t level
, uint32_t layer
,
2252 bool written_with_ccs
)
2254 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2256 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2257 switch (aux_state
) {
2258 case ISL_AUX_STATE_CLEAR
:
2259 assert(written_with_ccs
);
2260 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2261 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2264 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2265 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2266 assert(written_with_ccs
);
2267 break; /* Nothing to do */
2269 case ISL_AUX_STATE_PASS_THROUGH
:
2270 if (written_with_ccs
) {
2271 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2272 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2278 case ISL_AUX_STATE_RESOLVED
:
2279 case ISL_AUX_STATE_AUX_INVALID
:
2280 unreachable("Invalid aux state for CCS_E");
2283 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2284 /* CCS_D is a bit simpler */
2285 switch (aux_state
) {
2286 case ISL_AUX_STATE_CLEAR
:
2287 assert(written_with_ccs
);
2288 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2289 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2292 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2293 assert(written_with_ccs
);
2294 break; /* Nothing to do */
2296 case ISL_AUX_STATE_PASS_THROUGH
:
2300 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2301 case ISL_AUX_STATE_RESOLVED
:
2302 case ISL_AUX_STATE_AUX_INVALID
:
2303 unreachable("Invalid aux state for CCS_D");
2309 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2310 struct intel_mipmap_tree
*mt
,
2311 uint32_t level
, uint32_t layer
,
2312 bool written_with_aux
)
2314 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2315 case ISL_AUX_STATE_CLEAR
:
2316 assert(written_with_aux
);
2317 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2318 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2321 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2322 assert(written_with_aux
);
2323 break; /* Nothing to do */
2325 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2326 case ISL_AUX_STATE_RESOLVED
:
2327 case ISL_AUX_STATE_PASS_THROUGH
:
2328 case ISL_AUX_STATE_AUX_INVALID
:
2329 unreachable("Invalid aux state for MCS");
2334 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2335 struct intel_mipmap_tree
*mt
,
2336 uint32_t level
, uint32_t layer
,
2337 bool hiz_supported
, bool fast_clear_supported
)
2339 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2340 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2341 case ISL_AUX_STATE_CLEAR
:
2342 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2343 if (!hiz_supported
|| !fast_clear_supported
)
2344 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2347 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2349 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2352 case ISL_AUX_STATE_PASS_THROUGH
:
2353 case ISL_AUX_STATE_RESOLVED
:
2356 case ISL_AUX_STATE_AUX_INVALID
:
2358 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2362 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2363 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2366 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2367 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2368 ISL_AUX_STATE_RESOLVED
);
2371 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2372 /* The HiZ resolve operation is actually an ambiguate */
2373 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2374 ISL_AUX_STATE_PASS_THROUGH
);
2378 unreachable("Invalid HiZ op");
2384 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2385 struct intel_mipmap_tree
*mt
,
2386 uint32_t level
, uint32_t layer
,
2387 bool written_with_hiz
)
2389 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2390 case ISL_AUX_STATE_CLEAR
:
2391 assert(written_with_hiz
);
2392 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2393 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2396 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2397 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2398 assert(written_with_hiz
);
2399 break; /* Nothing to do */
2401 case ISL_AUX_STATE_RESOLVED
:
2402 if (written_with_hiz
) {
2403 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2404 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2406 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2407 ISL_AUX_STATE_AUX_INVALID
);
2411 case ISL_AUX_STATE_PASS_THROUGH
:
2412 if (written_with_hiz
) {
2413 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2414 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2418 case ISL_AUX_STATE_AUX_INVALID
:
2419 assert(!written_with_hiz
);
2424 static inline uint32_t
2425 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
2426 uint32_t start_level
, uint32_t num_levels
)
2428 assert(start_level
>= mt
->first_level
);
2429 assert(start_level
<= mt
->last_level
);
2431 if (num_levels
== INTEL_REMAINING_LAYERS
)
2432 num_levels
= mt
->last_level
- start_level
+ 1;
2433 /* Check for overflow */
2434 assert(start_level
+ num_levels
>= start_level
);
2435 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2440 static inline uint32_t
2441 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2442 uint32_t start_layer
, uint32_t num_layers
)
2444 assert(level
<= mt
->last_level
);
2445 uint32_t total_num_layers
;
2447 if (mt
->surf
.size
> 0)
2448 total_num_layers
= mt
->surf
.dim
== ISL_SURF_DIM_3D
?
2449 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
2450 mt
->surf
.phys_level0_sa
.array_len
;
2452 total_num_layers
= mt
->level
[level
].depth
;
2454 assert(start_layer
< total_num_layers
);
2455 if (num_layers
== INTEL_REMAINING_LAYERS
)
2456 num_layers
= total_num_layers
- start_layer
;
2457 /* Check for overflow */
2458 assert(start_layer
+ num_layers
>= start_layer
);
2459 assert(start_layer
+ num_layers
<= total_num_layers
);
2465 intel_miptree_prepare_access(struct brw_context
*brw
,
2466 struct intel_mipmap_tree
*mt
,
2467 uint32_t start_level
, uint32_t num_levels
,
2468 uint32_t start_layer
, uint32_t num_layers
,
2469 bool aux_supported
, bool fast_clear_supported
)
2471 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2473 if (_mesa_is_format_color_format(mt
->format
)) {
2477 if (mt
->num_samples
> 1) {
2478 /* Nothing to do for MSAA */
2479 assert(aux_supported
&& fast_clear_supported
);
2481 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2482 const uint32_t level
= start_level
+ l
;
2483 const uint32_t level_layers
=
2484 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2485 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2486 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2487 start_layer
+ a
, aux_supported
,
2488 fast_clear_supported
);
2492 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2493 /* Nothing to do for stencil */
2498 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2499 const uint32_t level
= start_level
+ l
;
2500 if (!intel_miptree_level_has_hiz(mt
, level
))
2503 const uint32_t level_layers
=
2504 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2505 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2506 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2508 fast_clear_supported
);
2515 intel_miptree_finish_write(struct brw_context
*brw
,
2516 struct intel_mipmap_tree
*mt
, uint32_t level
,
2517 uint32_t start_layer
, uint32_t num_layers
,
2518 bool written_with_aux
)
2520 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2522 if (_mesa_is_format_color_format(mt
->format
)) {
2526 if (mt
->num_samples
> 1) {
2527 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2528 intel_miptree_finish_mcs_write(brw
, mt
, level
, start_layer
+ a
,
2532 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2533 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2537 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2538 /* Nothing to do for stencil */
2540 if (!intel_miptree_level_has_hiz(mt
, level
))
2543 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2544 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2551 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2552 uint32_t level
, uint32_t layer
)
2554 intel_miptree_check_level_layer(mt
, level
, layer
);
2556 if (_mesa_is_format_color_format(mt
->format
)) {
2557 assert(mt
->mcs_buf
!= NULL
);
2558 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2559 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2560 unreachable("Cannot get aux state for stencil");
2562 assert(intel_miptree_level_has_hiz(mt
, level
));
2565 return mt
->aux_state
[level
][layer
];
2569 intel_miptree_set_aux_state(struct brw_context
*brw
,
2570 struct intel_mipmap_tree
*mt
, uint32_t level
,
2571 uint32_t start_layer
, uint32_t num_layers
,
2572 enum isl_aux_state aux_state
)
2574 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2576 if (_mesa_is_format_color_format(mt
->format
)) {
2577 assert(mt
->mcs_buf
!= NULL
);
2578 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2579 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2580 unreachable("Cannot get aux state for stencil");
2582 assert(intel_miptree_level_has_hiz(mt
, level
));
2585 for (unsigned a
= 0; a
< num_layers
; a
++)
2586 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2589 /* On Gen9 color buffers may be compressed by the hardware (lossless
2590 * compression). There are, however, format restrictions and care needs to be
2591 * taken that the sampler engine is capable for re-interpreting a buffer with
2592 * format different the buffer was originally written with.
2594 * For example, SRGB formats are not compressible and the sampler engine isn't
2595 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2596 * color buffer needs to be resolved so that the sampling surface can be
2597 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2601 can_texture_with_ccs(struct brw_context
*brw
,
2602 struct intel_mipmap_tree
*mt
,
2603 mesa_format view_format
)
2605 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2608 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2609 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2611 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2612 isl_mt_format
, isl_view_format
)) {
2613 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2614 _mesa_get_format_name(view_format
),
2615 _mesa_get_format_name(mt
->format
));
2623 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2624 struct intel_mipmap_tree
*mt
,
2625 mesa_format view_format
,
2626 uint32_t start_level
, uint32_t num_levels
,
2627 uint32_t start_layer
, uint32_t num_layers
,
2628 bool *aux_supported_out
)
2630 bool aux_supported
, clear_supported
;
2631 if (_mesa_is_format_color_format(mt
->format
)) {
2632 if (mt
->num_samples
> 1) {
2633 aux_supported
= clear_supported
= true;
2635 aux_supported
= can_texture_with_ccs(brw
, mt
, view_format
);
2637 /* Clear color is specified as ints or floats and the conversion is
2638 * done by the sampler. If we have a texture view, we would have to
2639 * perform the clear color conversion manually. Just disable clear
2642 clear_supported
= aux_supported
&& (mt
->format
== view_format
);
2644 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2645 aux_supported
= clear_supported
= false;
2647 aux_supported
= clear_supported
= intel_miptree_sample_with_hiz(brw
, mt
);
2650 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2651 start_layer
, num_layers
,
2652 aux_supported
, clear_supported
);
2653 if (aux_supported_out
)
2654 *aux_supported_out
= aux_supported
;
2658 intel_miptree_prepare_texture(struct brw_context
*brw
,
2659 struct intel_mipmap_tree
*mt
,
2660 mesa_format view_format
,
2661 bool *aux_supported_out
)
2663 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2664 0, INTEL_REMAINING_LEVELS
,
2665 0, INTEL_REMAINING_LAYERS
,
2670 intel_miptree_prepare_image(struct brw_context
*brw
,
2671 struct intel_mipmap_tree
*mt
)
2673 /* The data port doesn't understand any compression */
2674 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2675 0, INTEL_REMAINING_LAYERS
, false, false);
2679 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2680 struct intel_mipmap_tree
*mt
, uint32_t level
,
2681 uint32_t start_layer
, uint32_t num_layers
)
2683 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2684 start_layer
, num_layers
, NULL
);
2688 intel_miptree_prepare_render(struct brw_context
*brw
,
2689 struct intel_mipmap_tree
*mt
, uint32_t level
,
2690 uint32_t start_layer
, uint32_t layer_count
,
2693 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2694 * the single-sampled color renderbuffers because the CCS buffer isn't
2695 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2696 * enabled because otherwise the surface state will be programmed with
2697 * the linear equivalent format anyway.
2699 if (brw
->gen
== 9 && srgb_enabled
&& mt
->num_samples
<= 1 &&
2700 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2702 /* Lossless compression is not supported for SRGB formats, it
2703 * should be impossible to get here with such surfaces.
2705 assert(mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
);
2706 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2712 intel_miptree_finish_render(struct brw_context
*brw
,
2713 struct intel_mipmap_tree
*mt
, uint32_t level
,
2714 uint32_t start_layer
, uint32_t layer_count
)
2716 assert(_mesa_is_format_color_format(mt
->format
));
2717 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2718 mt
->mcs_buf
!= NULL
);
2722 intel_miptree_prepare_depth(struct brw_context
*brw
,
2723 struct intel_mipmap_tree
*mt
, uint32_t level
,
2724 uint32_t start_layer
, uint32_t layer_count
)
2726 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2727 mt
->hiz_buf
!= NULL
, mt
->hiz_buf
!= NULL
);
2731 intel_miptree_finish_depth(struct brw_context
*brw
,
2732 struct intel_mipmap_tree
*mt
, uint32_t level
,
2733 uint32_t start_layer
, uint32_t layer_count
,
2736 if (depth_written
) {
2737 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2738 mt
->hiz_buf
!= NULL
);
2743 * Make it possible to share the BO backing the given miptree with another
2744 * process or another miptree.
2746 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2747 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2748 * ensure that no MCS buffer gets allocated in the future.
2750 * HiZ is similarly unsafe with shared buffers.
2753 intel_miptree_make_shareable(struct brw_context
*brw
,
2754 struct intel_mipmap_tree
*mt
)
2756 /* MCS buffers are also used for multisample buffers, but we can't resolve
2757 * away a multisample MCS buffer because it's an integral part of how the
2758 * pixel data is stored. Fortunately this code path should never be
2759 * reached for multisample buffers.
2761 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
|| mt
->num_samples
<= 1);
2763 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2764 0, INTEL_REMAINING_LAYERS
, false, false);
2767 brw_bo_unreference(mt
->mcs_buf
->bo
);
2771 /* Any pending MCS/CCS operations are no longer needed. Trying to
2772 * execute any will likely crash due to the missing aux buffer. So let's
2773 * delete all pending ops.
2775 free(mt
->aux_state
);
2776 mt
->aux_state
= NULL
;
2780 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2783 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2784 mt
->level
[l
].has_hiz
= false;
2787 /* Any pending HiZ operations are no longer needed. Trying to execute
2788 * any will likely crash due to the missing aux buffer. So let's delete
2791 free(mt
->aux_state
);
2792 mt
->aux_state
= NULL
;
2795 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2800 * \brief Get pointer offset into stencil buffer.
2802 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2803 * must decode the tile's layout in software.
2806 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2808 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2810 * Even though the returned offset is always positive, the return type is
2812 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2813 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2816 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2818 uint32_t tile_size
= 4096;
2819 uint32_t tile_width
= 64;
2820 uint32_t tile_height
= 64;
2821 uint32_t row_size
= 64 * stride
;
2823 uint32_t tile_x
= x
/ tile_width
;
2824 uint32_t tile_y
= y
/ tile_height
;
2826 /* The byte's address relative to the tile's base addres. */
2827 uint32_t byte_x
= x
% tile_width
;
2828 uint32_t byte_y
= y
% tile_height
;
2830 uintptr_t u
= tile_y
* row_size
2831 + tile_x
* tile_size
2832 + 512 * (byte_x
/ 8)
2834 + 32 * ((byte_y
/ 4) % 2)
2835 + 16 * ((byte_x
/ 4) % 2)
2836 + 8 * ((byte_y
/ 2) % 2)
2837 + 4 * ((byte_x
/ 2) % 2)
2842 /* adjust for bit6 swizzling */
2843 if (((byte_x
/ 8) % 2) == 1) {
2844 if (((byte_y
/ 8) % 2) == 0) {
2856 intel_miptree_updownsample(struct brw_context
*brw
,
2857 struct intel_mipmap_tree
*src
,
2858 struct intel_mipmap_tree
*dst
)
2860 unsigned src_w
, src_h
, dst_w
, dst_h
;
2862 if (src
->surf
.size
> 0) {
2863 src_w
= src
->surf
.logical_level0_px
.width
;
2864 src_h
= src
->surf
.logical_level0_px
.height
;
2866 src_w
= src
->logical_width0
;
2867 src_h
= src
->logical_height0
;
2870 if (dst
->surf
.size
> 0) {
2871 dst_w
= dst
->surf
.logical_level0_px
.width
;
2872 dst_h
= dst
->surf
.logical_level0_px
.height
;
2874 dst_w
= dst
->logical_width0
;
2875 dst_h
= dst
->logical_height0
;
2878 brw_blorp_blit_miptrees(brw
,
2879 src
, 0 /* level */, 0 /* layer */,
2880 src
->format
, SWIZZLE_XYZW
,
2881 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2884 GL_NEAREST
, false, false /*mirror x, y*/,
2887 if (src
->stencil_mt
) {
2888 if (src
->stencil_mt
->surf
.size
> 0) {
2889 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2890 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2892 src_w
= src
->stencil_mt
->logical_width0
;
2893 src_h
= src
->stencil_mt
->logical_height0
;
2896 if (dst
->stencil_mt
->surf
.size
> 0) {
2897 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2898 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2900 dst_w
= dst
->stencil_mt
->logical_width0
;
2901 dst_h
= dst
->stencil_mt
->logical_height0
;
2904 brw_blorp_blit_miptrees(brw
,
2905 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2906 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2907 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2908 dst
->stencil_mt
->format
,
2911 GL_NEAREST
, false, false /*mirror x, y*/,
2912 false, false /* decode/encode srgb */);
2917 intel_update_r8stencil(struct brw_context
*brw
,
2918 struct intel_mipmap_tree
*mt
)
2920 assert(brw
->gen
>= 7);
2921 struct intel_mipmap_tree
*src
=
2922 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2923 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2926 if (!mt
->r8stencil_mt
) {
2927 const uint32_t r8stencil_flags
=
2928 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2929 MIPTREE_LAYOUT_DISABLE_AUX
;
2930 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2931 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2933 MESA_FORMAT_R_UINT8
,
2936 src
->logical_width0
,
2937 src
->logical_height0
,
2938 src
->logical_depth0
,
2941 assert(mt
->r8stencil_mt
);
2944 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2946 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2947 const unsigned depth
= src
->level
[level
].depth
;
2949 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2950 brw_blorp_copy_miptrees(brw
,
2954 minify(src
->logical_width0
, level
),
2955 minify(src
->logical_height0
, level
));
2959 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2960 src
->r8stencil_needs_update
= false;
2964 intel_miptree_map_raw(struct brw_context
*brw
,
2965 struct intel_mipmap_tree
*mt
,
2968 struct brw_bo
*bo
= mt
->bo
;
2970 if (brw_batch_references(&brw
->batch
, bo
))
2971 intel_batchbuffer_flush(brw
);
2973 return brw_bo_map(brw
, bo
, mode
);
2977 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2979 brw_bo_unmap(mt
->bo
);
2983 intel_miptree_map_gtt(struct brw_context
*brw
,
2984 struct intel_mipmap_tree
*mt
,
2985 struct intel_miptree_map
*map
,
2986 unsigned int level
, unsigned int slice
)
2988 unsigned int bw
, bh
;
2990 unsigned int image_x
, image_y
;
2991 intptr_t x
= map
->x
;
2992 intptr_t y
= map
->y
;
2994 /* For compressed formats, the stride is the number of bytes per
2995 * row of blocks. intel_miptree_get_image_offset() already does
2998 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2999 assert(y
% bh
== 0);
3000 assert(x
% bw
== 0);
3004 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3011 /* Note that in the case of cube maps, the caller must have passed the
3012 * slice number referencing the face.
3014 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3018 map
->stride
= mt
->pitch
;
3019 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3022 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3023 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3024 map
->x
, map
->y
, map
->w
, map
->h
,
3025 mt
, _mesa_get_format_name(mt
->format
),
3026 x
, y
, map
->ptr
, map
->stride
);
3030 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3032 intel_miptree_unmap_raw(mt
);
3036 intel_miptree_map_blit(struct brw_context
*brw
,
3037 struct intel_mipmap_tree
*mt
,
3038 struct intel_miptree_map
*map
,
3039 unsigned int level
, unsigned int slice
)
3041 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3042 /* first_level */ 0,
3046 MIPTREE_LAYOUT_TILING_NONE
);
3048 if (!map
->linear_mt
) {
3049 fprintf(stderr
, "Failed to allocate blit temporary\n");
3052 map
->stride
= map
->linear_mt
->pitch
;
3054 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3055 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3056 * invalidate is set, since we'll be writing the whole rectangle from our
3057 * temporary buffer back out.
3059 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3060 if (!intel_miptree_copy(brw
,
3061 mt
, level
, slice
, map
->x
, map
->y
,
3062 map
->linear_mt
, 0, 0, 0, 0,
3064 fprintf(stderr
, "Failed to blit\n");
3069 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3071 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3072 map
->x
, map
->y
, map
->w
, map
->h
,
3073 mt
, _mesa_get_format_name(mt
->format
),
3074 level
, slice
, map
->ptr
, map
->stride
);
3079 intel_miptree_release(&map
->linear_mt
);
3085 intel_miptree_unmap_blit(struct brw_context
*brw
,
3086 struct intel_mipmap_tree
*mt
,
3087 struct intel_miptree_map
*map
,
3091 struct gl_context
*ctx
= &brw
->ctx
;
3093 intel_miptree_unmap_raw(map
->linear_mt
);
3095 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3096 bool ok
= intel_miptree_copy(brw
,
3097 map
->linear_mt
, 0, 0, 0, 0,
3098 mt
, level
, slice
, map
->x
, map
->y
,
3100 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3103 intel_miptree_release(&map
->linear_mt
);
3107 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3109 #if defined(USE_SSE41)
3111 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3112 struct intel_mipmap_tree
*mt
,
3113 struct intel_miptree_map
*map
,
3114 unsigned int level
, unsigned int slice
)
3116 assert(map
->mode
& GL_MAP_READ_BIT
);
3117 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3119 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3120 map
->x
, map
->y
, map
->w
, map
->h
,
3121 mt
, _mesa_get_format_name(mt
->format
),
3122 level
, slice
, map
->ptr
, map
->stride
);
3124 /* Map the original image */
3127 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3131 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3137 src
+= image_y
* mt
->pitch
;
3138 src
+= image_x
* mt
->cpp
;
3140 /* Due to the pixel offsets for the particular image being mapped, our
3141 * src pointer may not be 16-byte aligned. However, if the pitch is
3142 * divisible by 16, then the amount by which it's misaligned will remain
3143 * consistent from row to row.
3145 assert((mt
->pitch
% 16) == 0);
3146 const int misalignment
= ((uintptr_t) src
) & 15;
3148 /* Create an untiled temporary buffer for the mapping. */
3149 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3151 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3153 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3154 /* Offset the destination so it has the same misalignment as src. */
3155 map
->ptr
= map
->buffer
+ misalignment
;
3157 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3159 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3160 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3161 void *src_ptr
= src
+ y
* mt
->pitch
;
3163 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3166 intel_miptree_unmap_raw(mt
);
3170 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3171 struct intel_mipmap_tree
*mt
,
3172 struct intel_miptree_map
*map
,
3176 _mesa_align_free(map
->buffer
);
3183 intel_miptree_map_s8(struct brw_context
*brw
,
3184 struct intel_mipmap_tree
*mt
,
3185 struct intel_miptree_map
*map
,
3186 unsigned int level
, unsigned int slice
)
3188 map
->stride
= map
->w
;
3189 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3193 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3194 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3195 * invalidate is set, since we'll be writing the whole rectangle from our
3196 * temporary buffer back out.
3198 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3199 /* ISL uses a stencil pitch value that is expected by hardware whereas
3200 * traditional miptree uses half of that. Below the value gets supplied
3201 * to intel_offset_S8() which expects the legacy interpretation.
3203 const unsigned pitch
= mt
->surf
.size
> 0 ?
3204 mt
->surf
.row_pitch
/ 2 : mt
->pitch
;
3205 uint8_t *untiled_s8_map
= map
->ptr
;
3206 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3207 unsigned int image_x
, image_y
;
3209 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3211 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3212 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3213 ptrdiff_t offset
= intel_offset_S8(pitch
,
3214 x
+ image_x
+ map
->x
,
3215 y
+ image_y
+ map
->y
,
3216 brw
->has_swizzling
);
3217 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3221 intel_miptree_unmap_raw(mt
);
3223 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3224 map
->x
, map
->y
, map
->w
, map
->h
,
3225 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3227 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3228 map
->x
, map
->y
, map
->w
, map
->h
,
3229 mt
, map
->ptr
, map
->stride
);
3234 intel_miptree_unmap_s8(struct brw_context
*brw
,
3235 struct intel_mipmap_tree
*mt
,
3236 struct intel_miptree_map
*map
,
3240 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3241 /* ISL uses a stencil pitch value that is expected by hardware whereas
3242 * traditional miptree uses half of that. Below the value gets supplied
3243 * to intel_offset_S8() which expects the legacy interpretation.
3245 const unsigned pitch
= mt
->surf
.size
> 0 ?
3246 mt
->surf
.row_pitch
/ 2: mt
->pitch
;
3247 unsigned int image_x
, image_y
;
3248 uint8_t *untiled_s8_map
= map
->ptr
;
3249 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3251 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3253 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3254 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3255 ptrdiff_t offset
= intel_offset_S8(pitch
,
3256 image_x
+ x
+ map
->x
,
3257 image_y
+ y
+ map
->y
,
3258 brw
->has_swizzling
);
3259 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3263 intel_miptree_unmap_raw(mt
);
3270 intel_miptree_map_etc(struct brw_context
*brw
,
3271 struct intel_mipmap_tree
*mt
,
3272 struct intel_miptree_map
*map
,
3276 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3277 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3278 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3281 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3282 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3284 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3285 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3286 map
->w
, map
->h
, 1));
3287 map
->ptr
= map
->buffer
;
3291 intel_miptree_unmap_etc(struct brw_context
*brw
,
3292 struct intel_mipmap_tree
*mt
,
3293 struct intel_miptree_map
*map
,
3299 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3304 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3305 + image_y
* mt
->pitch
3306 + image_x
* mt
->cpp
;
3308 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3309 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
3310 map
->ptr
, map
->stride
,
3313 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
3314 map
->ptr
, map
->stride
,
3315 map
->w
, map
->h
, mt
->etc_format
);
3317 intel_miptree_unmap_raw(mt
);
3322 * Mapping function for packed depth/stencil miptrees backed by real separate
3323 * miptrees for depth and stencil.
3325 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3326 * separate from the depth buffer. Yet at the GL API level, we have to expose
3327 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3328 * be able to map that memory for texture storage and glReadPixels-type
3329 * operations. We give Mesa core that access by mallocing a temporary and
3330 * copying the data between the actual backing store and the temporary.
3333 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3334 struct intel_mipmap_tree
*mt
,
3335 struct intel_miptree_map
*map
,
3336 unsigned int level
, unsigned int slice
)
3338 struct intel_mipmap_tree
*z_mt
= mt
;
3339 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3340 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3341 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3343 map
->stride
= map
->w
* packed_bpp
;
3344 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3348 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3349 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3350 * invalidate is set, since we'll be writing the whole rectangle from our
3351 * temporary buffer back out.
3353 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3354 /* ISL uses a stencil pitch value that is expected by hardware whereas
3355 * traditional miptree uses half of that. Below the value gets supplied
3356 * to intel_offset_S8() which expects the legacy interpretation.
3358 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3359 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3360 uint32_t *packed_map
= map
->ptr
;
3361 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3362 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3363 unsigned int s_image_x
, s_image_y
;
3364 unsigned int z_image_x
, z_image_y
;
3366 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3367 &s_image_x
, &s_image_y
);
3368 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3369 &z_image_x
, &z_image_y
);
3371 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3372 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3373 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3374 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3377 brw
->has_swizzling
);
3378 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3380 (map_x
+ z_image_x
));
3381 uint8_t s
= s_map
[s_offset
];
3382 uint32_t z
= z_map
[z_offset
];
3384 if (map_z32f_x24s8
) {
3385 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3386 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3388 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3393 intel_miptree_unmap_raw(s_mt
);
3394 intel_miptree_unmap_raw(z_mt
);
3396 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3398 map
->x
, map
->y
, map
->w
, map
->h
,
3399 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3400 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3401 map
->ptr
, map
->stride
);
3403 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3404 map
->x
, map
->y
, map
->w
, map
->h
,
3405 mt
, map
->ptr
, map
->stride
);
3410 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3411 struct intel_mipmap_tree
*mt
,
3412 struct intel_miptree_map
*map
,
3416 struct intel_mipmap_tree
*z_mt
= mt
;
3417 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3418 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3420 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3421 /* ISL uses a stencil pitch value that is expected by hardware whereas
3422 * traditional miptree uses half of that. Below the value gets supplied
3423 * to intel_offset_S8() which expects the legacy interpretation.
3425 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3426 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3427 uint32_t *packed_map
= map
->ptr
;
3428 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3429 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3430 unsigned int s_image_x
, s_image_y
;
3431 unsigned int z_image_x
, z_image_y
;
3433 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3434 &s_image_x
, &s_image_y
);
3435 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3436 &z_image_x
, &z_image_y
);
3438 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3439 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3440 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3441 x
+ s_image_x
+ map
->x
,
3442 y
+ s_image_y
+ map
->y
,
3443 brw
->has_swizzling
);
3444 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3446 (x
+ z_image_x
+ map
->x
));
3448 if (map_z32f_x24s8
) {
3449 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3450 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3452 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3453 s_map
[s_offset
] = packed
>> 24;
3454 z_map
[z_offset
] = packed
;
3459 intel_miptree_unmap_raw(s_mt
);
3460 intel_miptree_unmap_raw(z_mt
);
3462 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3464 map
->x
, map
->y
, map
->w
, map
->h
,
3465 z_mt
, _mesa_get_format_name(z_mt
->format
),
3466 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3467 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3468 map
->ptr
, map
->stride
);
3475 * Create and attach a map to the miptree at (level, slice). Return the
3478 static struct intel_miptree_map
*
3479 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3488 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3493 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3494 mt
->level
[level
].slice
[slice
].map
= map
;
3506 * Release the map at (level, slice).
3509 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3513 struct intel_miptree_map
**map
;
3515 map
= &mt
->level
[level
].slice
[slice
].map
;
3521 can_blit_slice(struct intel_mipmap_tree
*mt
,
3522 unsigned int level
, unsigned int slice
)
3524 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3525 if (mt
->pitch
>= 32768)
3532 use_intel_mipree_map_blit(struct brw_context
*brw
,
3533 struct intel_mipmap_tree
*mt
,
3539 /* It's probably not worth swapping to the blit ring because of
3540 * all the overhead involved.
3542 !(mode
& GL_MAP_WRITE_BIT
) &&
3544 (mt
->tiling
== I915_TILING_X
||
3545 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3546 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
3547 /* Fast copy blit on skl+ supports all tiling formats. */
3549 can_blit_slice(mt
, level
, slice
))
3552 if (mt
->tiling
!= I915_TILING_NONE
&&
3553 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3554 assert(can_blit_slice(mt
, level
, slice
));
3562 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3563 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3564 * arithmetic overflow.
3566 * If you call this function and use \a out_stride, then you're doing pointer
3567 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3568 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3569 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3570 * which usually have type uint32_t or GLuint.
3573 intel_miptree_map(struct brw_context
*brw
,
3574 struct intel_mipmap_tree
*mt
,
3583 ptrdiff_t *out_stride
)
3585 struct intel_miptree_map
*map
;
3587 assert(mt
->num_samples
<= 1);
3589 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3596 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3597 map
->mode
& GL_MAP_WRITE_BIT
);
3599 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3600 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3601 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3602 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3603 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3604 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3605 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3606 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3607 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3608 #if defined(USE_SSE41)
3609 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3610 !mt
->compressed
&& cpu_has_sse4_1
&&
3611 (mt
->pitch
% 16 == 0)) {
3612 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3615 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3618 *out_ptr
= map
->ptr
;
3619 *out_stride
= map
->stride
;
3621 if (map
->ptr
== NULL
)
3622 intel_miptree_release_map(mt
, level
, slice
);
3626 intel_miptree_unmap(struct brw_context
*brw
,
3627 struct intel_mipmap_tree
*mt
,
3631 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3633 assert(mt
->num_samples
<= 1);
3638 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3639 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3641 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3642 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3643 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3644 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3645 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3646 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3647 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3648 } else if (map
->linear_mt
) {
3649 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3650 #if defined(USE_SSE41)
3651 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3652 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3655 intel_miptree_unmap_gtt(mt
);
3658 intel_miptree_release_map(mt
, level
, slice
);
3662 get_isl_surf_dim(GLenum target
)
3666 case GL_TEXTURE_1D_ARRAY
:
3667 return ISL_SURF_DIM_1D
;
3670 case GL_TEXTURE_2D_ARRAY
:
3671 case GL_TEXTURE_RECTANGLE
:
3672 case GL_TEXTURE_CUBE_MAP
:
3673 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3674 case GL_TEXTURE_2D_MULTISAMPLE
:
3675 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3676 case GL_TEXTURE_EXTERNAL_OES
:
3677 return ISL_SURF_DIM_2D
;
3680 return ISL_SURF_DIM_3D
;
3683 unreachable("Invalid texture target");
3687 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3688 GLenum target
, enum miptree_array_layout array_layout
)
3690 if (array_layout
== GEN6_HIZ_STENCIL
)
3691 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
3695 case GL_TEXTURE_1D_ARRAY
:
3696 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3697 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3700 case GL_TEXTURE_2D_ARRAY
:
3701 case GL_TEXTURE_RECTANGLE
:
3702 case GL_TEXTURE_2D_MULTISAMPLE
:
3703 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3704 case GL_TEXTURE_EXTERNAL_OES
:
3705 return ISL_DIM_LAYOUT_GEN4_2D
;
3707 case GL_TEXTURE_CUBE_MAP
:
3708 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3709 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3710 ISL_DIM_LAYOUT_GEN4_2D
);
3713 return (devinfo
->gen
>= 9 ?
3714 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3717 unreachable("Invalid texture target");
3721 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3723 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3724 return ISL_TILING_W
;
3726 switch (mt
->tiling
) {
3727 case I915_TILING_NONE
:
3728 return ISL_TILING_LINEAR
;
3730 return ISL_TILING_X
;
3732 return ISL_TILING_Y0
;
3734 unreachable("Invalid tiling mode");
3740 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3741 const struct intel_mipmap_tree
*mt
,
3742 struct isl_surf
*surf
)
3744 surf
->dim
= get_isl_surf_dim(mt
->target
);
3745 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3746 mt
->tiling
, mt
->target
,
3749 if (mt
->num_samples
> 1) {
3750 switch (mt
->msaa_layout
) {
3751 case INTEL_MSAA_LAYOUT_IMS
:
3752 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3754 case INTEL_MSAA_LAYOUT_UMS
:
3755 case INTEL_MSAA_LAYOUT_CMS
:
3756 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3759 unreachable("Invalid MSAA layout");
3762 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3765 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3767 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3768 /* The ISL definition of row_pitch matches the surface state pitch field
3769 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3770 * the factor of 2 for W-tiling in row_pitch.
3772 surf
->row_pitch
= 2 * mt
->pitch
;
3774 surf
->row_pitch
= mt
->pitch
;
3777 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3779 if (brw
->gen
>= 9) {
3780 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3781 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3782 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3784 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3785 * alignment in terms of surface elements like we want.
3787 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3790 /* On earlier gens it's stored in pixels. */
3792 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3793 surf
->image_alignment_el
=
3794 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3797 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3798 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3799 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3800 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3801 surf
->logical_level0_px
.array_len
= 1;
3803 surf
->logical_level0_px
.depth
= 1;
3804 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3807 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3808 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3809 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3810 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3811 surf
->phys_level0_sa
.array_len
= 1;
3813 surf
->phys_level0_sa
.depth
= 1;
3814 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3817 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3818 surf
->samples
= MAX2(mt
->num_samples
, 1);
3820 surf
->size
= 0; /* TODO */
3821 surf
->alignment
= 0; /* TODO */
3823 switch (surf
->dim_layout
) {
3824 case ISL_DIM_LAYOUT_GEN4_2D
:
3825 case ISL_DIM_LAYOUT_GEN4_3D
:
3826 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
3827 if (brw
->gen
>= 9) {
3828 surf
->array_pitch_el_rows
= mt
->qpitch
;
3831 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3832 assert(mt
->qpitch
% bh
== 0);
3833 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3836 case ISL_DIM_LAYOUT_GEN9_1D
:
3837 surf
->array_pitch_el_rows
= 1;
3841 switch (mt
->array_layout
) {
3842 case ALL_LOD_IN_EACH_SLICE
:
3843 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3845 case ALL_SLICES_AT_EACH_LOD
:
3846 case GEN6_HIZ_STENCIL
:
3847 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3850 unreachable("Invalid array layout");
3853 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3854 switch (base_format
) {
3855 case GL_DEPTH_COMPONENT
:
3856 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3858 case GL_STENCIL_INDEX
:
3859 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3861 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3863 case GL_DEPTH_STENCIL
:
3864 /* In this case we only texture from the depth part */
3865 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3866 ISL_SURF_USAGE_TEXTURE_BIT
;
3869 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3870 if (brw
->mesa_format_supports_render
[mt
->format
])
3871 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3875 if (_mesa_is_cube_map_texture(mt
->target
))
3876 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3880 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3881 const struct intel_mipmap_tree
*mt
)
3884 return ISL_AUX_USAGE_HIZ
;
3887 return ISL_AUX_USAGE_NONE
;
3889 return mt
->aux_usage
;