2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_image.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
,
55 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
58 intel_miptree_alloc_aux(struct brw_context
*brw
,
59 struct intel_mipmap_tree
*mt
);
62 intel_miptree_supports_mcs(struct brw_context
*brw
,
63 const struct intel_mipmap_tree
*mt
)
65 /* MCS compression only applies to multisampled miptrees */
66 if (mt
->surf
.samples
<= 1)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(mt
->format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
100 intel_tiling_supports_ccs(const struct brw_context
*brw
,
101 enum isl_tiling tiling
)
103 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
104 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
106 * - Support is limited to tiled render targets.
108 * Gen9 changes the restriction to Y-tile only.
111 return tiling
== ISL_TILING_Y0
;
112 else if (brw
->gen
>= 7)
113 return tiling
!= ISL_TILING_LINEAR
;
119 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
120 * can be used. This doesn't (and should not) inspect any of the properties of
123 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
124 * beneath the "Fast Color Clear" bullet (p326):
126 * - Support is for non-mip-mapped and non-array surface types only.
128 * And then later, on p327:
130 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
133 * From the Skylake documentation, it is made clear that X-tiling is no longer
136 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
140 intel_miptree_supports_ccs(struct brw_context
*brw
,
141 const struct intel_mipmap_tree
*mt
)
143 /* MCS support does not exist prior to Gen7 */
147 /* This function applies only to non-multisampled render targets. */
148 if (mt
->surf
.samples
> 1)
151 /* MCS is only supported for color buffers */
152 switch (_mesa_get_format_base_format(mt
->format
)) {
153 case GL_DEPTH_COMPONENT
:
154 case GL_DEPTH_STENCIL
:
155 case GL_STENCIL_INDEX
:
159 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
162 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
163 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
164 mt
->surf
.logical_level0_px
.depth
> 1;
167 /* Multisample surfaces with the CMS layout are not layered surfaces,
168 * yet still have physical_depth0 > 1. Assert that we don't
169 * accidentally reject a multisampled surface here. We should have
170 * rejected it earlier by explicitly checking the sample count.
172 assert(mt
->surf
.samples
== 1);
175 /* Handle the hardware restrictions...
177 * All GENs have the following restriction: "MCS buffer for non-MSRT is
178 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
180 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
181 * Non-MultiSampler Render Target Restrictions) Support is for
182 * non-mip-mapped and non-array surface types only.
184 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
185 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
186 * surfaces are supported with MCS buffer layout with these alignments in
187 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
189 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
190 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
191 * surfaces are supported with MCS buffer layout with these alignments in
192 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
194 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
197 /* There's no point in using an MCS buffer if the surface isn't in a
200 if (!brw
->mesa_format_supports_render
[mt
->format
])
207 intel_tiling_supports_hiz(const struct brw_context
*brw
,
208 enum isl_tiling tiling
)
213 return tiling
== ISL_TILING_Y0
;
217 intel_miptree_supports_hiz(const struct brw_context
*brw
,
218 const struct intel_mipmap_tree
*mt
)
223 switch (mt
->format
) {
224 case MESA_FORMAT_Z_FLOAT32
:
225 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
226 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
227 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
228 case MESA_FORMAT_Z_UNORM16
:
236 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
237 const struct intel_mipmap_tree
*mt
)
242 /* For now compression is only enabled for integer formats even though
243 * there exist supported floating point formats also. This is a heuristic
244 * decision based on current public benchmarks. In none of the cases these
245 * formats provided any improvement but a few cases were seen to regress.
246 * Hence these are left to to be enabled in the future when they are known
249 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
252 if (!intel_miptree_supports_ccs(brw
, mt
))
255 /* Many window system buffers are sRGB even if they are never rendered as
256 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
257 * surface is used as sRGB, we fall back to CCS_D.
259 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
260 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
261 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
265 * Determine depth format corresponding to a depth+stencil format,
266 * for separate stencil.
269 intel_depth_format_for_depthstencil_format(mesa_format format
) {
271 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
272 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
273 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
274 return MESA_FORMAT_Z_FLOAT32
;
281 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
282 unsigned depth0
, struct intel_mipmap_level
*table
)
284 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
286 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
288 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
289 if (!table
[level
].slice
)
296 for (unsigned level
= first_level
; level
<= last_level
; level
++)
297 free(table
[level
].slice
);
303 needs_separate_stencil(const struct brw_context
*brw
,
304 struct intel_mipmap_tree
*mt
,
307 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
310 if (brw
->must_use_separate_stencil
)
313 return brw
->has_separate_stencil
&&
314 intel_miptree_supports_hiz(brw
, mt
);
318 * Choose the aux usage for this miptree. This function must be called fairly
319 * late in the miptree create process after we have a tiling.
322 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
323 struct intel_mipmap_tree
*mt
)
325 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
327 if (intel_miptree_supports_mcs(brw
, mt
)) {
328 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
329 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
330 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
331 intel_miptree_supports_ccs(brw
, mt
)) {
332 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
333 intel_miptree_supports_ccs_e(brw
, mt
)) {
334 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
336 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
338 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
339 intel_miptree_supports_hiz(brw
, mt
)) {
340 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
343 /* We can do fast-clear on all auxiliary surface types that are
344 * allocated through the normal texture creation paths.
346 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
347 mt
->supports_fast_clear
= true;
352 * Choose an appropriate uncompressed format for a requested
353 * compressed format, if unsupported.
356 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
358 /* No need to lower ETC formats on these platforms,
359 * they are supported natively.
361 if (brw
->gen
>= 8 || brw
->is_baytrail
)
365 case MESA_FORMAT_ETC1_RGB8
:
366 return MESA_FORMAT_R8G8B8X8_UNORM
;
367 case MESA_FORMAT_ETC2_RGB8
:
368 return MESA_FORMAT_R8G8B8X8_UNORM
;
369 case MESA_FORMAT_ETC2_SRGB8
:
370 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
371 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
372 return MESA_FORMAT_B8G8R8A8_SRGB
;
373 case MESA_FORMAT_ETC2_RGBA8_EAC
:
374 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
375 return MESA_FORMAT_R8G8B8A8_UNORM
;
376 case MESA_FORMAT_ETC2_R11_EAC
:
377 return MESA_FORMAT_R_UNORM16
;
378 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
379 return MESA_FORMAT_R_SNORM16
;
380 case MESA_FORMAT_ETC2_RG11_EAC
:
381 return MESA_FORMAT_R16G16_UNORM
;
382 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
383 return MESA_FORMAT_R16G16_SNORM
;
385 /* Non ETC1 / ETC2 format */
391 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
393 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
394 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
396 return mt
->surf
.logical_level0_px
.array_len
;
400 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
402 /* In case of physical dimensions one needs to consider also the layout.
403 * See isl_calc_phys_level0_extent_sa().
405 if (surf
->dim
!= ISL_SURF_DIM_3D
)
406 return surf
->phys_level0_sa
.array_len
;
408 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
409 return minify(surf
->phys_level0_sa
.array_len
, level
);
411 return minify(surf
->phys_level0_sa
.depth
, level
);
414 /** \brief Assert that the level and layer are valid for the miptree. */
416 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
424 assert(level
>= mt
->first_level
);
425 assert(level
<= mt
->last_level
);
426 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
429 static enum isl_aux_state
**
430 create_aux_state_map(struct intel_mipmap_tree
*mt
,
431 enum isl_aux_state initial
)
433 const uint32_t levels
= mt
->last_level
+ 1;
435 uint32_t total_slices
= 0;
436 for (uint32_t level
= 0; level
< levels
; level
++)
437 total_slices
+= brw_get_num_logical_layers(mt
, level
);
439 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
441 /* We're going to allocate a single chunk of data for both the per-level
442 * reference array and the arrays of aux_state. This makes cleanup
443 * significantly easier.
445 const size_t total_size
= per_level_array_size
+
446 total_slices
* sizeof(enum isl_aux_state
);
447 void *data
= malloc(total_size
);
451 enum isl_aux_state
**per_level_arr
= data
;
452 enum isl_aux_state
*s
= data
+ per_level_array_size
;
453 for (uint32_t level
= 0; level
< levels
; level
++) {
454 per_level_arr
[level
] = s
;
455 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
456 for (uint32_t a
= 0; a
< level_layers
; a
++)
459 assert((void *)s
== data
+ total_size
);
461 return per_level_arr
;
465 free_aux_state_map(enum isl_aux_state
**state
)
471 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
472 enum isl_tiling tiling
, unsigned samples
)
477 if (tiling
== ISL_TILING_LINEAR
)
480 /* If the width is much smaller than a tile, don't bother tiling. */
484 if (ALIGN(row_pitch
, 512) >= 32768) {
485 perf_debug("row pitch %u too large to blit, falling back to untiled",
494 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
495 enum isl_tiling tiling
)
497 /* If the BO is too large to fit in the aperture, we need to use the
498 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
499 * handle Y-tiling, so we need to fall back to X.
501 if (brw
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
502 tiling
== ISL_TILING_Y0
)
508 static struct intel_mipmap_tree
*
509 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
510 unsigned first_level
, unsigned last_level
,
511 unsigned width0
, unsigned height0
, unsigned depth0
,
512 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
513 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
514 unsigned row_pitch
, struct brw_bo
*bo
)
516 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
520 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
528 if (target
== GL_TEXTURE_CUBE_MAP
||
529 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
530 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
532 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
534 _mesa_enum_to_string(target
),
535 _mesa_get_format_name(format
),
536 num_samples
, width0
, height0
, depth0
,
537 first_level
, last_level
, mt
);
539 struct isl_surf_init_info init_info
= {
540 .dim
= get_isl_surf_dim(target
),
541 .format
= translate_tex_format(brw
, format
, false),
544 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
545 .levels
= last_level
- first_level
+ 1,
546 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
547 .samples
= num_samples
,
548 .row_pitch
= row_pitch
,
549 .usage
= isl_usage_flags
,
550 .tiling_flags
= tiling_flags
,
553 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
556 /* In case caller doesn't specifically request Y-tiling (needed
557 * unconditionally for depth), check for corner cases needing special
560 if (tiling_flags
& ~ISL_TILING_Y0_BIT
) {
561 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
562 mt
->surf
.tiling
, mt
->surf
.samples
)) {
563 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
564 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
566 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
567 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
568 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
573 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
574 * the size may not be multiple of row_pitch.
575 * See isl_apply_surface_padding().
577 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
578 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
581 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
583 isl_tiling_to_i915_tiling(
585 mt
->surf
.row_pitch
, alloc_flags
);
592 mt
->first_level
= first_level
;
593 mt
->last_level
= last_level
;
596 mt
->aux_state
= NULL
;
597 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
598 mt
->compressed
= _mesa_is_format_compressed(format
);
603 intel_miptree_release(&mt
);
608 make_separate_stencil_surface(struct brw_context
*brw
,
609 struct intel_mipmap_tree
*mt
)
611 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
612 0, mt
->surf
.levels
- 1,
613 mt
->surf
.logical_level0_px
.width
,
614 mt
->surf
.logical_level0_px
.height
,
615 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
616 mt
->surf
.logical_level0_px
.depth
:
617 mt
->surf
.logical_level0_px
.array_len
,
618 mt
->surf
.samples
, ISL_TILING_W_BIT
,
619 ISL_SURF_USAGE_STENCIL_BIT
|
620 ISL_SURF_USAGE_TEXTURE_BIT
,
621 BO_ALLOC_FOR_RENDER
, 0, NULL
);
626 mt
->stencil_mt
->r8stencil_needs_update
= true;
631 static struct intel_mipmap_tree
*
632 miptree_create(struct brw_context
*brw
,
641 enum intel_miptree_create_flags flags
)
643 if (format
== MESA_FORMAT_S_UINT8
)
644 return make_surface(brw
, target
, format
, first_level
, last_level
,
645 width0
, height0
, depth0
, num_samples
,
647 ISL_SURF_USAGE_STENCIL_BIT
|
648 ISL_SURF_USAGE_TEXTURE_BIT
,
653 const GLenum base_format
= _mesa_get_format_base_format(format
);
654 if ((base_format
== GL_DEPTH_COMPONENT
||
655 base_format
== GL_DEPTH_STENCIL
) &&
656 !(flags
& MIPTREE_CREATE_LINEAR
)) {
657 /* Fix up the Z miptree format for how we're splitting out separate
658 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
660 const mesa_format depth_only_format
=
661 intel_depth_format_for_depthstencil_format(format
);
662 struct intel_mipmap_tree
*mt
= make_surface(
663 brw
, target
, brw
->gen
>= 6 ? depth_only_format
: format
,
664 first_level
, last_level
,
665 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
666 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
667 BO_ALLOC_FOR_RENDER
, 0, NULL
);
669 if (needs_separate_stencil(brw
, mt
, format
) &&
670 !make_separate_stencil_surface(brw
, mt
)) {
671 intel_miptree_release(&mt
);
675 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
676 intel_miptree_choose_aux_usage(brw
, mt
);
681 mesa_format tex_format
= format
;
682 mesa_format etc_format
= MESA_FORMAT_NONE
;
683 uint32_t alloc_flags
= 0;
685 format
= intel_lower_compressed_format(brw
, format
);
687 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
689 if (flags
& MIPTREE_CREATE_BUSY
)
690 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
692 isl_tiling_flags_t tiling_flags
= (flags
& MIPTREE_CREATE_LINEAR
) ?
693 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
695 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
697 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
699 struct intel_mipmap_tree
*mt
= make_surface(
701 first_level
, last_level
,
702 width0
, height0
, depth0
,
703 num_samples
, tiling_flags
,
704 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
705 ISL_SURF_USAGE_TEXTURE_BIT
,
706 alloc_flags
, 0, NULL
);
710 mt
->etc_format
= etc_format
;
712 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
713 intel_miptree_choose_aux_usage(brw
, mt
);
718 struct intel_mipmap_tree
*
719 intel_miptree_create(struct brw_context
*brw
,
728 enum intel_miptree_create_flags flags
)
730 assert(num_samples
> 0);
732 struct intel_mipmap_tree
*mt
= miptree_create(
734 first_level
, last_level
,
735 width0
, height0
, depth0
, num_samples
,
742 if (!intel_miptree_alloc_aux(brw
, mt
)) {
743 intel_miptree_release(&mt
);
750 struct intel_mipmap_tree
*
751 intel_miptree_create_for_bo(struct brw_context
*brw
,
759 enum intel_miptree_create_flags flags
)
761 struct intel_mipmap_tree
*mt
;
762 uint32_t tiling
, swizzle
;
763 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
764 const GLenum base_format
= _mesa_get_format_base_format(format
);
766 if ((base_format
== GL_DEPTH_COMPONENT
||
767 base_format
== GL_DEPTH_STENCIL
)) {
768 const mesa_format depth_only_format
=
769 intel_depth_format_for_depthstencil_format(format
);
770 mt
= make_surface(brw
, target
,
771 brw
->gen
>= 6 ? depth_only_format
: format
,
772 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
773 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
774 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
778 brw_bo_reference(bo
);
780 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
781 intel_miptree_choose_aux_usage(brw
, mt
);
784 } else if (format
== MESA_FORMAT_S_UINT8
) {
785 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
786 0, 0, width
, height
, depth
, 1,
788 ISL_SURF_USAGE_STENCIL_BIT
|
789 ISL_SURF_USAGE_TEXTURE_BIT
,
790 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
794 assert(bo
->size
>= mt
->surf
.size
);
796 brw_bo_reference(bo
);
800 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
802 /* Nothing will be able to use this miptree with the BO if the offset isn't
805 if (tiling
!= I915_TILING_NONE
)
806 assert(offset
% 4096 == 0);
808 /* miptrees can't handle negative pitch. If you need flipping of images,
809 * that's outside of the scope of the mt.
813 /* The BO already has a tiling format and we shouldn't confuse the lower
814 * layers by making it try to find a tiling format again.
816 assert((flags
& MIPTREE_CREATE_LINEAR
) == 0);
818 mt
= make_surface(brw
, target
, format
,
819 0, 0, width
, height
, depth
, 1,
820 1lu << isl_tiling_from_i915_tiling(tiling
),
821 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
822 ISL_SURF_USAGE_TEXTURE_BIT
,
827 brw_bo_reference(bo
);
831 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
832 intel_miptree_choose_aux_usage(brw
, mt
);
834 if (!intel_miptree_alloc_aux(brw
, mt
)) {
835 intel_miptree_release(&mt
);
843 static struct intel_mipmap_tree
*
844 miptree_create_for_planar_image(struct brw_context
*brw
,
845 __DRIimage
*image
, GLenum target
)
847 const struct intel_image_format
*f
= image
->planar_format
;
848 struct intel_mipmap_tree
*planar_mt
= NULL
;
850 for (int i
= 0; i
< f
->nplanes
; i
++) {
851 const int index
= f
->planes
[i
].buffer_index
;
852 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
853 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
854 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
855 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
857 /* Disable creation of the texture's aux buffers because the driver
858 * exposes no EGL API to manage them. That is, there is no API for
859 * resolving the aux buffer's content to the main buffer nor for
860 * invalidating the aux buffer's content.
862 struct intel_mipmap_tree
*mt
=
863 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
864 image
->offsets
[index
],
866 image
->strides
[index
],
867 MIPTREE_CREATE_NO_AUX
);
876 planar_mt
->plane
[i
- 1] = mt
;
882 struct intel_mipmap_tree
*
883 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
884 __DRIimage
*image
, GLenum target
,
885 enum isl_colorspace colorspace
,
886 bool is_winsys_image
)
888 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1) {
889 assert(colorspace
== ISL_COLORSPACE_NONE
||
890 colorspace
== ISL_COLORSPACE_YUV
);
891 return miptree_create_for_planar_image(brw
, image
, target
);
894 if (image
->planar_format
)
895 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
897 mesa_format format
= image
->format
;
898 switch (colorspace
) {
899 case ISL_COLORSPACE_NONE
:
900 /* Keep the image format unmodified */
903 case ISL_COLORSPACE_LINEAR
:
904 format
=_mesa_get_srgb_format_linear(format
);
907 case ISL_COLORSPACE_SRGB
:
908 format
=_mesa_get_linear_format_srgb(format
);
912 unreachable("Inalid colorspace for non-planar image");
915 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
916 /* The texture storage paths in core Mesa detect if the driver does not
917 * support the user-requested format, and then searches for a
918 * fallback format. The DRIimage code bypasses core Mesa, though. So we
919 * do the fallbacks here for important formats.
921 * We must support DRM_FOURCC_XBGR8888 textures because the Android
922 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
923 * the Chrome OS compositor consumes as dma_buf EGLImages.
925 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
928 if (!brw
->ctx
.TextureFormatSupported
[format
])
931 /* If this image comes in from a window system, we have different
932 * requirements than if it comes in via an EGL import operation. Window
933 * system images can use any form of auxiliary compression we wish because
934 * they get "flushed" before being handed off to the window system and we
935 * have the opportunity to do resolves. Window system buffers also may be
936 * used for scanout so we need to flag that appropriately.
938 const enum intel_miptree_create_flags mt_create_flags
=
939 is_winsys_image
? 0 : MIPTREE_CREATE_NO_AUX
;
941 /* Disable creation of the texture's aux buffers because the driver exposes
942 * no EGL API to manage them. That is, there is no API for resolving the aux
943 * buffer's content to the main buffer nor for invalidating the aux buffer's
946 struct intel_mipmap_tree
*mt
=
947 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
948 image
->offset
, image
->width
, image
->height
, 1,
949 image
->pitch
, mt_create_flags
);
954 mt
->level
[0].level_x
= image
->tile_x
;
955 mt
->level
[0].level_y
= image
->tile_y
;
957 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
958 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
959 * trouble resolving back to destination image due to alignment issues.
961 if (!brw
->has_surface_tile_offset
) {
962 uint32_t draw_x
, draw_y
;
963 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
965 if (draw_x
!= 0 || draw_y
!= 0) {
966 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
967 intel_miptree_release(&mt
);
972 /* If this is a window-system image, then we can no longer assume it's
973 * cache-coherent because it may suddenly get scanned out which destroys
977 image
->bo
->cache_coherent
= false;
983 * For a singlesample renderbuffer, this simply wraps the given BO with a
986 * For a multisample renderbuffer, this wraps the window system's
987 * (singlesample) BO with a singlesample miptree attached to the
988 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
989 * that will contain the actual rendering (which is lazily resolved to
990 * irb->singlesample_mt).
993 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
994 struct intel_renderbuffer
*irb
,
995 struct intel_mipmap_tree
*singlesample_mt
,
996 uint32_t width
, uint32_t height
,
999 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1000 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1001 mesa_format format
= rb
->Format
;
1002 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1004 /* Only the front and back buffers, which are color buffers, are allocated
1005 * through the image loader.
1007 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1008 _mesa_get_format_base_format(format
) == GL_RGBA
);
1010 assert(singlesample_mt
);
1012 if (num_samples
== 1) {
1013 intel_miptree_release(&irb
->mt
);
1014 irb
->mt
= singlesample_mt
;
1016 assert(!irb
->singlesample_mt
);
1018 intel_miptree_release(&irb
->singlesample_mt
);
1019 irb
->singlesample_mt
= singlesample_mt
;
1022 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1023 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1024 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1029 if (!multisample_mt
)
1032 irb
->need_downsample
= false;
1033 intel_miptree_release(&irb
->mt
);
1034 irb
->mt
= multisample_mt
;
1040 intel_miptree_release(&irb
->mt
);
1044 struct intel_mipmap_tree
*
1045 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1049 uint32_t num_samples
)
1051 struct intel_mipmap_tree
*mt
;
1053 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1055 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1056 width
, height
, depth
, num_samples
,
1057 MIPTREE_CREATE_BUSY
);
1064 intel_miptree_release(&mt
);
1069 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1070 struct intel_mipmap_tree
*src
)
1075 intel_miptree_release(dst
);
1079 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1086 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1088 if (aux_buf
== NULL
)
1091 brw_bo_unreference(aux_buf
->bo
);
1097 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1102 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1103 if (--(*mt
)->refcount
<= 0) {
1106 DBG("%s deleting %p\n", __func__
, *mt
);
1108 brw_bo_unreference((*mt
)->bo
);
1109 intel_miptree_release(&(*mt
)->stencil_mt
);
1110 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1111 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1112 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1113 free_aux_state_map((*mt
)->aux_state
);
1115 intel_miptree_release(&(*mt
)->plane
[0]);
1116 intel_miptree_release(&(*mt
)->plane
[1]);
1118 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1119 free((*mt
)->level
[i
].slice
);
1129 intel_get_image_dims(struct gl_texture_image
*image
,
1130 int *width
, int *height
, int *depth
)
1132 switch (image
->TexObject
->Target
) {
1133 case GL_TEXTURE_1D_ARRAY
:
1134 /* For a 1D Array texture the OpenGL API will treat the image height as
1135 * the number of array slices. For Intel hardware, we treat the 1D array
1136 * as a 2D Array with a height of 1. So, here we want to swap image
1139 assert(image
->Depth
== 1);
1140 *width
= image
->Width
;
1142 *depth
= image
->Height
;
1144 case GL_TEXTURE_CUBE_MAP
:
1145 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1146 * though we really have 6 slices.
1148 assert(image
->Depth
== 1);
1149 *width
= image
->Width
;
1150 *height
= image
->Height
;
1154 *width
= image
->Width
;
1155 *height
= image
->Height
;
1156 *depth
= image
->Depth
;
1162 * Can the image be pulled into a unified mipmap tree? This mirrors
1163 * the completeness test in a lot of ways.
1165 * Not sure whether I want to pass gl_texture_image here.
1168 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1169 struct gl_texture_image
*image
)
1171 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1172 GLuint level
= intelImage
->base
.Base
.Level
;
1173 int width
, height
, depth
;
1175 /* glTexImage* choose the texture object based on the target passed in, and
1176 * objects can't change targets over their lifetimes, so this should be
1179 assert(image
->TexObject
->Target
== mt
->target
);
1181 mesa_format mt_format
= mt
->format
;
1182 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1183 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1184 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1185 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1186 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1187 mt_format
= mt
->etc_format
;
1189 if (image
->TexFormat
!= mt_format
)
1192 intel_get_image_dims(image
, &width
, &height
, &depth
);
1194 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1197 if (level
>= mt
->surf
.levels
)
1200 const unsigned level_depth
=
1201 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1202 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1203 mt
->surf
.logical_level0_px
.array_len
;
1205 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1206 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1207 depth
== level_depth
&&
1208 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1212 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1213 GLuint level
, GLuint slice
,
1214 GLuint
*x
, GLuint
*y
)
1216 if (level
== 0 && slice
== 0) {
1217 *x
= mt
->level
[0].level_x
;
1218 *y
= mt
->level
[0].level_y
;
1222 uint32_t x_offset_sa
, y_offset_sa
;
1224 /* Miptree itself can have an offset only if it represents a single
1225 * slice in an imported buffer object.
1226 * See intel_miptree_create_for_dri_image().
1228 assert(mt
->level
[0].level_x
== 0);
1229 assert(mt
->level
[0].level_y
== 0);
1231 /* Given level is relative to level zero while the miptree may be
1232 * represent just a subset of all levels starting from 'first_level'.
1234 assert(level
>= mt
->first_level
);
1235 level
-= mt
->first_level
;
1237 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1238 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1239 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1240 &x_offset_sa
, &y_offset_sa
);
1248 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1249 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1250 * and tile_h is set to 1.
1253 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1254 uint32_t *tile_w
, uint32_t *tile_h
)
1265 case ISL_TILING_LINEAR
:
1270 unreachable("not reached");
1276 * This function computes masks that may be used to select the bits of the X
1277 * and Y coordinates that indicate the offset within a tile. If the BO is
1278 * untiled, the masks are set to 0.
1281 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1282 uint32_t *mask_x
, uint32_t *mask_y
)
1284 uint32_t tile_w_bytes
, tile_h
;
1286 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1288 *mask_x
= tile_w_bytes
/ cpp
- 1;
1289 *mask_y
= tile_h
- 1;
1293 * Compute the offset (in bytes) from the start of the BO to the given x
1294 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1295 * multiples of the tile size.
1298 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1299 uint32_t x
, uint32_t y
)
1302 uint32_t pitch
= mt
->surf
.row_pitch
;
1304 switch (mt
->surf
.tiling
) {
1306 unreachable("not reached");
1307 case ISL_TILING_LINEAR
:
1308 return y
* pitch
+ x
* cpp
;
1310 assert((x
% (512 / cpp
)) == 0);
1311 assert((y
% 8) == 0);
1312 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1314 assert((x
% (128 / cpp
)) == 0);
1315 assert((y
% 32) == 0);
1316 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1321 * Rendering with tiled buffers requires that the base address of the buffer
1322 * be aligned to a page boundary. For renderbuffers, and sometimes with
1323 * textures, we may want the surface to point at a texture image level that
1324 * isn't at a page boundary.
1326 * This function returns an appropriately-aligned base offset
1327 * according to the tiling restrictions, plus any required x/y offset
1331 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1332 GLuint level
, GLuint slice
,
1337 uint32_t mask_x
, mask_y
;
1339 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1340 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1342 *tile_x
= x
& mask_x
;
1343 *tile_y
= y
& mask_y
;
1345 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1349 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1350 struct intel_mipmap_tree
*src_mt
,
1351 unsigned src_level
, unsigned src_layer
,
1352 struct intel_mipmap_tree
*dst_mt
,
1353 unsigned dst_level
, unsigned dst_layer
,
1354 unsigned width
, unsigned height
)
1357 ptrdiff_t src_stride
, dst_stride
;
1358 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1360 intel_miptree_map(brw
, src_mt
,
1361 src_level
, src_layer
,
1364 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1367 intel_miptree_map(brw
, dst_mt
,
1368 dst_level
, dst_layer
,
1371 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1375 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1376 _mesa_get_format_name(src_mt
->format
),
1377 src_mt
, src
, src_stride
,
1378 _mesa_get_format_name(dst_mt
->format
),
1379 dst_mt
, dst
, dst_stride
,
1382 int row_size
= cpp
* width
;
1383 if (src_stride
== row_size
&&
1384 dst_stride
== row_size
) {
1385 memcpy(dst
, src
, row_size
* height
);
1387 for (int i
= 0; i
< height
; i
++) {
1388 memcpy(dst
, src
, row_size
);
1394 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1395 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1397 /* Don't forget to copy the stencil data over, too. We could have skipped
1398 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1399 * shuffling the two data sources in/out of temporary storage instead of
1400 * the direct mapping we get this way.
1402 if (dst_mt
->stencil_mt
) {
1403 assert(src_mt
->stencil_mt
);
1404 intel_miptree_copy_slice_sw(brw
,
1405 src_mt
->stencil_mt
, src_level
, src_layer
,
1406 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1412 intel_miptree_copy_slice(struct brw_context
*brw
,
1413 struct intel_mipmap_tree
*src_mt
,
1414 unsigned src_level
, unsigned src_layer
,
1415 struct intel_mipmap_tree
*dst_mt
,
1416 unsigned dst_level
, unsigned dst_layer
)
1419 mesa_format format
= src_mt
->format
;
1420 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1421 src_level
- src_mt
->first_level
);
1422 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1423 src_level
- src_mt
->first_level
);
1425 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1426 src_level
- src_mt
->first_level
));
1428 assert(src_mt
->format
== dst_mt
->format
);
1430 if (dst_mt
->compressed
) {
1432 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1433 height
= ALIGN_NPOT(height
, j
) / j
;
1434 width
= ALIGN_NPOT(width
, i
) / i
;
1437 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1438 * below won't apply since we can't do the depth's Y tiling or the
1439 * stencil's W tiling in the blitter.
1441 if (src_mt
->stencil_mt
) {
1442 intel_miptree_copy_slice_sw(brw
,
1443 src_mt
, src_level
, src_layer
,
1444 dst_mt
, dst_level
, dst_layer
,
1449 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1450 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1452 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1455 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1456 _mesa_get_format_name(src_mt
->format
),
1457 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1458 _mesa_get_format_name(dst_mt
->format
),
1459 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1462 if (!intel_miptree_blit(brw
,
1463 src_mt
, src_level
, src_layer
, 0, 0, false,
1464 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1465 width
, height
, GL_COPY
)) {
1466 perf_debug("miptree validate blit for %s failed\n",
1467 _mesa_get_format_name(format
));
1469 intel_miptree_copy_slice_sw(brw
,
1470 src_mt
, src_level
, src_layer
,
1471 dst_mt
, dst_level
, dst_layer
,
1477 * Copies the image's current data to the given miptree, and associates that
1478 * miptree with the image.
1480 * If \c invalidate is true, then the actual image data does not need to be
1481 * copied, but the image still needs to be associated to the new miptree (this
1482 * is set to true if we're about to clear the image).
1485 intel_miptree_copy_teximage(struct brw_context
*brw
,
1486 struct intel_texture_image
*intelImage
,
1487 struct intel_mipmap_tree
*dst_mt
,
1490 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1491 struct intel_texture_object
*intel_obj
=
1492 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1493 int level
= intelImage
->base
.Base
.Level
;
1494 const unsigned face
= intelImage
->base
.Base
.Face
;
1495 unsigned start_layer
, end_layer
;
1497 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1499 assert(intelImage
->base
.Base
.Height
);
1501 end_layer
= intelImage
->base
.Base
.Height
- 1;
1502 } else if (face
> 0) {
1506 assert(intelImage
->base
.Base
.Depth
);
1508 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1512 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1513 intel_miptree_copy_slice(brw
,
1519 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1520 intel_obj
->needs_validate
= true;
1524 intel_miptree_init_mcs(struct brw_context
*brw
,
1525 struct intel_mipmap_tree
*mt
,
1528 assert(mt
->mcs_buf
!= NULL
);
1530 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1532 * When MCS buffer is enabled and bound to MSRT, it is required that it
1533 * is cleared prior to any rendering.
1535 * Since we don't use the MCS buffer for any purpose other than rendering,
1536 * it makes sense to just clear it immediately upon allocation.
1538 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1540 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1541 if (unlikely(map
== NULL
)) {
1542 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1543 brw_bo_unreference(mt
->mcs_buf
->bo
);
1548 memset(data
, init_value
, mt
->mcs_buf
->size
);
1549 brw_bo_unmap(mt
->mcs_buf
->bo
);
1552 static struct intel_miptree_aux_buffer
*
1553 intel_alloc_aux_buffer(struct brw_context
*brw
,
1555 const struct isl_surf
*aux_surf
,
1556 uint32_t alloc_flags
,
1557 struct intel_mipmap_tree
*mt
)
1559 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1563 buf
->size
= aux_surf
->size
;
1564 buf
->pitch
= aux_surf
->row_pitch
;
1565 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1567 /* ISL has stricter set of alignment rules then the drm allocator.
1568 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1569 * trying to recalculate based on different format block sizes.
1571 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1572 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1578 buf
->surf
= *aux_surf
;
1584 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1585 struct intel_mipmap_tree
*mt
,
1588 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1589 assert(mt
->mcs_buf
== NULL
);
1590 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1592 /* Multisampled miptrees are only supported for single level. */
1593 assert(mt
->first_level
== 0);
1594 enum isl_aux_state
**aux_state
=
1595 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1599 struct isl_surf temp_mcs_surf
;
1601 MAYBE_UNUSED
bool ok
=
1602 isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_mcs_surf
);
1605 /* Buffer needs to be initialised requiring the buffer to be immediately
1606 * mapped to cpu space for writing. Therefore do not use the gpu access
1607 * flag which can cause an unnecessary delay if the backing pages happened
1608 * to be just used by the GPU.
1610 const uint32_t alloc_flags
= 0;
1611 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1612 &temp_mcs_surf
, alloc_flags
, mt
);
1618 mt
->aux_state
= aux_state
;
1620 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1626 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1627 struct intel_mipmap_tree
*mt
)
1629 assert(mt
->mcs_buf
== NULL
);
1630 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1631 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1633 struct isl_surf temp_ccs_surf
;
1635 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
, 0))
1638 assert(temp_ccs_surf
.size
&&
1639 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1641 enum isl_aux_state
**aux_state
=
1642 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1646 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1647 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1649 * "If Software wants to enable Color Compression without Fast clear,
1650 * Software needs to initialize MCS with zeros."
1652 * A CCS value of 0 indicates that the corresponding block is in the
1653 * pass-through state which is what we want.
1655 * For CCS_D, on the other hand, we don't care as we're about to perform a
1656 * fast-clear operation. In that case, being hot in caches more useful.
1658 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1659 BO_ALLOC_ZEROED
: BO_ALLOC_FOR_RENDER
;
1660 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1661 &temp_ccs_surf
, alloc_flags
, mt
);
1667 mt
->aux_state
= aux_state
;
1673 * Helper for intel_miptree_alloc_hiz() that sets
1674 * \c mt->level[level].has_hiz. Return true if and only if
1675 * \c has_hiz was set.
1678 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1679 struct intel_mipmap_tree
*mt
,
1682 assert(mt
->hiz_buf
);
1683 assert(mt
->surf
.size
> 0);
1685 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1686 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1687 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1689 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1690 * and the height is 4 aligned. This allows our HiZ support
1691 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1692 * we can grow the width & height to allow the HiZ op to
1693 * force the proper size alignments.
1695 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1696 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1701 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1702 mt
->level
[level
].has_hiz
= true;
1707 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1708 struct intel_mipmap_tree
*mt
)
1710 assert(mt
->hiz_buf
== NULL
);
1711 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1713 enum isl_aux_state
**aux_state
=
1714 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1718 struct isl_surf temp_hiz_surf
;
1720 MAYBE_UNUSED
bool ok
=
1721 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
1724 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
1725 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1726 &temp_hiz_surf
, alloc_flags
, mt
);
1733 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1734 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1736 mt
->aux_state
= aux_state
;
1743 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1745 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1746 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1747 * compress clear color so we wait until an actual fast-clear to allocate it.
1750 intel_miptree_alloc_aux(struct brw_context
*brw
,
1751 struct intel_mipmap_tree
*mt
)
1753 switch (mt
->aux_usage
) {
1754 case ISL_AUX_USAGE_NONE
:
1757 case ISL_AUX_USAGE_HIZ
:
1758 assert(!_mesa_is_format_color_format(mt
->format
));
1759 if (!intel_miptree_alloc_hiz(brw
, mt
))
1763 case ISL_AUX_USAGE_MCS
:
1764 assert(_mesa_is_format_color_format(mt
->format
));
1765 assert(mt
->surf
.samples
> 1);
1766 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
1770 case ISL_AUX_USAGE_CCS_D
:
1771 /* Since CCS_D can only compress clear color so we wait until an actual
1772 * fast-clear to allocate it.
1776 case ISL_AUX_USAGE_CCS_E
:
1777 assert(_mesa_is_format_color_format(mt
->format
));
1778 assert(mt
->surf
.samples
== 1);
1779 if (!intel_miptree_alloc_ccs(brw
, mt
))
1784 unreachable("Invalid aux usage");
1789 * Can the miptree sample using the hiz buffer?
1792 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1793 struct intel_mipmap_tree
*mt
)
1795 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1796 * so keep things conservative for now and never enable it unless we're SKL+.
1806 /* It seems the hardware won't fallback to the depth buffer if some of the
1807 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1808 * of the texture to be HiZ enabled.
1810 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1811 if (!intel_miptree_level_has_hiz(mt
, level
))
1815 /* If compressed multisampling is enabled, then we use it for the auxiliary
1818 * From the BDW PRM (Volume 2d: Command Reference: Structures
1819 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1821 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1822 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1824 * There is no such blurb for 1D textures, but there is sufficient evidence
1825 * that this is broken on SKL+.
1827 return (mt
->surf
.samples
== 1 &&
1828 mt
->target
!= GL_TEXTURE_3D
&&
1829 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1833 * Does the miptree slice have hiz enabled?
1836 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1838 intel_miptree_check_level_layer(mt
, level
, 0);
1839 return mt
->level
[level
].has_hiz
;
1842 static inline uint32_t
1843 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1844 uint32_t start_level
, uint32_t num_levels
)
1846 assert(start_level
>= mt
->first_level
);
1847 assert(start_level
<= mt
->last_level
);
1849 if (num_levels
== INTEL_REMAINING_LAYERS
)
1850 num_levels
= mt
->last_level
- start_level
+ 1;
1851 /* Check for overflow */
1852 assert(start_level
+ num_levels
>= start_level
);
1853 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
1858 static inline uint32_t
1859 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
1860 uint32_t start_layer
, uint32_t num_layers
)
1862 assert(level
<= mt
->last_level
);
1864 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
1865 assert(start_layer
< total_num_layers
);
1866 if (num_layers
== INTEL_REMAINING_LAYERS
)
1867 num_layers
= total_num_layers
- start_layer
;
1868 /* Check for overflow */
1869 assert(start_layer
+ num_layers
>= start_layer
);
1870 assert(start_layer
+ num_layers
<= total_num_layers
);
1876 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1877 unsigned start_level
, unsigned num_levels
,
1878 unsigned start_layer
, unsigned num_layers
)
1880 assert(_mesa_is_format_color_format(mt
->format
));
1885 /* Clamp the level range to fit the miptree */
1886 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
1888 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1889 const uint32_t level
= start_level
+ l
;
1890 const uint32_t level_layers
=
1891 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
1892 for (unsigned a
= 0; a
< level_layers
; a
++) {
1893 enum isl_aux_state aux_state
=
1894 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
1895 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
1896 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
1905 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
1906 const struct intel_mipmap_tree
*mt
,
1907 unsigned level
, unsigned layer
)
1913 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
1914 assert(brw
->gen
>= 8 ||
1915 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
1917 /* Compression of arrayed msaa surfaces is supported. */
1918 if (mt
->surf
.samples
> 1)
1921 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
1922 assert(brw
->gen
>= 8 ||
1924 mt
->surf
.logical_level0_px
.depth
== 1 &&
1925 mt
->surf
.logical_level0_px
.array_len
== 1));
1931 static enum blorp_fast_clear_op
1932 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
1933 enum isl_aux_usage aux_usage
,
1934 bool fast_clear_supported
)
1936 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
1938 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
1940 assert(ccs_supported
== fast_clear_supported
);
1942 switch (aux_state
) {
1943 case ISL_AUX_STATE_CLEAR
:
1944 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1946 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1948 return BLORP_FAST_CLEAR_OP_NONE
;
1950 case ISL_AUX_STATE_PASS_THROUGH
:
1951 return BLORP_FAST_CLEAR_OP_NONE
;
1953 case ISL_AUX_STATE_RESOLVED
:
1954 case ISL_AUX_STATE_AUX_INVALID
:
1955 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1956 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1960 unreachable("Invalid aux state for CCS_D");
1963 static enum blorp_fast_clear_op
1964 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
1965 enum isl_aux_usage aux_usage
,
1966 bool fast_clear_supported
)
1968 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
1969 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
1970 aux_usage
== ISL_AUX_USAGE_CCS_D
||
1971 aux_usage
== ISL_AUX_USAGE_CCS_E
);
1973 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
1974 assert(fast_clear_supported
);
1976 switch (aux_state
) {
1977 case ISL_AUX_STATE_CLEAR
:
1978 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1979 if (fast_clear_supported
)
1980 return BLORP_FAST_CLEAR_OP_NONE
;
1981 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
1982 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
1984 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1986 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1987 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1988 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1989 else if (!fast_clear_supported
)
1990 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
1992 return BLORP_FAST_CLEAR_OP_NONE
;
1994 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1995 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1996 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1998 return BLORP_FAST_CLEAR_OP_NONE
;
2000 case ISL_AUX_STATE_PASS_THROUGH
:
2001 return BLORP_FAST_CLEAR_OP_NONE
;
2003 case ISL_AUX_STATE_RESOLVED
:
2004 case ISL_AUX_STATE_AUX_INVALID
:
2008 unreachable("Invalid aux state for CCS_E");
2012 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2013 struct intel_mipmap_tree
*mt
,
2014 uint32_t level
, uint32_t layer
,
2015 enum isl_aux_usage aux_usage
,
2016 bool fast_clear_supported
)
2018 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2020 enum blorp_fast_clear_op resolve_op
;
2021 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2022 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2023 fast_clear_supported
);
2025 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2026 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2027 fast_clear_supported
);
2030 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2031 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2032 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2034 switch (resolve_op
) {
2035 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2036 /* The CCS full resolve operation destroys the CCS and sets it to the
2037 * pass-through state. (You can also think of this as being both a
2038 * resolve and an ambiguate in one operation.)
2040 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2041 ISL_AUX_STATE_PASS_THROUGH
);
2044 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2045 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2046 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2050 unreachable("Invalid resolve op");
2056 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2057 struct intel_mipmap_tree
*mt
,
2058 uint32_t level
, uint32_t layer
,
2059 enum isl_aux_usage aux_usage
)
2061 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2062 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2063 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2065 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2067 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2068 switch (aux_state
) {
2069 case ISL_AUX_STATE_CLEAR
:
2070 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2071 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2072 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2074 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2075 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2076 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2077 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2078 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2079 ISL_AUX_STATE_PARTIAL_CLEAR
);
2083 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2084 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2085 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2086 break; /* Nothing to do */
2088 case ISL_AUX_STATE_PASS_THROUGH
:
2089 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2090 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2091 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2097 case ISL_AUX_STATE_RESOLVED
:
2098 case ISL_AUX_STATE_AUX_INVALID
:
2099 unreachable("Invalid aux state for CCS_E");
2102 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2103 /* CCS_D is a bit simpler */
2104 switch (aux_state
) {
2105 case ISL_AUX_STATE_CLEAR
:
2106 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2107 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2108 ISL_AUX_STATE_PARTIAL_CLEAR
);
2111 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2112 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2113 break; /* Nothing to do */
2115 case ISL_AUX_STATE_PASS_THROUGH
:
2119 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2120 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2121 case ISL_AUX_STATE_RESOLVED
:
2122 case ISL_AUX_STATE_AUX_INVALID
:
2123 unreachable("Invalid aux state for CCS_D");
2129 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2130 struct intel_mipmap_tree
*mt
,
2132 enum isl_aux_usage aux_usage
,
2133 bool fast_clear_supported
)
2135 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2137 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2138 case ISL_AUX_STATE_CLEAR
:
2139 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2140 if (!fast_clear_supported
) {
2141 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2142 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2143 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2147 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2148 break; /* Nothing to do */
2150 case ISL_AUX_STATE_RESOLVED
:
2151 case ISL_AUX_STATE_PASS_THROUGH
:
2152 case ISL_AUX_STATE_AUX_INVALID
:
2153 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2154 unreachable("Invalid aux state for MCS");
2159 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2160 struct intel_mipmap_tree
*mt
,
2162 enum isl_aux_usage aux_usage
)
2164 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2166 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2167 case ISL_AUX_STATE_CLEAR
:
2168 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2169 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2172 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2173 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2174 break; /* Nothing to do */
2176 case ISL_AUX_STATE_RESOLVED
:
2177 case ISL_AUX_STATE_PASS_THROUGH
:
2178 case ISL_AUX_STATE_AUX_INVALID
:
2179 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2180 unreachable("Invalid aux state for MCS");
2185 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2186 struct intel_mipmap_tree
*mt
,
2187 uint32_t level
, uint32_t layer
,
2188 enum isl_aux_usage aux_usage
,
2189 bool fast_clear_supported
)
2191 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2193 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2194 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2195 case ISL_AUX_STATE_CLEAR
:
2196 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2197 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2198 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2201 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2202 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2203 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2206 case ISL_AUX_STATE_PASS_THROUGH
:
2207 case ISL_AUX_STATE_RESOLVED
:
2210 case ISL_AUX_STATE_AUX_INVALID
:
2211 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2212 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2215 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2216 unreachable("Invalid HiZ state");
2219 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2220 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2223 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2224 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2225 ISL_AUX_STATE_RESOLVED
);
2228 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2229 /* The HiZ resolve operation is actually an ambiguate */
2230 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2231 ISL_AUX_STATE_PASS_THROUGH
);
2235 unreachable("Invalid HiZ op");
2241 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2242 struct intel_mipmap_tree
*mt
,
2243 uint32_t level
, uint32_t layer
,
2244 enum isl_aux_usage aux_usage
)
2246 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2248 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2249 case ISL_AUX_STATE_CLEAR
:
2250 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2251 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2252 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2255 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2256 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2257 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2258 break; /* Nothing to do */
2260 case ISL_AUX_STATE_RESOLVED
:
2261 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2262 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2263 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2265 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2266 ISL_AUX_STATE_AUX_INVALID
);
2270 case ISL_AUX_STATE_PASS_THROUGH
:
2271 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2272 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2273 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2277 case ISL_AUX_STATE_AUX_INVALID
:
2278 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2281 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2282 unreachable("Invalid HiZ state");
2287 intel_miptree_prepare_access(struct brw_context
*brw
,
2288 struct intel_mipmap_tree
*mt
,
2289 uint32_t start_level
, uint32_t num_levels
,
2290 uint32_t start_layer
, uint32_t num_layers
,
2291 enum isl_aux_usage aux_usage
,
2292 bool fast_clear_supported
)
2294 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2296 switch (mt
->aux_usage
) {
2297 case ISL_AUX_USAGE_NONE
:
2301 case ISL_AUX_USAGE_MCS
:
2302 assert(mt
->mcs_buf
);
2303 assert(start_level
== 0 && num_levels
== 1);
2304 const uint32_t level_layers
=
2305 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2306 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2307 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2308 aux_usage
, fast_clear_supported
);
2312 case ISL_AUX_USAGE_CCS_D
:
2313 case ISL_AUX_USAGE_CCS_E
:
2317 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2318 const uint32_t level
= start_level
+ l
;
2319 const uint32_t level_layers
=
2320 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2321 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2322 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2324 aux_usage
, fast_clear_supported
);
2329 case ISL_AUX_USAGE_HIZ
:
2330 assert(mt
->hiz_buf
);
2331 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2332 const uint32_t level
= start_level
+ l
;
2333 if (!intel_miptree_level_has_hiz(mt
, level
))
2336 const uint32_t level_layers
=
2337 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2338 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2339 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2340 aux_usage
, fast_clear_supported
);
2346 unreachable("Invalid aux usage");
2351 intel_miptree_finish_write(struct brw_context
*brw
,
2352 struct intel_mipmap_tree
*mt
, uint32_t level
,
2353 uint32_t start_layer
, uint32_t num_layers
,
2354 enum isl_aux_usage aux_usage
)
2356 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2358 switch (mt
->aux_usage
) {
2359 case ISL_AUX_USAGE_NONE
:
2363 case ISL_AUX_USAGE_MCS
:
2364 assert(mt
->mcs_buf
);
2365 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2366 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2371 case ISL_AUX_USAGE_CCS_D
:
2372 case ISL_AUX_USAGE_CCS_E
:
2376 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2377 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2382 case ISL_AUX_USAGE_HIZ
:
2383 if (!intel_miptree_level_has_hiz(mt
, level
))
2386 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2387 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2393 unreachable("Invavlid aux usage");
2398 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2399 uint32_t level
, uint32_t layer
)
2401 intel_miptree_check_level_layer(mt
, level
, layer
);
2403 if (_mesa_is_format_color_format(mt
->format
)) {
2404 assert(mt
->mcs_buf
!= NULL
);
2405 assert(mt
->surf
.samples
== 1 ||
2406 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2407 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2408 unreachable("Cannot get aux state for stencil");
2410 assert(intel_miptree_level_has_hiz(mt
, level
));
2413 return mt
->aux_state
[level
][layer
];
2417 intel_miptree_set_aux_state(struct brw_context
*brw
,
2418 struct intel_mipmap_tree
*mt
, uint32_t level
,
2419 uint32_t start_layer
, uint32_t num_layers
,
2420 enum isl_aux_state aux_state
)
2422 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2424 if (_mesa_is_format_color_format(mt
->format
)) {
2425 assert(mt
->mcs_buf
!= NULL
);
2426 assert(mt
->surf
.samples
== 1 ||
2427 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2428 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2429 unreachable("Cannot get aux state for stencil");
2431 assert(intel_miptree_level_has_hiz(mt
, level
));
2434 for (unsigned a
= 0; a
< num_layers
; a
++)
2435 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2438 /* On Gen9 color buffers may be compressed by the hardware (lossless
2439 * compression). There are, however, format restrictions and care needs to be
2440 * taken that the sampler engine is capable for re-interpreting a buffer with
2441 * format different the buffer was originally written with.
2443 * For example, SRGB formats are not compressible and the sampler engine isn't
2444 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2445 * color buffer needs to be resolved so that the sampling surface can be
2446 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2450 can_texture_with_ccs(struct brw_context
*brw
,
2451 struct intel_mipmap_tree
*mt
,
2452 enum isl_format view_format
)
2454 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2457 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2458 mt
->surf
.format
, view_format
)) {
2459 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2460 isl_format_get_layout(view_format
)->name
,
2461 _mesa_get_format_name(mt
->format
));
2469 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2470 struct intel_mipmap_tree
*mt
,
2471 enum isl_format view_format
)
2473 switch (mt
->aux_usage
) {
2474 case ISL_AUX_USAGE_HIZ
:
2475 if (intel_miptree_sample_with_hiz(brw
, mt
))
2476 return ISL_AUX_USAGE_HIZ
;
2479 case ISL_AUX_USAGE_MCS
:
2480 return ISL_AUX_USAGE_MCS
;
2482 case ISL_AUX_USAGE_CCS_D
:
2483 case ISL_AUX_USAGE_CCS_E
:
2484 if (mt
->mcs_buf
&& can_texture_with_ccs(brw
, mt
, view_format
))
2485 return ISL_AUX_USAGE_CCS_E
;
2492 return ISL_AUX_USAGE_NONE
;
2496 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2498 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2499 * values so sRGB curve application was a no-op for all fast-clearable
2502 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2503 * values, the hardware interprets the floats, not as what would be
2504 * returned from the sampler (or written by the shader), but as being
2505 * between format conversion and sRGB curve application. This means that
2506 * we can switch between sRGB and UNORM without having to whack the clear
2509 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2513 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2514 struct intel_mipmap_tree
*mt
,
2515 enum isl_format view_format
,
2516 uint32_t start_level
, uint32_t num_levels
,
2517 uint32_t start_layer
, uint32_t num_layers
,
2518 bool *aux_supported_out
)
2520 enum isl_aux_usage aux_usage
=
2521 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2522 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2524 /* Clear color is specified as ints or floats and the conversion is done by
2525 * the sampler. If we have a texture view, we would have to perform the
2526 * clear color conversion manually. Just disable clear color.
2528 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2529 clear_supported
= false;
2531 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2532 start_layer
, num_layers
,
2533 aux_usage
, clear_supported
);
2534 if (aux_supported_out
)
2535 *aux_supported_out
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2539 intel_miptree_prepare_texture(struct brw_context
*brw
,
2540 struct intel_mipmap_tree
*mt
,
2541 enum isl_format view_format
,
2542 bool *aux_supported_out
)
2544 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2545 0, INTEL_REMAINING_LEVELS
,
2546 0, INTEL_REMAINING_LAYERS
,
2551 intel_miptree_prepare_image(struct brw_context
*brw
,
2552 struct intel_mipmap_tree
*mt
)
2554 /* The data port doesn't understand any compression */
2555 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2556 0, INTEL_REMAINING_LAYERS
,
2557 ISL_AUX_USAGE_NONE
, false);
2561 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2562 struct intel_mipmap_tree
*mt
, uint32_t level
,
2563 uint32_t start_layer
, uint32_t num_layers
)
2565 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->surf
.format
, level
, 1,
2566 start_layer
, num_layers
, NULL
);
2570 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2571 struct intel_mipmap_tree
*mt
,
2572 bool srgb_enabled
, bool blend_enabled
)
2574 switch (mt
->aux_usage
) {
2575 case ISL_AUX_USAGE_MCS
:
2576 assert(mt
->mcs_buf
);
2577 return ISL_AUX_USAGE_MCS
;
2579 case ISL_AUX_USAGE_CCS_D
:
2580 return mt
->mcs_buf
? ISL_AUX_USAGE_CCS_D
: ISL_AUX_USAGE_NONE
;
2582 case ISL_AUX_USAGE_CCS_E
: {
2583 mesa_format mesa_format
=
2584 srgb_enabled
? mt
->format
:_mesa_get_srgb_format_linear(mt
->format
);
2585 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
2587 /* If the format supports CCS_E, then we can just use it */
2588 if (isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
))
2589 return ISL_AUX_USAGE_CCS_E
;
2591 /* Otherwise, we have to fall back to CCS_D */
2593 /* gen9 hardware technically supports non-0/1 clear colors with sRGB
2594 * formats. However, there are issues with blending where it doesn't
2595 * properly apply the sRGB curve to the clear color when blending.
2597 if (blend_enabled
&& isl_format_is_srgb(isl_format
) &&
2598 !isl_color_value_is_zero_one(mt
->fast_clear_color
, isl_format
))
2599 return ISL_AUX_USAGE_NONE
;
2601 return ISL_AUX_USAGE_CCS_D
;
2605 return ISL_AUX_USAGE_NONE
;
2610 intel_miptree_prepare_render(struct brw_context
*brw
,
2611 struct intel_mipmap_tree
*mt
, uint32_t level
,
2612 uint32_t start_layer
, uint32_t layer_count
,
2613 bool srgb_enabled
, bool blend_enabled
)
2615 enum isl_aux_usage aux_usage
=
2616 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
, blend_enabled
);
2617 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2618 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2622 intel_miptree_finish_render(struct brw_context
*brw
,
2623 struct intel_mipmap_tree
*mt
, uint32_t level
,
2624 uint32_t start_layer
, uint32_t layer_count
,
2625 bool srgb_enabled
, bool blend_enabled
)
2627 assert(_mesa_is_format_color_format(mt
->format
));
2629 enum isl_aux_usage aux_usage
=
2630 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
, blend_enabled
);
2631 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2636 intel_miptree_prepare_depth(struct brw_context
*brw
,
2637 struct intel_mipmap_tree
*mt
, uint32_t level
,
2638 uint32_t start_layer
, uint32_t layer_count
)
2640 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2641 mt
->aux_usage
, mt
->hiz_buf
!= NULL
);
2645 intel_miptree_finish_depth(struct brw_context
*brw
,
2646 struct intel_mipmap_tree
*mt
, uint32_t level
,
2647 uint32_t start_layer
, uint32_t layer_count
,
2650 if (depth_written
) {
2651 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2652 mt
->hiz_buf
!= NULL
);
2657 * Make it possible to share the BO backing the given miptree with another
2658 * process or another miptree.
2660 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2661 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2662 * ensure that no MCS buffer gets allocated in the future.
2664 * HiZ is similarly unsafe with shared buffers.
2667 intel_miptree_make_shareable(struct brw_context
*brw
,
2668 struct intel_mipmap_tree
*mt
)
2670 /* MCS buffers are also used for multisample buffers, but we can't resolve
2671 * away a multisample MCS buffer because it's an integral part of how the
2672 * pixel data is stored. Fortunately this code path should never be
2673 * reached for multisample buffers.
2675 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2676 mt
->surf
.samples
== 1);
2678 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2679 0, INTEL_REMAINING_LAYERS
,
2680 ISL_AUX_USAGE_NONE
, false);
2683 brw_bo_unreference(mt
->mcs_buf
->bo
);
2687 /* Any pending MCS/CCS operations are no longer needed. Trying to
2688 * execute any will likely crash due to the missing aux buffer. So let's
2689 * delete all pending ops.
2691 free(mt
->aux_state
);
2692 mt
->aux_state
= NULL
;
2696 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2699 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2700 mt
->level
[l
].has_hiz
= false;
2703 /* Any pending HiZ operations are no longer needed. Trying to execute
2704 * any will likely crash due to the missing aux buffer. So let's delete
2707 free(mt
->aux_state
);
2708 mt
->aux_state
= NULL
;
2711 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2712 mt
->supports_fast_clear
= false;
2717 * \brief Get pointer offset into stencil buffer.
2719 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2720 * must decode the tile's layout in software.
2723 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2725 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2727 * Even though the returned offset is always positive, the return type is
2729 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2730 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2733 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2735 uint32_t tile_size
= 4096;
2736 uint32_t tile_width
= 64;
2737 uint32_t tile_height
= 64;
2738 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2740 uint32_t tile_x
= x
/ tile_width
;
2741 uint32_t tile_y
= y
/ tile_height
;
2743 /* The byte's address relative to the tile's base addres. */
2744 uint32_t byte_x
= x
% tile_width
;
2745 uint32_t byte_y
= y
% tile_height
;
2747 uintptr_t u
= tile_y
* row_size
2748 + tile_x
* tile_size
2749 + 512 * (byte_x
/ 8)
2751 + 32 * ((byte_y
/ 4) % 2)
2752 + 16 * ((byte_x
/ 4) % 2)
2753 + 8 * ((byte_y
/ 2) % 2)
2754 + 4 * ((byte_x
/ 2) % 2)
2759 /* adjust for bit6 swizzling */
2760 if (((byte_x
/ 8) % 2) == 1) {
2761 if (((byte_y
/ 8) % 2) == 0) {
2773 intel_miptree_updownsample(struct brw_context
*brw
,
2774 struct intel_mipmap_tree
*src
,
2775 struct intel_mipmap_tree
*dst
)
2777 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2778 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2779 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2780 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2782 brw_blorp_blit_miptrees(brw
,
2783 src
, 0 /* level */, 0 /* layer */,
2784 src
->format
, SWIZZLE_XYZW
,
2785 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2788 GL_NEAREST
, false, false /*mirror x, y*/,
2791 if (src
->stencil_mt
) {
2792 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2793 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2794 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2795 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2797 brw_blorp_blit_miptrees(brw
,
2798 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2799 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2800 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2801 dst
->stencil_mt
->format
,
2804 GL_NEAREST
, false, false /*mirror x, y*/,
2805 false, false /* decode/encode srgb */);
2810 intel_update_r8stencil(struct brw_context
*brw
,
2811 struct intel_mipmap_tree
*mt
)
2813 assert(brw
->gen
>= 7);
2814 struct intel_mipmap_tree
*src
=
2815 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2816 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2819 assert(src
->surf
.size
> 0);
2821 if (!mt
->r8stencil_mt
) {
2822 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2823 mt
->r8stencil_mt
= make_surface(
2826 MESA_FORMAT_R_UINT8
,
2827 src
->first_level
, src
->last_level
,
2828 src
->surf
.logical_level0_px
.width
,
2829 src
->surf
.logical_level0_px
.height
,
2830 src
->surf
.dim
== ISL_SURF_DIM_3D
?
2831 src
->surf
.logical_level0_px
.depth
:
2832 src
->surf
.logical_level0_px
.array_len
,
2835 ISL_SURF_USAGE_TEXTURE_BIT
,
2836 BO_ALLOC_FOR_RENDER
, 0, NULL
);
2837 assert(mt
->r8stencil_mt
);
2840 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2842 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2843 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
2844 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
2845 src
->surf
.phys_level0_sa
.array_len
;
2847 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2848 brw_blorp_copy_miptrees(brw
,
2852 minify(src
->surf
.logical_level0_px
.width
,
2854 minify(src
->surf
.logical_level0_px
.height
,
2859 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2860 src
->r8stencil_needs_update
= false;
2864 intel_miptree_map_raw(struct brw_context
*brw
,
2865 struct intel_mipmap_tree
*mt
,
2868 struct brw_bo
*bo
= mt
->bo
;
2870 if (brw_batch_references(&brw
->batch
, bo
))
2871 intel_batchbuffer_flush(brw
);
2873 return brw_bo_map(brw
, bo
, mode
);
2877 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2879 brw_bo_unmap(mt
->bo
);
2883 intel_miptree_map_gtt(struct brw_context
*brw
,
2884 struct intel_mipmap_tree
*mt
,
2885 struct intel_miptree_map
*map
,
2886 unsigned int level
, unsigned int slice
)
2888 unsigned int bw
, bh
;
2890 unsigned int image_x
, image_y
;
2891 intptr_t x
= map
->x
;
2892 intptr_t y
= map
->y
;
2894 /* For compressed formats, the stride is the number of bytes per
2895 * row of blocks. intel_miptree_get_image_offset() already does
2898 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2899 assert(y
% bh
== 0);
2900 assert(x
% bw
== 0);
2904 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
2911 /* Note that in the case of cube maps, the caller must have passed the
2912 * slice number referencing the face.
2914 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2918 map
->stride
= mt
->surf
.row_pitch
;
2919 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2922 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2923 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2924 map
->x
, map
->y
, map
->w
, map
->h
,
2925 mt
, _mesa_get_format_name(mt
->format
),
2926 x
, y
, map
->ptr
, map
->stride
);
2930 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2932 intel_miptree_unmap_raw(mt
);
2936 intel_miptree_map_blit(struct brw_context
*brw
,
2937 struct intel_mipmap_tree
*mt
,
2938 struct intel_miptree_map
*map
,
2939 unsigned int level
, unsigned int slice
)
2941 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2942 /* first_level */ 0,
2946 MIPTREE_CREATE_LINEAR
);
2948 if (!map
->linear_mt
) {
2949 fprintf(stderr
, "Failed to allocate blit temporary\n");
2952 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
2954 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2955 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2956 * invalidate is set, since we'll be writing the whole rectangle from our
2957 * temporary buffer back out.
2959 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2960 if (!intel_miptree_copy(brw
,
2961 mt
, level
, slice
, map
->x
, map
->y
,
2962 map
->linear_mt
, 0, 0, 0, 0,
2964 fprintf(stderr
, "Failed to blit\n");
2969 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
2971 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2972 map
->x
, map
->y
, map
->w
, map
->h
,
2973 mt
, _mesa_get_format_name(mt
->format
),
2974 level
, slice
, map
->ptr
, map
->stride
);
2979 intel_miptree_release(&map
->linear_mt
);
2985 intel_miptree_unmap_blit(struct brw_context
*brw
,
2986 struct intel_mipmap_tree
*mt
,
2987 struct intel_miptree_map
*map
,
2991 struct gl_context
*ctx
= &brw
->ctx
;
2993 intel_miptree_unmap_raw(map
->linear_mt
);
2995 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2996 bool ok
= intel_miptree_copy(brw
,
2997 map
->linear_mt
, 0, 0, 0, 0,
2998 mt
, level
, slice
, map
->x
, map
->y
,
3000 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3003 intel_miptree_release(&map
->linear_mt
);
3007 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3009 #if defined(USE_SSE41)
3011 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3012 struct intel_mipmap_tree
*mt
,
3013 struct intel_miptree_map
*map
,
3014 unsigned int level
, unsigned int slice
)
3016 assert(map
->mode
& GL_MAP_READ_BIT
);
3017 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3019 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3020 map
->x
, map
->y
, map
->w
, map
->h
,
3021 mt
, _mesa_get_format_name(mt
->format
),
3022 level
, slice
, map
->ptr
, map
->stride
);
3024 /* Map the original image */
3027 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3031 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3037 src
+= image_y
* mt
->surf
.row_pitch
;
3038 src
+= image_x
* mt
->cpp
;
3040 /* Due to the pixel offsets for the particular image being mapped, our
3041 * src pointer may not be 16-byte aligned. However, if the pitch is
3042 * divisible by 16, then the amount by which it's misaligned will remain
3043 * consistent from row to row.
3045 assert((mt
->surf
.row_pitch
% 16) == 0);
3046 const int misalignment
= ((uintptr_t) src
) & 15;
3048 /* Create an untiled temporary buffer for the mapping. */
3049 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3051 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3053 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3054 /* Offset the destination so it has the same misalignment as src. */
3055 map
->ptr
= map
->buffer
+ misalignment
;
3057 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3059 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3060 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3061 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3063 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3066 intel_miptree_unmap_raw(mt
);
3070 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3071 struct intel_mipmap_tree
*mt
,
3072 struct intel_miptree_map
*map
,
3076 _mesa_align_free(map
->buffer
);
3083 intel_miptree_map_s8(struct brw_context
*brw
,
3084 struct intel_mipmap_tree
*mt
,
3085 struct intel_miptree_map
*map
,
3086 unsigned int level
, unsigned int slice
)
3088 map
->stride
= map
->w
;
3089 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3093 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3094 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3095 * invalidate is set, since we'll be writing the whole rectangle from our
3096 * temporary buffer back out.
3098 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3099 uint8_t *untiled_s8_map
= map
->ptr
;
3100 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3101 unsigned int image_x
, image_y
;
3103 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3105 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3106 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3107 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3108 x
+ image_x
+ map
->x
,
3109 y
+ image_y
+ map
->y
,
3110 brw
->has_swizzling
);
3111 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3115 intel_miptree_unmap_raw(mt
);
3117 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3118 map
->x
, map
->y
, map
->w
, map
->h
,
3119 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3121 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3122 map
->x
, map
->y
, map
->w
, map
->h
,
3123 mt
, map
->ptr
, map
->stride
);
3128 intel_miptree_unmap_s8(struct brw_context
*brw
,
3129 struct intel_mipmap_tree
*mt
,
3130 struct intel_miptree_map
*map
,
3134 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3135 unsigned int image_x
, image_y
;
3136 uint8_t *untiled_s8_map
= map
->ptr
;
3137 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3139 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3141 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3142 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3143 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3144 image_x
+ x
+ map
->x
,
3145 image_y
+ y
+ map
->y
,
3146 brw
->has_swizzling
);
3147 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3151 intel_miptree_unmap_raw(mt
);
3158 intel_miptree_map_etc(struct brw_context
*brw
,
3159 struct intel_mipmap_tree
*mt
,
3160 struct intel_miptree_map
*map
,
3164 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3165 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3166 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3169 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3170 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3172 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3173 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3174 map
->w
, map
->h
, 1));
3175 map
->ptr
= map
->buffer
;
3179 intel_miptree_unmap_etc(struct brw_context
*brw
,
3180 struct intel_mipmap_tree
*mt
,
3181 struct intel_miptree_map
*map
,
3187 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3192 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3193 + image_y
* mt
->surf
.row_pitch
3194 + image_x
* mt
->cpp
;
3196 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3197 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3198 map
->ptr
, map
->stride
,
3201 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3202 map
->ptr
, map
->stride
,
3203 map
->w
, map
->h
, mt
->etc_format
);
3205 intel_miptree_unmap_raw(mt
);
3210 * Mapping function for packed depth/stencil miptrees backed by real separate
3211 * miptrees for depth and stencil.
3213 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3214 * separate from the depth buffer. Yet at the GL API level, we have to expose
3215 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3216 * be able to map that memory for texture storage and glReadPixels-type
3217 * operations. We give Mesa core that access by mallocing a temporary and
3218 * copying the data between the actual backing store and the temporary.
3221 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3222 struct intel_mipmap_tree
*mt
,
3223 struct intel_miptree_map
*map
,
3224 unsigned int level
, unsigned int slice
)
3226 struct intel_mipmap_tree
*z_mt
= mt
;
3227 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3228 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3229 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3231 map
->stride
= map
->w
* packed_bpp
;
3232 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3236 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3237 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3238 * invalidate is set, since we'll be writing the whole rectangle from our
3239 * temporary buffer back out.
3241 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3242 uint32_t *packed_map
= map
->ptr
;
3243 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3244 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3245 unsigned int s_image_x
, s_image_y
;
3246 unsigned int z_image_x
, z_image_y
;
3248 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3249 &s_image_x
, &s_image_y
);
3250 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3251 &z_image_x
, &z_image_y
);
3253 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3254 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3255 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3256 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3259 brw
->has_swizzling
);
3260 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3261 (z_mt
->surf
.row_pitch
/ 4) +
3262 (map_x
+ z_image_x
));
3263 uint8_t s
= s_map
[s_offset
];
3264 uint32_t z
= z_map
[z_offset
];
3266 if (map_z32f_x24s8
) {
3267 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3268 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3270 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3275 intel_miptree_unmap_raw(s_mt
);
3276 intel_miptree_unmap_raw(z_mt
);
3278 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3280 map
->x
, map
->y
, map
->w
, map
->h
,
3281 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3282 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3283 map
->ptr
, map
->stride
);
3285 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3286 map
->x
, map
->y
, map
->w
, map
->h
,
3287 mt
, map
->ptr
, map
->stride
);
3292 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3293 struct intel_mipmap_tree
*mt
,
3294 struct intel_miptree_map
*map
,
3298 struct intel_mipmap_tree
*z_mt
= mt
;
3299 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3300 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3302 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3303 uint32_t *packed_map
= map
->ptr
;
3304 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3305 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3306 unsigned int s_image_x
, s_image_y
;
3307 unsigned int z_image_x
, z_image_y
;
3309 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3310 &s_image_x
, &s_image_y
);
3311 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3312 &z_image_x
, &z_image_y
);
3314 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3315 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3316 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3317 x
+ s_image_x
+ map
->x
,
3318 y
+ s_image_y
+ map
->y
,
3319 brw
->has_swizzling
);
3320 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3321 (z_mt
->surf
.row_pitch
/ 4) +
3322 (x
+ z_image_x
+ map
->x
));
3324 if (map_z32f_x24s8
) {
3325 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3326 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3328 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3329 s_map
[s_offset
] = packed
>> 24;
3330 z_map
[z_offset
] = packed
;
3335 intel_miptree_unmap_raw(s_mt
);
3336 intel_miptree_unmap_raw(z_mt
);
3338 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3340 map
->x
, map
->y
, map
->w
, map
->h
,
3341 z_mt
, _mesa_get_format_name(z_mt
->format
),
3342 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3343 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3344 map
->ptr
, map
->stride
);
3351 * Create and attach a map to the miptree at (level, slice). Return the
3354 static struct intel_miptree_map
*
3355 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3364 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3369 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3370 mt
->level
[level
].slice
[slice
].map
= map
;
3382 * Release the map at (level, slice).
3385 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3389 struct intel_miptree_map
**map
;
3391 map
= &mt
->level
[level
].slice
[slice
].map
;
3397 can_blit_slice(struct intel_mipmap_tree
*mt
,
3398 unsigned int level
, unsigned int slice
)
3400 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3401 if (mt
->surf
.row_pitch
>= 32768)
3408 use_intel_mipree_map_blit(struct brw_context
*brw
,
3409 struct intel_mipmap_tree
*mt
,
3415 /* It's probably not worth swapping to the blit ring because of
3416 * all the overhead involved.
3418 !(mode
& GL_MAP_WRITE_BIT
) &&
3420 (mt
->surf
.tiling
== ISL_TILING_X
||
3421 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3422 (brw
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3423 /* Fast copy blit on skl+ supports all tiling formats. */
3425 can_blit_slice(mt
, level
, slice
))
3428 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3429 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3430 assert(can_blit_slice(mt
, level
, slice
));
3438 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3439 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3440 * arithmetic overflow.
3442 * If you call this function and use \a out_stride, then you're doing pointer
3443 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3444 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3445 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3446 * which usually have type uint32_t or GLuint.
3449 intel_miptree_map(struct brw_context
*brw
,
3450 struct intel_mipmap_tree
*mt
,
3459 ptrdiff_t *out_stride
)
3461 struct intel_miptree_map
*map
;
3463 assert(mt
->surf
.samples
== 1);
3465 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3472 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3473 map
->mode
& GL_MAP_WRITE_BIT
);
3475 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3476 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3477 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3478 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3479 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3480 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3481 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3482 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3483 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3484 #if defined(USE_SSE41)
3485 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3486 !mt
->compressed
&& cpu_has_sse4_1
&&
3487 (mt
->surf
.row_pitch
% 16 == 0)) {
3488 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3491 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3494 *out_ptr
= map
->ptr
;
3495 *out_stride
= map
->stride
;
3497 if (map
->ptr
== NULL
)
3498 intel_miptree_release_map(mt
, level
, slice
);
3502 intel_miptree_unmap(struct brw_context
*brw
,
3503 struct intel_mipmap_tree
*mt
,
3507 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3509 assert(mt
->surf
.samples
== 1);
3514 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3515 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3517 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3518 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3519 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3520 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3521 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3522 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3523 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3524 } else if (map
->linear_mt
) {
3525 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3526 #if defined(USE_SSE41)
3527 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3528 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3531 intel_miptree_unmap_gtt(mt
);
3534 intel_miptree_release_map(mt
, level
, slice
);
3538 get_isl_surf_dim(GLenum target
)
3542 case GL_TEXTURE_1D_ARRAY
:
3543 return ISL_SURF_DIM_1D
;
3546 case GL_TEXTURE_2D_ARRAY
:
3547 case GL_TEXTURE_RECTANGLE
:
3548 case GL_TEXTURE_CUBE_MAP
:
3549 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3550 case GL_TEXTURE_2D_MULTISAMPLE
:
3551 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3552 case GL_TEXTURE_EXTERNAL_OES
:
3553 return ISL_SURF_DIM_2D
;
3556 return ISL_SURF_DIM_3D
;
3559 unreachable("Invalid texture target");
3563 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3564 enum isl_tiling tiling
, GLenum target
)
3568 case GL_TEXTURE_1D_ARRAY
:
3569 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3570 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3573 case GL_TEXTURE_2D_ARRAY
:
3574 case GL_TEXTURE_RECTANGLE
:
3575 case GL_TEXTURE_2D_MULTISAMPLE
:
3576 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3577 case GL_TEXTURE_EXTERNAL_OES
:
3578 return ISL_DIM_LAYOUT_GEN4_2D
;
3580 case GL_TEXTURE_CUBE_MAP
:
3581 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3582 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3583 ISL_DIM_LAYOUT_GEN4_2D
);
3586 return (devinfo
->gen
>= 9 ?
3587 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3590 unreachable("Invalid texture target");
3594 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3595 const struct intel_mipmap_tree
*mt
)
3598 return ISL_AUX_USAGE_HIZ
;
3601 return ISL_AUX_USAGE_NONE
;
3603 return mt
->aux_usage
;