1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_resolve_map.h"
34 #include "intel_tex.h"
35 #include "intel_blit.h"
36 #include "intel_fbo.h"
38 #include "brw_blorp.h"
39 #include "brw_context.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
48 #include "x86/common_x86_asm.h"
50 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
53 intel_miptree_alloc_mcs(struct brw_context
*brw
,
54 struct intel_mipmap_tree
*mt
,
58 * Determine which MSAA layout should be used by the MSAA surface being
59 * created, based on the chip generation and the surface type.
61 static enum intel_msaa_layout
62 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
, GLenum target
,
63 bool disable_aux_buffers
)
65 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
67 return INTEL_MSAA_LAYOUT_IMS
;
69 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
70 switch (_mesa_get_format_base_format(format
)) {
71 case GL_DEPTH_COMPONENT
:
72 case GL_STENCIL_INDEX
:
73 case GL_DEPTH_STENCIL
:
74 return INTEL_MSAA_LAYOUT_IMS
;
76 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
78 * This field must be set to 0 for all SINT MSRTs when all RT channels
81 * In practice this means that we have to disable MCS for all signed
82 * integer MSAA buffers. The alternative, to disable MCS only when one
83 * of the render target channels is disabled, is impractical because it
84 * would require converting between CMS and UMS MSAA layouts on the fly,
87 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
88 return INTEL_MSAA_LAYOUT_UMS
;
89 } else if (disable_aux_buffers
) {
90 /* We can't use the CMS layout because it uses an aux buffer, the MCS
91 * buffer. So fallback to UMS, which is identical to CMS without the
93 return INTEL_MSAA_LAYOUT_UMS
;
95 return INTEL_MSAA_LAYOUT_CMS
;
102 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
103 * scaled-down bitfield representation of the color buffer which is capable of
104 * recording when blocks of the color buffer are equal to the clear value.
105 * This function returns the block size that will be used by the MCS buffer
106 * corresponding to a certain color miptree.
108 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
109 * beneath the "Fast Color Clear" bullet (p327):
111 * The following table describes the RT alignment
125 * This alignment has the following uses:
127 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
128 * buffer contains 128 blocks horizontally and 256 blocks vertically.
130 * - For figuring out alignment restrictions for a fast clear operation. Fast
131 * clear operations must always clear aligned multiples of 16 blocks
132 * horizontally and 32 blocks vertically.
134 * - For scaling down the coordinates sent through the render pipeline during
135 * a fast clear. X coordinates must be scaled down by 8 times the block
136 * width, and Y coordinates by 16 times the block height.
138 * - For scaling down the coordinates sent through the render pipeline during
139 * a "Render Target Resolve" operation. X coordinates must be scaled down
140 * by half the block width, and Y coordinates by half the block height.
143 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
144 struct intel_mipmap_tree
*mt
,
145 unsigned *width_px
, unsigned *height
)
147 switch (mt
->tiling
) {
149 unreachable("Non-MSRT MCS requires X or Y tiling");
150 /* In release builds, fall through */
152 *width_px
= 32 / mt
->cpp
;
156 *width_px
= 64 / mt
->cpp
;
163 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
166 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
167 * beneath the "Fast Color Clear" bullet (p326):
169 * - Support is limited to tiled render targets.
170 * - Support is for non-mip-mapped and non-array surface types only.
172 * And then later, on p327:
174 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
178 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
179 struct intel_mipmap_tree
*mt
)
181 /* MCS support does not exist prior to Gen7 */
185 if (mt
->disable_aux_buffers
)
188 /* MCS is only supported for color buffers */
189 switch (_mesa_get_format_base_format(mt
->format
)) {
190 case GL_DEPTH_COMPONENT
:
191 case GL_DEPTH_STENCIL
:
192 case GL_STENCIL_INDEX
:
196 if (mt
->tiling
!= I915_TILING_X
&&
197 mt
->tiling
!= I915_TILING_Y
)
199 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
201 if (mt
->first_level
!= 0 || mt
->last_level
!= 0)
203 if (mt
->physical_depth0
!= 1)
206 /* There's no point in using an MCS buffer if the surface isn't in a
209 if (!brw
->format_supported_as_render_target
[mt
->format
])
217 * Determine depth format corresponding to a depth+stencil format,
218 * for separate stencil.
221 intel_depth_format_for_depthstencil_format(mesa_format format
) {
223 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
224 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
225 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
226 return MESA_FORMAT_Z_FLOAT32
;
234 * @param for_bo Indicates that the caller is
235 * intel_miptree_create_for_bo(). If true, then do not create
238 static struct intel_mipmap_tree
*
239 intel_miptree_create_layout(struct brw_context
*brw
,
249 bool force_all_slices_at_each_lod
,
250 bool disable_aux_buffers
)
252 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
256 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __FUNCTION__
,
257 _mesa_lookup_enum_by_nr(target
),
258 _mesa_get_format_name(format
),
259 first_level
, last_level
, depth0
, mt
);
261 if (target
== GL_TEXTURE_1D_ARRAY
) {
262 /* For a 1D Array texture the OpenGL API will treat the height0
263 * parameter as the number of array slices. For Intel hardware, we treat
264 * the 1D array as a 2D Array with a height of 1.
266 * So, when we first come through this path to create a 1D Array
267 * texture, height0 stores the number of slices, and depth0 is 1. In
268 * this case, we want to swap height0 and depth0.
270 * Since some miptrees will be created based on the base miptree, we may
271 * come through this path and see height0 as 1 and depth0 being the
272 * number of slices. In this case we don't need to do the swap.
274 assert(height0
== 1 || depth0
== 1);
283 mt
->first_level
= first_level
;
284 mt
->last_level
= last_level
;
285 mt
->logical_width0
= width0
;
286 mt
->logical_height0
= height0
;
287 mt
->logical_depth0
= depth0
;
288 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
289 mt
->disable_aux_buffers
= disable_aux_buffers
;
290 exec_list_make_empty(&mt
->hiz_map
);
292 /* The cpp is bytes per (1, blockheight)-sized block for compressed
293 * textures. This is why you'll see divides by blockheight all over
296 _mesa_get_format_block_size(format
, &bw
, &bh
);
297 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
298 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
300 mt
->num_samples
= num_samples
;
301 mt
->compressed
= _mesa_is_format_compressed(format
);
302 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
305 if (num_samples
> 1) {
306 /* Adjust width/height/depth for MSAA */
307 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
308 mt
->target
, mt
->disable_aux_buffers
);
309 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
310 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
311 * "If the surface is multisampled and it is a depth or stencil
312 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
313 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
316 * +----------------------------------------------------------------+
317 * | Num Multisamples | W_l = | H_l = |
318 * +----------------------------------------------------------------+
319 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
320 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
321 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
322 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
323 * +----------------------------------------------------------------+
326 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
327 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
328 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
330 * Another more complicated explanation for these adjustments comes
331 * from the Sandybridge PRM, volume 4, part 1, page 31:
333 * "Any of the other messages (sample*, LOD, load4) used with a
334 * (4x) multisampled surface will in-effect sample a surface with
335 * double the height and width as that indicated in the surface
336 * state. Each pixel position on the original-sized surface is
337 * replaced with a 2x2 of samples with the following arrangement:
342 * Thus, when sampling from a multisampled texture, it behaves as
343 * though the layout in memory for (x,y,sample) is:
345 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
346 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
348 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
349 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
351 * However, the actual layout of multisampled data in memory is:
353 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
354 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
356 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
357 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
359 * This pattern repeats for each 2x2 pixel block.
361 * As a result, when calculating the size of our 4-sample buffer for
362 * an odd width or height, we have to align before scaling up because
363 * sample 3 is in that bottom right 2x2 block.
365 switch (num_samples
) {
367 assert(brw
->gen
>= 8);
368 width0
= ALIGN(width0
, 2) * 2;
369 height0
= ALIGN(height0
, 2);
372 width0
= ALIGN(width0
, 2) * 2;
373 height0
= ALIGN(height0
, 2) * 2;
376 width0
= ALIGN(width0
, 2) * 4;
377 height0
= ALIGN(height0
, 2) * 2;
380 /* num_samples should already have been quantized to 0, 1, 2, 4, or
383 unreachable("not reached");
386 /* Non-interleaved */
387 depth0
*= num_samples
;
391 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when gen7+ array_spacing_lod0
392 * can be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces.
393 * TODO: can we use it elsewhere?
395 switch (mt
->msaa_layout
) {
396 case INTEL_MSAA_LAYOUT_NONE
:
397 case INTEL_MSAA_LAYOUT_IMS
:
398 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
400 case INTEL_MSAA_LAYOUT_UMS
:
401 case INTEL_MSAA_LAYOUT_CMS
:
402 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
406 if (target
== GL_TEXTURE_CUBE_MAP
) {
411 mt
->physical_width0
= width0
;
412 mt
->physical_height0
= height0
;
413 mt
->physical_depth0
= depth0
;
416 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
417 (brw
->must_use_separate_stencil
||
418 (brw
->has_separate_stencil
&&
419 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
420 const bool force_all_slices_at_each_lod
= brw
->gen
== 6;
421 mt
->stencil_mt
= intel_miptree_create(brw
,
431 INTEL_MIPTREE_TILING_ANY
,
432 force_all_slices_at_each_lod
);
433 if (!mt
->stencil_mt
) {
434 intel_miptree_release(&mt
);
438 /* Fix up the Z miptree format for how we're splitting out separate
439 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
441 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
444 if (format
== mt
->format
) {
445 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
446 _mesa_get_format_name(mt
->format
));
450 if (force_all_slices_at_each_lod
)
451 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
453 brw_miptree_layout(brw
, mt
);
455 if (mt
->disable_aux_buffers
)
456 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
462 * \brief Helper function for intel_miptree_create().
465 intel_miptree_choose_tiling(struct brw_context
*brw
,
468 uint32_t num_samples
,
469 enum intel_miptree_tiling_mode requested
,
470 struct intel_mipmap_tree
*mt
)
472 if (format
== MESA_FORMAT_S_UINT8
) {
473 /* The stencil buffer is W tiled. However, we request from the kernel a
474 * non-tiled buffer because the GTT is incapable of W fencing.
476 return I915_TILING_NONE
;
479 /* Some usages may want only one type of tiling, like depth miptrees (Y
480 * tiled), or temporary BOs for uploading data once (linear).
483 case INTEL_MIPTREE_TILING_ANY
:
485 case INTEL_MIPTREE_TILING_Y
:
486 return I915_TILING_Y
;
487 case INTEL_MIPTREE_TILING_NONE
:
488 return I915_TILING_NONE
;
491 if (num_samples
> 1) {
492 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
495 * [DevSNB+]: For multi-sample render targets, this field must be
496 * 1. MSRTs can only be tiled.
498 * Our usual reason for preferring X tiling (fast blits using the
499 * blitting engine) doesn't apply to MSAA, since we'll generally be
500 * downsampling or upsampling when blitting between the MSAA buffer
501 * and another buffer, and the blitting engine doesn't support that.
502 * So use Y tiling, since it makes better use of the cache.
504 return I915_TILING_Y
;
507 GLenum base_format
= _mesa_get_format_base_format(format
);
508 if (base_format
== GL_DEPTH_COMPONENT
||
509 base_format
== GL_DEPTH_STENCIL_EXT
)
510 return I915_TILING_Y
;
512 /* 1D textures (and 1D array textures) don't get any benefit from tiling,
513 * in fact it leads to a less efficient use of memory space and bandwidth
514 * due to tile alignment.
516 if (mt
->logical_height0
== 1)
517 return I915_TILING_NONE
;
519 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
521 /* If the width is much smaller than a tile, don't bother tiling. */
522 if (minimum_pitch
< 64)
523 return I915_TILING_NONE
;
525 if (ALIGN(minimum_pitch
, 512) >= 32768 ||
526 mt
->total_width
>= 32768 || mt
->total_height
>= 32768) {
527 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
528 mt
->total_width
, mt
->total_height
);
529 return I915_TILING_NONE
;
532 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
534 return I915_TILING_X
;
536 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
537 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
539 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
540 * all the way back to 965, but is permitted on Gen7+.
542 if (brw
->gen
< 7 && mt
->cpp
>= 16)
543 return I915_TILING_X
;
545 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
546 * messages), on p64, under the heading "Surface Vertical Alignment":
548 * This field must be set to VALIGN_4 for all tiled Y Render Target
551 * So if the surface is renderable and uses a vertical alignment of 2,
552 * force it to be X tiled. This is somewhat conservative (it's possible
553 * that the client won't ever render to this surface), but it's difficult
554 * to know that ahead of time. And besides, since we use a vertical
555 * alignment of 4 as often as we can, this shouldn't happen very often.
557 if (brw
->gen
== 7 && mt
->align_h
== 2 &&
558 brw
->format_supported_as_render_target
[format
]) {
559 return I915_TILING_X
;
562 return I915_TILING_Y
| I915_TILING_X
;
567 * Choose an appropriate uncompressed format for a requested
568 * compressed format, if unsupported.
571 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
573 /* No need to lower ETC formats on these platforms,
574 * they are supported natively.
576 if (brw
->gen
>= 8 || brw
->is_baytrail
)
580 case MESA_FORMAT_ETC1_RGB8
:
581 return MESA_FORMAT_R8G8B8X8_UNORM
;
582 case MESA_FORMAT_ETC2_RGB8
:
583 return MESA_FORMAT_R8G8B8X8_UNORM
;
584 case MESA_FORMAT_ETC2_SRGB8
:
585 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
586 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
587 return MESA_FORMAT_B8G8R8A8_SRGB
;
588 case MESA_FORMAT_ETC2_RGBA8_EAC
:
589 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
590 return MESA_FORMAT_R8G8B8A8_UNORM
;
591 case MESA_FORMAT_ETC2_R11_EAC
:
592 return MESA_FORMAT_R_UNORM16
;
593 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
594 return MESA_FORMAT_R_SNORM16
;
595 case MESA_FORMAT_ETC2_RG11_EAC
:
596 return MESA_FORMAT_R16G16_UNORM
;
597 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
598 return MESA_FORMAT_R16G16_SNORM
;
600 /* Non ETC1 / ETC2 format */
606 struct intel_mipmap_tree
*
607 intel_miptree_create(struct brw_context
*brw
,
615 bool expect_accelerated_upload
,
617 enum intel_miptree_tiling_mode requested_tiling
,
618 bool force_all_slices_at_each_lod
)
620 struct intel_mipmap_tree
*mt
;
621 mesa_format tex_format
= format
;
622 mesa_format etc_format
= MESA_FORMAT_NONE
;
623 GLuint total_width
, total_height
;
625 format
= intel_lower_compressed_format(brw
, format
);
627 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
629 mt
= intel_miptree_create_layout(brw
, target
, format
,
630 first_level
, last_level
, width0
,
633 force_all_slices_at_each_lod
,
634 false /*disable_aux_buffers*/);
636 * pitch == 0 || height == 0 indicates the null texture
638 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
639 intel_miptree_release(&mt
);
643 total_width
= mt
->total_width
;
644 total_height
= mt
->total_height
;
646 if (format
== MESA_FORMAT_S_UINT8
) {
647 /* Align to size of W tile, 64x64. */
648 total_width
= ALIGN(total_width
, 64);
649 total_height
= ALIGN(total_height
, 64);
652 uint32_t tiling
= intel_miptree_choose_tiling(brw
, format
, width0
,
653 num_samples
, requested_tiling
,
657 if (tiling
== (I915_TILING_Y
| I915_TILING_X
)) {
659 mt
->tiling
= I915_TILING_Y
;
665 mt
->etc_format
= etc_format
;
666 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
667 total_width
, total_height
, mt
->cpp
,
669 (expect_accelerated_upload
?
670 BO_ALLOC_FOR_RENDER
: 0));
673 /* If the BO is too large to fit in the aperture, we need to use the
674 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
675 * handle Y-tiling, so we need to fall back to X.
677 if (brw
->gen
< 6 && y_or_x
&& mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
678 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
679 mt
->total_width
, mt
->total_height
);
681 mt
->tiling
= I915_TILING_X
;
682 drm_intel_bo_unreference(mt
->bo
);
683 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
684 total_width
, total_height
, mt
->cpp
,
686 (expect_accelerated_upload
?
687 BO_ALLOC_FOR_RENDER
: 0));
694 intel_miptree_release(&mt
);
699 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
700 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
701 intel_miptree_release(&mt
);
706 /* If this miptree is capable of supporting fast color clears, set
707 * fast_clear_state appropriately to ensure that fast clears will occur.
708 * Allocation of the MCS miptree will be deferred until the first fast
709 * clear actually occurs.
711 if (intel_is_non_msrt_mcs_buffer_supported(brw
, mt
))
712 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
717 struct intel_mipmap_tree
*
718 intel_miptree_create_for_bo(struct brw_context
*brw
,
726 bool disable_aux_buffers
)
728 struct intel_mipmap_tree
*mt
;
729 uint32_t tiling
, swizzle
;
732 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
734 /* Nothing will be able to use this miptree with the BO if the offset isn't
737 if (tiling
!= I915_TILING_NONE
)
738 assert(offset
% 4096 == 0);
740 /* miptrees can't handle negative pitch. If you need flipping of images,
741 * that's outside of the scope of the mt.
745 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
747 mt
= intel_miptree_create_layout(brw
, target
, format
,
749 width
, height
, depth
,
751 disable_aux_buffers
);
757 drm_intel_bo_reference(bo
);
767 * For a singlesample renderbuffer, this simply wraps the given BO with a
770 * For a multisample renderbuffer, this wraps the window system's
771 * (singlesample) BO with a singlesample miptree attached to the
772 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
773 * that will contain the actual rendering (which is lazily resolved to
774 * irb->singlesample_mt).
777 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
778 struct intel_renderbuffer
*irb
,
780 uint32_t width
, uint32_t height
,
783 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
784 struct intel_mipmap_tree
*multisample_mt
= NULL
;
785 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
786 mesa_format format
= rb
->Format
;
787 int num_samples
= rb
->NumSamples
;
789 /* Only the front and back buffers, which are color buffers, are allocated
790 * through the image loader.
792 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
793 _mesa_get_format_base_format(format
) == GL_RGBA
);
795 singlesample_mt
= intel_miptree_create_for_bo(intel
,
804 if (!singlesample_mt
)
807 /* If this miptree is capable of supporting fast color clears, set
808 * mcs_state appropriately to ensure that fast clears will occur.
809 * Allocation of the MCS miptree will be deferred until the first fast
810 * clear actually occurs.
812 if (intel_is_non_msrt_mcs_buffer_supported(intel
, singlesample_mt
))
813 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
815 if (num_samples
== 0) {
816 intel_miptree_release(&irb
->mt
);
817 irb
->mt
= singlesample_mt
;
819 assert(!irb
->singlesample_mt
);
821 intel_miptree_release(&irb
->singlesample_mt
);
822 irb
->singlesample_mt
= singlesample_mt
;
825 irb
->mt
->logical_width0
!= width
||
826 irb
->mt
->logical_height0
!= height
) {
827 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
835 irb
->need_downsample
= false;
836 intel_miptree_release(&irb
->mt
);
837 irb
->mt
= multisample_mt
;
843 intel_miptree_release(&irb
->singlesample_mt
);
844 intel_miptree_release(&irb
->mt
);
848 struct intel_mipmap_tree
*
849 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
853 uint32_t num_samples
)
855 struct intel_mipmap_tree
*mt
;
858 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
860 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
861 width
, height
, depth
, true, num_samples
,
862 INTEL_MIPTREE_TILING_ANY
, false);
866 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
867 ok
= intel_miptree_alloc_hiz(brw
, mt
);
875 intel_miptree_release(&mt
);
880 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
881 struct intel_mipmap_tree
*src
)
886 intel_miptree_release(dst
);
890 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
898 intel_miptree_release(struct intel_mipmap_tree
**mt
)
903 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
904 if (--(*mt
)->refcount
<= 0) {
907 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
909 drm_intel_bo_unreference((*mt
)->bo
);
910 intel_miptree_release(&(*mt
)->stencil_mt
);
911 if ((*mt
)->hiz_buf
) {
912 if ((*mt
)->hiz_buf
->mt
)
913 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
915 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
916 free((*mt
)->hiz_buf
);
918 intel_miptree_release(&(*mt
)->mcs_mt
);
919 intel_resolve_map_clear(&(*mt
)->hiz_map
);
921 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
922 free((*mt
)->level
[i
].slice
);
931 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
932 int *width
, int *height
, int *depth
)
934 switch (image
->TexObject
->Target
) {
935 case GL_TEXTURE_1D_ARRAY
:
936 *width
= image
->Width
;
938 *depth
= image
->Height
;
941 *width
= image
->Width
;
942 *height
= image
->Height
;
943 *depth
= image
->Depth
;
949 * Can the image be pulled into a unified mipmap tree? This mirrors
950 * the completeness test in a lot of ways.
952 * Not sure whether I want to pass gl_texture_image here.
955 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
956 struct gl_texture_image
*image
)
958 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
959 GLuint level
= intelImage
->base
.Base
.Level
;
960 int width
, height
, depth
;
962 /* glTexImage* choose the texture object based on the target passed in, and
963 * objects can't change targets over their lifetimes, so this should be
966 assert(image
->TexObject
->Target
== mt
->target
);
968 mesa_format mt_format
= mt
->format
;
969 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
970 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
971 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
972 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
973 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
974 mt_format
= mt
->etc_format
;
976 if (image
->TexFormat
!= mt_format
)
979 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
981 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
984 int level_depth
= mt
->level
[level
].depth
;
985 if (mt
->num_samples
> 1) {
986 switch (mt
->msaa_layout
) {
987 case INTEL_MSAA_LAYOUT_NONE
:
988 case INTEL_MSAA_LAYOUT_IMS
:
990 case INTEL_MSAA_LAYOUT_UMS
:
991 case INTEL_MSAA_LAYOUT_CMS
:
992 level_depth
/= mt
->num_samples
;
997 /* Test image dimensions against the base level image adjusted for
998 * minification. This will also catch images not present in the
999 * tree, changed targets, etc.
1001 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1002 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1003 depth
!= level_depth
) {
1007 if (image
->NumSamples
!= mt
->num_samples
)
1015 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1017 GLuint x
, GLuint y
, GLuint d
)
1019 mt
->level
[level
].depth
= d
;
1020 mt
->level
[level
].level_x
= x
;
1021 mt
->level
[level
].level_y
= y
;
1023 DBG("%s level %d, depth %d, offset %d,%d\n", __FUNCTION__
,
1026 assert(mt
->level
[level
].slice
== NULL
);
1028 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1029 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1030 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1035 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1036 GLuint level
, GLuint img
,
1039 if (img
== 0 && level
== 0)
1040 assert(x
== 0 && y
== 0);
1042 assert(img
< mt
->level
[level
].depth
);
1044 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1045 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1047 DBG("%s level %d img %d pos %d,%d\n",
1048 __FUNCTION__
, level
, img
,
1049 mt
->level
[level
].slice
[img
].x_offset
,
1050 mt
->level
[level
].slice
[img
].y_offset
);
1054 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1055 GLuint level
, GLuint slice
,
1056 GLuint
*x
, GLuint
*y
)
1058 assert(slice
< mt
->level
[level
].depth
);
1060 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1061 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1065 * This function computes masks that may be used to select the bits of the X
1066 * and Y coordinates that indicate the offset within a tile. If the BO is
1067 * untiled, the masks are set to 0.
1070 intel_miptree_get_tile_masks(const struct intel_mipmap_tree
*mt
,
1071 uint32_t *mask_x
, uint32_t *mask_y
,
1072 bool map_stencil_as_y_tiled
)
1075 uint32_t tiling
= mt
->tiling
;
1077 if (map_stencil_as_y_tiled
)
1078 tiling
= I915_TILING_Y
;
1082 unreachable("not reached");
1083 case I915_TILING_NONE
:
1084 *mask_x
= *mask_y
= 0;
1087 *mask_x
= 512 / cpp
- 1;
1091 *mask_x
= 128 / cpp
- 1;
1098 * Compute the offset (in bytes) from the start of the BO to the given x
1099 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1100 * multiples of the tile size.
1103 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1104 uint32_t x
, uint32_t y
,
1105 bool map_stencil_as_y_tiled
)
1108 uint32_t pitch
= mt
->pitch
;
1109 uint32_t tiling
= mt
->tiling
;
1111 if (map_stencil_as_y_tiled
) {
1112 tiling
= I915_TILING_Y
;
1114 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1115 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1116 * the resulting surface is twice the pitch of the original miptree,
1117 * since each row in the Y-tiled view corresponds to two rows in the
1118 * actual W-tiled surface. So we need to correct the pitch before
1119 * computing the offsets.
1126 unreachable("not reached");
1127 case I915_TILING_NONE
:
1128 return y
* pitch
+ x
* cpp
;
1130 assert((x
% (512 / cpp
)) == 0);
1131 assert((y
% 8) == 0);
1132 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1134 assert((x
% (128 / cpp
)) == 0);
1135 assert((y
% 32) == 0);
1136 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1141 * Rendering with tiled buffers requires that the base address of the buffer
1142 * be aligned to a page boundary. For renderbuffers, and sometimes with
1143 * textures, we may want the surface to point at a texture image level that
1144 * isn't at a page boundary.
1146 * This function returns an appropriately-aligned base offset
1147 * according to the tiling restrictions, plus any required x/y offset
1151 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1152 GLuint level
, GLuint slice
,
1157 uint32_t mask_x
, mask_y
;
1159 intel_miptree_get_tile_masks(mt
, &mask_x
, &mask_y
, false);
1160 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1162 *tile_x
= x
& mask_x
;
1163 *tile_y
= y
& mask_y
;
1165 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1169 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1170 struct intel_mipmap_tree
*dst_mt
,
1171 struct intel_mipmap_tree
*src_mt
,
1178 ptrdiff_t src_stride
, dst_stride
;
1179 int cpp
= dst_mt
->cpp
;
1181 intel_miptree_map(brw
, src_mt
,
1185 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1188 intel_miptree_map(brw
, dst_mt
,
1192 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1196 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1197 _mesa_get_format_name(src_mt
->format
),
1198 src_mt
, src
, src_stride
,
1199 _mesa_get_format_name(dst_mt
->format
),
1200 dst_mt
, dst
, dst_stride
,
1203 int row_size
= cpp
* width
;
1204 if (src_stride
== row_size
&&
1205 dst_stride
== row_size
) {
1206 memcpy(dst
, src
, row_size
* height
);
1208 for (int i
= 0; i
< height
; i
++) {
1209 memcpy(dst
, src
, row_size
);
1215 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1216 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1218 /* Don't forget to copy the stencil data over, too. We could have skipped
1219 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1220 * shuffling the two data sources in/out of temporary storage instead of
1221 * the direct mapping we get this way.
1223 if (dst_mt
->stencil_mt
) {
1224 assert(src_mt
->stencil_mt
);
1225 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1226 level
, slice
, width
, height
);
1231 intel_miptree_copy_slice(struct brw_context
*brw
,
1232 struct intel_mipmap_tree
*dst_mt
,
1233 struct intel_mipmap_tree
*src_mt
,
1239 mesa_format format
= src_mt
->format
;
1240 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1241 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1249 assert(depth
< src_mt
->level
[level
].depth
);
1250 assert(src_mt
->format
== dst_mt
->format
);
1252 if (dst_mt
->compressed
) {
1253 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1254 width
= ALIGN(width
, dst_mt
->align_w
);
1257 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1258 * below won't apply since we can't do the depth's Y tiling or the
1259 * stencil's W tiling in the blitter.
1261 if (src_mt
->stencil_mt
) {
1262 intel_miptree_copy_slice_sw(brw
,
1269 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1270 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1271 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1273 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1274 _mesa_get_format_name(src_mt
->format
),
1275 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1276 _mesa_get_format_name(dst_mt
->format
),
1277 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1280 if (!intel_miptree_blit(brw
,
1281 src_mt
, level
, slice
, 0, 0, false,
1282 dst_mt
, level
, slice
, 0, 0, false,
1283 width
, height
, GL_COPY
)) {
1284 perf_debug("miptree validate blit for %s failed\n",
1285 _mesa_get_format_name(format
));
1287 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1293 * Copies the image's current data to the given miptree, and associates that
1294 * miptree with the image.
1296 * If \c invalidate is true, then the actual image data does not need to be
1297 * copied, but the image still needs to be associated to the new miptree (this
1298 * is set to true if we're about to clear the image).
1301 intel_miptree_copy_teximage(struct brw_context
*brw
,
1302 struct intel_texture_image
*intelImage
,
1303 struct intel_mipmap_tree
*dst_mt
,
1306 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1307 struct intel_texture_object
*intel_obj
=
1308 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1309 int level
= intelImage
->base
.Base
.Level
;
1310 int face
= intelImage
->base
.Base
.Face
;
1313 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1314 depth
= intelImage
->base
.Base
.Height
;
1316 depth
= intelImage
->base
.Base
.Depth
;
1319 for (int slice
= 0; slice
< depth
; slice
++) {
1320 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1324 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1325 intel_obj
->needs_validate
= true;
1329 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1330 struct intel_mipmap_tree
*mt
,
1333 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1334 assert(mt
->mcs_mt
== NULL
);
1335 assert(!mt
->disable_aux_buffers
);
1337 /* Choose the correct format for the MCS buffer. All that really matters
1338 * is that we allocate the right buffer size, since we'll always be
1339 * accessing this miptree using MCS-specific hardware mechanisms, which
1340 * infer the correct format based on num_samples.
1343 switch (num_samples
) {
1346 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1349 format
= MESA_FORMAT_R_UNORM8
;
1352 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1353 * for each sample, plus 8 padding bits).
1355 format
= MESA_FORMAT_R_UINT32
;
1358 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1361 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1363 * "The MCS surface must be stored as Tile Y."
1365 mt
->mcs_mt
= intel_miptree_create(brw
,
1371 mt
->logical_height0
,
1374 0 /* num_samples */,
1375 INTEL_MIPTREE_TILING_Y
,
1378 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1380 * When MCS buffer is enabled and bound to MSRT, it is required that it
1381 * is cleared prior to any rendering.
1383 * Since we don't use the MCS buffer for any purpose other than rendering,
1384 * it makes sense to just clear it immediately upon allocation.
1386 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1388 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1389 memset(data
, 0xff, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1390 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1391 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1398 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1399 struct intel_mipmap_tree
*mt
)
1401 assert(mt
->mcs_mt
== NULL
);
1402 assert(!mt
->disable_aux_buffers
);
1404 /* The format of the MCS buffer is opaque to the driver; all that matters
1405 * is that we get its size and pitch right. We'll pretend that the format
1406 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1407 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1408 * the block width and then a further factor of 4. Since an MCS tile
1409 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1410 * we'll need to scale the height down by the block height and then a
1411 * further factor of 8.
1413 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1414 unsigned block_width_px
;
1415 unsigned block_height
;
1416 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1417 unsigned width_divisor
= block_width_px
* 4;
1418 unsigned height_divisor
= block_height
* 8;
1419 unsigned mcs_width
=
1420 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1421 unsigned mcs_height
=
1422 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1423 assert(mt
->logical_depth0
== 1);
1424 mt
->mcs_mt
= intel_miptree_create(brw
,
1433 0 /* num_samples */,
1434 INTEL_MIPTREE_TILING_Y
,
1442 * Helper for intel_miptree_alloc_hiz() that sets
1443 * \c mt->level[level].has_hiz. Return true if and only if
1444 * \c has_hiz was set.
1447 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1448 struct intel_mipmap_tree
*mt
,
1451 assert(mt
->hiz_buf
);
1453 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1454 uint32_t width
= minify(mt
->physical_width0
, level
);
1455 uint32_t height
= minify(mt
->physical_height0
, level
);
1457 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1458 * and the height is 4 aligned. This allows our HiZ support
1459 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1460 * we can grow the width & height to allow the HiZ op to
1461 * force the proper size alignments.
1463 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1464 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1469 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1470 mt
->level
[level
].has_hiz
= true;
1476 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1477 * buffer dimensions and allocates a bo for the hiz buffer.
1479 static struct intel_miptree_aux_buffer
*
1480 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1481 struct intel_mipmap_tree
*mt
)
1483 unsigned z_width
= mt
->logical_width0
;
1484 unsigned z_height
= mt
->logical_height0
;
1485 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1486 unsigned hz_width
, hz_height
;
1487 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1492 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1493 * adjustments required for Z_Height and Z_Width based on multisampling.
1495 switch (mt
->num_samples
) {
1509 unreachable("unsupported sample count");
1512 const unsigned vertical_align
= 8; /* 'j' in the docs */
1513 const unsigned H0
= z_height
;
1514 const unsigned h0
= ALIGN(H0
, vertical_align
);
1515 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1516 const unsigned Z0
= z_depth
;
1518 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1519 hz_width
= ALIGN(z_width
, 16);
1521 if (mt
->target
== GL_TEXTURE_3D
) {
1525 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1526 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1527 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1528 hz_height
+= h_i
* Z_i
;
1529 H_i
= minify(H_i
, 1);
1530 Z_i
= minify(Z_i
, 1);
1533 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1535 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1537 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1538 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1539 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1540 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth * 6/2) /8 ) * 8 */
1541 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
* 6, 2 * 8) * 8;
1543 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1544 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1548 unsigned long pitch
;
1549 uint32_t tiling
= I915_TILING_Y
;
1550 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1551 hz_width
, hz_height
, 1,
1553 BO_ALLOC_FOR_RENDER
);
1557 } else if (tiling
!= I915_TILING_Y
) {
1558 drm_intel_bo_unreference(buf
->bo
);
1570 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1571 * buffer dimensions and allocates a bo for the hiz buffer.
1573 static struct intel_miptree_aux_buffer
*
1574 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1575 struct intel_mipmap_tree
*mt
)
1577 unsigned z_width
= mt
->logical_width0
;
1578 unsigned z_height
= mt
->logical_height0
;
1579 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1580 unsigned hz_width
, hz_height
;
1581 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1586 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1587 * adjustments required for Z_Height and Z_Width based on multisampling.
1589 switch (mt
->num_samples
) {
1603 unreachable("unsupported sample count");
1606 const unsigned vertical_align
= 8; /* 'j' in the docs */
1607 const unsigned H0
= z_height
;
1608 const unsigned h0
= ALIGN(H0
, vertical_align
);
1609 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1610 const unsigned Z0
= z_depth
;
1612 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1613 hz_width
= ALIGN(z_width
, 16);
1617 unsigned sum_h_i
= 0;
1618 unsigned hz_height_3d_sum
= 0;
1619 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1620 unsigned i
= level
- mt
->first_level
;
1621 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1622 /* sum(i=2 to m; h_i) */
1626 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1627 hz_height_3d_sum
+= h_i
* Z_i
;
1628 H_i
= minify(H_i
, 1);
1629 Z_i
= minify(Z_i
, 1);
1631 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1632 buf
->qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1634 if (mt
->target
== GL_TEXTURE_3D
) {
1635 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1636 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1638 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1639 hz_height
= DIV_ROUND_UP(buf
->qpitch
, 2 * 8) * 8 * Z0
;
1640 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1641 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1642 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * 6 * Z_Depth
1644 * We can can just take our hz_height calculation from above, and
1645 * multiply by 6 for the cube map and cube map array types.
1651 unsigned long pitch
;
1652 uint32_t tiling
= I915_TILING_Y
;
1653 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1654 hz_width
, hz_height
, 1,
1656 BO_ALLOC_FOR_RENDER
);
1660 } else if (tiling
!= I915_TILING_Y
) {
1661 drm_intel_bo_unreference(buf
->bo
);
1672 static struct intel_miptree_aux_buffer
*
1673 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1674 struct intel_mipmap_tree
*mt
)
1676 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1677 const bool force_all_slices_at_each_lod
= brw
->gen
== 6;
1682 buf
->mt
= intel_miptree_create(brw
,
1688 mt
->logical_height0
,
1692 INTEL_MIPTREE_TILING_ANY
,
1693 force_all_slices_at_each_lod
);
1699 buf
->bo
= buf
->mt
->bo
;
1700 buf
->pitch
= buf
->mt
->pitch
;
1701 buf
->qpitch
= buf
->mt
->qpitch
;
1707 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1708 struct intel_mipmap_tree
*mt
)
1713 if (mt
->hiz_buf
!= NULL
)
1716 if (mt
->disable_aux_buffers
)
1719 switch (mt
->format
) {
1720 case MESA_FORMAT_Z_FLOAT32
:
1721 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1722 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1723 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1724 case MESA_FORMAT_Z_UNORM16
:
1732 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1733 struct intel_mipmap_tree
*mt
)
1735 assert(mt
->hiz_buf
== NULL
);
1736 assert(!mt
->disable_aux_buffers
);
1738 if (brw
->gen
== 7) {
1739 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1740 } else if (brw
->gen
>= 8) {
1741 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1743 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1749 /* Mark that all slices need a HiZ resolve. */
1750 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1751 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1754 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1755 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1756 exec_node_init(&m
->link
);
1759 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1761 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1769 * Does the miptree slice have hiz enabled?
1772 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1774 intel_miptree_check_level_layer(mt
, level
, 0);
1775 return mt
->level
[level
].has_hiz
;
1779 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1783 if (!intel_miptree_level_has_hiz(mt
, level
))
1786 intel_resolve_map_set(&mt
->hiz_map
,
1787 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1792 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1796 if (!intel_miptree_level_has_hiz(mt
, level
))
1799 intel_resolve_map_set(&mt
->hiz_map
,
1800 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1804 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1808 uint32_t end_layer
= mt
->level
[level
].depth
;
1810 for (layer
= 0; layer
< end_layer
; layer
++) {
1811 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1816 intel_miptree_slice_resolve(struct brw_context
*brw
,
1817 struct intel_mipmap_tree
*mt
,
1820 enum gen6_hiz_op need
)
1822 intel_miptree_check_level_layer(mt
, level
, layer
);
1824 struct intel_resolve_map
*item
=
1825 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1827 if (!item
|| item
->need
!= need
)
1830 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1831 intel_resolve_map_remove(item
);
1836 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1837 struct intel_mipmap_tree
*mt
,
1841 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1842 GEN6_HIZ_OP_HIZ_RESOLVE
);
1846 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1847 struct intel_mipmap_tree
*mt
,
1851 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1852 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1856 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1857 struct intel_mipmap_tree
*mt
,
1858 enum gen6_hiz_op need
)
1860 bool did_resolve
= false;
1862 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
1863 if (map
->need
!= need
)
1866 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
1867 intel_resolve_map_remove(map
);
1875 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1876 struct intel_mipmap_tree
*mt
)
1878 return intel_miptree_all_slices_resolve(brw
, mt
,
1879 GEN6_HIZ_OP_HIZ_RESOLVE
);
1883 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1884 struct intel_mipmap_tree
*mt
)
1886 return intel_miptree_all_slices_resolve(brw
, mt
,
1887 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1892 intel_miptree_resolve_color(struct brw_context
*brw
,
1893 struct intel_mipmap_tree
*mt
)
1895 switch (mt
->fast_clear_state
) {
1896 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1897 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1898 /* No resolve needed */
1900 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1901 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1902 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1903 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1904 brw_meta_resolve_color(brw
, mt
);
1911 * Make it possible to share the BO backing the given miptree with another
1912 * process or another miptree.
1914 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1915 * then discard the MCS buffer, if present. We also set the fast_clear_state
1916 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1917 * allocated in the future.
1920 intel_miptree_make_shareable(struct brw_context
*brw
,
1921 struct intel_mipmap_tree
*mt
)
1923 /* MCS buffers are also used for multisample buffers, but we can't resolve
1924 * away a multisample MCS buffer because it's an integral part of how the
1925 * pixel data is stored. Fortunately this code path should never be
1926 * reached for multisample buffers.
1928 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1931 intel_miptree_resolve_color(brw
, mt
);
1932 intel_miptree_release(&mt
->mcs_mt
);
1933 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
1939 * \brief Get pointer offset into stencil buffer.
1941 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1942 * must decode the tile's layout in software.
1945 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1947 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1949 * Even though the returned offset is always positive, the return type is
1951 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1952 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1955 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1957 uint32_t tile_size
= 4096;
1958 uint32_t tile_width
= 64;
1959 uint32_t tile_height
= 64;
1960 uint32_t row_size
= 64 * stride
;
1962 uint32_t tile_x
= x
/ tile_width
;
1963 uint32_t tile_y
= y
/ tile_height
;
1965 /* The byte's address relative to the tile's base addres. */
1966 uint32_t byte_x
= x
% tile_width
;
1967 uint32_t byte_y
= y
% tile_height
;
1969 uintptr_t u
= tile_y
* row_size
1970 + tile_x
* tile_size
1971 + 512 * (byte_x
/ 8)
1973 + 32 * ((byte_y
/ 4) % 2)
1974 + 16 * ((byte_x
/ 4) % 2)
1975 + 8 * ((byte_y
/ 2) % 2)
1976 + 4 * ((byte_x
/ 2) % 2)
1981 /* adjust for bit6 swizzling */
1982 if (((byte_x
/ 8) % 2) == 1) {
1983 if (((byte_y
/ 8) % 2) == 0) {
1995 intel_miptree_updownsample(struct brw_context
*brw
,
1996 struct intel_mipmap_tree
*src
,
1997 struct intel_mipmap_tree
*dst
)
2000 brw_blorp_blit_miptrees(brw
,
2001 src
, 0 /* level */, 0 /* layer */, src
->format
,
2002 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2004 src
->logical_width0
, src
->logical_height0
,
2006 dst
->logical_width0
, dst
->logical_height0
,
2007 GL_NEAREST
, false, false /*mirror x, y*/);
2008 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
2009 brw_meta_stencil_updownsample(brw
, src
, dst
);
2011 brw_meta_updownsample(brw
, src
, dst
);
2014 if (src
->stencil_mt
) {
2015 if (brw
->gen
>= 8) {
2016 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
2020 brw_blorp_blit_miptrees(brw
,
2021 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2022 src
->stencil_mt
->format
,
2023 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2024 dst
->stencil_mt
->format
,
2026 src
->logical_width0
, src
->logical_height0
,
2028 dst
->logical_width0
, dst
->logical_height0
,
2029 GL_NEAREST
, false, false /*mirror x, y*/);
2034 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2036 /* CPU accesses to color buffers don't understand fast color clears, so
2037 * resolve any pending fast color clears before we map.
2039 intel_miptree_resolve_color(brw
, mt
);
2041 drm_intel_bo
*bo
= mt
->bo
;
2043 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2044 intel_batchbuffer_flush(brw
);
2046 if (mt
->tiling
!= I915_TILING_NONE
)
2047 brw_bo_map_gtt(brw
, bo
, "miptree");
2049 brw_bo_map(brw
, bo
, true, "miptree");
2055 intel_miptree_unmap_raw(struct brw_context
*brw
,
2056 struct intel_mipmap_tree
*mt
)
2058 drm_intel_bo_unmap(mt
->bo
);
2062 intel_miptree_map_gtt(struct brw_context
*brw
,
2063 struct intel_mipmap_tree
*mt
,
2064 struct intel_miptree_map
*map
,
2065 unsigned int level
, unsigned int slice
)
2067 unsigned int bw
, bh
;
2069 unsigned int image_x
, image_y
;
2070 intptr_t x
= map
->x
;
2071 intptr_t y
= map
->y
;
2073 /* For compressed formats, the stride is the number of bytes per
2074 * row of blocks. intel_miptree_get_image_offset() already does
2077 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2078 assert(y
% bh
== 0);
2081 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2086 /* Note that in the case of cube maps, the caller must have passed the
2087 * slice number referencing the face.
2089 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2093 map
->stride
= mt
->pitch
;
2094 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2097 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2098 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __FUNCTION__
,
2099 map
->x
, map
->y
, map
->w
, map
->h
,
2100 mt
, _mesa_get_format_name(mt
->format
),
2101 x
, y
, map
->ptr
, map
->stride
);
2105 intel_miptree_unmap_gtt(struct brw_context
*brw
,
2106 struct intel_mipmap_tree
*mt
,
2107 struct intel_miptree_map
*map
,
2111 intel_miptree_unmap_raw(brw
, mt
);
2115 intel_miptree_map_blit(struct brw_context
*brw
,
2116 struct intel_mipmap_tree
*mt
,
2117 struct intel_miptree_map
*map
,
2118 unsigned int level
, unsigned int slice
)
2120 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2124 INTEL_MIPTREE_TILING_NONE
,
2127 fprintf(stderr
, "Failed to allocate blit temporary\n");
2130 map
->stride
= map
->mt
->pitch
;
2132 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2133 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2134 * invalidate is set, since we'll be writing the whole rectangle from our
2135 * temporary buffer back out.
2137 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2138 if (!intel_miptree_blit(brw
,
2140 map
->x
, map
->y
, false,
2143 map
->w
, map
->h
, GL_COPY
)) {
2144 fprintf(stderr
, "Failed to blit\n");
2149 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
2151 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
2152 map
->x
, map
->y
, map
->w
, map
->h
,
2153 mt
, _mesa_get_format_name(mt
->format
),
2154 level
, slice
, map
->ptr
, map
->stride
);
2159 intel_miptree_release(&map
->mt
);
2165 intel_miptree_unmap_blit(struct brw_context
*brw
,
2166 struct intel_mipmap_tree
*mt
,
2167 struct intel_miptree_map
*map
,
2171 struct gl_context
*ctx
= &brw
->ctx
;
2173 intel_miptree_unmap_raw(brw
, map
->mt
);
2175 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2176 bool ok
= intel_miptree_blit(brw
,
2180 map
->x
, map
->y
, false,
2181 map
->w
, map
->h
, GL_COPY
);
2182 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2185 intel_miptree_release(&map
->mt
);
2189 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2191 #if defined(USE_SSE41)
2193 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2194 struct intel_mipmap_tree
*mt
,
2195 struct intel_miptree_map
*map
,
2196 unsigned int level
, unsigned int slice
)
2198 assert(map
->mode
& GL_MAP_READ_BIT
);
2199 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2201 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
2202 map
->x
, map
->y
, map
->w
, map
->h
,
2203 mt
, _mesa_get_format_name(mt
->format
),
2204 level
, slice
, map
->ptr
, map
->stride
);
2206 /* Map the original image */
2209 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2213 void *src
= intel_miptree_map_raw(brw
, mt
);
2216 src
+= image_y
* mt
->pitch
;
2217 src
+= image_x
* mt
->cpp
;
2219 /* Due to the pixel offsets for the particular image being mapped, our
2220 * src pointer may not be 16-byte aligned. However, if the pitch is
2221 * divisible by 16, then the amount by which it's misaligned will remain
2222 * consistent from row to row.
2224 assert((mt
->pitch
% 16) == 0);
2225 const int misalignment
= ((uintptr_t) src
) & 15;
2227 /* Create an untiled temporary buffer for the mapping. */
2228 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2230 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2232 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2233 /* Offset the destination so it has the same misalignment as src. */
2234 map
->ptr
= map
->buffer
+ misalignment
;
2236 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2238 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2239 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2240 void *src_ptr
= src
+ y
* mt
->pitch
;
2242 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2245 intel_miptree_unmap_raw(brw
, mt
);
2249 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2250 struct intel_mipmap_tree
*mt
,
2251 struct intel_miptree_map
*map
,
2255 _mesa_align_free(map
->buffer
);
2262 intel_miptree_map_s8(struct brw_context
*brw
,
2263 struct intel_mipmap_tree
*mt
,
2264 struct intel_miptree_map
*map
,
2265 unsigned int level
, unsigned int slice
)
2267 map
->stride
= map
->w
;
2268 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2272 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2273 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2274 * invalidate is set, since we'll be writing the whole rectangle from our
2275 * temporary buffer back out.
2277 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2278 uint8_t *untiled_s8_map
= map
->ptr
;
2279 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2280 unsigned int image_x
, image_y
;
2282 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2284 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2285 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2286 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2287 x
+ image_x
+ map
->x
,
2288 y
+ image_y
+ map
->y
,
2289 brw
->has_swizzling
);
2290 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2294 intel_miptree_unmap_raw(brw
, mt
);
2296 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
2297 map
->x
, map
->y
, map
->w
, map
->h
,
2298 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2300 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
2301 map
->x
, map
->y
, map
->w
, map
->h
,
2302 mt
, map
->ptr
, map
->stride
);
2307 intel_miptree_unmap_s8(struct brw_context
*brw
,
2308 struct intel_mipmap_tree
*mt
,
2309 struct intel_miptree_map
*map
,
2313 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2314 unsigned int image_x
, image_y
;
2315 uint8_t *untiled_s8_map
= map
->ptr
;
2316 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2318 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2320 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2321 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2322 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2325 brw
->has_swizzling
);
2326 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2330 intel_miptree_unmap_raw(brw
, mt
);
2337 intel_miptree_map_etc(struct brw_context
*brw
,
2338 struct intel_mipmap_tree
*mt
,
2339 struct intel_miptree_map
*map
,
2343 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2344 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2345 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2348 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2349 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2351 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2352 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2353 map
->w
, map
->h
, 1));
2354 map
->ptr
= map
->buffer
;
2358 intel_miptree_unmap_etc(struct brw_context
*brw
,
2359 struct intel_mipmap_tree
*mt
,
2360 struct intel_miptree_map
*map
,
2366 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2371 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2372 + image_y
* mt
->pitch
2373 + image_x
* mt
->cpp
;
2375 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2376 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2377 map
->ptr
, map
->stride
,
2380 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2381 map
->ptr
, map
->stride
,
2382 map
->w
, map
->h
, mt
->etc_format
);
2384 intel_miptree_unmap_raw(brw
, mt
);
2389 * Mapping function for packed depth/stencil miptrees backed by real separate
2390 * miptrees for depth and stencil.
2392 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2393 * separate from the depth buffer. Yet at the GL API level, we have to expose
2394 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2395 * be able to map that memory for texture storage and glReadPixels-type
2396 * operations. We give Mesa core that access by mallocing a temporary and
2397 * copying the data between the actual backing store and the temporary.
2400 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2401 struct intel_mipmap_tree
*mt
,
2402 struct intel_miptree_map
*map
,
2403 unsigned int level
, unsigned int slice
)
2405 struct intel_mipmap_tree
*z_mt
= mt
;
2406 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2407 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2408 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2410 map
->stride
= map
->w
* packed_bpp
;
2411 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2415 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2416 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2417 * invalidate is set, since we'll be writing the whole rectangle from our
2418 * temporary buffer back out.
2420 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2421 uint32_t *packed_map
= map
->ptr
;
2422 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2423 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2424 unsigned int s_image_x
, s_image_y
;
2425 unsigned int z_image_x
, z_image_y
;
2427 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2428 &s_image_x
, &s_image_y
);
2429 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2430 &z_image_x
, &z_image_y
);
2432 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2433 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2434 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2435 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2438 brw
->has_swizzling
);
2439 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2441 (map_x
+ z_image_x
));
2442 uint8_t s
= s_map
[s_offset
];
2443 uint32_t z
= z_map
[z_offset
];
2445 if (map_z32f_x24s8
) {
2446 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2447 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2449 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2454 intel_miptree_unmap_raw(brw
, s_mt
);
2455 intel_miptree_unmap_raw(brw
, z_mt
);
2457 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2459 map
->x
, map
->y
, map
->w
, map
->h
,
2460 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2461 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2462 map
->ptr
, map
->stride
);
2464 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
2465 map
->x
, map
->y
, map
->w
, map
->h
,
2466 mt
, map
->ptr
, map
->stride
);
2471 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2472 struct intel_mipmap_tree
*mt
,
2473 struct intel_miptree_map
*map
,
2477 struct intel_mipmap_tree
*z_mt
= mt
;
2478 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2479 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2481 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2482 uint32_t *packed_map
= map
->ptr
;
2483 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2484 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2485 unsigned int s_image_x
, s_image_y
;
2486 unsigned int z_image_x
, z_image_y
;
2488 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2489 &s_image_x
, &s_image_y
);
2490 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2491 &z_image_x
, &z_image_y
);
2493 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2494 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2495 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2496 x
+ s_image_x
+ map
->x
,
2497 y
+ s_image_y
+ map
->y
,
2498 brw
->has_swizzling
);
2499 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2501 (x
+ z_image_x
+ map
->x
));
2503 if (map_z32f_x24s8
) {
2504 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2505 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2507 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2508 s_map
[s_offset
] = packed
>> 24;
2509 z_map
[z_offset
] = packed
;
2514 intel_miptree_unmap_raw(brw
, s_mt
);
2515 intel_miptree_unmap_raw(brw
, z_mt
);
2517 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2519 map
->x
, map
->y
, map
->w
, map
->h
,
2520 z_mt
, _mesa_get_format_name(z_mt
->format
),
2521 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2522 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2523 map
->ptr
, map
->stride
);
2530 * Create and attach a map to the miptree at (level, slice). Return the
2533 static struct intel_miptree_map
*
2534 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2543 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2548 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2549 mt
->level
[level
].slice
[slice
].map
= map
;
2561 * Release the map at (level, slice).
2564 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2568 struct intel_miptree_map
**map
;
2570 map
= &mt
->level
[level
].slice
[slice
].map
;
2576 can_blit_slice(struct intel_mipmap_tree
*mt
,
2577 unsigned int level
, unsigned int slice
)
2581 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2582 if (image_x
>= 32768 || image_y
>= 32768)
2585 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2586 if (mt
->pitch
>= 32768)
2593 use_intel_mipree_map_blit(struct brw_context
*brw
,
2594 struct intel_mipmap_tree
*mt
,
2600 /* It's probably not worth swapping to the blit ring because of
2601 * all the overhead involved.
2603 !(mode
& GL_MAP_WRITE_BIT
) &&
2605 (mt
->tiling
== I915_TILING_X
||
2606 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2607 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
)) &&
2608 can_blit_slice(mt
, level
, slice
))
2611 if (mt
->tiling
!= I915_TILING_NONE
&&
2612 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2613 assert(can_blit_slice(mt
, level
, slice
));
2621 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2622 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2623 * arithmetic overflow.
2625 * If you call this function and use \a out_stride, then you're doing pointer
2626 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2627 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2628 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2629 * which usually have type uint32_t or GLuint.
2632 intel_miptree_map(struct brw_context
*brw
,
2633 struct intel_mipmap_tree
*mt
,
2642 ptrdiff_t *out_stride
)
2644 struct intel_miptree_map
*map
;
2646 assert(mt
->num_samples
<= 1);
2648 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2655 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2656 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2657 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2660 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2661 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2662 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2663 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2664 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2665 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2666 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2667 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2668 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2669 #if defined(USE_SSE41)
2670 } else if (!(mode
& GL_MAP_WRITE_BIT
) && !mt
->compressed
&& cpu_has_sse4_1
) {
2671 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2674 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2677 *out_ptr
= map
->ptr
;
2678 *out_stride
= map
->stride
;
2680 if (map
->ptr
== NULL
)
2681 intel_miptree_release_map(mt
, level
, slice
);
2685 intel_miptree_unmap(struct brw_context
*brw
,
2686 struct intel_mipmap_tree
*mt
,
2690 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2692 assert(mt
->num_samples
<= 1);
2697 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
2698 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2700 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2701 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2702 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2703 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2704 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2705 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2706 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2707 } else if (map
->mt
) {
2708 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2709 #if defined(USE_SSE41)
2710 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2711 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2714 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2717 intel_miptree_release_map(mt
, level
, slice
);