2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_tex.h"
32 #include "intel_blit.h"
33 #include "intel_fbo.h"
35 #include "brw_blorp.h"
36 #include "brw_context.h"
37 #include "brw_state.h"
39 #include "main/enums.h"
40 #include "main/fbobject.h"
41 #include "main/formats.h"
42 #include "main/glformats.h"
43 #include "main/texcompress_etc.h"
44 #include "main/teximage.h"
45 #include "main/streaming-load-memcpy.h"
46 #include "x86/common_x86_asm.h"
48 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
50 static void *intel_miptree_map_raw(struct brw_context
*brw
,
51 struct intel_mipmap_tree
*mt
,
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 enum intel_aux_disable aux_disable
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (aux_disable
& INTEL_AUX_DISABLE_MCS
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
105 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
108 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
109 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
111 * - Support is limited to tiled render targets.
113 * Gen9 changes the restriction to Y-tile only.
116 return tiling
== I915_TILING_Y
;
117 else if (brw
->gen
>= 7)
118 return tiling
!= I915_TILING_NONE
;
124 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
125 * can be used. This doesn't (and should not) inspect any of the properties of
128 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
129 * beneath the "Fast Color Clear" bullet (p326):
131 * - Support is for non-mip-mapped and non-array surface types only.
133 * And then later, on p327:
135 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
138 * From the Skylake documentation, it is made clear that X-tiling is no longer
141 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
145 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
146 const struct intel_mipmap_tree
*mt
)
148 /* MCS support does not exist prior to Gen7 */
152 if (mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
)
155 /* This function applies only to non-multisampled render targets. */
156 if (mt
->num_samples
> 1)
159 /* MCS is only supported for color buffers */
160 switch (_mesa_get_format_base_format(mt
->format
)) {
161 case GL_DEPTH_COMPONENT
:
162 case GL_DEPTH_STENCIL
:
163 case GL_STENCIL_INDEX
:
167 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
170 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
171 const bool arrayed
= mt
->physical_depth0
!= 1;
174 /* Multisample surfaces with the CMS layout are not layered surfaces,
175 * yet still have physical_depth0 > 1. Assert that we don't
176 * accidentally reject a multisampled surface here. We should have
177 * rejected it earlier by explicitly checking the sample count.
179 assert(mt
->num_samples
<= 1);
182 /* Handle the hardware restrictions...
184 * All GENs have the following restriction: "MCS buffer for non-MSRT is
185 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
187 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
188 * Non-MultiSampler Render Target Restrictions) Support is for
189 * non-mip-mapped and non-array surface types only.
191 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
192 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
193 * surfaces are supported with MCS buffer layout with these alignments in
194 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
196 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
197 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
198 * surfaces are supported with MCS buffer layout with these alignments in
199 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
201 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
204 /* There's no point in using an MCS buffer if the surface isn't in a
207 if (!brw
->mesa_format_supports_render
[mt
->format
])
211 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
212 const enum isl_format isl_format
=
213 brw_isl_format_for_mesa_format(linear_format
);
214 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
219 /* On Gen9 support for color buffer compression was extended to single
220 * sampled surfaces. This is a helper considering both auxiliary buffer
221 * type and number of samples telling if the given miptree represents
222 * the new single sampled case - also called lossless compression.
225 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
226 const struct intel_mipmap_tree
*mt
)
228 /* Only available from Gen9 onwards. */
232 /* Compression always requires auxiliary buffer. */
236 /* Single sample compression is represented re-using msaa compression
237 * layout type: "Compressed Multisampled Surfaces".
239 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
242 /* And finally distinguish between msaa and single sample case. */
243 return mt
->num_samples
<= 1;
247 intel_miptree_supports_lossless_compressed(struct brw_context
*brw
,
248 const struct intel_mipmap_tree
*mt
)
250 /* For now compression is only enabled for integer formats even though
251 * there exist supported floating point formats also. This is a heuristic
252 * decision based on current public benchmarks. In none of the cases these
253 * formats provided any improvement but a few cases were seen to regress.
254 * Hence these are left to to be enabled in the future when they are known
257 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
260 /* Fast clear mechanism and lossless compression go hand in hand. */
261 if (!intel_miptree_supports_non_msrt_fast_clear(brw
, mt
))
264 /* Fast clear can be also used to clear srgb surfaces by using equivalent
265 * linear format. This trick, however, can't be extended to be used with
266 * lossless compression and therefore a check is needed to see if the format
269 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
273 * Determine depth format corresponding to a depth+stencil format,
274 * for separate stencil.
277 intel_depth_format_for_depthstencil_format(mesa_format format
) {
279 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
280 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
281 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
282 return MESA_FORMAT_Z_FLOAT32
;
289 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
290 unsigned depth0
, struct intel_mipmap_level
*table
)
292 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
294 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
296 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
297 if (!table
[level
].slice
)
304 for (unsigned level
= first_level
; level
<= last_level
; level
++)
305 free(table
[level
].slice
);
311 * @param for_bo Indicates that the caller is
312 * intel_miptree_create_for_bo(). If true, then do not create
315 static struct intel_mipmap_tree
*
316 intel_miptree_create_layout(struct brw_context
*brw
,
325 uint32_t layout_flags
)
327 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
331 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
332 _mesa_enum_to_string(target
),
333 _mesa_get_format_name(format
),
334 first_level
, last_level
, depth0
, mt
);
336 if (target
== GL_TEXTURE_1D_ARRAY
)
337 assert(height0
== 1);
341 mt
->first_level
= first_level
;
342 mt
->last_level
= last_level
;
343 mt
->logical_width0
= width0
;
344 mt
->logical_height0
= height0
;
345 mt
->logical_depth0
= depth0
;
346 mt
->aux_disable
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0 ?
347 INTEL_AUX_DISABLE_ALL
: INTEL_AUX_DISABLE_NONE
;
348 mt
->aux_disable
|= INTEL_AUX_DISABLE_CCS
;
349 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
350 mt
->aux_state
= NULL
;
351 mt
->cpp
= _mesa_get_format_bytes(format
);
352 mt
->num_samples
= num_samples
;
353 mt
->compressed
= _mesa_is_format_compressed(format
);
354 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
357 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
358 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
360 int depth_multiply
= 1;
361 if (num_samples
> 1) {
362 /* Adjust width/height/depth for MSAA */
363 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->aux_disable
);
364 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
365 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
366 * "If the surface is multisampled and it is a depth or stencil
367 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
368 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
371 * +----------------------------------------------------------------+
372 * | Num Multisamples | W_l = | H_l = |
373 * +----------------------------------------------------------------+
374 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
375 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
376 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
377 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
378 * +----------------------------------------------------------------+
381 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
382 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
383 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
385 * Another more complicated explanation for these adjustments comes
386 * from the Sandybridge PRM, volume 4, part 1, page 31:
388 * "Any of the other messages (sample*, LOD, load4) used with a
389 * (4x) multisampled surface will in-effect sample a surface with
390 * double the height and width as that indicated in the surface
391 * state. Each pixel position on the original-sized surface is
392 * replaced with a 2x2 of samples with the following arrangement:
397 * Thus, when sampling from a multisampled texture, it behaves as
398 * though the layout in memory for (x,y,sample) is:
400 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
401 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
403 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
404 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
406 * However, the actual layout of multisampled data in memory is:
408 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
409 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
411 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
412 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
414 * This pattern repeats for each 2x2 pixel block.
416 * As a result, when calculating the size of our 4-sample buffer for
417 * an odd width or height, we have to align before scaling up because
418 * sample 3 is in that bottom right 2x2 block.
420 switch (num_samples
) {
422 assert(brw
->gen
>= 8);
423 width0
= ALIGN(width0
, 2) * 2;
424 height0
= ALIGN(height0
, 2);
427 width0
= ALIGN(width0
, 2) * 2;
428 height0
= ALIGN(height0
, 2) * 2;
431 width0
= ALIGN(width0
, 2) * 4;
432 height0
= ALIGN(height0
, 2) * 2;
435 width0
= ALIGN(width0
, 2) * 4;
436 height0
= ALIGN(height0
, 2) * 4;
439 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
442 unreachable("not reached");
445 /* Non-interleaved */
446 depth_multiply
= num_samples
;
447 depth0
*= depth_multiply
;
451 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
457 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
458 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
459 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
460 * used on Gen8 to make it pick a qpitch value which doesn't include space
461 * for the mipmaps. On Gen9 this is not necessary because it will
462 * automatically pick a packed qpitch value whenever mt->first_level ==
464 * TODO: can we use it elsewhere?
465 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
468 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
470 switch (mt
->msaa_layout
) {
471 case INTEL_MSAA_LAYOUT_NONE
:
472 case INTEL_MSAA_LAYOUT_IMS
:
473 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
475 case INTEL_MSAA_LAYOUT_UMS
:
476 case INTEL_MSAA_LAYOUT_CMS
:
477 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
482 if (target
== GL_TEXTURE_CUBE_MAP
)
483 assert(depth0
== 6 * depth_multiply
);
485 mt
->physical_width0
= width0
;
486 mt
->physical_height0
= height0
;
487 mt
->physical_depth0
= depth0
;
489 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
490 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
491 (brw
->must_use_separate_stencil
||
492 (brw
->has_separate_stencil
&&
493 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
494 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
496 stencil_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
499 mt
->stencil_mt
= intel_miptree_create(brw
,
510 if (!mt
->stencil_mt
) {
511 intel_miptree_release(&mt
);
514 mt
->stencil_mt
->r8stencil_needs_update
= true;
516 /* Fix up the Z miptree format for how we're splitting out separate
517 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
519 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
522 if (format
== mt
->format
) {
523 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
524 _mesa_get_format_name(mt
->format
));
528 if (layout_flags
& MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
)
529 mt
->array_layout
= GEN6_HIZ_STENCIL
;
532 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
533 * multisampled or have an AUX buffer attached to it.
535 * GEN | MSRT | AUX_CCS_* or AUX_MCS
536 * -------------------------------------------
537 * 9 | HALIGN_16 | HALIGN_16
538 * 8 | HALIGN_ANY | HALIGN_16
542 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
543 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
544 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
545 } else if (brw
->gen
>= 9 && num_samples
> 1) {
546 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
548 const UNUSED
bool is_lossless_compressed_aux
=
549 brw
->gen
>= 9 && num_samples
== 1 &&
550 mt
->format
== MESA_FORMAT_R_UINT32
;
552 /* For now, nothing else has this requirement */
553 assert(is_lossless_compressed_aux
||
554 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
557 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
558 intel_miptree_release(&mt
);
562 if (mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
)
563 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
570 * Choose an appropriate uncompressed format for a requested
571 * compressed format, if unsupported.
574 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
576 /* No need to lower ETC formats on these platforms,
577 * they are supported natively.
579 if (brw
->gen
>= 8 || brw
->is_baytrail
)
583 case MESA_FORMAT_ETC1_RGB8
:
584 return MESA_FORMAT_R8G8B8X8_UNORM
;
585 case MESA_FORMAT_ETC2_RGB8
:
586 return MESA_FORMAT_R8G8B8X8_UNORM
;
587 case MESA_FORMAT_ETC2_SRGB8
:
588 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
589 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
590 return MESA_FORMAT_B8G8R8A8_SRGB
;
591 case MESA_FORMAT_ETC2_RGBA8_EAC
:
592 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
593 return MESA_FORMAT_R8G8B8A8_UNORM
;
594 case MESA_FORMAT_ETC2_R11_EAC
:
595 return MESA_FORMAT_R_UNORM16
;
596 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
597 return MESA_FORMAT_R_SNORM16
;
598 case MESA_FORMAT_ETC2_RG11_EAC
:
599 return MESA_FORMAT_R16G16_UNORM
;
600 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
601 return MESA_FORMAT_R16G16_SNORM
;
603 /* Non ETC1 / ETC2 format */
608 /** \brief Assert that the level and layer are valid for the miptree. */
610 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
618 assert(level
>= mt
->first_level
);
619 assert(level
<= mt
->last_level
);
621 if (mt
->surf
.size
> 0)
622 assert(layer
< (mt
->surf
.dim
== ISL_SURF_DIM_3D
?
623 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
624 mt
->surf
.phys_level0_sa
.array_len
));
626 assert(layer
< mt
->level
[level
].depth
);
629 static enum isl_aux_state
**
630 create_aux_state_map(struct intel_mipmap_tree
*mt
,
631 enum isl_aux_state initial
)
633 const uint32_t levels
= mt
->last_level
+ 1;
635 uint32_t total_slices
= 0;
636 for (uint32_t level
= 0; level
< levels
; level
++)
637 total_slices
+= mt
->level
[level
].depth
;
639 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
641 /* We're going to allocate a single chunk of data for both the per-level
642 * reference array and the arrays of aux_state. This makes cleanup
643 * significantly easier.
645 const size_t total_size
= per_level_array_size
+
646 total_slices
* sizeof(enum isl_aux_state
);
647 void *data
= malloc(total_size
);
651 enum isl_aux_state
**per_level_arr
= data
;
652 enum isl_aux_state
*s
= data
+ per_level_array_size
;
653 for (uint32_t level
= 0; level
< levels
; level
++) {
654 per_level_arr
[level
] = s
;
655 for (uint32_t a
= 0; a
< mt
->level
[level
].depth
; a
++)
658 assert((void *)s
== data
+ total_size
);
660 return per_level_arr
;
664 free_aux_state_map(enum isl_aux_state
**state
)
669 static struct intel_mipmap_tree
*
670 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
671 unsigned first_level
, unsigned last_level
,
672 unsigned width0
, unsigned height0
, unsigned depth0
,
673 unsigned num_samples
, enum isl_tiling isl_tiling
,
674 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
677 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
681 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
687 if (target
== GL_TEXTURE_CUBE_MAP
||
688 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
689 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
691 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
693 _mesa_enum_to_string(target
),
694 _mesa_get_format_name(format
),
695 num_samples
, width0
, height0
, depth0
,
696 first_level
, last_level
, mt
);
698 struct isl_surf_init_info init_info
= {
699 .dim
= get_isl_surf_dim(target
),
700 .format
= translate_tex_format(brw
, format
, false),
703 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
704 .levels
= last_level
- first_level
+ 1,
705 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
706 .samples
= MAX2(num_samples
, 1),
707 .usage
= isl_usage_flags
,
708 .tiling_flags
= 1u << isl_tiling
711 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
714 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
717 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
719 isl_tiling_to_bufmgr_tiling(isl_tiling
),
720 mt
->surf
.row_pitch
, alloc_flags
);
727 mt
->first_level
= first_level
;
728 mt
->last_level
= last_level
;
732 mt
->aux_state
= NULL
;
737 intel_miptree_release(&mt
);
741 static struct intel_mipmap_tree
*
742 miptree_create(struct brw_context
*brw
,
751 uint32_t layout_flags
)
753 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
754 return make_surface(brw
, target
, format
, first_level
, last_level
,
755 width0
, height0
, depth0
, num_samples
, ISL_TILING_W
,
756 ISL_SURF_USAGE_STENCIL_BIT
|
757 ISL_SURF_USAGE_TEXTURE_BIT
,
758 BO_ALLOC_FOR_RENDER
, NULL
);
760 struct intel_mipmap_tree
*mt
;
761 mesa_format tex_format
= format
;
762 mesa_format etc_format
= MESA_FORMAT_NONE
;
763 uint32_t alloc_flags
= 0;
765 format
= intel_lower_compressed_format(brw
, format
);
767 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
769 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
770 mt
= intel_miptree_create_layout(brw
, target
, format
,
771 first_level
, last_level
, width0
,
772 height0
, depth0
, num_samples
,
777 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
778 mt
->tiling
= I915_TILING_Y
;
780 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
781 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
783 mt
->etc_format
= etc_format
;
785 if (format
== MESA_FORMAT_S_UINT8
) {
786 /* Align to size of W tile, 64x64. */
787 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
788 ALIGN(mt
->total_width
, 64),
789 ALIGN(mt
->total_height
, 64),
790 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
793 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
794 mt
->total_width
, mt
->total_height
,
795 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
799 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
800 mt
->bo
->cache_coherent
= false;
805 struct intel_mipmap_tree
*
806 intel_miptree_create(struct brw_context
*brw
,
815 uint32_t layout_flags
)
817 struct intel_mipmap_tree
*mt
= miptree_create(
819 first_level
, last_level
,
820 width0
, height0
, depth0
, num_samples
,
823 /* If the BO is too large to fit in the aperture, we need to use the
824 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
825 * handle Y-tiling, so we need to fall back to X.
827 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
828 mt
->tiling
== I915_TILING_Y
) {
829 const uint32_t alloc_flags
=
830 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
831 BO_ALLOC_FOR_RENDER
: 0;
832 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
833 mt
->total_width
, mt
->total_height
);
835 mt
->tiling
= I915_TILING_X
;
836 brw_bo_unreference(mt
->bo
);
837 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
838 mt
->total_width
, mt
->total_height
, mt
->cpp
,
839 mt
->tiling
, &mt
->pitch
, alloc_flags
);
845 intel_miptree_release(&mt
);
850 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
851 assert(mt
->num_samples
> 1);
852 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
853 intel_miptree_release(&mt
);
858 /* If this miptree is capable of supporting fast color clears, set
859 * fast_clear_state appropriately to ensure that fast clears will occur.
860 * Allocation of the MCS miptree will be deferred until the first fast
861 * clear actually occurs or when compressed single sampled buffer is
862 * written by the GPU for the first time.
864 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
865 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
866 mt
->aux_disable
&= ~INTEL_AUX_DISABLE_CCS
;
867 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
869 /* On Gen9+ clients are not currently capable of consuming compressed
870 * single-sampled buffers. Disabling compression allows us to skip
873 const bool lossless_compression_disabled
= INTEL_DEBUG
& DEBUG_NO_RBC
;
874 const bool is_lossless_compressed
=
875 unlikely(!lossless_compression_disabled
) &&
876 brw
->gen
>= 9 && !mt
->is_scanout
&&
877 intel_miptree_supports_lossless_compressed(brw
, mt
);
879 if (is_lossless_compressed
) {
880 intel_miptree_alloc_non_msrt_mcs(brw
, mt
, is_lossless_compressed
);
887 struct intel_mipmap_tree
*
888 intel_miptree_create_for_bo(struct brw_context
*brw
,
896 uint32_t layout_flags
)
898 struct intel_mipmap_tree
*mt
;
899 uint32_t tiling
, swizzle
;
900 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
902 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
) {
903 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
904 0, 0, width
, height
, depth
, 1, ISL_TILING_W
,
905 ISL_SURF_USAGE_STENCIL_BIT
|
906 ISL_SURF_USAGE_TEXTURE_BIT
,
907 BO_ALLOC_FOR_RENDER
, bo
);
911 assert(bo
->size
>= mt
->surf
.size
);
913 brw_bo_reference(bo
);
917 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
919 /* Nothing will be able to use this miptree with the BO if the offset isn't
922 if (tiling
!= I915_TILING_NONE
)
923 assert(offset
% 4096 == 0);
925 /* miptrees can't handle negative pitch. If you need flipping of images,
926 * that's outside of the scope of the mt.
930 /* The BO already has a tiling format and we shouldn't confuse the lower
931 * layers by making it try to find a tiling format again.
933 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
934 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
936 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
937 mt
= intel_miptree_create_layout(brw
, target
, format
,
939 width
, height
, depth
, 0,
944 brw_bo_reference(bo
);
954 * For a singlesample renderbuffer, this simply wraps the given BO with a
957 * For a multisample renderbuffer, this wraps the window system's
958 * (singlesample) BO with a singlesample miptree attached to the
959 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
960 * that will contain the actual rendering (which is lazily resolved to
961 * irb->singlesample_mt).
964 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
965 struct intel_renderbuffer
*irb
,
967 uint32_t width
, uint32_t height
,
970 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
971 struct intel_mipmap_tree
*multisample_mt
= NULL
;
972 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
973 mesa_format format
= rb
->Format
;
974 int num_samples
= rb
->NumSamples
;
976 /* Only the front and back buffers, which are color buffers, are allocated
977 * through the image loader.
979 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
980 _mesa_get_format_base_format(format
) == GL_RGBA
);
982 singlesample_mt
= intel_miptree_create_for_bo(intel
,
990 MIPTREE_LAYOUT_FOR_SCANOUT
);
991 if (!singlesample_mt
)
994 /* If this miptree is capable of supporting fast color clears, set
995 * mcs_state appropriately to ensure that fast clears will occur.
996 * Allocation of the MCS miptree will be deferred until the first fast
997 * clear actually occurs.
999 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
1000 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
1001 singlesample_mt
->aux_disable
&= ~INTEL_AUX_DISABLE_CCS
;
1004 if (num_samples
== 0) {
1005 intel_miptree_release(&irb
->mt
);
1006 irb
->mt
= singlesample_mt
;
1008 assert(!irb
->singlesample_mt
);
1010 intel_miptree_release(&irb
->singlesample_mt
);
1011 irb
->singlesample_mt
= singlesample_mt
;
1014 irb
->mt
->logical_width0
!= width
||
1015 irb
->mt
->logical_height0
!= height
) {
1016 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1021 if (!multisample_mt
)
1024 irb
->need_downsample
= false;
1025 intel_miptree_release(&irb
->mt
);
1026 irb
->mt
= multisample_mt
;
1032 intel_miptree_release(&irb
->singlesample_mt
);
1033 intel_miptree_release(&irb
->mt
);
1037 struct intel_mipmap_tree
*
1038 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1042 uint32_t num_samples
)
1044 struct intel_mipmap_tree
*mt
;
1047 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1048 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1049 MIPTREE_LAYOUT_TILING_ANY
|
1050 MIPTREE_LAYOUT_FOR_SCANOUT
;
1052 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1053 width
, height
, depth
, num_samples
,
1058 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
1059 ok
= intel_miptree_alloc_hiz(brw
, mt
);
1067 intel_miptree_release(&mt
);
1072 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1073 struct intel_mipmap_tree
*src
)
1078 intel_miptree_release(dst
);
1082 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1089 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1091 if (aux_buf
== NULL
)
1094 brw_bo_unreference(aux_buf
->bo
);
1100 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1105 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1106 if (--(*mt
)->refcount
<= 0) {
1109 DBG("%s deleting %p\n", __func__
, *mt
);
1111 brw_bo_unreference((*mt
)->bo
);
1112 intel_miptree_release(&(*mt
)->stencil_mt
);
1113 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1114 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1115 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1116 free_aux_state_map((*mt
)->aux_state
);
1118 intel_miptree_release(&(*mt
)->plane
[0]);
1119 intel_miptree_release(&(*mt
)->plane
[1]);
1121 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1122 free((*mt
)->level
[i
].slice
);
1132 intel_get_image_dims(struct gl_texture_image
*image
,
1133 int *width
, int *height
, int *depth
)
1135 switch (image
->TexObject
->Target
) {
1136 case GL_TEXTURE_1D_ARRAY
:
1137 /* For a 1D Array texture the OpenGL API will treat the image height as
1138 * the number of array slices. For Intel hardware, we treat the 1D array
1139 * as a 2D Array with a height of 1. So, here we want to swap image
1142 assert(image
->Depth
== 1);
1143 *width
= image
->Width
;
1145 *depth
= image
->Height
;
1147 case GL_TEXTURE_CUBE_MAP
:
1148 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1149 * though we really have 6 slices.
1151 assert(image
->Depth
== 1);
1152 *width
= image
->Width
;
1153 *height
= image
->Height
;
1157 *width
= image
->Width
;
1158 *height
= image
->Height
;
1159 *depth
= image
->Depth
;
1165 * Can the image be pulled into a unified mipmap tree? This mirrors
1166 * the completeness test in a lot of ways.
1168 * Not sure whether I want to pass gl_texture_image here.
1171 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1172 struct gl_texture_image
*image
)
1174 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1175 GLuint level
= intelImage
->base
.Base
.Level
;
1176 int width
, height
, depth
;
1178 /* glTexImage* choose the texture object based on the target passed in, and
1179 * objects can't change targets over their lifetimes, so this should be
1182 assert(image
->TexObject
->Target
== mt
->target
);
1184 mesa_format mt_format
= mt
->format
;
1185 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1186 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1187 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1188 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1189 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1190 mt_format
= mt
->etc_format
;
1192 if (image
->TexFormat
!= mt_format
)
1195 intel_get_image_dims(image
, &width
, &height
, &depth
);
1197 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1200 if (mt
->surf
.size
> 0) {
1201 if (level
>= mt
->surf
.levels
)
1204 const unsigned level_depth
=
1205 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1206 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1207 mt
->surf
.logical_level0_px
.array_len
;
1209 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1210 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1211 depth
== level_depth
&&
1212 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1215 int level_depth
= mt
->level
[level
].depth
;
1216 if (mt
->num_samples
> 1) {
1217 switch (mt
->msaa_layout
) {
1218 case INTEL_MSAA_LAYOUT_NONE
:
1219 case INTEL_MSAA_LAYOUT_IMS
:
1221 case INTEL_MSAA_LAYOUT_UMS
:
1222 case INTEL_MSAA_LAYOUT_CMS
:
1223 level_depth
/= mt
->num_samples
;
1228 /* Test image dimensions against the base level image adjusted for
1229 * minification. This will also catch images not present in the
1230 * tree, changed targets, etc.
1232 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1233 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1234 depth
!= level_depth
) {
1238 if (image
->NumSamples
!= mt
->num_samples
)
1246 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1248 GLuint x
, GLuint y
, GLuint d
)
1250 mt
->level
[level
].depth
= d
;
1251 mt
->level
[level
].level_x
= x
;
1252 mt
->level
[level
].level_y
= y
;
1254 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1257 assert(mt
->level
[level
].slice
);
1259 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1260 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1265 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1266 GLuint level
, GLuint img
,
1269 if (img
== 0 && level
== 0)
1270 assert(x
== 0 && y
== 0);
1272 assert(img
< mt
->level
[level
].depth
);
1274 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1275 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1277 DBG("%s level %d img %d pos %d,%d\n",
1278 __func__
, level
, img
,
1279 mt
->level
[level
].slice
[img
].x_offset
,
1280 mt
->level
[level
].slice
[img
].y_offset
);
1284 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1285 GLuint level
, GLuint slice
,
1286 GLuint
*x
, GLuint
*y
)
1288 if (mt
->surf
.size
> 0) {
1289 uint32_t x_offset_sa
, y_offset_sa
;
1291 /* Given level is relative to level zero while the miptree may be
1292 * represent just a subset of all levels starting from 'first_level'.
1294 assert(level
>= mt
->first_level
);
1295 level
-= mt
->first_level
;
1297 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1298 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1299 isl_surf_get_image_offset_sa(&mt
->surf
, level
, slice
, z
,
1300 &x_offset_sa
, &y_offset_sa
);
1307 assert(slice
< mt
->level
[level
].depth
);
1309 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1310 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1315 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1316 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1317 * and tile_h is set to 1.
1320 intel_get_tile_dims(uint32_t tiling
, uint32_t cpp
,
1321 uint32_t *tile_w
, uint32_t *tile_h
)
1332 case I915_TILING_NONE
:
1337 unreachable("not reached");
1343 * This function computes masks that may be used to select the bits of the X
1344 * and Y coordinates that indicate the offset within a tile. If the BO is
1345 * untiled, the masks are set to 0.
1348 intel_get_tile_masks(uint32_t tiling
, uint32_t cpp
,
1349 uint32_t *mask_x
, uint32_t *mask_y
)
1351 uint32_t tile_w_bytes
, tile_h
;
1353 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1355 *mask_x
= tile_w_bytes
/ cpp
- 1;
1356 *mask_y
= tile_h
- 1;
1360 * Compute the offset (in bytes) from the start of the BO to the given x
1361 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1362 * multiples of the tile size.
1365 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1366 uint32_t x
, uint32_t y
)
1369 uint32_t pitch
= mt
->pitch
;
1370 uint32_t tiling
= mt
->tiling
;
1374 unreachable("not reached");
1375 case I915_TILING_NONE
:
1376 return y
* pitch
+ x
* cpp
;
1378 assert((x
% (512 / cpp
)) == 0);
1379 assert((y
% 8) == 0);
1380 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1382 assert((x
% (128 / cpp
)) == 0);
1383 assert((y
% 32) == 0);
1384 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1389 * Rendering with tiled buffers requires that the base address of the buffer
1390 * be aligned to a page boundary. For renderbuffers, and sometimes with
1391 * textures, we may want the surface to point at a texture image level that
1392 * isn't at a page boundary.
1394 * This function returns an appropriately-aligned base offset
1395 * according to the tiling restrictions, plus any required x/y offset
1399 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1400 GLuint level
, GLuint slice
,
1405 uint32_t mask_x
, mask_y
;
1407 intel_get_tile_masks(mt
->tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1408 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1410 *tile_x
= x
& mask_x
;
1411 *tile_y
= y
& mask_y
;
1413 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1417 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1418 struct intel_mipmap_tree
*src_mt
,
1419 unsigned src_level
, unsigned src_layer
,
1420 struct intel_mipmap_tree
*dst_mt
,
1421 unsigned dst_level
, unsigned dst_layer
,
1422 unsigned width
, unsigned height
)
1425 ptrdiff_t src_stride
, dst_stride
;
1426 const unsigned cpp
= dst_mt
->surf
.size
> 0 ?
1427 (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8) : dst_mt
->cpp
;
1429 intel_miptree_map(brw
, src_mt
,
1430 src_level
, src_layer
,
1433 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1436 intel_miptree_map(brw
, dst_mt
,
1437 dst_level
, dst_layer
,
1440 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1444 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1445 _mesa_get_format_name(src_mt
->format
),
1446 src_mt
, src
, src_stride
,
1447 _mesa_get_format_name(dst_mt
->format
),
1448 dst_mt
, dst
, dst_stride
,
1451 int row_size
= cpp
* width
;
1452 if (src_stride
== row_size
&&
1453 dst_stride
== row_size
) {
1454 memcpy(dst
, src
, row_size
* height
);
1456 for (int i
= 0; i
< height
; i
++) {
1457 memcpy(dst
, src
, row_size
);
1463 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1464 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1466 /* Don't forget to copy the stencil data over, too. We could have skipped
1467 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1468 * shuffling the two data sources in/out of temporary storage instead of
1469 * the direct mapping we get this way.
1471 if (dst_mt
->stencil_mt
) {
1472 assert(src_mt
->stencil_mt
);
1473 intel_miptree_copy_slice_sw(brw
,
1474 src_mt
->stencil_mt
, src_level
, src_layer
,
1475 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1481 intel_miptree_copy_slice(struct brw_context
*brw
,
1482 struct intel_mipmap_tree
*src_mt
,
1483 unsigned src_level
, unsigned src_layer
,
1484 struct intel_mipmap_tree
*dst_mt
,
1485 unsigned dst_level
, unsigned dst_layer
)
1488 mesa_format format
= src_mt
->format
;
1489 uint32_t width
, height
;
1491 if (src_mt
->surf
.size
> 0) {
1492 width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1493 src_level
- src_mt
->first_level
);
1494 height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1495 src_level
- src_mt
->first_level
);
1497 if (src_mt
->surf
.dim
== ISL_SURF_DIM_3D
)
1498 assert(src_layer
< minify(src_mt
->surf
.phys_level0_sa
.depth
,
1499 src_level
- src_mt
->first_level
));
1501 assert(src_layer
< src_mt
->surf
.phys_level0_sa
.array_len
);
1503 width
= minify(src_mt
->physical_width0
,
1504 src_level
- src_mt
->first_level
);
1505 height
= minify(src_mt
->physical_height0
,
1506 src_level
- src_mt
->first_level
);
1507 assert(src_layer
< src_mt
->level
[src_level
].depth
);
1510 assert(src_mt
->format
== dst_mt
->format
);
1512 if (dst_mt
->compressed
) {
1514 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1515 height
= ALIGN_NPOT(height
, j
) / j
;
1516 width
= ALIGN_NPOT(width
, i
) / i
;
1519 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1520 * below won't apply since we can't do the depth's Y tiling or the
1521 * stencil's W tiling in the blitter.
1523 if (src_mt
->stencil_mt
) {
1524 intel_miptree_copy_slice_sw(brw
,
1525 src_mt
, src_level
, src_layer
,
1526 dst_mt
, dst_level
, dst_layer
,
1531 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1532 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1534 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1537 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1538 _mesa_get_format_name(src_mt
->format
),
1539 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1540 _mesa_get_format_name(dst_mt
->format
),
1541 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1544 if (!intel_miptree_blit(brw
,
1545 src_mt
, src_level
, src_layer
, 0, 0, false,
1546 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1547 width
, height
, GL_COPY
)) {
1548 perf_debug("miptree validate blit for %s failed\n",
1549 _mesa_get_format_name(format
));
1551 intel_miptree_copy_slice_sw(brw
,
1552 src_mt
, src_level
, src_layer
,
1553 dst_mt
, dst_level
, dst_layer
,
1559 * Copies the image's current data to the given miptree, and associates that
1560 * miptree with the image.
1562 * If \c invalidate is true, then the actual image data does not need to be
1563 * copied, but the image still needs to be associated to the new miptree (this
1564 * is set to true if we're about to clear the image).
1567 intel_miptree_copy_teximage(struct brw_context
*brw
,
1568 struct intel_texture_image
*intelImage
,
1569 struct intel_mipmap_tree
*dst_mt
,
1572 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1573 struct intel_texture_object
*intel_obj
=
1574 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1575 int level
= intelImage
->base
.Base
.Level
;
1576 const unsigned face
= intelImage
->base
.Base
.Face
;
1577 unsigned start_layer
, end_layer
;
1579 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1581 assert(intelImage
->base
.Base
.Height
);
1583 end_layer
= intelImage
->base
.Base
.Height
- 1;
1584 } else if (face
> 0) {
1588 assert(intelImage
->base
.Base
.Depth
);
1590 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1594 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1595 intel_miptree_copy_slice(brw
,
1601 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1602 intel_obj
->needs_validate
= true;
1606 intel_miptree_init_mcs(struct brw_context
*brw
,
1607 struct intel_mipmap_tree
*mt
,
1610 assert(mt
->mcs_buf
!= NULL
);
1612 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1614 * When MCS buffer is enabled and bound to MSRT, it is required that it
1615 * is cleared prior to any rendering.
1617 * Since we don't use the MCS buffer for any purpose other than rendering,
1618 * it makes sense to just clear it immediately upon allocation.
1620 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1622 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1623 if (unlikely(map
== NULL
)) {
1624 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1625 brw_bo_unreference(mt
->mcs_buf
->bo
);
1630 memset(data
, init_value
, mt
->mcs_buf
->size
);
1631 brw_bo_unmap(mt
->mcs_buf
->bo
);
1634 static struct intel_miptree_aux_buffer
*
1635 intel_alloc_aux_buffer(struct brw_context
*brw
,
1637 const struct isl_surf
*aux_surf
,
1638 uint32_t alloc_flags
,
1639 struct intel_mipmap_tree
*mt
)
1641 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1645 buf
->size
= aux_surf
->size
;
1646 buf
->pitch
= aux_surf
->row_pitch
;
1647 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1649 /* ISL has stricter set of alignment rules then the drm allocator.
1650 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1651 * trying to recalculate based on different format block sizes.
1653 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1654 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1660 buf
->surf
= *aux_surf
;
1666 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1667 struct intel_mipmap_tree
*mt
,
1670 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1671 assert(mt
->mcs_buf
== NULL
);
1672 assert((mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
) == 0);
1674 /* Multisampled miptrees are only supported for single level. */
1675 assert(mt
->first_level
== 0);
1676 enum isl_aux_state
**aux_state
=
1677 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1681 struct isl_surf temp_main_surf
;
1682 struct isl_surf temp_mcs_surf
;
1684 /* Create first an ISL presentation for the main color surface and let ISL
1685 * calculate equivalent MCS surface against it.
1687 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1688 MAYBE_UNUSED
bool ok
=
1689 isl_surf_get_mcs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_mcs_surf
);
1692 /* Buffer needs to be initialised requiring the buffer to be immediately
1693 * mapped to cpu space for writing. Therefore do not use the gpu access
1694 * flag which can cause an unnecessary delay if the backing pages happened
1695 * to be just used by the GPU.
1697 const uint32_t alloc_flags
= 0;
1698 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1699 &temp_mcs_surf
, alloc_flags
, mt
);
1705 mt
->aux_state
= aux_state
;
1707 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1713 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1714 struct intel_mipmap_tree
*mt
,
1715 bool is_lossless_compressed
)
1717 assert(mt
->mcs_buf
== NULL
);
1718 assert(!(mt
->aux_disable
& (INTEL_AUX_DISABLE_MCS
| INTEL_AUX_DISABLE_CCS
)));
1720 struct isl_surf temp_main_surf
;
1721 struct isl_surf temp_ccs_surf
;
1723 /* Create first an ISL presentation for the main color surface and let ISL
1724 * calculate equivalent CCS surface against it.
1726 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1727 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_ccs_surf
))
1730 assert(temp_ccs_surf
.size
&&
1731 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1733 enum isl_aux_state
**aux_state
=
1734 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1738 /* In case of compression mcs buffer needs to be initialised requiring the
1739 * buffer to be immediately mapped to cpu space for writing. Therefore do
1740 * not use the gpu access flag which can cause an unnecessary delay if the
1741 * backing pages happened to be just used by the GPU.
1743 const uint32_t alloc_flags
=
1744 is_lossless_compressed
? 0 : BO_ALLOC_FOR_RENDER
;
1745 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1746 &temp_ccs_surf
, alloc_flags
, mt
);
1752 mt
->aux_state
= aux_state
;
1754 /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
1755 * used for lossless compression which requires similar initialisation
1756 * as multi-sample compression.
1758 if (is_lossless_compressed
) {
1759 /* Hardware sets the auxiliary buffer to all zeroes when it does full
1760 * resolve. Initialize it accordingly in case the first renderer is
1761 * cpu (or other none compression aware party).
1763 * This is also explicitly stated in the spec (MCS Buffer for Render
1765 * "If Software wants to enable Color Compression without Fast clear,
1766 * Software needs to initialize MCS with zeros."
1768 intel_miptree_init_mcs(brw
, mt
, 0);
1769 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_CMS
;
1776 * Helper for intel_miptree_alloc_hiz() that sets
1777 * \c mt->level[level].has_hiz. Return true if and only if
1778 * \c has_hiz was set.
1781 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1782 struct intel_mipmap_tree
*mt
,
1785 assert(mt
->hiz_buf
);
1787 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1788 uint32_t width
= minify(mt
->physical_width0
, level
);
1789 uint32_t height
= minify(mt
->physical_height0
, level
);
1791 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1792 * and the height is 4 aligned. This allows our HiZ support
1793 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1794 * we can grow the width & height to allow the HiZ op to
1795 * force the proper size alignments.
1797 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1798 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1803 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1804 mt
->level
[level
].has_hiz
= true;
1809 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1810 struct intel_mipmap_tree
*mt
)
1815 if (mt
->hiz_buf
!= NULL
)
1818 if (mt
->aux_disable
& INTEL_AUX_DISABLE_HIZ
)
1821 switch (mt
->format
) {
1822 case MESA_FORMAT_Z_FLOAT32
:
1823 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1824 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1825 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1826 case MESA_FORMAT_Z_UNORM16
:
1834 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1835 struct intel_mipmap_tree
*mt
)
1837 assert(mt
->hiz_buf
== NULL
);
1838 assert((mt
->aux_disable
& INTEL_AUX_DISABLE_HIZ
) == 0);
1840 enum isl_aux_state
**aux_state
=
1841 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1845 struct isl_surf temp_main_surf
;
1846 struct isl_surf temp_hiz_surf
;
1848 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1849 MAYBE_UNUSED
bool ok
=
1850 isl_surf_get_hiz_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_hiz_surf
);
1853 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
1854 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1855 &temp_hiz_surf
, alloc_flags
, mt
);
1862 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1863 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1865 mt
->aux_state
= aux_state
;
1871 * Can the miptree sample using the hiz buffer?
1874 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1875 struct intel_mipmap_tree
*mt
)
1877 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1878 * so keep things conservative for now and never enable it unless we're SKL+.
1888 /* It seems the hardware won't fallback to the depth buffer if some of the
1889 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1890 * of the texture to be HiZ enabled.
1892 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1893 if (!intel_miptree_level_has_hiz(mt
, level
))
1897 /* If compressed multisampling is enabled, then we use it for the auxiliary
1900 * From the BDW PRM (Volume 2d: Command Reference: Structures
1901 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1903 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1904 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1906 * There is no such blurb for 1D textures, but there is sufficient evidence
1907 * that this is broken on SKL+.
1909 return (mt
->num_samples
<= 1 &&
1910 mt
->target
!= GL_TEXTURE_3D
&&
1911 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1915 * Does the miptree slice have hiz enabled?
1918 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1920 intel_miptree_check_level_layer(mt
, level
, 0);
1921 return mt
->level
[level
].has_hiz
;
1925 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1926 unsigned start_level
, unsigned num_levels
,
1927 unsigned start_layer
, unsigned num_layers
)
1929 assert(_mesa_is_format_color_format(mt
->format
));
1934 /* Clamp the level range to fit the miptree */
1935 assert(start_level
+ num_levels
>= start_level
);
1936 const uint32_t last_level
=
1937 MIN2(mt
->last_level
, start_level
+ num_levels
- 1);
1938 start_level
= MAX2(mt
->first_level
, start_level
);
1939 num_levels
= last_level
- start_level
+ 1;
1941 for (uint32_t level
= start_level
; level
<= last_level
; level
++) {
1942 const uint32_t level_layers
= MIN2(num_layers
, mt
->level
[level
].depth
);
1943 for (unsigned a
= 0; a
< level_layers
; a
++) {
1944 enum isl_aux_state aux_state
=
1945 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
1946 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
1947 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
1956 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
1957 const struct intel_mipmap_tree
*mt
,
1958 unsigned level
, unsigned layer
)
1961 if ((mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) || !mt
->mcs_buf
)
1964 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
1965 assert(brw
->gen
>= 8 ||
1966 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
1968 /* Compression of arrayed msaa surfaces is supported. */
1969 if (mt
->num_samples
> 1)
1972 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
1973 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
1979 static enum blorp_fast_clear_op
1980 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
1981 bool ccs_supported
, bool fast_clear_supported
)
1983 assert(ccs_supported
== fast_clear_supported
);
1985 switch (aux_state
) {
1986 case ISL_AUX_STATE_CLEAR
:
1987 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1989 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1991 return BLORP_FAST_CLEAR_OP_NONE
;
1993 case ISL_AUX_STATE_PASS_THROUGH
:
1994 return BLORP_FAST_CLEAR_OP_NONE
;
1996 case ISL_AUX_STATE_RESOLVED
:
1997 case ISL_AUX_STATE_AUX_INVALID
:
1998 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2002 unreachable("Invalid aux state for CCS_D");
2005 static enum blorp_fast_clear_op
2006 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2007 bool ccs_supported
, bool fast_clear_supported
)
2009 switch (aux_state
) {
2010 case ISL_AUX_STATE_CLEAR
:
2011 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2013 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2014 else if (!fast_clear_supported
)
2015 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2017 return BLORP_FAST_CLEAR_OP_NONE
;
2019 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2021 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2023 return BLORP_FAST_CLEAR_OP_NONE
;
2025 case ISL_AUX_STATE_PASS_THROUGH
:
2026 return BLORP_FAST_CLEAR_OP_NONE
;
2028 case ISL_AUX_STATE_RESOLVED
:
2029 case ISL_AUX_STATE_AUX_INVALID
:
2033 unreachable("Invalid aux state for CCS_E");
2037 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2038 struct intel_mipmap_tree
*mt
,
2039 uint32_t level
, uint32_t layer
,
2041 bool fast_clear_supported
)
2043 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2045 enum blorp_fast_clear_op resolve_op
;
2046 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
2047 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_supported
,
2048 fast_clear_supported
);
2050 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_supported
,
2051 fast_clear_supported
);
2054 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2055 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2056 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2058 switch (resolve_op
) {
2059 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2060 /* The CCS full resolve operation destroys the CCS and sets it to the
2061 * pass-through state. (You can also think of this as being both a
2062 * resolve and an ambiguate in one operation.)
2064 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2065 ISL_AUX_STATE_PASS_THROUGH
);
2068 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2069 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2070 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2074 unreachable("Invalid resolve op");
2080 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2081 struct intel_mipmap_tree
*mt
,
2082 uint32_t level
, uint32_t layer
,
2083 bool written_with_ccs
)
2085 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2087 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
2088 switch (aux_state
) {
2089 case ISL_AUX_STATE_CLEAR
:
2090 assert(written_with_ccs
);
2091 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2092 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2095 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2096 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2097 assert(written_with_ccs
);
2098 break; /* Nothing to do */
2100 case ISL_AUX_STATE_PASS_THROUGH
:
2101 if (written_with_ccs
) {
2102 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2103 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2109 case ISL_AUX_STATE_RESOLVED
:
2110 case ISL_AUX_STATE_AUX_INVALID
:
2111 unreachable("Invalid aux state for CCS_E");
2114 /* CCS_D is a bit simpler */
2115 switch (aux_state
) {
2116 case ISL_AUX_STATE_CLEAR
:
2117 assert(written_with_ccs
);
2118 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2119 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2122 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2123 assert(written_with_ccs
);
2124 break; /* Nothing to do */
2126 case ISL_AUX_STATE_PASS_THROUGH
:
2130 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2131 case ISL_AUX_STATE_RESOLVED
:
2132 case ISL_AUX_STATE_AUX_INVALID
:
2133 unreachable("Invalid aux state for CCS_D");
2139 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2140 struct intel_mipmap_tree
*mt
,
2141 uint32_t level
, uint32_t layer
,
2142 bool written_with_aux
)
2144 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2145 case ISL_AUX_STATE_CLEAR
:
2146 assert(written_with_aux
);
2147 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2148 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2151 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2152 assert(written_with_aux
);
2153 break; /* Nothing to do */
2155 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2156 case ISL_AUX_STATE_RESOLVED
:
2157 case ISL_AUX_STATE_PASS_THROUGH
:
2158 case ISL_AUX_STATE_AUX_INVALID
:
2159 unreachable("Invalid aux state for MCS");
2164 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2165 struct intel_mipmap_tree
*mt
,
2166 uint32_t level
, uint32_t layer
,
2167 bool hiz_supported
, bool fast_clear_supported
)
2169 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2170 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2171 case ISL_AUX_STATE_CLEAR
:
2172 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2173 if (!hiz_supported
|| !fast_clear_supported
)
2174 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2177 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2179 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2182 case ISL_AUX_STATE_PASS_THROUGH
:
2183 case ISL_AUX_STATE_RESOLVED
:
2186 case ISL_AUX_STATE_AUX_INVALID
:
2188 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2192 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2193 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2196 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2197 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2198 ISL_AUX_STATE_RESOLVED
);
2201 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2202 /* The HiZ resolve operation is actually an ambiguate */
2203 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2204 ISL_AUX_STATE_PASS_THROUGH
);
2208 unreachable("Invalid HiZ op");
2214 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2215 struct intel_mipmap_tree
*mt
,
2216 uint32_t level
, uint32_t layer
,
2217 bool written_with_hiz
)
2219 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2220 case ISL_AUX_STATE_CLEAR
:
2221 assert(written_with_hiz
);
2222 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2223 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2226 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2227 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2228 assert(written_with_hiz
);
2229 break; /* Nothing to do */
2231 case ISL_AUX_STATE_RESOLVED
:
2232 if (written_with_hiz
) {
2233 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2234 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2236 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2237 ISL_AUX_STATE_AUX_INVALID
);
2241 case ISL_AUX_STATE_PASS_THROUGH
:
2242 if (written_with_hiz
) {
2243 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2244 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2248 case ISL_AUX_STATE_AUX_INVALID
:
2249 assert(!written_with_hiz
);
2254 static inline uint32_t
2255 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
2256 uint32_t start_level
, uint32_t num_levels
)
2258 assert(start_level
>= mt
->first_level
);
2259 assert(start_level
<= mt
->last_level
);
2261 if (num_levels
== INTEL_REMAINING_LAYERS
)
2262 num_levels
= mt
->last_level
- start_level
+ 1;
2263 /* Check for overflow */
2264 assert(start_level
+ num_levels
>= start_level
);
2265 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2270 static inline uint32_t
2271 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2272 uint32_t start_layer
, uint32_t num_layers
)
2274 assert(level
<= mt
->last_level
);
2275 uint32_t total_num_layers
;
2277 if (mt
->surf
.size
> 0)
2278 total_num_layers
= mt
->surf
.dim
== ISL_SURF_DIM_3D
?
2279 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
2280 mt
->surf
.phys_level0_sa
.array_len
;
2282 total_num_layers
= mt
->level
[level
].depth
;
2284 assert(start_layer
< total_num_layers
);
2285 if (num_layers
== INTEL_REMAINING_LAYERS
)
2286 num_layers
= total_num_layers
- start_layer
;
2287 /* Check for overflow */
2288 assert(start_layer
+ num_layers
>= start_layer
);
2289 assert(start_layer
+ num_layers
<= total_num_layers
);
2295 intel_miptree_prepare_access(struct brw_context
*brw
,
2296 struct intel_mipmap_tree
*mt
,
2297 uint32_t start_level
, uint32_t num_levels
,
2298 uint32_t start_layer
, uint32_t num_layers
,
2299 bool aux_supported
, bool fast_clear_supported
)
2301 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2303 if (_mesa_is_format_color_format(mt
->format
)) {
2307 if (mt
->num_samples
> 1) {
2308 /* Nothing to do for MSAA */
2309 assert(aux_supported
&& fast_clear_supported
);
2311 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2312 const uint32_t level
= start_level
+ l
;
2313 const uint32_t level_layers
=
2314 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2315 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2316 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2317 start_layer
+ a
, aux_supported
,
2318 fast_clear_supported
);
2322 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2323 /* Nothing to do for stencil */
2328 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2329 const uint32_t level
= start_level
+ l
;
2330 if (!intel_miptree_level_has_hiz(mt
, level
))
2333 const uint32_t level_layers
=
2334 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2335 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2336 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2338 fast_clear_supported
);
2345 intel_miptree_finish_write(struct brw_context
*brw
,
2346 struct intel_mipmap_tree
*mt
, uint32_t level
,
2347 uint32_t start_layer
, uint32_t num_layers
,
2348 bool written_with_aux
)
2350 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2352 if (_mesa_is_format_color_format(mt
->format
)) {
2356 if (mt
->num_samples
> 1) {
2357 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2358 intel_miptree_finish_mcs_write(brw
, mt
, level
, start_layer
+ a
,
2362 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2363 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2367 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2368 /* Nothing to do for stencil */
2370 if (!intel_miptree_level_has_hiz(mt
, level
))
2373 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2374 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2381 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2382 uint32_t level
, uint32_t layer
)
2384 intel_miptree_check_level_layer(mt
, level
, layer
);
2386 if (_mesa_is_format_color_format(mt
->format
)) {
2387 assert(mt
->mcs_buf
!= NULL
);
2388 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2389 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2390 unreachable("Cannot get aux state for stencil");
2392 assert(intel_miptree_level_has_hiz(mt
, level
));
2395 return mt
->aux_state
[level
][layer
];
2399 intel_miptree_set_aux_state(struct brw_context
*brw
,
2400 struct intel_mipmap_tree
*mt
, uint32_t level
,
2401 uint32_t start_layer
, uint32_t num_layers
,
2402 enum isl_aux_state aux_state
)
2404 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2406 if (_mesa_is_format_color_format(mt
->format
)) {
2407 assert(mt
->mcs_buf
!= NULL
);
2408 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2409 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2410 unreachable("Cannot get aux state for stencil");
2412 assert(intel_miptree_level_has_hiz(mt
, level
));
2415 for (unsigned a
= 0; a
< num_layers
; a
++)
2416 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2419 /* On Gen9 color buffers may be compressed by the hardware (lossless
2420 * compression). There are, however, format restrictions and care needs to be
2421 * taken that the sampler engine is capable for re-interpreting a buffer with
2422 * format different the buffer was originally written with.
2424 * For example, SRGB formats are not compressible and the sampler engine isn't
2425 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2426 * color buffer needs to be resolved so that the sampling surface can be
2427 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2431 can_texture_with_ccs(struct brw_context
*brw
,
2432 struct intel_mipmap_tree
*mt
,
2433 mesa_format view_format
)
2435 if (!intel_miptree_is_lossless_compressed(brw
, mt
))
2438 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2439 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2441 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2442 isl_mt_format
, isl_view_format
)) {
2443 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2444 _mesa_get_format_name(view_format
),
2445 _mesa_get_format_name(mt
->format
));
2453 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2454 struct intel_mipmap_tree
*mt
,
2455 mesa_format view_format
,
2456 uint32_t start_level
, uint32_t num_levels
,
2457 uint32_t start_layer
, uint32_t num_layers
,
2458 bool *aux_supported_out
)
2460 bool aux_supported
, clear_supported
;
2461 if (_mesa_is_format_color_format(mt
->format
)) {
2462 if (mt
->num_samples
> 1) {
2463 aux_supported
= clear_supported
= true;
2465 aux_supported
= can_texture_with_ccs(brw
, mt
, view_format
);
2467 /* Clear color is specified as ints or floats and the conversion is
2468 * done by the sampler. If we have a texture view, we would have to
2469 * perform the clear color conversion manually. Just disable clear
2472 clear_supported
= aux_supported
&& (mt
->format
== view_format
);
2474 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2475 aux_supported
= clear_supported
= false;
2477 aux_supported
= clear_supported
= intel_miptree_sample_with_hiz(brw
, mt
);
2480 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2481 start_layer
, num_layers
,
2482 aux_supported
, clear_supported
);
2483 if (aux_supported_out
)
2484 *aux_supported_out
= aux_supported
;
2488 intel_miptree_prepare_texture(struct brw_context
*brw
,
2489 struct intel_mipmap_tree
*mt
,
2490 mesa_format view_format
,
2491 bool *aux_supported_out
)
2493 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2494 0, INTEL_REMAINING_LEVELS
,
2495 0, INTEL_REMAINING_LAYERS
,
2500 intel_miptree_prepare_image(struct brw_context
*brw
,
2501 struct intel_mipmap_tree
*mt
)
2503 /* The data port doesn't understand any compression */
2504 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2505 0, INTEL_REMAINING_LAYERS
, false, false);
2509 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2510 struct intel_mipmap_tree
*mt
, uint32_t level
,
2511 uint32_t start_layer
, uint32_t num_layers
)
2513 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2514 start_layer
, num_layers
, NULL
);
2518 intel_miptree_prepare_render(struct brw_context
*brw
,
2519 struct intel_mipmap_tree
*mt
, uint32_t level
,
2520 uint32_t start_layer
, uint32_t layer_count
,
2523 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2524 * the single-sampled color renderbuffers because the CCS buffer isn't
2525 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2526 * enabled because otherwise the surface state will be programmed with
2527 * the linear equivalent format anyway.
2529 if (brw
->gen
== 9 && srgb_enabled
&& mt
->num_samples
<= 1 &&
2530 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2532 /* Lossless compression is not supported for SRGB formats, it
2533 * should be impossible to get here with such surfaces.
2535 assert(!intel_miptree_is_lossless_compressed(brw
, mt
));
2536 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2540 /* For layered rendering non-compressed fast cleared buffers need to be
2541 * resolved. Surface state can carry only one fast color clear value
2542 * while each layer may have its own fast clear color value. For
2543 * compressed buffers color value is available in the color buffer.
2545 if (layer_count
> 1 &&
2546 !(mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) &&
2547 !intel_miptree_is_lossless_compressed(brw
, mt
)) {
2548 assert(brw
->gen
>= 8);
2550 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2556 intel_miptree_finish_render(struct brw_context
*brw
,
2557 struct intel_mipmap_tree
*mt
, uint32_t level
,
2558 uint32_t start_layer
, uint32_t layer_count
)
2560 assert(_mesa_is_format_color_format(mt
->format
));
2561 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2562 mt
->mcs_buf
!= NULL
);
2566 intel_miptree_prepare_depth(struct brw_context
*brw
,
2567 struct intel_mipmap_tree
*mt
, uint32_t level
,
2568 uint32_t start_layer
, uint32_t layer_count
)
2570 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2571 mt
->hiz_buf
!= NULL
, mt
->hiz_buf
!= NULL
);
2575 intel_miptree_finish_depth(struct brw_context
*brw
,
2576 struct intel_mipmap_tree
*mt
, uint32_t level
,
2577 uint32_t start_layer
, uint32_t layer_count
,
2580 if (depth_written
) {
2581 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2582 mt
->hiz_buf
!= NULL
);
2587 * Make it possible to share the BO backing the given miptree with another
2588 * process or another miptree.
2590 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2591 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2592 * ensure that no MCS buffer gets allocated in the future.
2594 * HiZ is similarly unsafe with shared buffers.
2597 intel_miptree_make_shareable(struct brw_context
*brw
,
2598 struct intel_mipmap_tree
*mt
)
2600 /* MCS buffers are also used for multisample buffers, but we can't resolve
2601 * away a multisample MCS buffer because it's an integral part of how the
2602 * pixel data is stored. Fortunately this code path should never be
2603 * reached for multisample buffers.
2605 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
|| mt
->num_samples
<= 1);
2607 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2608 0, INTEL_REMAINING_LAYERS
, false, false);
2611 mt
->aux_disable
|= (INTEL_AUX_DISABLE_CCS
| INTEL_AUX_DISABLE_MCS
);
2612 brw_bo_unreference(mt
->mcs_buf
->bo
);
2616 /* Any pending MCS/CCS operations are no longer needed. Trying to
2617 * execute any will likely crash due to the missing aux buffer. So let's
2618 * delete all pending ops.
2620 free(mt
->aux_state
);
2621 mt
->aux_state
= NULL
;
2625 mt
->aux_disable
|= INTEL_AUX_DISABLE_HIZ
;
2626 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2629 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2630 mt
->level
[l
].has_hiz
= false;
2633 /* Any pending HiZ operations are no longer needed. Trying to execute
2634 * any will likely crash due to the missing aux buffer. So let's delete
2637 free(mt
->aux_state
);
2638 mt
->aux_state
= NULL
;
2644 * \brief Get pointer offset into stencil buffer.
2646 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2647 * must decode the tile's layout in software.
2650 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2652 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2654 * Even though the returned offset is always positive, the return type is
2656 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2657 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2660 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2662 uint32_t tile_size
= 4096;
2663 uint32_t tile_width
= 64;
2664 uint32_t tile_height
= 64;
2665 uint32_t row_size
= 64 * stride
;
2667 uint32_t tile_x
= x
/ tile_width
;
2668 uint32_t tile_y
= y
/ tile_height
;
2670 /* The byte's address relative to the tile's base addres. */
2671 uint32_t byte_x
= x
% tile_width
;
2672 uint32_t byte_y
= y
% tile_height
;
2674 uintptr_t u
= tile_y
* row_size
2675 + tile_x
* tile_size
2676 + 512 * (byte_x
/ 8)
2678 + 32 * ((byte_y
/ 4) % 2)
2679 + 16 * ((byte_x
/ 4) % 2)
2680 + 8 * ((byte_y
/ 2) % 2)
2681 + 4 * ((byte_x
/ 2) % 2)
2686 /* adjust for bit6 swizzling */
2687 if (((byte_x
/ 8) % 2) == 1) {
2688 if (((byte_y
/ 8) % 2) == 0) {
2700 intel_miptree_updownsample(struct brw_context
*brw
,
2701 struct intel_mipmap_tree
*src
,
2702 struct intel_mipmap_tree
*dst
)
2704 unsigned src_w
, src_h
, dst_w
, dst_h
;
2706 if (src
->surf
.size
> 0) {
2707 src_w
= src
->surf
.logical_level0_px
.width
;
2708 src_h
= src
->surf
.logical_level0_px
.height
;
2710 src_w
= src
->logical_width0
;
2711 src_h
= src
->logical_height0
;
2714 if (dst
->surf
.size
> 0) {
2715 dst_w
= dst
->surf
.logical_level0_px
.width
;
2716 dst_h
= dst
->surf
.logical_level0_px
.height
;
2718 dst_w
= dst
->logical_width0
;
2719 dst_h
= dst
->logical_height0
;
2722 brw_blorp_blit_miptrees(brw
,
2723 src
, 0 /* level */, 0 /* layer */,
2724 src
->format
, SWIZZLE_XYZW
,
2725 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2728 GL_NEAREST
, false, false /*mirror x, y*/,
2731 if (src
->stencil_mt
) {
2732 if (src
->stencil_mt
->surf
.size
> 0) {
2733 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2734 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2736 src_w
= src
->stencil_mt
->logical_width0
;
2737 src_h
= src
->stencil_mt
->logical_height0
;
2740 if (dst
->stencil_mt
->surf
.size
> 0) {
2741 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2742 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2744 dst_w
= dst
->stencil_mt
->logical_width0
;
2745 dst_h
= dst
->stencil_mt
->logical_height0
;
2748 brw_blorp_blit_miptrees(brw
,
2749 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2750 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2751 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2752 dst
->stencil_mt
->format
,
2755 GL_NEAREST
, false, false /*mirror x, y*/,
2756 false, false /* decode/encode srgb */);
2761 intel_update_r8stencil(struct brw_context
*brw
,
2762 struct intel_mipmap_tree
*mt
)
2764 assert(brw
->gen
>= 7);
2765 struct intel_mipmap_tree
*src
=
2766 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2767 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2770 if (!mt
->r8stencil_mt
) {
2771 const uint32_t r8stencil_flags
=
2772 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2773 MIPTREE_LAYOUT_DISABLE_AUX
;
2774 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2775 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2777 MESA_FORMAT_R_UINT8
,
2780 src
->logical_width0
,
2781 src
->logical_height0
,
2782 src
->logical_depth0
,
2785 assert(mt
->r8stencil_mt
);
2788 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2790 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2791 const unsigned depth
= src
->level
[level
].depth
;
2793 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2794 brw_blorp_copy_miptrees(brw
,
2798 minify(src
->logical_width0
, level
),
2799 minify(src
->logical_height0
, level
));
2803 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2804 src
->r8stencil_needs_update
= false;
2808 intel_miptree_map_raw(struct brw_context
*brw
,
2809 struct intel_mipmap_tree
*mt
,
2812 struct brw_bo
*bo
= mt
->bo
;
2814 if (brw_batch_references(&brw
->batch
, bo
))
2815 intel_batchbuffer_flush(brw
);
2817 return brw_bo_map(brw
, bo
, mode
);
2821 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2823 brw_bo_unmap(mt
->bo
);
2827 intel_miptree_map_gtt(struct brw_context
*brw
,
2828 struct intel_mipmap_tree
*mt
,
2829 struct intel_miptree_map
*map
,
2830 unsigned int level
, unsigned int slice
)
2832 unsigned int bw
, bh
;
2834 unsigned int image_x
, image_y
;
2835 intptr_t x
= map
->x
;
2836 intptr_t y
= map
->y
;
2838 /* For compressed formats, the stride is the number of bytes per
2839 * row of blocks. intel_miptree_get_image_offset() already does
2842 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2843 assert(y
% bh
== 0);
2844 assert(x
% bw
== 0);
2848 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
) + mt
->offset
;
2853 /* Note that in the case of cube maps, the caller must have passed the
2854 * slice number referencing the face.
2856 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2860 map
->stride
= mt
->pitch
;
2861 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2864 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2865 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2866 map
->x
, map
->y
, map
->w
, map
->h
,
2867 mt
, _mesa_get_format_name(mt
->format
),
2868 x
, y
, map
->ptr
, map
->stride
);
2872 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2874 intel_miptree_unmap_raw(mt
);
2878 intel_miptree_map_blit(struct brw_context
*brw
,
2879 struct intel_mipmap_tree
*mt
,
2880 struct intel_miptree_map
*map
,
2881 unsigned int level
, unsigned int slice
)
2883 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2884 /* first_level */ 0,
2888 MIPTREE_LAYOUT_TILING_NONE
);
2890 if (!map
->linear_mt
) {
2891 fprintf(stderr
, "Failed to allocate blit temporary\n");
2894 map
->stride
= map
->linear_mt
->pitch
;
2896 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2897 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2898 * invalidate is set, since we'll be writing the whole rectangle from our
2899 * temporary buffer back out.
2901 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2902 if (!intel_miptree_copy(brw
,
2903 mt
, level
, slice
, map
->x
, map
->y
,
2904 map
->linear_mt
, 0, 0, 0, 0,
2906 fprintf(stderr
, "Failed to blit\n");
2911 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
2913 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2914 map
->x
, map
->y
, map
->w
, map
->h
,
2915 mt
, _mesa_get_format_name(mt
->format
),
2916 level
, slice
, map
->ptr
, map
->stride
);
2921 intel_miptree_release(&map
->linear_mt
);
2927 intel_miptree_unmap_blit(struct brw_context
*brw
,
2928 struct intel_mipmap_tree
*mt
,
2929 struct intel_miptree_map
*map
,
2933 struct gl_context
*ctx
= &brw
->ctx
;
2935 intel_miptree_unmap_raw(map
->linear_mt
);
2937 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2938 bool ok
= intel_miptree_copy(brw
,
2939 map
->linear_mt
, 0, 0, 0, 0,
2940 mt
, level
, slice
, map
->x
, map
->y
,
2942 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2945 intel_miptree_release(&map
->linear_mt
);
2949 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2951 #if defined(USE_SSE41)
2953 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2954 struct intel_mipmap_tree
*mt
,
2955 struct intel_miptree_map
*map
,
2956 unsigned int level
, unsigned int slice
)
2958 assert(map
->mode
& GL_MAP_READ_BIT
);
2959 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2961 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2962 map
->x
, map
->y
, map
->w
, map
->h
,
2963 mt
, _mesa_get_format_name(mt
->format
),
2964 level
, slice
, map
->ptr
, map
->stride
);
2966 /* Map the original image */
2969 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2973 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
2979 src
+= image_y
* mt
->pitch
;
2980 src
+= image_x
* mt
->cpp
;
2982 /* Due to the pixel offsets for the particular image being mapped, our
2983 * src pointer may not be 16-byte aligned. However, if the pitch is
2984 * divisible by 16, then the amount by which it's misaligned will remain
2985 * consistent from row to row.
2987 assert((mt
->pitch
% 16) == 0);
2988 const int misalignment
= ((uintptr_t) src
) & 15;
2990 /* Create an untiled temporary buffer for the mapping. */
2991 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2993 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2995 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2996 /* Offset the destination so it has the same misalignment as src. */
2997 map
->ptr
= map
->buffer
+ misalignment
;
2999 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3001 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3002 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3003 void *src_ptr
= src
+ y
* mt
->pitch
;
3005 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3008 intel_miptree_unmap_raw(mt
);
3012 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3013 struct intel_mipmap_tree
*mt
,
3014 struct intel_miptree_map
*map
,
3018 _mesa_align_free(map
->buffer
);
3025 intel_miptree_map_s8(struct brw_context
*brw
,
3026 struct intel_mipmap_tree
*mt
,
3027 struct intel_miptree_map
*map
,
3028 unsigned int level
, unsigned int slice
)
3030 map
->stride
= map
->w
;
3031 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3035 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3036 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3037 * invalidate is set, since we'll be writing the whole rectangle from our
3038 * temporary buffer back out.
3040 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3041 /* ISL uses a stencil pitch value that is expected by hardware whereas
3042 * traditional miptree uses half of that. Below the value gets supplied
3043 * to intel_offset_S8() which expects the legacy interpretation.
3045 const unsigned pitch
= mt
->surf
.size
> 0 ?
3046 mt
->surf
.row_pitch
/ 2 : mt
->pitch
;
3047 uint8_t *untiled_s8_map
= map
->ptr
;
3048 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3049 unsigned int image_x
, image_y
;
3051 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3053 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3054 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3055 ptrdiff_t offset
= intel_offset_S8(pitch
,
3056 x
+ image_x
+ map
->x
,
3057 y
+ image_y
+ map
->y
,
3058 brw
->has_swizzling
);
3059 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3063 intel_miptree_unmap_raw(mt
);
3065 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3066 map
->x
, map
->y
, map
->w
, map
->h
,
3067 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3069 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3070 map
->x
, map
->y
, map
->w
, map
->h
,
3071 mt
, map
->ptr
, map
->stride
);
3076 intel_miptree_unmap_s8(struct brw_context
*brw
,
3077 struct intel_mipmap_tree
*mt
,
3078 struct intel_miptree_map
*map
,
3082 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3083 /* ISL uses a stencil pitch value that is expected by hardware whereas
3084 * traditional miptree uses half of that. Below the value gets supplied
3085 * to intel_offset_S8() which expects the legacy interpretation.
3087 const unsigned pitch
= mt
->surf
.size
> 0 ?
3088 mt
->surf
.row_pitch
/ 2: mt
->pitch
;
3089 unsigned int image_x
, image_y
;
3090 uint8_t *untiled_s8_map
= map
->ptr
;
3091 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3093 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3095 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3096 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3097 ptrdiff_t offset
= intel_offset_S8(pitch
,
3098 image_x
+ x
+ map
->x
,
3099 image_y
+ y
+ map
->y
,
3100 brw
->has_swizzling
);
3101 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3105 intel_miptree_unmap_raw(mt
);
3112 intel_miptree_map_etc(struct brw_context
*brw
,
3113 struct intel_mipmap_tree
*mt
,
3114 struct intel_miptree_map
*map
,
3118 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3119 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3120 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3123 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3124 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3126 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3127 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3128 map
->w
, map
->h
, 1));
3129 map
->ptr
= map
->buffer
;
3133 intel_miptree_unmap_etc(struct brw_context
*brw
,
3134 struct intel_mipmap_tree
*mt
,
3135 struct intel_miptree_map
*map
,
3141 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3146 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3147 + image_y
* mt
->pitch
3148 + image_x
* mt
->cpp
;
3150 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3151 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
3152 map
->ptr
, map
->stride
,
3155 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
3156 map
->ptr
, map
->stride
,
3157 map
->w
, map
->h
, mt
->etc_format
);
3159 intel_miptree_unmap_raw(mt
);
3164 * Mapping function for packed depth/stencil miptrees backed by real separate
3165 * miptrees for depth and stencil.
3167 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3168 * separate from the depth buffer. Yet at the GL API level, we have to expose
3169 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3170 * be able to map that memory for texture storage and glReadPixels-type
3171 * operations. We give Mesa core that access by mallocing a temporary and
3172 * copying the data between the actual backing store and the temporary.
3175 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3176 struct intel_mipmap_tree
*mt
,
3177 struct intel_miptree_map
*map
,
3178 unsigned int level
, unsigned int slice
)
3180 struct intel_mipmap_tree
*z_mt
= mt
;
3181 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3182 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3183 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3185 map
->stride
= map
->w
* packed_bpp
;
3186 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3190 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3191 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3192 * invalidate is set, since we'll be writing the whole rectangle from our
3193 * temporary buffer back out.
3195 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3196 /* ISL uses a stencil pitch value that is expected by hardware whereas
3197 * traditional miptree uses half of that. Below the value gets supplied
3198 * to intel_offset_S8() which expects the legacy interpretation.
3200 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3201 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3202 uint32_t *packed_map
= map
->ptr
;
3203 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3204 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3205 unsigned int s_image_x
, s_image_y
;
3206 unsigned int z_image_x
, z_image_y
;
3208 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3209 &s_image_x
, &s_image_y
);
3210 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3211 &z_image_x
, &z_image_y
);
3213 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3214 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3215 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3216 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3219 brw
->has_swizzling
);
3220 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3222 (map_x
+ z_image_x
));
3223 uint8_t s
= s_map
[s_offset
];
3224 uint32_t z
= z_map
[z_offset
];
3226 if (map_z32f_x24s8
) {
3227 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3228 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3230 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3235 intel_miptree_unmap_raw(s_mt
);
3236 intel_miptree_unmap_raw(z_mt
);
3238 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3240 map
->x
, map
->y
, map
->w
, map
->h
,
3241 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3242 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3243 map
->ptr
, map
->stride
);
3245 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3246 map
->x
, map
->y
, map
->w
, map
->h
,
3247 mt
, map
->ptr
, map
->stride
);
3252 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3253 struct intel_mipmap_tree
*mt
,
3254 struct intel_miptree_map
*map
,
3258 struct intel_mipmap_tree
*z_mt
= mt
;
3259 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3260 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3262 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3263 /* ISL uses a stencil pitch value that is expected by hardware whereas
3264 * traditional miptree uses half of that. Below the value gets supplied
3265 * to intel_offset_S8() which expects the legacy interpretation.
3267 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3268 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3269 uint32_t *packed_map
= map
->ptr
;
3270 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3271 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3272 unsigned int s_image_x
, s_image_y
;
3273 unsigned int z_image_x
, z_image_y
;
3275 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3276 &s_image_x
, &s_image_y
);
3277 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3278 &z_image_x
, &z_image_y
);
3280 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3281 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3282 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3283 x
+ s_image_x
+ map
->x
,
3284 y
+ s_image_y
+ map
->y
,
3285 brw
->has_swizzling
);
3286 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3288 (x
+ z_image_x
+ map
->x
));
3290 if (map_z32f_x24s8
) {
3291 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3292 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3294 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3295 s_map
[s_offset
] = packed
>> 24;
3296 z_map
[z_offset
] = packed
;
3301 intel_miptree_unmap_raw(s_mt
);
3302 intel_miptree_unmap_raw(z_mt
);
3304 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3306 map
->x
, map
->y
, map
->w
, map
->h
,
3307 z_mt
, _mesa_get_format_name(z_mt
->format
),
3308 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3309 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3310 map
->ptr
, map
->stride
);
3317 * Create and attach a map to the miptree at (level, slice). Return the
3320 static struct intel_miptree_map
*
3321 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3330 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3335 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3336 mt
->level
[level
].slice
[slice
].map
= map
;
3348 * Release the map at (level, slice).
3351 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3355 struct intel_miptree_map
**map
;
3357 map
= &mt
->level
[level
].slice
[slice
].map
;
3363 can_blit_slice(struct intel_mipmap_tree
*mt
,
3364 unsigned int level
, unsigned int slice
)
3366 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3367 if (mt
->pitch
>= 32768)
3374 use_intel_mipree_map_blit(struct brw_context
*brw
,
3375 struct intel_mipmap_tree
*mt
,
3381 /* It's probably not worth swapping to the blit ring because of
3382 * all the overhead involved.
3384 !(mode
& GL_MAP_WRITE_BIT
) &&
3386 (mt
->tiling
== I915_TILING_X
||
3387 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3388 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
3389 /* Fast copy blit on skl+ supports all tiling formats. */
3391 can_blit_slice(mt
, level
, slice
))
3394 if (mt
->tiling
!= I915_TILING_NONE
&&
3395 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3396 assert(can_blit_slice(mt
, level
, slice
));
3404 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3405 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3406 * arithmetic overflow.
3408 * If you call this function and use \a out_stride, then you're doing pointer
3409 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3410 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3411 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3412 * which usually have type uint32_t or GLuint.
3415 intel_miptree_map(struct brw_context
*brw
,
3416 struct intel_mipmap_tree
*mt
,
3425 ptrdiff_t *out_stride
)
3427 struct intel_miptree_map
*map
;
3429 assert(mt
->num_samples
<= 1);
3431 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3438 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3439 map
->mode
& GL_MAP_WRITE_BIT
);
3441 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3442 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3443 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3444 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3445 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3446 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3447 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3448 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3449 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3450 #if defined(USE_SSE41)
3451 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3452 !mt
->compressed
&& cpu_has_sse4_1
&&
3453 (mt
->pitch
% 16 == 0)) {
3454 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3457 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3460 *out_ptr
= map
->ptr
;
3461 *out_stride
= map
->stride
;
3463 if (map
->ptr
== NULL
)
3464 intel_miptree_release_map(mt
, level
, slice
);
3468 intel_miptree_unmap(struct brw_context
*brw
,
3469 struct intel_mipmap_tree
*mt
,
3473 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3475 assert(mt
->num_samples
<= 1);
3480 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3481 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3483 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3484 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3485 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3486 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3487 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3488 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3489 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3490 } else if (map
->linear_mt
) {
3491 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3492 #if defined(USE_SSE41)
3493 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3494 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3497 intel_miptree_unmap_gtt(mt
);
3500 intel_miptree_release_map(mt
, level
, slice
);
3504 get_isl_surf_dim(GLenum target
)
3508 case GL_TEXTURE_1D_ARRAY
:
3509 return ISL_SURF_DIM_1D
;
3512 case GL_TEXTURE_2D_ARRAY
:
3513 case GL_TEXTURE_RECTANGLE
:
3514 case GL_TEXTURE_CUBE_MAP
:
3515 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3516 case GL_TEXTURE_2D_MULTISAMPLE
:
3517 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3518 case GL_TEXTURE_EXTERNAL_OES
:
3519 return ISL_SURF_DIM_2D
;
3522 return ISL_SURF_DIM_3D
;
3525 unreachable("Invalid texture target");
3529 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3530 GLenum target
, enum miptree_array_layout array_layout
)
3532 if (array_layout
== GEN6_HIZ_STENCIL
)
3533 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
3537 case GL_TEXTURE_1D_ARRAY
:
3538 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3539 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3542 case GL_TEXTURE_2D_ARRAY
:
3543 case GL_TEXTURE_RECTANGLE
:
3544 case GL_TEXTURE_2D_MULTISAMPLE
:
3545 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3546 case GL_TEXTURE_EXTERNAL_OES
:
3547 return ISL_DIM_LAYOUT_GEN4_2D
;
3549 case GL_TEXTURE_CUBE_MAP
:
3550 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3551 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3552 ISL_DIM_LAYOUT_GEN4_2D
);
3555 return (devinfo
->gen
>= 9 ?
3556 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3559 unreachable("Invalid texture target");
3563 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3565 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3566 return ISL_TILING_W
;
3568 switch (mt
->tiling
) {
3569 case I915_TILING_NONE
:
3570 return ISL_TILING_LINEAR
;
3572 return ISL_TILING_X
;
3574 return ISL_TILING_Y0
;
3576 unreachable("Invalid tiling mode");
3582 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3583 const struct intel_mipmap_tree
*mt
,
3584 struct isl_surf
*surf
)
3586 surf
->dim
= get_isl_surf_dim(mt
->target
);
3587 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3588 mt
->tiling
, mt
->target
,
3591 if (mt
->num_samples
> 1) {
3592 switch (mt
->msaa_layout
) {
3593 case INTEL_MSAA_LAYOUT_IMS
:
3594 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3596 case INTEL_MSAA_LAYOUT_UMS
:
3597 case INTEL_MSAA_LAYOUT_CMS
:
3598 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3601 unreachable("Invalid MSAA layout");
3604 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3607 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3609 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3610 /* The ISL definition of row_pitch matches the surface state pitch field
3611 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3612 * the factor of 2 for W-tiling in row_pitch.
3614 surf
->row_pitch
= 2 * mt
->pitch
;
3616 surf
->row_pitch
= mt
->pitch
;
3619 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3621 if (brw
->gen
>= 9) {
3622 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3623 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3624 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3626 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3627 * alignment in terms of surface elements like we want.
3629 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3632 /* On earlier gens it's stored in pixels. */
3634 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3635 surf
->image_alignment_el
=
3636 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3639 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3640 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3641 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3642 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3643 surf
->logical_level0_px
.array_len
= 1;
3645 surf
->logical_level0_px
.depth
= 1;
3646 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3649 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3650 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3651 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3652 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3653 surf
->phys_level0_sa
.array_len
= 1;
3655 surf
->phys_level0_sa
.depth
= 1;
3656 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3659 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3660 surf
->samples
= MAX2(mt
->num_samples
, 1);
3662 surf
->size
= 0; /* TODO */
3663 surf
->alignment
= 0; /* TODO */
3665 switch (surf
->dim_layout
) {
3666 case ISL_DIM_LAYOUT_GEN4_2D
:
3667 case ISL_DIM_LAYOUT_GEN4_3D
:
3668 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
3669 if (brw
->gen
>= 9) {
3670 surf
->array_pitch_el_rows
= mt
->qpitch
;
3673 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3674 assert(mt
->qpitch
% bh
== 0);
3675 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3678 case ISL_DIM_LAYOUT_GEN9_1D
:
3679 surf
->array_pitch_el_rows
= 1;
3683 switch (mt
->array_layout
) {
3684 case ALL_LOD_IN_EACH_SLICE
:
3685 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3687 case ALL_SLICES_AT_EACH_LOD
:
3688 case GEN6_HIZ_STENCIL
:
3689 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3692 unreachable("Invalid array layout");
3695 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3696 switch (base_format
) {
3697 case GL_DEPTH_COMPONENT
:
3698 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3700 case GL_STENCIL_INDEX
:
3701 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3703 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3705 case GL_DEPTH_STENCIL
:
3706 /* In this case we only texture from the depth part */
3707 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3708 ISL_SURF_USAGE_TEXTURE_BIT
;
3711 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3712 if (brw
->mesa_format_supports_render
[mt
->format
])
3713 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3717 if (_mesa_is_cube_map_texture(mt
->target
))
3718 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3722 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3723 const struct intel_mipmap_tree
*mt
)
3726 return ISL_AUX_USAGE_HIZ
;
3729 return ISL_AUX_USAGE_NONE
;
3731 if (mt
->num_samples
> 1) {
3732 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
3733 return ISL_AUX_USAGE_MCS
;
3736 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
3737 assert(brw
->gen
>= 9);
3738 return ISL_AUX_USAGE_CCS_E
;
3741 if ((mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) == 0)
3742 return ISL_AUX_USAGE_CCS_D
;
3744 unreachable("Invalid MCS miptree");