1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_chipset.h"
33 #include "intel_mipmap_tree.h"
34 #include "intel_regions.h"
35 #include "intel_resolve_map.h"
36 #include "intel_tex.h"
37 #include "intel_blit.h"
39 #include "brw_blorp.h"
40 #include "brw_context.h"
42 #include "main/enums.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
48 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 target_to_target(GLenum target
)
54 case GL_TEXTURE_CUBE_MAP_POSITIVE_X_ARB
:
55 case GL_TEXTURE_CUBE_MAP_NEGATIVE_X_ARB
:
56 case GL_TEXTURE_CUBE_MAP_POSITIVE_Y_ARB
:
57 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y_ARB
:
58 case GL_TEXTURE_CUBE_MAP_POSITIVE_Z_ARB
:
59 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z_ARB
:
60 return GL_TEXTURE_CUBE_MAP_ARB
;
68 * Determine which MSAA layout should be used by the MSAA surface being
69 * created, based on the chip generation and the surface type.
71 static enum intel_msaa_layout
72 compute_msaa_layout(struct brw_context
*brw
, gl_format format
, GLenum target
)
74 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
76 return INTEL_MSAA_LAYOUT_IMS
;
78 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
79 switch (_mesa_get_format_base_format(format
)) {
80 case GL_DEPTH_COMPONENT
:
81 case GL_STENCIL_INDEX
:
82 case GL_DEPTH_STENCIL
:
83 return INTEL_MSAA_LAYOUT_IMS
;
85 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
87 * This field must be set to 0 for all SINT MSRTs when all RT channels
90 * In practice this means that we have to disable MCS for all signed
91 * integer MSAA buffers. The alternative, to disable MCS only when one
92 * of the render target channels is disabled, is impractical because it
93 * would require converting between CMS and UMS MSAA layouts on the fly,
96 if (_mesa_get_format_datatype(format
) == GL_INT
) {
97 /* TODO: is this workaround needed for future chipsets? */
98 assert(brw
->gen
== 7);
99 return INTEL_MSAA_LAYOUT_UMS
;
101 /* For now, if we're going to be texturing from this surface,
102 * force UMS, so that the shader doesn't have to do different things
103 * based on whether there's a multisample control surface needing sampled first.
104 * We can't just blindly read the MCS surface in all cases because:
106 * From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
108 * If this field is disabled and the sampling engine <ld_mcs> message
109 * is issued on this surface, the MCS surface may be accessed. Software
110 * must ensure that the surface is defined to avoid GTT errors.
112 if (target
== GL_TEXTURE_2D_MULTISAMPLE
||
113 target
== GL_TEXTURE_2D_MULTISAMPLE_ARRAY
) {
114 return INTEL_MSAA_LAYOUT_UMS
;
116 return INTEL_MSAA_LAYOUT_CMS
;
124 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
125 * scaled-down bitfield representation of the color buffer which is capable of
126 * recording when blocks of the color buffer are equal to the clear value.
127 * This function returns the block size that will be used by the MCS buffer
128 * corresponding to a certain color miptree.
130 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
131 * beneath the "Fast Color Clear" bullet (p327):
133 * The following table describes the RT alignment
147 * This alignment has the following uses:
149 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
150 * buffer contains 128 blocks horizontally and 256 blocks vertically.
152 * - For figuring out alignment restrictions for a fast clear operation. Fast
153 * clear operations must always clear aligned multiples of 16 blocks
154 * horizontally and 32 blocks vertically.
156 * - For scaling down the coordinates sent through the render pipeline during
157 * a fast clear. X coordinates must be scaled down by 8 times the block
158 * width, and Y coordinates by 16 times the block height.
160 * - For scaling down the coordinates sent through the render pipeline during
161 * a "Render Target Resolve" operation. X coordinates must be scaled down
162 * by half the block width, and Y coordinates by half the block height.
165 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
166 struct intel_mipmap_tree
*mt
,
167 unsigned *width_px
, unsigned *height
)
169 switch (mt
->region
->tiling
) {
171 assert(!"Non-MSRT MCS requires X or Y tiling");
172 /* In release builds, fall through */
174 *width_px
= 32 / mt
->cpp
;
178 *width_px
= 64 / mt
->cpp
;
185 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
188 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
189 * beneath the "Fast Color Clear" bullet (p326):
191 * - Support is limited to tiled render targets.
192 * - Support is for non-mip-mapped and non-array surface types only.
194 * And then later, on p327:
196 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
200 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
201 struct intel_mipmap_tree
*mt
)
203 /* MCS support does not exist prior to Gen7 */
207 /* MCS is only supported for color buffers */
208 switch (_mesa_get_format_base_format(mt
->format
)) {
209 case GL_DEPTH_COMPONENT
:
210 case GL_DEPTH_STENCIL
:
211 case GL_STENCIL_INDEX
:
215 if (mt
->region
->tiling
!= I915_TILING_X
&&
216 mt
->region
->tiling
!= I915_TILING_Y
)
218 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
220 if (mt
->first_level
!= 0 || mt
->last_level
!= 0)
222 if (mt
->physical_depth0
!= 1)
225 /* There's no point in using an MCS buffer if the surface isn't in a
228 if (!brw
->format_supported_as_render_target
[mt
->format
])
236 * @param for_bo Indicates that the caller is
237 * intel_miptree_create_for_bo(). If true, then do not create
240 struct intel_mipmap_tree
*
241 intel_miptree_create_layout(struct brw_context
*brw
,
252 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
256 DBG("%s target %s format %s level %d..%d <-- %p\n", __FUNCTION__
,
257 _mesa_lookup_enum_by_nr(target
),
258 _mesa_get_format_name(format
),
259 first_level
, last_level
, mt
);
261 mt
->target
= target_to_target(target
);
263 mt
->first_level
= first_level
;
264 mt
->last_level
= last_level
;
265 mt
->logical_width0
= width0
;
266 mt
->logical_height0
= height0
;
267 mt
->logical_depth0
= depth0
;
268 mt
->mcs_state
= INTEL_MCS_STATE_NONE
;
270 /* The cpp is bytes per (1, blockheight)-sized block for compressed
271 * textures. This is why you'll see divides by blockheight all over
274 _mesa_get_format_block_size(format
, &bw
, &bh
);
275 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
276 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
278 mt
->num_samples
= num_samples
;
279 mt
->compressed
= _mesa_is_format_compressed(format
);
280 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
283 if (num_samples
> 1) {
284 /* Adjust width/height/depth for MSAA */
285 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->target
);
286 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
287 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says:
289 * "Any of the other messages (sample*, LOD, load4) used with a
290 * (4x) multisampled surface will in-effect sample a surface with
291 * double the height and width as that indicated in the surface
292 * state. Each pixel position on the original-sized surface is
293 * replaced with a 2x2 of samples with the following arrangement:
298 * Thus, when sampling from a multisampled texture, it behaves as
299 * though the layout in memory for (x,y,sample) is:
301 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
302 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
304 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
305 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
307 * However, the actual layout of multisampled data in memory is:
309 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
310 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
312 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
313 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
315 * This pattern repeats for each 2x2 pixel block.
317 * As a result, when calculating the size of our 4-sample buffer for
318 * an odd width or height, we have to align before scaling up because
319 * sample 3 is in that bottom right 2x2 block.
321 switch (num_samples
) {
323 width0
= ALIGN(width0
, 2) * 2;
324 height0
= ALIGN(height0
, 2) * 2;
327 width0
= ALIGN(width0
, 2) * 4;
328 height0
= ALIGN(height0
, 2) * 2;
331 /* num_samples should already have been quantized to 0, 1, 4, or
337 /* Non-interleaved */
338 depth0
*= num_samples
;
342 /* array_spacing_lod0 is only used for non-IMS MSAA surfaces. TODO: can we
345 switch (mt
->msaa_layout
) {
346 case INTEL_MSAA_LAYOUT_NONE
:
347 case INTEL_MSAA_LAYOUT_IMS
:
348 mt
->array_spacing_lod0
= false;
350 case INTEL_MSAA_LAYOUT_UMS
:
351 case INTEL_MSAA_LAYOUT_CMS
:
352 mt
->array_spacing_lod0
= true;
356 if (target
== GL_TEXTURE_CUBE_MAP
) {
361 mt
->physical_width0
= width0
;
362 mt
->physical_height0
= height0
;
363 mt
->physical_depth0
= depth0
;
366 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
367 (brw
->must_use_separate_stencil
||
368 (brw
->has_separate_stencil
&& brw_is_hiz_depth_format(brw
, format
)))) {
369 mt
->stencil_mt
= intel_miptree_create(brw
,
379 INTEL_MIPTREE_TILING_ANY
);
380 if (!mt
->stencil_mt
) {
381 intel_miptree_release(&mt
);
385 /* Fix up the Z miptree format for how we're splitting out separate
386 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
388 if (mt
->format
== MESA_FORMAT_S8_Z24
) {
389 mt
->format
= MESA_FORMAT_X8_Z24
;
390 } else if (mt
->format
== MESA_FORMAT_Z32_FLOAT_X24S8
) {
391 mt
->format
= MESA_FORMAT_Z32_FLOAT
;
394 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
395 _mesa_get_format_name(mt
->format
));
399 brw_miptree_layout(brw
, mt
);
405 * \brief Helper function for intel_miptree_create().
408 intel_miptree_choose_tiling(struct brw_context
*brw
,
411 uint32_t num_samples
,
412 enum intel_miptree_tiling_mode requested
,
413 struct intel_mipmap_tree
*mt
)
415 if (format
== MESA_FORMAT_S8
) {
416 /* The stencil buffer is W tiled. However, we request from the kernel a
417 * non-tiled buffer because the GTT is incapable of W fencing.
419 return I915_TILING_NONE
;
422 /* Some usages may want only one type of tiling, like depth miptrees (Y
423 * tiled), or temporary BOs for uploading data once (linear).
426 case INTEL_MIPTREE_TILING_ANY
:
428 case INTEL_MIPTREE_TILING_Y
:
429 return I915_TILING_Y
;
430 case INTEL_MIPTREE_TILING_NONE
:
431 return I915_TILING_NONE
;
434 if (num_samples
> 1) {
435 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
438 * [DevSNB+]: For multi-sample render targets, this field must be
439 * 1. MSRTs can only be tiled.
441 * Our usual reason for preferring X tiling (fast blits using the
442 * blitting engine) doesn't apply to MSAA, since we'll generally be
443 * downsampling or upsampling when blitting between the MSAA buffer
444 * and another buffer, and the blitting engine doesn't support that.
445 * So use Y tiling, since it makes better use of the cache.
447 return I915_TILING_Y
;
450 GLenum base_format
= _mesa_get_format_base_format(format
);
451 if (base_format
== GL_DEPTH_COMPONENT
||
452 base_format
== GL_DEPTH_STENCIL_EXT
)
453 return I915_TILING_Y
;
455 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
457 /* If the width is much smaller than a tile, don't bother tiling. */
458 if (minimum_pitch
< 64)
459 return I915_TILING_NONE
;
461 if (ALIGN(minimum_pitch
, 512) >= 32768) {
462 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
463 mt
->total_width
, mt
->total_height
);
464 return I915_TILING_NONE
;
467 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
469 return I915_TILING_X
;
471 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
472 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
474 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
475 * all the way back to 965, but is explicitly permitted on Gen7.
477 if (brw
->gen
!= 7 && mt
->cpp
>= 16)
478 return I915_TILING_X
;
480 return I915_TILING_Y
| I915_TILING_X
;
483 struct intel_mipmap_tree
*
484 intel_miptree_create(struct brw_context
*brw
,
492 bool expect_accelerated_upload
,
494 enum intel_miptree_tiling_mode requested_tiling
)
496 struct intel_mipmap_tree
*mt
;
497 gl_format tex_format
= format
;
498 gl_format etc_format
= MESA_FORMAT_NONE
;
499 GLuint total_width
, total_height
;
501 if (!brw
->is_baytrail
) {
503 case MESA_FORMAT_ETC1_RGB8
:
504 format
= MESA_FORMAT_RGBX8888_REV
;
506 case MESA_FORMAT_ETC2_RGB8
:
507 format
= MESA_FORMAT_RGBX8888_REV
;
509 case MESA_FORMAT_ETC2_SRGB8
:
510 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
511 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
512 format
= MESA_FORMAT_SARGB8
;
514 case MESA_FORMAT_ETC2_RGBA8_EAC
:
515 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
516 format
= MESA_FORMAT_RGBA8888_REV
;
518 case MESA_FORMAT_ETC2_R11_EAC
:
519 format
= MESA_FORMAT_R16
;
521 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
522 format
= MESA_FORMAT_SIGNED_R16
;
524 case MESA_FORMAT_ETC2_RG11_EAC
:
525 format
= MESA_FORMAT_GR1616
;
527 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
528 format
= MESA_FORMAT_SIGNED_GR1616
;
531 /* Non ETC1 / ETC2 format */
536 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
538 mt
= intel_miptree_create_layout(brw
, target
, format
,
539 first_level
, last_level
, width0
,
543 * pitch == 0 || height == 0 indicates the null texture
545 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
546 intel_miptree_release(&mt
);
550 total_width
= mt
->total_width
;
551 total_height
= mt
->total_height
;
553 if (format
== MESA_FORMAT_S8
) {
554 /* Align to size of W tile, 64x64. */
555 total_width
= ALIGN(total_width
, 64);
556 total_height
= ALIGN(total_height
, 64);
559 uint32_t tiling
= intel_miptree_choose_tiling(brw
, format
, width0
,
560 num_samples
, requested_tiling
,
562 bool y_or_x
= tiling
== (I915_TILING_Y
| I915_TILING_X
);
564 mt
->etc_format
= etc_format
;
565 mt
->region
= intel_region_alloc(brw
->intelScreen
,
566 y_or_x
? I915_TILING_Y
: tiling
,
570 expect_accelerated_upload
);
572 /* If the region is too large to fit in the aperture, we need to use the
573 * BLT engine to support it. The BLT paths can't currently handle Y-tiling,
574 * so we need to fall back to X.
576 if (y_or_x
&& mt
->region
->bo
->size
>= brw
->max_gtt_map_object_size
) {
577 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
578 mt
->total_width
, mt
->total_height
);
579 intel_region_release(&mt
->region
);
581 mt
->region
= intel_region_alloc(brw
->intelScreen
,
586 expect_accelerated_upload
);
592 intel_miptree_release(&mt
);
596 /* If this miptree is capable of supporting fast color clears, set
597 * mcs_state appropriately to ensure that fast clears will occur.
598 * Allocation of the MCS miptree will be deferred until the first fast
599 * clear actually occurs.
601 if (intel_is_non_msrt_mcs_buffer_supported(brw
, mt
))
602 mt
->mcs_state
= INTEL_MCS_STATE_RESOLVED
;
607 struct intel_mipmap_tree
*
608 intel_miptree_create_for_bo(struct brw_context
*brw
,
617 struct intel_mipmap_tree
*mt
;
619 struct intel_region
*region
= calloc(1, sizeof(*region
));
623 /* Nothing will be able to use this miptree with the BO if the offset isn't
626 if (tiling
!= I915_TILING_NONE
)
627 assert(offset
% 4096 == 0);
629 /* miptrees can't handle negative pitch. If you need flipping of images,
630 * that's outside of the scope of the mt.
634 mt
= intel_miptree_create_layout(brw
, GL_TEXTURE_2D
, format
,
637 true, 0 /* num_samples */);
641 region
->cpp
= mt
->cpp
;
642 region
->width
= width
;
643 region
->height
= height
;
644 region
->pitch
= pitch
;
645 region
->refcount
= 1;
646 drm_intel_bo_reference(bo
);
648 region
->tiling
= tiling
;
658 * For a singlesample DRI2 buffer, this simply wraps the given region with a miptree.
660 * For a multisample DRI2 buffer, this wraps the given region with
661 * a singlesample miptree, then creates a multisample miptree into which the
662 * singlesample miptree is embedded as a child.
664 struct intel_mipmap_tree
*
665 intel_miptree_create_for_dri2_buffer(struct brw_context
*brw
,
666 unsigned dri_attachment
,
668 uint32_t num_samples
,
669 struct intel_region
*region
)
671 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
672 struct intel_mipmap_tree
*multisample_mt
= NULL
;
674 /* Only the front and back buffers, which are color buffers, are shared
677 assert(dri_attachment
== __DRI_BUFFER_BACK_LEFT
||
678 dri_attachment
== __DRI_BUFFER_FRONT_LEFT
||
679 dri_attachment
== __DRI_BUFFER_FAKE_FRONT_LEFT
);
680 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
681 _mesa_get_format_base_format(format
) == GL_RGBA
);
683 singlesample_mt
= intel_miptree_create_for_bo(brw
,
691 if (!singlesample_mt
)
693 singlesample_mt
->region
->name
= region
->name
;
695 /* If this miptree is capable of supporting fast color clears, set
696 * mcs_state appropriately to ensure that fast clears will occur.
697 * Allocation of the MCS miptree will be deferred until the first fast
698 * clear actually occurs.
700 if (intel_is_non_msrt_mcs_buffer_supported(brw
, singlesample_mt
))
701 singlesample_mt
->mcs_state
= INTEL_MCS_STATE_RESOLVED
;
703 if (num_samples
== 0)
704 return singlesample_mt
;
706 multisample_mt
= intel_miptree_create_for_renderbuffer(brw
,
711 if (!multisample_mt
) {
712 intel_miptree_release(&singlesample_mt
);
716 multisample_mt
->singlesample_mt
= singlesample_mt
;
717 multisample_mt
->need_downsample
= false;
719 if (brw
->is_front_buffer_rendering
&&
720 (dri_attachment
== __DRI_BUFFER_FRONT_LEFT
||
721 dri_attachment
== __DRI_BUFFER_FAKE_FRONT_LEFT
)) {
722 intel_miptree_upsample(brw
, multisample_mt
);
725 return multisample_mt
;
728 struct intel_mipmap_tree
*
729 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
733 uint32_t num_samples
)
735 struct intel_mipmap_tree
*mt
;
739 mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, format
, 0, 0,
740 width
, height
, depth
, true, num_samples
,
741 INTEL_MIPTREE_TILING_ANY
);
745 if (brw_is_hiz_depth_format(brw
, format
)) {
746 ok
= intel_miptree_alloc_hiz(brw
, mt
);
751 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
752 ok
= intel_miptree_alloc_mcs(brw
, mt
, num_samples
);
760 intel_miptree_release(&mt
);
765 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
766 struct intel_mipmap_tree
*src
)
771 intel_miptree_release(dst
);
775 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
783 intel_miptree_release(struct intel_mipmap_tree
**mt
)
788 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
789 if (--(*mt
)->refcount
<= 0) {
792 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
794 intel_region_release(&((*mt
)->region
));
795 intel_miptree_release(&(*mt
)->stencil_mt
);
796 intel_miptree_release(&(*mt
)->hiz_mt
);
797 intel_miptree_release(&(*mt
)->mcs_mt
);
798 intel_miptree_release(&(*mt
)->singlesample_mt
);
799 intel_resolve_map_clear(&(*mt
)->hiz_map
);
801 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
802 free((*mt
)->level
[i
].slice
);
811 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
812 int *width
, int *height
, int *depth
)
814 switch (image
->TexObject
->Target
) {
815 case GL_TEXTURE_1D_ARRAY
:
816 *width
= image
->Width
;
818 *depth
= image
->Height
;
821 *width
= image
->Width
;
822 *height
= image
->Height
;
823 *depth
= image
->Depth
;
829 * Can the image be pulled into a unified mipmap tree? This mirrors
830 * the completeness test in a lot of ways.
832 * Not sure whether I want to pass gl_texture_image here.
835 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
836 struct gl_texture_image
*image
)
838 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
839 GLuint level
= intelImage
->base
.Base
.Level
;
840 int width
, height
, depth
;
842 /* glTexImage* choose the texture object based on the target passed in, and
843 * objects can't change targets over their lifetimes, so this should be
846 assert(target_to_target(image
->TexObject
->Target
) == mt
->target
);
848 gl_format mt_format
= mt
->format
;
849 if (mt
->format
== MESA_FORMAT_X8_Z24
&& mt
->stencil_mt
)
850 mt_format
= MESA_FORMAT_S8_Z24
;
851 if (mt
->format
== MESA_FORMAT_Z32_FLOAT
&& mt
->stencil_mt
)
852 mt_format
= MESA_FORMAT_Z32_FLOAT_X24S8
;
853 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
854 mt_format
= mt
->etc_format
;
856 if (image
->TexFormat
!= mt_format
)
859 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
861 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
864 /* Test image dimensions against the base level image adjusted for
865 * minification. This will also catch images not present in the
866 * tree, changed targets, etc.
868 if (mt
->target
== GL_TEXTURE_2D_MULTISAMPLE
||
869 mt
->target
== GL_TEXTURE_2D_MULTISAMPLE_ARRAY
) {
870 /* nonzero level here is always bogus */
873 if (width
!= mt
->logical_width0
||
874 height
!= mt
->logical_height0
||
875 depth
!= mt
->logical_depth0
) {
880 /* all normal textures, renderbuffers, etc */
881 if (width
!= mt
->level
[level
].width
||
882 height
!= mt
->level
[level
].height
||
883 depth
!= mt
->level
[level
].depth
) {
888 if (image
->NumSamples
!= mt
->num_samples
)
896 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
899 GLuint w
, GLuint h
, GLuint d
)
901 mt
->level
[level
].width
= w
;
902 mt
->level
[level
].height
= h
;
903 mt
->level
[level
].depth
= d
;
904 mt
->level
[level
].level_x
= x
;
905 mt
->level
[level
].level_y
= y
;
907 DBG("%s level %d size: %d,%d,%d offset %d,%d\n", __FUNCTION__
,
908 level
, w
, h
, d
, x
, y
);
910 assert(mt
->level
[level
].slice
== NULL
);
912 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
913 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
914 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
919 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
920 GLuint level
, GLuint img
,
923 if (img
== 0 && level
== 0)
924 assert(x
== 0 && y
== 0);
926 assert(img
< mt
->level
[level
].depth
);
928 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
929 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
931 DBG("%s level %d img %d pos %d,%d\n",
932 __FUNCTION__
, level
, img
,
933 mt
->level
[level
].slice
[img
].x_offset
,
934 mt
->level
[level
].slice
[img
].y_offset
);
938 intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt
,
939 GLuint level
, GLuint slice
,
940 GLuint
*x
, GLuint
*y
)
942 assert(slice
< mt
->level
[level
].depth
);
944 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
945 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
949 * Rendering with tiled buffers requires that the base address of the buffer
950 * be aligned to a page boundary. For renderbuffers, and sometimes with
951 * textures, we may want the surface to point at a texture image level that
952 * isn't at a page boundary.
954 * This function returns an appropriately-aligned base offset
955 * according to the tiling restrictions, plus any required x/y offset
959 intel_miptree_get_tile_offsets(struct intel_mipmap_tree
*mt
,
960 GLuint level
, GLuint slice
,
964 struct intel_region
*region
= mt
->region
;
966 uint32_t mask_x
, mask_y
;
968 intel_region_get_tile_masks(region
, &mask_x
, &mask_y
, false);
969 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
971 *tile_x
= x
& mask_x
;
972 *tile_y
= y
& mask_y
;
974 return intel_region_get_aligned_offset(region
, x
& ~mask_x
, y
& ~mask_y
,
979 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
980 struct intel_mipmap_tree
*dst_mt
,
981 struct intel_mipmap_tree
*src_mt
,
988 int src_stride
, dst_stride
;
989 int cpp
= dst_mt
->cpp
;
991 intel_miptree_map(brw
, src_mt
,
995 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
998 intel_miptree_map(brw
, dst_mt
,
1002 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1006 DBG("sw blit %s mt %p %p/%d -> %s mt %p %p/%d (%dx%d)\n",
1007 _mesa_get_format_name(src_mt
->format
),
1008 src_mt
, src
, src_stride
,
1009 _mesa_get_format_name(dst_mt
->format
),
1010 dst_mt
, dst
, dst_stride
,
1013 int row_size
= cpp
* width
;
1014 if (src_stride
== row_size
&&
1015 dst_stride
== row_size
) {
1016 memcpy(dst
, src
, row_size
* height
);
1018 for (int i
= 0; i
< height
; i
++) {
1019 memcpy(dst
, src
, row_size
);
1025 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1026 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1028 /* Don't forget to copy the stencil data over, too. We could have skipped
1029 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1030 * shuffling the two data sources in/out of temporary storage instead of
1031 * the direct mapping we get this way.
1033 if (dst_mt
->stencil_mt
) {
1034 assert(src_mt
->stencil_mt
);
1035 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1036 level
, slice
, width
, height
);
1041 intel_miptree_copy_slice(struct brw_context
*brw
,
1042 struct intel_mipmap_tree
*dst_mt
,
1043 struct intel_mipmap_tree
*src_mt
,
1049 gl_format format
= src_mt
->format
;
1050 uint32_t width
= src_mt
->level
[level
].width
;
1051 uint32_t height
= src_mt
->level
[level
].height
;
1059 assert(depth
< src_mt
->level
[level
].depth
);
1060 assert(src_mt
->format
== dst_mt
->format
);
1062 if (dst_mt
->compressed
) {
1063 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1064 width
= ALIGN(width
, dst_mt
->align_w
);
1067 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1068 * below won't apply since we can't do the depth's Y tiling or the
1069 * stencil's W tiling in the blitter.
1071 if (src_mt
->stencil_mt
) {
1072 intel_miptree_copy_slice_sw(brw
,
1079 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1080 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1081 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1083 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1084 _mesa_get_format_name(src_mt
->format
),
1085 src_mt
, src_x
, src_y
, src_mt
->region
->pitch
,
1086 _mesa_get_format_name(dst_mt
->format
),
1087 dst_mt
, dst_x
, dst_y
, dst_mt
->region
->pitch
,
1090 if (!intel_miptree_blit(brw
,
1091 src_mt
, level
, slice
, 0, 0, false,
1092 dst_mt
, level
, slice
, 0, 0, false,
1093 width
, height
, GL_COPY
)) {
1094 perf_debug("miptree validate blit for %s failed\n",
1095 _mesa_get_format_name(format
));
1097 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1103 * Copies the image's current data to the given miptree, and associates that
1104 * miptree with the image.
1106 * If \c invalidate is true, then the actual image data does not need to be
1107 * copied, but the image still needs to be associated to the new miptree (this
1108 * is set to true if we're about to clear the image).
1111 intel_miptree_copy_teximage(struct brw_context
*brw
,
1112 struct intel_texture_image
*intelImage
,
1113 struct intel_mipmap_tree
*dst_mt
,
1116 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1117 struct intel_texture_object
*intel_obj
=
1118 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1119 int level
= intelImage
->base
.Base
.Level
;
1120 int face
= intelImage
->base
.Base
.Face
;
1121 GLuint depth
= intelImage
->base
.Base
.Depth
;
1124 for (int slice
= 0; slice
< depth
; slice
++) {
1125 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1129 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1130 intel_obj
->needs_validate
= true;
1134 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1135 struct intel_mipmap_tree
*mt
,
1138 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1139 assert(mt
->mcs_mt
== NULL
);
1141 /* Choose the correct format for the MCS buffer. All that really matters
1142 * is that we allocate the right buffer size, since we'll always be
1143 * accessing this miptree using MCS-specific hardware mechanisms, which
1144 * infer the correct format based on num_samples.
1147 switch (num_samples
) {
1149 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1152 format
= MESA_FORMAT_R8
;
1155 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1156 * for each sample, plus 8 padding bits).
1158 format
= MESA_FORMAT_R_UINT32
;
1161 assert(!"Unrecognized sample count in intel_miptree_alloc_mcs");
1165 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1167 * "The MCS surface must be stored as Tile Y."
1169 mt
->mcs_state
= INTEL_MCS_STATE_MSAA
;
1170 mt
->mcs_mt
= intel_miptree_create(brw
,
1176 mt
->logical_height0
,
1179 0 /* num_samples */,
1180 INTEL_MIPTREE_TILING_Y
);
1182 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1184 * When MCS buffer is enabled and bound to MSRT, it is required that it
1185 * is cleared prior to any rendering.
1187 * Since we don't use the MCS buffer for any purpose other than rendering,
1188 * it makes sense to just clear it immediately upon allocation.
1190 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1192 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1193 memset(data
, 0xff, mt
->mcs_mt
->region
->bo
->size
);
1194 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1201 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1202 struct intel_mipmap_tree
*mt
)
1204 assert(mt
->mcs_mt
== NULL
);
1206 /* The format of the MCS buffer is opaque to the driver; all that matters
1207 * is that we get its size and pitch right. We'll pretend that the format
1208 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1209 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1210 * the block width and then a further factor of 4. Since an MCS tile
1211 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1212 * we'll need to scale the height down by the block height and then a
1213 * further factor of 8.
1215 const gl_format format
= MESA_FORMAT_R_UINT32
;
1216 unsigned block_width_px
;
1217 unsigned block_height
;
1218 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1219 unsigned width_divisor
= block_width_px
* 4;
1220 unsigned height_divisor
= block_height
* 8;
1221 unsigned mcs_width
=
1222 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1223 unsigned mcs_height
=
1224 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1225 assert(mt
->logical_depth0
== 1);
1226 mt
->mcs_mt
= intel_miptree_create(brw
,
1235 0 /* num_samples */,
1236 INTEL_MIPTREE_TILING_Y
);
1243 * Helper for intel_miptree_alloc_hiz() that sets
1244 * \c mt->level[level].slice[layer].has_hiz. Return true if and only if
1245 * \c has_hiz was set.
1248 intel_miptree_slice_enable_hiz(struct brw_context
*brw
,
1249 struct intel_mipmap_tree
*mt
,
1255 if (brw
->is_haswell
) {
1256 const struct intel_mipmap_level
*l
= &mt
->level
[level
];
1258 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1259 * and the height is 4 aligned. This allows our HiZ support
1260 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1261 * we can grow the width & height to allow the HiZ op to
1262 * force the proper size alignments.
1264 if (level
> 0 && ((l
->width
& 7) || (l
->height
& 3))) {
1269 mt
->level
[level
].slice
[layer
].has_hiz
= true;
1276 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1277 struct intel_mipmap_tree
*mt
)
1279 assert(mt
->hiz_mt
== NULL
);
1280 mt
->hiz_mt
= intel_miptree_create(brw
,
1286 mt
->logical_height0
,
1290 INTEL_MIPTREE_TILING_ANY
);
1295 /* Mark that all slices need a HiZ resolve. */
1296 struct intel_resolve_map
*head
= &mt
->hiz_map
;
1297 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1298 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1299 if (!intel_miptree_slice_enable_hiz(brw
, mt
, level
, layer
))
1302 head
->next
= malloc(sizeof(*head
->next
));
1303 head
->next
->prev
= head
;
1304 head
->next
->next
= NULL
;
1307 head
->level
= level
;
1308 head
->layer
= layer
;
1309 head
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1317 * Does the miptree slice have hiz enabled?
1320 intel_miptree_slice_has_hiz(struct intel_mipmap_tree
*mt
,
1324 intel_miptree_check_level_layer(mt
, level
, layer
);
1325 return mt
->level
[level
].slice
[layer
].has_hiz
;
1329 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1333 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1336 intel_resolve_map_set(&mt
->hiz_map
,
1337 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1342 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1346 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1349 intel_resolve_map_set(&mt
->hiz_map
,
1350 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1354 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1358 uint32_t end_layer
= mt
->level
[level
].depth
;
1360 for (layer
= 0; layer
< end_layer
; layer
++) {
1361 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1366 intel_miptree_slice_resolve(struct brw_context
*brw
,
1367 struct intel_mipmap_tree
*mt
,
1370 enum gen6_hiz_op need
)
1372 intel_miptree_check_level_layer(mt
, level
, layer
);
1374 struct intel_resolve_map
*item
=
1375 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1377 if (!item
|| item
->need
!= need
)
1380 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1381 intel_resolve_map_remove(item
);
1386 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1387 struct intel_mipmap_tree
*mt
,
1391 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1392 GEN6_HIZ_OP_HIZ_RESOLVE
);
1396 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1397 struct intel_mipmap_tree
*mt
,
1401 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1402 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1406 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1407 struct intel_mipmap_tree
*mt
,
1408 enum gen6_hiz_op need
)
1410 bool did_resolve
= false;
1411 struct intel_resolve_map
*i
, *next
;
1413 for (i
= mt
->hiz_map
.next
; i
; i
= next
) {
1415 if (i
->need
!= need
)
1418 intel_hiz_exec(brw
, mt
, i
->level
, i
->layer
, need
);
1419 intel_resolve_map_remove(i
);
1427 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1428 struct intel_mipmap_tree
*mt
)
1430 return intel_miptree_all_slices_resolve(brw
, mt
,
1431 GEN6_HIZ_OP_HIZ_RESOLVE
);
1435 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1436 struct intel_mipmap_tree
*mt
)
1438 return intel_miptree_all_slices_resolve(brw
, mt
,
1439 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1444 intel_miptree_resolve_color(struct brw_context
*brw
,
1445 struct intel_mipmap_tree
*mt
)
1447 switch (mt
->mcs_state
) {
1448 case INTEL_MCS_STATE_NONE
:
1449 case INTEL_MCS_STATE_MSAA
:
1450 case INTEL_MCS_STATE_RESOLVED
:
1451 /* No resolve needed */
1453 case INTEL_MCS_STATE_UNRESOLVED
:
1454 case INTEL_MCS_STATE_CLEAR
:
1455 brw_blorp_resolve_color(brw
, mt
);
1462 * Make it possible to share the region backing the given miptree with another
1463 * process or another miptree.
1465 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1466 * then discard the MCS buffer, if present. We also set the mcs_state to
1467 * INTEL_MCS_STATE_NONE to ensure that no MCS buffer gets allocated in the
1471 intel_miptree_make_shareable(struct brw_context
*brw
,
1472 struct intel_mipmap_tree
*mt
)
1474 /* MCS buffers are also used for multisample buffers, but we can't resolve
1475 * away a multisample MCS buffer because it's an integral part of how the
1476 * pixel data is stored. Fortunately this code path should never be
1477 * reached for multisample buffers.
1479 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1482 intel_miptree_resolve_color(brw
, mt
);
1483 intel_miptree_release(&mt
->mcs_mt
);
1484 mt
->mcs_state
= INTEL_MCS_STATE_NONE
;
1490 * \brief Get pointer offset into stencil buffer.
1492 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1493 * must decode the tile's layout in software.
1496 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1498 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1500 * Even though the returned offset is always positive, the return type is
1502 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1503 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1506 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1508 uint32_t tile_size
= 4096;
1509 uint32_t tile_width
= 64;
1510 uint32_t tile_height
= 64;
1511 uint32_t row_size
= 64 * stride
;
1513 uint32_t tile_x
= x
/ tile_width
;
1514 uint32_t tile_y
= y
/ tile_height
;
1516 /* The byte's address relative to the tile's base addres. */
1517 uint32_t byte_x
= x
% tile_width
;
1518 uint32_t byte_y
= y
% tile_height
;
1520 uintptr_t u
= tile_y
* row_size
1521 + tile_x
* tile_size
1522 + 512 * (byte_x
/ 8)
1524 + 32 * ((byte_y
/ 4) % 2)
1525 + 16 * ((byte_x
/ 4) % 2)
1526 + 8 * ((byte_y
/ 2) % 2)
1527 + 4 * ((byte_x
/ 2) % 2)
1532 /* adjust for bit6 swizzling */
1533 if (((byte_x
/ 8) % 2) == 1) {
1534 if (((byte_y
/ 8) % 2) == 0) {
1546 intel_miptree_updownsample(struct brw_context
*brw
,
1547 struct intel_mipmap_tree
*src
,
1548 struct intel_mipmap_tree
*dst
,
1557 brw_blorp_blit_miptrees(brw
,
1558 src
, 0 /* level */, 0 /* layer */,
1559 dst
, 0 /* level */, 0 /* layer */,
1564 false, false /*mirror x, y*/);
1566 if (src
->stencil_mt
) {
1567 brw_blorp_blit_miptrees(brw
,
1568 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1569 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1574 false, false /*mirror x, y*/);
1579 assert_is_flat(struct intel_mipmap_tree
*mt
)
1581 assert(mt
->target
== GL_TEXTURE_2D
);
1582 assert(mt
->first_level
== 0);
1583 assert(mt
->last_level
== 0);
1587 * \brief Downsample from mt to mt->singlesample_mt.
1589 * If the miptree needs no downsample, then skip.
1592 intel_miptree_downsample(struct brw_context
*brw
,
1593 struct intel_mipmap_tree
*mt
)
1595 /* Only flat, renderbuffer-like miptrees are supported. */
1598 if (!mt
->need_downsample
)
1600 intel_miptree_updownsample(brw
,
1601 mt
, mt
->singlesample_mt
,
1603 mt
->logical_height0
);
1604 mt
->need_downsample
= false;
1608 * \brief Upsample from mt->singlesample_mt to mt.
1610 * The upsample is done unconditionally.
1613 intel_miptree_upsample(struct brw_context
*brw
,
1614 struct intel_mipmap_tree
*mt
)
1616 /* Only flat, renderbuffer-like miptrees are supported. */
1618 assert(!mt
->need_downsample
);
1620 intel_miptree_updownsample(brw
,
1621 mt
->singlesample_mt
, mt
,
1623 mt
->logical_height0
);
1627 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
1629 struct gl_context
*ctx
= &brw
->ctx
;
1630 /* CPU accesses to color buffers don't understand fast color clears, so
1631 * resolve any pending fast color clears before we map.
1633 intel_miptree_resolve_color(brw
, mt
);
1635 drm_intel_bo
*bo
= mt
->region
->bo
;
1637 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1638 if (drm_intel_bo_busy(bo
)) {
1639 perf_debug("Mapping a busy BO, causing a stall on the GPU.\n");
1645 if (mt
->region
->tiling
!= I915_TILING_NONE
)
1646 drm_intel_gem_bo_map_gtt(bo
);
1648 drm_intel_bo_map(bo
, true);
1654 intel_miptree_unmap_raw(struct brw_context
*brw
,
1655 struct intel_mipmap_tree
*mt
)
1657 drm_intel_bo_unmap(mt
->region
->bo
);
1661 intel_miptree_map_gtt(struct brw_context
*brw
,
1662 struct intel_mipmap_tree
*mt
,
1663 struct intel_miptree_map
*map
,
1664 unsigned int level
, unsigned int slice
)
1666 unsigned int bw
, bh
;
1668 unsigned int image_x
, image_y
;
1672 /* For compressed formats, the stride is the number of bytes per
1673 * row of blocks. intel_miptree_get_image_offset() already does
1676 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1677 assert(y
% bh
== 0);
1680 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
1685 /* Note that in the case of cube maps, the caller must have passed the
1686 * slice number referencing the face.
1688 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1692 map
->stride
= mt
->region
->pitch
;
1693 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1696 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1697 map
->x
, map
->y
, map
->w
, map
->h
,
1698 mt
, _mesa_get_format_name(mt
->format
),
1699 x
, y
, map
->ptr
, map
->stride
);
1703 intel_miptree_unmap_gtt(struct brw_context
*brw
,
1704 struct intel_mipmap_tree
*mt
,
1705 struct intel_miptree_map
*map
,
1709 intel_miptree_unmap_raw(brw
, mt
);
1713 intel_miptree_map_blit(struct brw_context
*brw
,
1714 struct intel_mipmap_tree
*mt
,
1715 struct intel_miptree_map
*map
,
1716 unsigned int level
, unsigned int slice
)
1718 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
1722 INTEL_MIPTREE_TILING_NONE
);
1724 fprintf(stderr
, "Failed to allocate blit temporary\n");
1727 map
->stride
= map
->mt
->region
->pitch
;
1729 if (!intel_miptree_blit(brw
,
1731 map
->x
, map
->y
, false,
1734 map
->w
, map
->h
, GL_COPY
)) {
1735 fprintf(stderr
, "Failed to blit\n");
1739 intel_batchbuffer_flush(brw
);
1740 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
1742 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1743 map
->x
, map
->y
, map
->w
, map
->h
,
1744 mt
, _mesa_get_format_name(mt
->format
),
1745 level
, slice
, map
->ptr
, map
->stride
);
1750 intel_miptree_release(&map
->mt
);
1756 intel_miptree_unmap_blit(struct brw_context
*brw
,
1757 struct intel_mipmap_tree
*mt
,
1758 struct intel_miptree_map
*map
,
1762 struct gl_context
*ctx
= &brw
->ctx
;
1764 intel_miptree_unmap_raw(brw
, map
->mt
);
1766 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1767 bool ok
= intel_miptree_blit(brw
,
1771 map
->x
, map
->y
, false,
1772 map
->w
, map
->h
, GL_COPY
);
1773 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
1776 intel_miptree_release(&map
->mt
);
1780 intel_miptree_map_s8(struct brw_context
*brw
,
1781 struct intel_mipmap_tree
*mt
,
1782 struct intel_miptree_map
*map
,
1783 unsigned int level
, unsigned int slice
)
1785 map
->stride
= map
->w
;
1786 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1790 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1791 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1792 * invalidate is set, since we'll be writing the whole rectangle from our
1793 * temporary buffer back out.
1795 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1796 uint8_t *untiled_s8_map
= map
->ptr
;
1797 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1798 unsigned int image_x
, image_y
;
1800 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1802 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1803 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1804 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1805 x
+ image_x
+ map
->x
,
1806 y
+ image_y
+ map
->y
,
1807 brw
->has_swizzling
);
1808 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
1812 intel_miptree_unmap_raw(brw
, mt
);
1814 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
1815 map
->x
, map
->y
, map
->w
, map
->h
,
1816 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
1818 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1819 map
->x
, map
->y
, map
->w
, map
->h
,
1820 mt
, map
->ptr
, map
->stride
);
1825 intel_miptree_unmap_s8(struct brw_context
*brw
,
1826 struct intel_mipmap_tree
*mt
,
1827 struct intel_miptree_map
*map
,
1831 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1832 unsigned int image_x
, image_y
;
1833 uint8_t *untiled_s8_map
= map
->ptr
;
1834 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1836 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1838 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1839 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1840 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1843 brw
->has_swizzling
);
1844 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
1848 intel_miptree_unmap_raw(brw
, mt
);
1855 intel_miptree_map_etc(struct brw_context
*brw
,
1856 struct intel_mipmap_tree
*mt
,
1857 struct intel_miptree_map
*map
,
1861 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
1862 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
1863 assert(mt
->format
== MESA_FORMAT_RGBX8888_REV
);
1866 assert(map
->mode
& GL_MAP_WRITE_BIT
);
1867 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
1869 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
1870 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
1871 map
->w
, map
->h
, 1));
1872 map
->ptr
= map
->buffer
;
1876 intel_miptree_unmap_etc(struct brw_context
*brw
,
1877 struct intel_mipmap_tree
*mt
,
1878 struct intel_miptree_map
*map
,
1884 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1889 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
1890 + image_y
* mt
->region
->pitch
1891 + image_x
* mt
->region
->cpp
;
1893 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
1894 _mesa_etc1_unpack_rgba8888(dst
, mt
->region
->pitch
,
1895 map
->ptr
, map
->stride
,
1898 _mesa_unpack_etc2_format(dst
, mt
->region
->pitch
,
1899 map
->ptr
, map
->stride
,
1900 map
->w
, map
->h
, mt
->etc_format
);
1902 intel_miptree_unmap_raw(brw
, mt
);
1907 * Mapping function for packed depth/stencil miptrees backed by real separate
1908 * miptrees for depth and stencil.
1910 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
1911 * separate from the depth buffer. Yet at the GL API level, we have to expose
1912 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
1913 * be able to map that memory for texture storage and glReadPixels-type
1914 * operations. We give Mesa core that access by mallocing a temporary and
1915 * copying the data between the actual backing store and the temporary.
1918 intel_miptree_map_depthstencil(struct brw_context
*brw
,
1919 struct intel_mipmap_tree
*mt
,
1920 struct intel_miptree_map
*map
,
1921 unsigned int level
, unsigned int slice
)
1923 struct intel_mipmap_tree
*z_mt
= mt
;
1924 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
1925 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z32_FLOAT
;
1926 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
1928 map
->stride
= map
->w
* packed_bpp
;
1929 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1933 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1934 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1935 * invalidate is set, since we'll be writing the whole rectangle from our
1936 * temporary buffer back out.
1938 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1939 uint32_t *packed_map
= map
->ptr
;
1940 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
1941 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
1942 unsigned int s_image_x
, s_image_y
;
1943 unsigned int z_image_x
, z_image_y
;
1945 intel_miptree_get_image_offset(s_mt
, level
, slice
,
1946 &s_image_x
, &s_image_y
);
1947 intel_miptree_get_image_offset(z_mt
, level
, slice
,
1948 &z_image_x
, &z_image_y
);
1950 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1951 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1952 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
1953 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
1956 brw
->has_swizzling
);
1957 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
1958 (z_mt
->region
->pitch
/ 4) +
1959 (map_x
+ z_image_x
));
1960 uint8_t s
= s_map
[s_offset
];
1961 uint32_t z
= z_map
[z_offset
];
1963 if (map_z32f_x24s8
) {
1964 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
1965 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
1967 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
1972 intel_miptree_unmap_raw(brw
, s_mt
);
1973 intel_miptree_unmap_raw(brw
, z_mt
);
1975 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
1977 map
->x
, map
->y
, map
->w
, map
->h
,
1978 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
1979 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
1980 map
->ptr
, map
->stride
);
1982 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1983 map
->x
, map
->y
, map
->w
, map
->h
,
1984 mt
, map
->ptr
, map
->stride
);
1989 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
1990 struct intel_mipmap_tree
*mt
,
1991 struct intel_miptree_map
*map
,
1995 struct intel_mipmap_tree
*z_mt
= mt
;
1996 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
1997 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z32_FLOAT
;
1999 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2000 uint32_t *packed_map
= map
->ptr
;
2001 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2002 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2003 unsigned int s_image_x
, s_image_y
;
2004 unsigned int z_image_x
, z_image_y
;
2006 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2007 &s_image_x
, &s_image_y
);
2008 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2009 &z_image_x
, &z_image_y
);
2011 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2012 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2013 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
2014 x
+ s_image_x
+ map
->x
,
2015 y
+ s_image_y
+ map
->y
,
2016 brw
->has_swizzling
);
2017 ptrdiff_t z_offset
= ((y
+ z_image_y
) *
2018 (z_mt
->region
->pitch
/ 4) +
2021 if (map_z32f_x24s8
) {
2022 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2023 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2025 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2026 s_map
[s_offset
] = packed
>> 24;
2027 z_map
[z_offset
] = packed
;
2032 intel_miptree_unmap_raw(brw
, s_mt
);
2033 intel_miptree_unmap_raw(brw
, z_mt
);
2035 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2037 map
->x
, map
->y
, map
->w
, map
->h
,
2038 z_mt
, _mesa_get_format_name(z_mt
->format
),
2039 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2040 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2041 map
->ptr
, map
->stride
);
2048 * Create and attach a map to the miptree at (level, slice). Return the
2051 static struct intel_miptree_map
*
2052 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2061 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2066 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2067 mt
->level
[level
].slice
[slice
].map
= map
;
2079 * Release the map at (level, slice).
2082 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2086 struct intel_miptree_map
**map
;
2088 map
= &mt
->level
[level
].slice
[slice
].map
;
2094 intel_miptree_map_singlesample(struct brw_context
*brw
,
2095 struct intel_mipmap_tree
*mt
,
2106 struct intel_miptree_map
*map
;
2108 assert(mt
->num_samples
<= 1);
2110 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2117 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2118 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2119 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2122 if (mt
->format
== MESA_FORMAT_S8
) {
2123 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2124 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2125 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2126 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2127 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2128 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2130 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2131 else if (brw
->has_llc
&&
2132 !(mode
& GL_MAP_WRITE_BIT
) &&
2134 (mt
->region
->tiling
== I915_TILING_X
||
2135 (brw
->gen
>= 6 && mt
->region
->tiling
== I915_TILING_Y
)) &&
2136 mt
->region
->pitch
< 32768) {
2137 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2138 } else if (mt
->region
->tiling
!= I915_TILING_NONE
&&
2139 mt
->region
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2140 assert(mt
->region
->pitch
< 32768);
2141 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2143 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2146 *out_ptr
= map
->ptr
;
2147 *out_stride
= map
->stride
;
2149 if (map
->ptr
== NULL
)
2150 intel_miptree_release_map(mt
, level
, slice
);
2154 intel_miptree_unmap_singlesample(struct brw_context
*brw
,
2155 struct intel_mipmap_tree
*mt
,
2159 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2161 assert(mt
->num_samples
<= 1);
2166 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
2167 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2169 if (mt
->format
== MESA_FORMAT_S8
) {
2170 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2171 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2172 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2173 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2174 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2175 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2176 } else if (map
->mt
) {
2177 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2179 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2182 intel_miptree_release_map(mt
, level
, slice
);
2186 intel_miptree_map_multisample(struct brw_context
*brw
,
2187 struct intel_mipmap_tree
*mt
,
2198 struct gl_context
*ctx
= &brw
->ctx
;
2199 struct intel_miptree_map
*map
;
2201 assert(mt
->num_samples
> 1);
2203 /* Only flat, renderbuffer-like miptrees are supported. */
2204 if (mt
->target
!= GL_TEXTURE_2D
||
2205 mt
->first_level
!= 0 ||
2206 mt
->last_level
!= 0) {
2207 _mesa_problem(ctx
, "attempt to map a multisample miptree for "
2208 "which (target, first_level, last_level != "
2209 "(GL_TEXTURE_2D, 0, 0)");
2213 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2217 if (!mt
->singlesample_mt
) {
2218 mt
->singlesample_mt
=
2219 intel_miptree_create_for_renderbuffer(brw
,
2222 mt
->logical_height0
,
2224 if (!mt
->singlesample_mt
)
2227 map
->singlesample_mt_is_tmp
= true;
2228 mt
->need_downsample
= true;
2231 intel_miptree_downsample(brw
, mt
);
2232 intel_miptree_map_singlesample(brw
, mt
->singlesample_mt
,
2236 out_ptr
, out_stride
);
2240 intel_miptree_release_map(mt
, level
, slice
);
2246 intel_miptree_unmap_multisample(struct brw_context
*brw
,
2247 struct intel_mipmap_tree
*mt
,
2251 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2253 assert(mt
->num_samples
> 1);
2258 intel_miptree_unmap_singlesample(brw
, mt
->singlesample_mt
, level
, slice
);
2260 mt
->need_downsample
= false;
2261 if (map
->mode
& GL_MAP_WRITE_BIT
)
2262 intel_miptree_upsample(brw
, mt
);
2264 if (map
->singlesample_mt_is_tmp
)
2265 intel_miptree_release(&mt
->singlesample_mt
);
2267 intel_miptree_release_map(mt
, level
, slice
);
2271 intel_miptree_map(struct brw_context
*brw
,
2272 struct intel_mipmap_tree
*mt
,
2283 if (mt
->num_samples
<= 1)
2284 intel_miptree_map_singlesample(brw
, mt
,
2288 out_ptr
, out_stride
);
2290 intel_miptree_map_multisample(brw
, mt
,
2294 out_ptr
, out_stride
);
2298 intel_miptree_unmap(struct brw_context
*brw
,
2299 struct intel_mipmap_tree
*mt
,
2303 if (mt
->num_samples
<= 1)
2304 intel_miptree_unmap_singlesample(brw
, mt
, level
, slice
);
2306 intel_miptree_unmap_multisample(brw
, mt
, level
, slice
);