2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
28 #include <drm_fourcc.h>
30 #include "intel_batchbuffer.h"
31 #include "intel_image.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_tex.h"
34 #include "intel_blit.h"
35 #include "intel_fbo.h"
37 #include "brw_blorp.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
48 #include "x86/common_x86_asm.h"
50 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
52 static void *intel_miptree_map_raw(struct brw_context
*brw
,
53 struct intel_mipmap_tree
*mt
,
56 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
59 intel_miptree_alloc_aux(struct brw_context
*brw
,
60 struct intel_mipmap_tree
*mt
);
63 intel_miptree_supports_mcs(struct brw_context
*brw
,
64 const struct intel_mipmap_tree
*mt
)
66 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
68 /* MCS compression only applies to multisampled miptrees */
69 if (mt
->surf
.samples
<= 1)
72 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
76 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
77 switch (_mesa_get_format_base_format(mt
->format
)) {
78 case GL_DEPTH_COMPONENT
:
79 case GL_STENCIL_INDEX
:
80 case GL_DEPTH_STENCIL
:
83 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
85 * This field must be set to 0 for all SINT MSRTs when all RT channels
88 * In practice this means that we have to disable MCS for all signed
89 * integer MSAA buffers. The alternative, to disable MCS only when one
90 * of the render target channels is disabled, is impractical because it
91 * would require converting between CMS and UMS MSAA layouts on the fly,
94 if (devinfo
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
103 intel_tiling_supports_ccs(const struct brw_context
*brw
,
104 enum isl_tiling tiling
)
106 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
108 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
109 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
111 * - Support is limited to tiled render targets.
113 * Gen9 changes the restriction to Y-tile only.
115 if (devinfo
->gen
>= 9)
116 return tiling
== ISL_TILING_Y0
;
117 else if (devinfo
->gen
>= 7)
118 return tiling
!= ISL_TILING_LINEAR
;
124 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
125 * can be used. This doesn't (and should not) inspect any of the properties of
128 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
129 * beneath the "Fast Color Clear" bullet (p326):
131 * - Support is for non-mip-mapped and non-array surface types only.
133 * And then later, on p327:
135 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
138 * From the Skylake documentation, it is made clear that X-tiling is no longer
141 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
145 intel_miptree_supports_ccs(struct brw_context
*brw
,
146 const struct intel_mipmap_tree
*mt
)
148 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
150 /* MCS support does not exist prior to Gen7 */
151 if (devinfo
->gen
< 7)
154 /* This function applies only to non-multisampled render targets. */
155 if (mt
->surf
.samples
> 1)
158 /* MCS is only supported for color buffers */
159 switch (_mesa_get_format_base_format(mt
->format
)) {
160 case GL_DEPTH_COMPONENT
:
161 case GL_DEPTH_STENCIL
:
162 case GL_STENCIL_INDEX
:
166 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
169 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
170 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
171 mt
->surf
.logical_level0_px
.depth
> 1;
174 /* Multisample surfaces with the CMS layout are not layered surfaces,
175 * yet still have physical_depth0 > 1. Assert that we don't
176 * accidentally reject a multisampled surface here. We should have
177 * rejected it earlier by explicitly checking the sample count.
179 assert(mt
->surf
.samples
== 1);
182 /* Handle the hardware restrictions...
184 * All GENs have the following restriction: "MCS buffer for non-MSRT is
185 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
187 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
188 * Non-MultiSampler Render Target Restrictions) Support is for
189 * non-mip-mapped and non-array surface types only.
191 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
192 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
193 * surfaces are supported with MCS buffer layout with these alignments in
194 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
196 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
197 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
198 * surfaces are supported with MCS buffer layout with these alignments in
199 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
201 if (devinfo
->gen
< 8 && (mip_mapped
|| arrayed
))
204 /* There's no point in using an MCS buffer if the surface isn't in a
207 if (!brw
->mesa_format_supports_render
[mt
->format
])
214 intel_tiling_supports_hiz(const struct brw_context
*brw
,
215 enum isl_tiling tiling
)
217 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
219 if (devinfo
->gen
< 6)
222 return tiling
== ISL_TILING_Y0
;
226 intel_miptree_supports_hiz(const struct brw_context
*brw
,
227 const struct intel_mipmap_tree
*mt
)
232 switch (mt
->format
) {
233 case MESA_FORMAT_Z_FLOAT32
:
234 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
235 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
236 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
237 case MESA_FORMAT_Z_UNORM16
:
245 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
246 const struct intel_mipmap_tree
*mt
)
248 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
250 if (devinfo
->gen
< 9)
253 /* For now compression is only enabled for integer formats even though
254 * there exist supported floating point formats also. This is a heuristic
255 * decision based on current public benchmarks. In none of the cases these
256 * formats provided any improvement but a few cases were seen to regress.
257 * Hence these are left to to be enabled in the future when they are known
260 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
263 if (!intel_miptree_supports_ccs(brw
, mt
))
266 /* Many window system buffers are sRGB even if they are never rendered as
267 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
268 * surface is used as sRGB, we fall back to CCS_D.
270 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
271 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
272 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
276 * Determine depth format corresponding to a depth+stencil format,
277 * for separate stencil.
280 intel_depth_format_for_depthstencil_format(mesa_format format
) {
282 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
283 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
284 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
285 return MESA_FORMAT_Z_FLOAT32
;
292 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
293 unsigned depth0
, struct intel_mipmap_level
*table
)
295 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
297 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
299 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
300 if (!table
[level
].slice
)
307 for (unsigned level
= first_level
; level
<= last_level
; level
++)
308 free(table
[level
].slice
);
314 needs_separate_stencil(const struct brw_context
*brw
,
315 struct intel_mipmap_tree
*mt
,
318 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
320 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
323 if (devinfo
->must_use_separate_stencil
)
326 return brw
->has_separate_stencil
&&
327 intel_miptree_supports_hiz(brw
, mt
);
331 * Choose the aux usage for this miptree. This function must be called fairly
332 * late in the miptree create process after we have a tiling.
335 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
336 struct intel_mipmap_tree
*mt
)
338 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
340 if (intel_miptree_supports_mcs(brw
, mt
)) {
341 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
342 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
343 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
344 intel_miptree_supports_ccs(brw
, mt
)) {
345 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
346 intel_miptree_supports_ccs_e(brw
, mt
)) {
347 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
349 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
351 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
352 intel_miptree_supports_hiz(brw
, mt
)) {
353 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
356 /* We can do fast-clear on all auxiliary surface types that are
357 * allocated through the normal texture creation paths.
359 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
360 mt
->supports_fast_clear
= true;
365 * Choose an appropriate uncompressed format for a requested
366 * compressed format, if unsupported.
369 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
371 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
373 /* No need to lower ETC formats on these platforms,
374 * they are supported natively.
376 if (devinfo
->gen
>= 8 || devinfo
->is_baytrail
)
380 case MESA_FORMAT_ETC1_RGB8
:
381 return MESA_FORMAT_R8G8B8X8_UNORM
;
382 case MESA_FORMAT_ETC2_RGB8
:
383 return MESA_FORMAT_R8G8B8X8_UNORM
;
384 case MESA_FORMAT_ETC2_SRGB8
:
385 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
386 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
387 return MESA_FORMAT_B8G8R8A8_SRGB
;
388 case MESA_FORMAT_ETC2_RGBA8_EAC
:
389 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
390 return MESA_FORMAT_R8G8B8A8_UNORM
;
391 case MESA_FORMAT_ETC2_R11_EAC
:
392 return MESA_FORMAT_R_UNORM16
;
393 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
394 return MESA_FORMAT_R_SNORM16
;
395 case MESA_FORMAT_ETC2_RG11_EAC
:
396 return MESA_FORMAT_R16G16_UNORM
;
397 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
398 return MESA_FORMAT_R16G16_SNORM
;
400 /* Non ETC1 / ETC2 format */
406 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
408 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
409 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
411 return mt
->surf
.logical_level0_px
.array_len
;
414 UNUSED
static unsigned
415 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
417 /* In case of physical dimensions one needs to consider also the layout.
418 * See isl_calc_phys_level0_extent_sa().
420 if (surf
->dim
!= ISL_SURF_DIM_3D
)
421 return surf
->phys_level0_sa
.array_len
;
423 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
424 return minify(surf
->phys_level0_sa
.array_len
, level
);
426 return minify(surf
->phys_level0_sa
.depth
, level
);
429 /** \brief Assert that the level and layer are valid for the miptree. */
431 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
439 assert(level
>= mt
->first_level
);
440 assert(level
<= mt
->last_level
);
441 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
444 static enum isl_aux_state
**
445 create_aux_state_map(struct intel_mipmap_tree
*mt
,
446 enum isl_aux_state initial
)
448 const uint32_t levels
= mt
->last_level
+ 1;
450 uint32_t total_slices
= 0;
451 for (uint32_t level
= 0; level
< levels
; level
++)
452 total_slices
+= brw_get_num_logical_layers(mt
, level
);
454 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
456 /* We're going to allocate a single chunk of data for both the per-level
457 * reference array and the arrays of aux_state. This makes cleanup
458 * significantly easier.
460 const size_t total_size
= per_level_array_size
+
461 total_slices
* sizeof(enum isl_aux_state
);
462 void *data
= malloc(total_size
);
466 enum isl_aux_state
**per_level_arr
= data
;
467 enum isl_aux_state
*s
= data
+ per_level_array_size
;
468 for (uint32_t level
= 0; level
< levels
; level
++) {
469 per_level_arr
[level
] = s
;
470 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
471 for (uint32_t a
= 0; a
< level_layers
; a
++)
474 assert((void *)s
== data
+ total_size
);
476 return per_level_arr
;
480 free_aux_state_map(enum isl_aux_state
**state
)
486 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
487 enum isl_tiling tiling
, unsigned samples
)
492 if (tiling
== ISL_TILING_LINEAR
)
495 /* If the width is much smaller than a tile, don't bother tiling. */
499 if (ALIGN(row_pitch
, 512) >= 32768) {
500 perf_debug("row pitch %u too large to blit, falling back to untiled",
509 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
510 enum isl_tiling tiling
)
512 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
514 /* If the BO is too large to fit in the aperture, we need to use the
515 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
516 * handle Y-tiling, so we need to fall back to X.
518 if (devinfo
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
519 tiling
== ISL_TILING_Y0
)
525 static struct intel_mipmap_tree
*
526 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
527 unsigned first_level
, unsigned last_level
,
528 unsigned width0
, unsigned height0
, unsigned depth0
,
529 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
530 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
531 unsigned row_pitch
, struct brw_bo
*bo
)
533 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
537 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
545 if (target
== GL_TEXTURE_CUBE_MAP
||
546 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
547 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
549 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
551 _mesa_enum_to_string(target
),
552 _mesa_get_format_name(format
),
553 num_samples
, width0
, height0
, depth0
,
554 first_level
, last_level
, mt
);
556 struct isl_surf_init_info init_info
= {
557 .dim
= get_isl_surf_dim(target
),
558 .format
= translate_tex_format(brw
, format
, false),
561 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
562 .levels
= last_level
- first_level
+ 1,
563 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
564 .samples
= num_samples
,
565 .row_pitch
= row_pitch
,
566 .usage
= isl_usage_flags
,
567 .tiling_flags
= tiling_flags
,
570 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
573 /* In case caller doesn't specifically request Y-tiling (needed
574 * unconditionally for depth), check for corner cases needing special
577 if (tiling_flags
& ~ISL_TILING_Y0_BIT
) {
578 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
579 mt
->surf
.tiling
, mt
->surf
.samples
)) {
580 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
581 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
583 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
584 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
585 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
590 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
591 * the size may not be multiple of row_pitch.
592 * See isl_apply_surface_padding().
594 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
595 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
598 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
600 isl_tiling_to_i915_tiling(
602 mt
->surf
.row_pitch
, alloc_flags
);
609 mt
->first_level
= first_level
;
610 mt
->last_level
= last_level
;
613 mt
->aux_state
= NULL
;
614 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
615 mt
->compressed
= _mesa_is_format_compressed(format
);
616 mt
->drm_modifier
= DRM_FORMAT_MOD_INVALID
;
621 intel_miptree_release(&mt
);
626 make_separate_stencil_surface(struct brw_context
*brw
,
627 struct intel_mipmap_tree
*mt
)
629 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
630 0, mt
->surf
.levels
- 1,
631 mt
->surf
.logical_level0_px
.width
,
632 mt
->surf
.logical_level0_px
.height
,
633 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
634 mt
->surf
.logical_level0_px
.depth
:
635 mt
->surf
.logical_level0_px
.array_len
,
636 mt
->surf
.samples
, ISL_TILING_W_BIT
,
637 ISL_SURF_USAGE_STENCIL_BIT
|
638 ISL_SURF_USAGE_TEXTURE_BIT
,
639 BO_ALLOC_BUSY
, 0, NULL
);
644 mt
->stencil_mt
->r8stencil_needs_update
= true;
649 static struct intel_mipmap_tree
*
650 miptree_create(struct brw_context
*brw
,
659 enum intel_miptree_create_flags flags
)
661 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
663 if (format
== MESA_FORMAT_S_UINT8
)
664 return make_surface(brw
, target
, format
, first_level
, last_level
,
665 width0
, height0
, depth0
, num_samples
,
667 ISL_SURF_USAGE_STENCIL_BIT
|
668 ISL_SURF_USAGE_TEXTURE_BIT
,
673 const GLenum base_format
= _mesa_get_format_base_format(format
);
674 if ((base_format
== GL_DEPTH_COMPONENT
||
675 base_format
== GL_DEPTH_STENCIL
) &&
676 !(flags
& MIPTREE_CREATE_LINEAR
)) {
677 /* Fix up the Z miptree format for how we're splitting out separate
678 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
680 const mesa_format depth_only_format
=
681 intel_depth_format_for_depthstencil_format(format
);
682 struct intel_mipmap_tree
*mt
= make_surface(
683 brw
, target
, devinfo
->gen
>= 6 ? depth_only_format
: format
,
684 first_level
, last_level
,
685 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
686 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
687 BO_ALLOC_BUSY
, 0, NULL
);
689 if (needs_separate_stencil(brw
, mt
, format
) &&
690 !make_separate_stencil_surface(brw
, mt
)) {
691 intel_miptree_release(&mt
);
695 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
696 intel_miptree_choose_aux_usage(brw
, mt
);
701 mesa_format tex_format
= format
;
702 mesa_format etc_format
= MESA_FORMAT_NONE
;
703 uint32_t alloc_flags
= 0;
705 format
= intel_lower_compressed_format(brw
, format
);
707 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
709 if (flags
& MIPTREE_CREATE_BUSY
)
710 alloc_flags
|= BO_ALLOC_BUSY
;
712 isl_tiling_flags_t tiling_flags
= (flags
& MIPTREE_CREATE_LINEAR
) ?
713 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
715 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
716 if (devinfo
->gen
< 6)
717 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
719 struct intel_mipmap_tree
*mt
= make_surface(
721 first_level
, last_level
,
722 width0
, height0
, depth0
,
723 num_samples
, tiling_flags
,
724 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
725 ISL_SURF_USAGE_TEXTURE_BIT
,
726 alloc_flags
, 0, NULL
);
730 mt
->etc_format
= etc_format
;
732 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
733 intel_miptree_choose_aux_usage(brw
, mt
);
738 struct intel_mipmap_tree
*
739 intel_miptree_create(struct brw_context
*brw
,
748 enum intel_miptree_create_flags flags
)
750 assert(num_samples
> 0);
752 struct intel_mipmap_tree
*mt
= miptree_create(
754 first_level
, last_level
,
755 width0
, height0
, depth0
, num_samples
,
762 if (!intel_miptree_alloc_aux(brw
, mt
)) {
763 intel_miptree_release(&mt
);
770 struct intel_mipmap_tree
*
771 intel_miptree_create_for_bo(struct brw_context
*brw
,
779 enum intel_miptree_create_flags flags
)
781 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
782 struct intel_mipmap_tree
*mt
;
783 uint32_t tiling
, swizzle
;
784 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
785 const GLenum base_format
= _mesa_get_format_base_format(format
);
787 if ((base_format
== GL_DEPTH_COMPONENT
||
788 base_format
== GL_DEPTH_STENCIL
)) {
789 const mesa_format depth_only_format
=
790 intel_depth_format_for_depthstencil_format(format
);
791 mt
= make_surface(brw
, target
,
792 devinfo
->gen
>= 6 ? depth_only_format
: format
,
793 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
794 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
795 BO_ALLOC_BUSY
, pitch
, bo
);
799 brw_bo_reference(bo
);
801 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
802 intel_miptree_choose_aux_usage(brw
, mt
);
805 } else if (format
== MESA_FORMAT_S_UINT8
) {
806 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
807 0, 0, width
, height
, depth
, 1,
809 ISL_SURF_USAGE_STENCIL_BIT
|
810 ISL_SURF_USAGE_TEXTURE_BIT
,
811 BO_ALLOC_BUSY
, pitch
, bo
);
815 assert(bo
->size
>= mt
->surf
.size
);
817 brw_bo_reference(bo
);
821 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
823 /* Nothing will be able to use this miptree with the BO if the offset isn't
826 if (tiling
!= I915_TILING_NONE
)
827 assert(offset
% 4096 == 0);
829 /* miptrees can't handle negative pitch. If you need flipping of images,
830 * that's outside of the scope of the mt.
834 /* The BO already has a tiling format and we shouldn't confuse the lower
835 * layers by making it try to find a tiling format again.
837 assert((flags
& MIPTREE_CREATE_LINEAR
) == 0);
839 mt
= make_surface(brw
, target
, format
,
840 0, 0, width
, height
, depth
, 1,
841 1lu << isl_tiling_from_i915_tiling(tiling
),
842 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
843 ISL_SURF_USAGE_TEXTURE_BIT
,
848 brw_bo_reference(bo
);
852 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
853 intel_miptree_choose_aux_usage(brw
, mt
);
855 if (!intel_miptree_alloc_aux(brw
, mt
)) {
856 intel_miptree_release(&mt
);
864 static struct intel_mipmap_tree
*
865 miptree_create_for_planar_image(struct brw_context
*brw
,
866 __DRIimage
*image
, GLenum target
)
868 const struct intel_image_format
*f
= image
->planar_format
;
869 struct intel_mipmap_tree
*planar_mt
= NULL
;
871 for (int i
= 0; i
< f
->nplanes
; i
++) {
872 const int index
= f
->planes
[i
].buffer_index
;
873 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
874 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
875 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
876 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
878 /* Disable creation of the texture's aux buffers because the driver
879 * exposes no EGL API to manage them. That is, there is no API for
880 * resolving the aux buffer's content to the main buffer nor for
881 * invalidating the aux buffer's content.
883 struct intel_mipmap_tree
*mt
=
884 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
885 image
->offsets
[index
],
887 image
->strides
[index
],
888 MIPTREE_CREATE_NO_AUX
);
897 planar_mt
->plane
[i
- 1] = mt
;
900 planar_mt
->drm_modifier
= image
->modifier
;
906 create_ccs_buf_for_image(struct brw_context
*brw
,
908 struct intel_mipmap_tree
*mt
,
909 enum isl_aux_state initial_state
)
911 struct isl_surf temp_ccs_surf
;
913 /* CCS is only supported for very simple miptrees */
914 assert(image
->aux_offset
!= 0 && image
->aux_pitch
!= 0);
915 assert(image
->tile_x
== 0 && image
->tile_y
== 0);
916 assert(mt
->surf
.samples
== 1);
917 assert(mt
->surf
.levels
== 1);
918 assert(mt
->surf
.logical_level0_px
.depth
== 1);
919 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
920 assert(mt
->first_level
== 0);
921 assert(mt
->last_level
== 0);
923 /* We shouldn't already have a CCS */
924 assert(!mt
->mcs_buf
);
926 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
,
930 assert(image
->aux_offset
< image
->bo
->size
);
931 assert(temp_ccs_surf
.size
<= image
->bo
->size
- image
->aux_offset
);
933 mt
->mcs_buf
= calloc(sizeof(*mt
->mcs_buf
), 1);
934 if (mt
->mcs_buf
== NULL
)
937 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
938 if (!mt
->aux_state
) {
944 mt
->mcs_buf
->bo
= image
->bo
;
945 brw_bo_reference(image
->bo
);
947 mt
->mcs_buf
->offset
= image
->aux_offset
;
948 mt
->mcs_buf
->size
= image
->bo
->size
- image
->aux_offset
;
949 mt
->mcs_buf
->pitch
= image
->aux_pitch
;
950 mt
->mcs_buf
->qpitch
= 0;
951 mt
->mcs_buf
->surf
= temp_ccs_surf
;
956 struct intel_mipmap_tree
*
957 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
958 __DRIimage
*image
, GLenum target
,
959 enum isl_colorspace colorspace
,
960 bool is_winsys_image
)
962 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1) {
963 assert(colorspace
== ISL_COLORSPACE_NONE
||
964 colorspace
== ISL_COLORSPACE_YUV
);
965 return miptree_create_for_planar_image(brw
, image
, target
);
968 if (image
->planar_format
)
969 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
971 mesa_format format
= image
->format
;
972 switch (colorspace
) {
973 case ISL_COLORSPACE_NONE
:
974 /* Keep the image format unmodified */
977 case ISL_COLORSPACE_LINEAR
:
978 format
=_mesa_get_srgb_format_linear(format
);
981 case ISL_COLORSPACE_SRGB
:
982 format
=_mesa_get_linear_format_srgb(format
);
986 unreachable("Inalid colorspace for non-planar image");
989 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
990 /* The texture storage paths in core Mesa detect if the driver does not
991 * support the user-requested format, and then searches for a
992 * fallback format. The DRIimage code bypasses core Mesa, though. So we
993 * do the fallbacks here for important formats.
995 * We must support DRM_FOURCC_XBGR8888 textures because the Android
996 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
997 * the Chrome OS compositor consumes as dma_buf EGLImages.
999 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1002 if (!brw
->ctx
.TextureFormatSupported
[format
])
1005 const struct isl_drm_modifier_info
*mod_info
=
1006 isl_drm_modifier_get_info(image
->modifier
);
1008 enum intel_miptree_create_flags mt_create_flags
= 0;
1010 /* If this image comes in from a window system, we have different
1011 * requirements than if it comes in via an EGL import operation. Window
1012 * system images can use any form of auxiliary compression we wish because
1013 * they get "flushed" before being handed off to the window system and we
1014 * have the opportunity to do resolves. Non window-system images, on the
1015 * other hand, have no resolve point so we can't have aux without a
1018 if (!is_winsys_image
)
1019 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1021 /* If we have a modifier which specifies aux, don't create one yet */
1022 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
1023 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1025 /* Disable creation of the texture's aux buffers because the driver exposes
1026 * no EGL API to manage them. That is, there is no API for resolving the aux
1027 * buffer's content to the main buffer nor for invalidating the aux buffer's
1030 struct intel_mipmap_tree
*mt
=
1031 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1032 image
->offset
, image
->width
, image
->height
, 1,
1033 image
->pitch
, mt_create_flags
);
1037 mt
->target
= target
;
1038 mt
->level
[0].level_x
= image
->tile_x
;
1039 mt
->level
[0].level_y
= image
->tile_y
;
1040 mt
->drm_modifier
= image
->modifier
;
1042 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1043 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1044 * trouble resolving back to destination image due to alignment issues.
1046 if (!brw
->has_surface_tile_offset
) {
1047 uint32_t draw_x
, draw_y
;
1048 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1050 if (draw_x
!= 0 || draw_y
!= 0) {
1051 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1052 intel_miptree_release(&mt
);
1057 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1058 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1060 mt
->aux_usage
= mod_info
->aux_usage
;
1061 /* If we are a window system buffer, then we can support fast-clears
1062 * even if the modifier doesn't support them by doing a partial resolve
1063 * as part of the flush operation.
1065 mt
->supports_fast_clear
=
1066 is_winsys_image
|| mod_info
->supports_clear_color
;
1068 /* We don't know the actual state of the surface when we get it but we
1069 * can make a pretty good guess based on the modifier. What we do know
1070 * for sure is that it isn't in the AUX_INVALID state, so we just assume
1071 * a worst case of compression.
1073 enum isl_aux_state initial_state
=
1074 mod_info
->supports_clear_color
? ISL_AUX_STATE_COMPRESSED_CLEAR
:
1075 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
;
1077 if (!create_ccs_buf_for_image(brw
, image
, mt
, initial_state
)) {
1078 intel_miptree_release(&mt
);
1083 /* Don't assume coherency for imported EGLimages. We don't know what
1084 * external clients are going to do with it. They may scan it out.
1086 image
->bo
->cache_coherent
= false;
1092 * For a singlesample renderbuffer, this simply wraps the given BO with a
1095 * For a multisample renderbuffer, this wraps the window system's
1096 * (singlesample) BO with a singlesample miptree attached to the
1097 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1098 * that will contain the actual rendering (which is lazily resolved to
1099 * irb->singlesample_mt).
1102 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1103 struct intel_renderbuffer
*irb
,
1104 struct intel_mipmap_tree
*singlesample_mt
,
1105 uint32_t width
, uint32_t height
,
1108 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1109 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1110 mesa_format format
= rb
->Format
;
1111 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1113 /* Only the front and back buffers, which are color buffers, are allocated
1114 * through the image loader.
1116 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1117 _mesa_get_format_base_format(format
) == GL_RGBA
);
1119 assert(singlesample_mt
);
1121 if (num_samples
== 1) {
1122 intel_miptree_release(&irb
->mt
);
1123 irb
->mt
= singlesample_mt
;
1125 assert(!irb
->singlesample_mt
);
1127 intel_miptree_release(&irb
->singlesample_mt
);
1128 irb
->singlesample_mt
= singlesample_mt
;
1131 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1132 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1133 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1138 if (!multisample_mt
)
1141 irb
->need_downsample
= false;
1142 intel_miptree_release(&irb
->mt
);
1143 irb
->mt
= multisample_mt
;
1149 intel_miptree_release(&irb
->mt
);
1153 struct intel_mipmap_tree
*
1154 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1158 uint32_t num_samples
)
1160 struct intel_mipmap_tree
*mt
;
1162 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1164 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1165 width
, height
, depth
, num_samples
,
1166 MIPTREE_CREATE_BUSY
);
1173 intel_miptree_release(&mt
);
1178 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1179 struct intel_mipmap_tree
*src
)
1184 intel_miptree_release(dst
);
1188 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1195 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1197 if (aux_buf
== NULL
)
1200 brw_bo_unreference(aux_buf
->bo
);
1206 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1211 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1212 if (--(*mt
)->refcount
<= 0) {
1215 DBG("%s deleting %p\n", __func__
, *mt
);
1217 brw_bo_unreference((*mt
)->bo
);
1218 intel_miptree_release(&(*mt
)->stencil_mt
);
1219 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1220 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1221 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1222 free_aux_state_map((*mt
)->aux_state
);
1224 intel_miptree_release(&(*mt
)->plane
[0]);
1225 intel_miptree_release(&(*mt
)->plane
[1]);
1227 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1228 free((*mt
)->level
[i
].slice
);
1238 intel_get_image_dims(struct gl_texture_image
*image
,
1239 int *width
, int *height
, int *depth
)
1241 switch (image
->TexObject
->Target
) {
1242 case GL_TEXTURE_1D_ARRAY
:
1243 /* For a 1D Array texture the OpenGL API will treat the image height as
1244 * the number of array slices. For Intel hardware, we treat the 1D array
1245 * as a 2D Array with a height of 1. So, here we want to swap image
1248 assert(image
->Depth
== 1);
1249 *width
= image
->Width
;
1251 *depth
= image
->Height
;
1253 case GL_TEXTURE_CUBE_MAP
:
1254 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1255 * though we really have 6 slices.
1257 assert(image
->Depth
== 1);
1258 *width
= image
->Width
;
1259 *height
= image
->Height
;
1263 *width
= image
->Width
;
1264 *height
= image
->Height
;
1265 *depth
= image
->Depth
;
1271 * Can the image be pulled into a unified mipmap tree? This mirrors
1272 * the completeness test in a lot of ways.
1274 * Not sure whether I want to pass gl_texture_image here.
1277 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1278 struct gl_texture_image
*image
)
1280 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1281 GLuint level
= intelImage
->base
.Base
.Level
;
1282 int width
, height
, depth
;
1284 /* glTexImage* choose the texture object based on the target passed in, and
1285 * objects can't change targets over their lifetimes, so this should be
1288 assert(image
->TexObject
->Target
== mt
->target
);
1290 mesa_format mt_format
= mt
->format
;
1291 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1292 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1293 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1294 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1295 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1296 mt_format
= mt
->etc_format
;
1298 if (image
->TexFormat
!= mt_format
)
1301 intel_get_image_dims(image
, &width
, &height
, &depth
);
1303 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1306 if (level
>= mt
->surf
.levels
)
1309 const unsigned level_depth
=
1310 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1311 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1312 mt
->surf
.logical_level0_px
.array_len
;
1314 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1315 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1316 depth
== level_depth
&&
1317 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1321 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1322 GLuint level
, GLuint slice
,
1323 GLuint
*x
, GLuint
*y
)
1325 if (level
== 0 && slice
== 0) {
1326 *x
= mt
->level
[0].level_x
;
1327 *y
= mt
->level
[0].level_y
;
1331 uint32_t x_offset_sa
, y_offset_sa
;
1333 /* Miptree itself can have an offset only if it represents a single
1334 * slice in an imported buffer object.
1335 * See intel_miptree_create_for_dri_image().
1337 assert(mt
->level
[0].level_x
== 0);
1338 assert(mt
->level
[0].level_y
== 0);
1340 /* Given level is relative to level zero while the miptree may be
1341 * represent just a subset of all levels starting from 'first_level'.
1343 assert(level
>= mt
->first_level
);
1344 level
-= mt
->first_level
;
1346 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1347 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1348 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1349 &x_offset_sa
, &y_offset_sa
);
1357 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1358 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1359 * and tile_h is set to 1.
1362 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1363 uint32_t *tile_w
, uint32_t *tile_h
)
1374 case ISL_TILING_LINEAR
:
1379 unreachable("not reached");
1385 * This function computes masks that may be used to select the bits of the X
1386 * and Y coordinates that indicate the offset within a tile. If the BO is
1387 * untiled, the masks are set to 0.
1390 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1391 uint32_t *mask_x
, uint32_t *mask_y
)
1393 uint32_t tile_w_bytes
, tile_h
;
1395 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1397 *mask_x
= tile_w_bytes
/ cpp
- 1;
1398 *mask_y
= tile_h
- 1;
1402 * Compute the offset (in bytes) from the start of the BO to the given x
1403 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1404 * multiples of the tile size.
1407 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1408 uint32_t x
, uint32_t y
)
1411 uint32_t pitch
= mt
->surf
.row_pitch
;
1413 switch (mt
->surf
.tiling
) {
1415 unreachable("not reached");
1416 case ISL_TILING_LINEAR
:
1417 return y
* pitch
+ x
* cpp
;
1419 assert((x
% (512 / cpp
)) == 0);
1420 assert((y
% 8) == 0);
1421 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1423 assert((x
% (128 / cpp
)) == 0);
1424 assert((y
% 32) == 0);
1425 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1430 * Rendering with tiled buffers requires that the base address of the buffer
1431 * be aligned to a page boundary. For renderbuffers, and sometimes with
1432 * textures, we may want the surface to point at a texture image level that
1433 * isn't at a page boundary.
1435 * This function returns an appropriately-aligned base offset
1436 * according to the tiling restrictions, plus any required x/y offset
1440 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1441 GLuint level
, GLuint slice
,
1446 uint32_t mask_x
, mask_y
;
1448 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1449 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1451 *tile_x
= x
& mask_x
;
1452 *tile_y
= y
& mask_y
;
1454 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1458 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1459 struct intel_mipmap_tree
*src_mt
,
1460 unsigned src_level
, unsigned src_layer
,
1461 struct intel_mipmap_tree
*dst_mt
,
1462 unsigned dst_level
, unsigned dst_layer
,
1463 unsigned width
, unsigned height
)
1466 ptrdiff_t src_stride
, dst_stride
;
1467 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1469 intel_miptree_map(brw
, src_mt
,
1470 src_level
, src_layer
,
1473 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1476 intel_miptree_map(brw
, dst_mt
,
1477 dst_level
, dst_layer
,
1480 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1484 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1485 _mesa_get_format_name(src_mt
->format
),
1486 src_mt
, src
, src_stride
,
1487 _mesa_get_format_name(dst_mt
->format
),
1488 dst_mt
, dst
, dst_stride
,
1491 int row_size
= cpp
* width
;
1492 if (src_stride
== row_size
&&
1493 dst_stride
== row_size
) {
1494 memcpy(dst
, src
, row_size
* height
);
1496 for (int i
= 0; i
< height
; i
++) {
1497 memcpy(dst
, src
, row_size
);
1503 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1504 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1506 /* Don't forget to copy the stencil data over, too. We could have skipped
1507 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1508 * shuffling the two data sources in/out of temporary storage instead of
1509 * the direct mapping we get this way.
1511 if (dst_mt
->stencil_mt
) {
1512 assert(src_mt
->stencil_mt
);
1513 intel_miptree_copy_slice_sw(brw
,
1514 src_mt
->stencil_mt
, src_level
, src_layer
,
1515 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1521 intel_miptree_copy_slice(struct brw_context
*brw
,
1522 struct intel_mipmap_tree
*src_mt
,
1523 unsigned src_level
, unsigned src_layer
,
1524 struct intel_mipmap_tree
*dst_mt
,
1525 unsigned dst_level
, unsigned dst_layer
)
1528 mesa_format format
= src_mt
->format
;
1529 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1530 src_level
- src_mt
->first_level
);
1531 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1532 src_level
- src_mt
->first_level
);
1534 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1535 src_level
- src_mt
->first_level
));
1537 assert(src_mt
->format
== dst_mt
->format
);
1539 if (dst_mt
->compressed
) {
1541 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1542 height
= ALIGN_NPOT(height
, j
) / j
;
1543 width
= ALIGN_NPOT(width
, i
) / i
;
1546 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1547 * below won't apply since we can't do the depth's Y tiling or the
1548 * stencil's W tiling in the blitter.
1550 if (src_mt
->stencil_mt
) {
1551 intel_miptree_copy_slice_sw(brw
,
1552 src_mt
, src_level
, src_layer
,
1553 dst_mt
, dst_level
, dst_layer
,
1558 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1559 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1561 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1564 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1565 _mesa_get_format_name(src_mt
->format
),
1566 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1567 _mesa_get_format_name(dst_mt
->format
),
1568 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1571 if (!intel_miptree_blit(brw
,
1572 src_mt
, src_level
, src_layer
, 0, 0, false,
1573 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1574 width
, height
, GL_COPY
)) {
1575 perf_debug("miptree validate blit for %s failed\n",
1576 _mesa_get_format_name(format
));
1578 intel_miptree_copy_slice_sw(brw
,
1579 src_mt
, src_level
, src_layer
,
1580 dst_mt
, dst_level
, dst_layer
,
1586 * Copies the image's current data to the given miptree, and associates that
1587 * miptree with the image.
1589 * If \c invalidate is true, then the actual image data does not need to be
1590 * copied, but the image still needs to be associated to the new miptree (this
1591 * is set to true if we're about to clear the image).
1594 intel_miptree_copy_teximage(struct brw_context
*brw
,
1595 struct intel_texture_image
*intelImage
,
1596 struct intel_mipmap_tree
*dst_mt
,
1599 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1600 struct intel_texture_object
*intel_obj
=
1601 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1602 int level
= intelImage
->base
.Base
.Level
;
1603 const unsigned face
= intelImage
->base
.Base
.Face
;
1604 unsigned start_layer
, end_layer
;
1606 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1608 assert(intelImage
->base
.Base
.Height
);
1610 end_layer
= intelImage
->base
.Base
.Height
- 1;
1611 } else if (face
> 0) {
1615 assert(intelImage
->base
.Base
.Depth
);
1617 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1621 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1622 intel_miptree_copy_slice(brw
,
1628 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1629 intel_obj
->needs_validate
= true;
1633 intel_miptree_init_mcs(struct brw_context
*brw
,
1634 struct intel_mipmap_tree
*mt
,
1637 assert(mt
->mcs_buf
!= NULL
);
1639 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1641 * When MCS buffer is enabled and bound to MSRT, it is required that it
1642 * is cleared prior to any rendering.
1644 * Since we don't use the MCS buffer for any purpose other than rendering,
1645 * it makes sense to just clear it immediately upon allocation.
1647 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1649 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1650 if (unlikely(map
== NULL
)) {
1651 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1652 brw_bo_unreference(mt
->mcs_buf
->bo
);
1657 memset(data
, init_value
, mt
->mcs_buf
->size
);
1658 brw_bo_unmap(mt
->mcs_buf
->bo
);
1661 static struct intel_miptree_aux_buffer
*
1662 intel_alloc_aux_buffer(struct brw_context
*brw
,
1664 const struct isl_surf
*aux_surf
,
1665 uint32_t alloc_flags
,
1666 struct intel_mipmap_tree
*mt
)
1668 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1672 buf
->size
= aux_surf
->size
;
1673 buf
->pitch
= aux_surf
->row_pitch
;
1674 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1676 /* ISL has stricter set of alignment rules then the drm allocator.
1677 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1678 * trying to recalculate based on different format block sizes.
1680 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1681 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1687 buf
->surf
= *aux_surf
;
1693 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1694 struct intel_mipmap_tree
*mt
,
1697 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1699 assert(devinfo
->gen
>= 7); /* MCS only used on Gen7+ */
1700 assert(mt
->mcs_buf
== NULL
);
1701 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1703 /* Multisampled miptrees are only supported for single level. */
1704 assert(mt
->first_level
== 0);
1705 enum isl_aux_state
**aux_state
=
1706 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1710 struct isl_surf temp_mcs_surf
;
1712 MAYBE_UNUSED
bool ok
=
1713 isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_mcs_surf
);
1716 /* Buffer needs to be initialised requiring the buffer to be immediately
1717 * mapped to cpu space for writing. Therefore do not use the gpu access
1718 * flag which can cause an unnecessary delay if the backing pages happened
1719 * to be just used by the GPU.
1721 const uint32_t alloc_flags
= 0;
1722 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1723 &temp_mcs_surf
, alloc_flags
, mt
);
1729 mt
->aux_state
= aux_state
;
1731 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1737 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1738 struct intel_mipmap_tree
*mt
)
1740 assert(mt
->mcs_buf
== NULL
);
1741 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1742 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1744 struct isl_surf temp_ccs_surf
;
1746 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
, 0))
1749 assert(temp_ccs_surf
.size
&&
1750 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1752 enum isl_aux_state
**aux_state
=
1753 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1757 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1758 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1760 * "If Software wants to enable Color Compression without Fast clear,
1761 * Software needs to initialize MCS with zeros."
1763 * A CCS value of 0 indicates that the corresponding block is in the
1764 * pass-through state which is what we want.
1766 * For CCS_D, on the other hand, we don't care as we're about to perform a
1767 * fast-clear operation. In that case, being hot in caches more useful.
1769 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1770 BO_ALLOC_ZEROED
: BO_ALLOC_BUSY
;
1771 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1772 &temp_ccs_surf
, alloc_flags
, mt
);
1778 mt
->aux_state
= aux_state
;
1784 * Helper for intel_miptree_alloc_hiz() that sets
1785 * \c mt->level[level].has_hiz. Return true if and only if
1786 * \c has_hiz was set.
1789 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1790 struct intel_mipmap_tree
*mt
,
1793 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1795 assert(mt
->hiz_buf
);
1796 assert(mt
->surf
.size
> 0);
1798 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
1799 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1800 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1802 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1803 * and the height is 4 aligned. This allows our HiZ support
1804 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1805 * we can grow the width & height to allow the HiZ op to
1806 * force the proper size alignments.
1808 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1809 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1814 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1815 mt
->level
[level
].has_hiz
= true;
1820 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1821 struct intel_mipmap_tree
*mt
)
1823 assert(mt
->hiz_buf
== NULL
);
1824 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1826 enum isl_aux_state
**aux_state
=
1827 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1831 struct isl_surf temp_hiz_surf
;
1833 MAYBE_UNUSED
bool ok
=
1834 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
1837 const uint32_t alloc_flags
= BO_ALLOC_BUSY
;
1838 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1839 &temp_hiz_surf
, alloc_flags
, mt
);
1846 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1847 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1849 mt
->aux_state
= aux_state
;
1856 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1858 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1859 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1860 * compress clear color so we wait until an actual fast-clear to allocate it.
1863 intel_miptree_alloc_aux(struct brw_context
*brw
,
1864 struct intel_mipmap_tree
*mt
)
1866 switch (mt
->aux_usage
) {
1867 case ISL_AUX_USAGE_NONE
:
1870 case ISL_AUX_USAGE_HIZ
:
1871 assert(!_mesa_is_format_color_format(mt
->format
));
1872 if (!intel_miptree_alloc_hiz(brw
, mt
))
1876 case ISL_AUX_USAGE_MCS
:
1877 assert(_mesa_is_format_color_format(mt
->format
));
1878 assert(mt
->surf
.samples
> 1);
1879 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
1883 case ISL_AUX_USAGE_CCS_D
:
1884 /* Since CCS_D can only compress clear color so we wait until an actual
1885 * fast-clear to allocate it.
1889 case ISL_AUX_USAGE_CCS_E
:
1890 assert(_mesa_is_format_color_format(mt
->format
));
1891 assert(mt
->surf
.samples
== 1);
1892 if (!intel_miptree_alloc_ccs(brw
, mt
))
1897 unreachable("Invalid aux usage");
1902 * Can the miptree sample using the hiz buffer?
1905 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1906 struct intel_mipmap_tree
*mt
)
1908 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1910 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1911 * so keep things conservative for now and never enable it unless we're SKL+.
1913 if (devinfo
->gen
< 9) {
1921 /* It seems the hardware won't fallback to the depth buffer if some of the
1922 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1923 * of the texture to be HiZ enabled.
1925 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1926 if (!intel_miptree_level_has_hiz(mt
, level
))
1930 /* If compressed multisampling is enabled, then we use it for the auxiliary
1933 * From the BDW PRM (Volume 2d: Command Reference: Structures
1934 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1936 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1937 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1939 * There is no such blurb for 1D textures, but there is sufficient evidence
1940 * that this is broken on SKL+.
1942 return (mt
->surf
.samples
== 1 &&
1943 mt
->target
!= GL_TEXTURE_3D
&&
1944 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1948 * Does the miptree slice have hiz enabled?
1951 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1953 intel_miptree_check_level_layer(mt
, level
, 0);
1954 return mt
->level
[level
].has_hiz
;
1957 static inline uint32_t
1958 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1959 uint32_t start_level
, uint32_t num_levels
)
1961 assert(start_level
>= mt
->first_level
);
1962 assert(start_level
<= mt
->last_level
);
1964 if (num_levels
== INTEL_REMAINING_LAYERS
)
1965 num_levels
= mt
->last_level
- start_level
+ 1;
1966 /* Check for overflow */
1967 assert(start_level
+ num_levels
>= start_level
);
1968 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
1973 static inline uint32_t
1974 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
1975 uint32_t start_layer
, uint32_t num_layers
)
1977 assert(level
<= mt
->last_level
);
1979 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
1980 assert(start_layer
< total_num_layers
);
1981 if (num_layers
== INTEL_REMAINING_LAYERS
)
1982 num_layers
= total_num_layers
- start_layer
;
1983 /* Check for overflow */
1984 assert(start_layer
+ num_layers
>= start_layer
);
1985 assert(start_layer
+ num_layers
<= total_num_layers
);
1991 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1992 unsigned start_level
, unsigned num_levels
,
1993 unsigned start_layer
, unsigned num_layers
)
1995 assert(_mesa_is_format_color_format(mt
->format
));
2000 /* Clamp the level range to fit the miptree */
2001 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2003 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2004 const uint32_t level
= start_level
+ l
;
2005 const uint32_t level_layers
=
2006 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2007 for (unsigned a
= 0; a
< level_layers
; a
++) {
2008 enum isl_aux_state aux_state
=
2009 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2010 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2011 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2020 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2021 const struct intel_mipmap_tree
*mt
,
2022 unsigned level
, unsigned layer
)
2024 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2029 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2030 assert(devinfo
->gen
>= 8 ||
2031 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2033 /* Compression of arrayed msaa surfaces is supported. */
2034 if (mt
->surf
.samples
> 1)
2037 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2038 assert(devinfo
->gen
>= 8 ||
2040 mt
->surf
.logical_level0_px
.depth
== 1 &&
2041 mt
->surf
.logical_level0_px
.array_len
== 1));
2047 static enum blorp_fast_clear_op
2048 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2049 enum isl_aux_usage aux_usage
,
2050 bool fast_clear_supported
)
2052 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
2054 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
2056 assert(ccs_supported
== fast_clear_supported
);
2058 switch (aux_state
) {
2059 case ISL_AUX_STATE_CLEAR
:
2060 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2062 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2064 return BLORP_FAST_CLEAR_OP_NONE
;
2066 case ISL_AUX_STATE_PASS_THROUGH
:
2067 return BLORP_FAST_CLEAR_OP_NONE
;
2069 case ISL_AUX_STATE_RESOLVED
:
2070 case ISL_AUX_STATE_AUX_INVALID
:
2071 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2072 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2076 unreachable("Invalid aux state for CCS_D");
2079 static enum blorp_fast_clear_op
2080 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2081 enum isl_aux_usage aux_usage
,
2082 bool fast_clear_supported
)
2084 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
2085 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2086 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2087 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2089 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
2090 assert(fast_clear_supported
);
2092 switch (aux_state
) {
2093 case ISL_AUX_STATE_CLEAR
:
2094 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2095 if (fast_clear_supported
)
2096 return BLORP_FAST_CLEAR_OP_NONE
;
2097 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
2098 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2100 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2102 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2103 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2104 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2105 else if (!fast_clear_supported
)
2106 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2108 return BLORP_FAST_CLEAR_OP_NONE
;
2110 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2111 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2112 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2114 return BLORP_FAST_CLEAR_OP_NONE
;
2116 case ISL_AUX_STATE_PASS_THROUGH
:
2117 return BLORP_FAST_CLEAR_OP_NONE
;
2119 case ISL_AUX_STATE_RESOLVED
:
2120 case ISL_AUX_STATE_AUX_INVALID
:
2124 unreachable("Invalid aux state for CCS_E");
2128 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2129 struct intel_mipmap_tree
*mt
,
2130 uint32_t level
, uint32_t layer
,
2131 enum isl_aux_usage aux_usage
,
2132 bool fast_clear_supported
)
2134 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2136 enum blorp_fast_clear_op resolve_op
;
2137 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2138 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2139 fast_clear_supported
);
2141 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2142 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2143 fast_clear_supported
);
2146 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2147 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2148 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2150 switch (resolve_op
) {
2151 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2152 /* The CCS full resolve operation destroys the CCS and sets it to the
2153 * pass-through state. (You can also think of this as being both a
2154 * resolve and an ambiguate in one operation.)
2156 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2157 ISL_AUX_STATE_PASS_THROUGH
);
2160 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2161 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2162 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2166 unreachable("Invalid resolve op");
2172 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2173 struct intel_mipmap_tree
*mt
,
2174 uint32_t level
, uint32_t layer
,
2175 enum isl_aux_usage aux_usage
)
2177 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2178 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2179 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2181 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2183 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2184 switch (aux_state
) {
2185 case ISL_AUX_STATE_CLEAR
:
2186 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2187 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2188 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2190 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2191 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2192 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2193 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2194 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2195 ISL_AUX_STATE_PARTIAL_CLEAR
);
2199 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2200 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2201 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2202 break; /* Nothing to do */
2204 case ISL_AUX_STATE_PASS_THROUGH
:
2205 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2206 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2207 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2213 case ISL_AUX_STATE_RESOLVED
:
2214 case ISL_AUX_STATE_AUX_INVALID
:
2215 unreachable("Invalid aux state for CCS_E");
2218 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2219 /* CCS_D is a bit simpler */
2220 switch (aux_state
) {
2221 case ISL_AUX_STATE_CLEAR
:
2222 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2223 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2224 ISL_AUX_STATE_PARTIAL_CLEAR
);
2227 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2228 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2229 break; /* Nothing to do */
2231 case ISL_AUX_STATE_PASS_THROUGH
:
2235 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2236 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2237 case ISL_AUX_STATE_RESOLVED
:
2238 case ISL_AUX_STATE_AUX_INVALID
:
2239 unreachable("Invalid aux state for CCS_D");
2245 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2246 struct intel_mipmap_tree
*mt
,
2248 enum isl_aux_usage aux_usage
,
2249 bool fast_clear_supported
)
2251 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2253 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2254 case ISL_AUX_STATE_CLEAR
:
2255 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2256 if (!fast_clear_supported
) {
2257 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2258 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2259 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2263 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2264 break; /* Nothing to do */
2266 case ISL_AUX_STATE_RESOLVED
:
2267 case ISL_AUX_STATE_PASS_THROUGH
:
2268 case ISL_AUX_STATE_AUX_INVALID
:
2269 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2270 unreachable("Invalid aux state for MCS");
2275 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2276 struct intel_mipmap_tree
*mt
,
2278 enum isl_aux_usage aux_usage
)
2280 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2282 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2283 case ISL_AUX_STATE_CLEAR
:
2284 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2285 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2288 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2289 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2290 break; /* Nothing to do */
2292 case ISL_AUX_STATE_RESOLVED
:
2293 case ISL_AUX_STATE_PASS_THROUGH
:
2294 case ISL_AUX_STATE_AUX_INVALID
:
2295 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2296 unreachable("Invalid aux state for MCS");
2301 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2302 struct intel_mipmap_tree
*mt
,
2303 uint32_t level
, uint32_t layer
,
2304 enum isl_aux_usage aux_usage
,
2305 bool fast_clear_supported
)
2307 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2309 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2310 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2311 case ISL_AUX_STATE_CLEAR
:
2312 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2313 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2314 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2317 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2318 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2319 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2322 case ISL_AUX_STATE_PASS_THROUGH
:
2323 case ISL_AUX_STATE_RESOLVED
:
2326 case ISL_AUX_STATE_AUX_INVALID
:
2327 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2328 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2331 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2332 unreachable("Invalid HiZ state");
2335 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2336 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2339 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2340 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2341 ISL_AUX_STATE_RESOLVED
);
2344 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2345 /* The HiZ resolve operation is actually an ambiguate */
2346 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2347 ISL_AUX_STATE_PASS_THROUGH
);
2351 unreachable("Invalid HiZ op");
2357 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2358 struct intel_mipmap_tree
*mt
,
2359 uint32_t level
, uint32_t layer
,
2360 enum isl_aux_usage aux_usage
)
2362 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2364 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2365 case ISL_AUX_STATE_CLEAR
:
2366 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2367 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2368 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2371 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2372 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2373 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2374 break; /* Nothing to do */
2376 case ISL_AUX_STATE_RESOLVED
:
2377 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2378 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2379 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2381 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2382 ISL_AUX_STATE_AUX_INVALID
);
2386 case ISL_AUX_STATE_PASS_THROUGH
:
2387 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2388 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2389 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2393 case ISL_AUX_STATE_AUX_INVALID
:
2394 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2397 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2398 unreachable("Invalid HiZ state");
2403 intel_miptree_prepare_access(struct brw_context
*brw
,
2404 struct intel_mipmap_tree
*mt
,
2405 uint32_t start_level
, uint32_t num_levels
,
2406 uint32_t start_layer
, uint32_t num_layers
,
2407 enum isl_aux_usage aux_usage
,
2408 bool fast_clear_supported
)
2410 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2412 switch (mt
->aux_usage
) {
2413 case ISL_AUX_USAGE_NONE
:
2417 case ISL_AUX_USAGE_MCS
:
2418 assert(mt
->mcs_buf
);
2419 assert(start_level
== 0 && num_levels
== 1);
2420 const uint32_t level_layers
=
2421 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2422 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2423 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2424 aux_usage
, fast_clear_supported
);
2428 case ISL_AUX_USAGE_CCS_D
:
2429 case ISL_AUX_USAGE_CCS_E
:
2433 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2434 const uint32_t level
= start_level
+ l
;
2435 const uint32_t level_layers
=
2436 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2437 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2438 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2440 aux_usage
, fast_clear_supported
);
2445 case ISL_AUX_USAGE_HIZ
:
2446 assert(mt
->hiz_buf
);
2447 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2448 const uint32_t level
= start_level
+ l
;
2449 if (!intel_miptree_level_has_hiz(mt
, level
))
2452 const uint32_t level_layers
=
2453 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2454 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2455 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2456 aux_usage
, fast_clear_supported
);
2462 unreachable("Invalid aux usage");
2467 intel_miptree_finish_write(struct brw_context
*brw
,
2468 struct intel_mipmap_tree
*mt
, uint32_t level
,
2469 uint32_t start_layer
, uint32_t num_layers
,
2470 enum isl_aux_usage aux_usage
)
2472 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2474 switch (mt
->aux_usage
) {
2475 case ISL_AUX_USAGE_NONE
:
2479 case ISL_AUX_USAGE_MCS
:
2480 assert(mt
->mcs_buf
);
2481 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2482 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2487 case ISL_AUX_USAGE_CCS_D
:
2488 case ISL_AUX_USAGE_CCS_E
:
2492 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2493 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2498 case ISL_AUX_USAGE_HIZ
:
2499 if (!intel_miptree_level_has_hiz(mt
, level
))
2502 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2503 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2509 unreachable("Invavlid aux usage");
2514 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2515 uint32_t level
, uint32_t layer
)
2517 intel_miptree_check_level_layer(mt
, level
, layer
);
2519 if (_mesa_is_format_color_format(mt
->format
)) {
2520 assert(mt
->mcs_buf
!= NULL
);
2521 assert(mt
->surf
.samples
== 1 ||
2522 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2523 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2524 unreachable("Cannot get aux state for stencil");
2526 assert(intel_miptree_level_has_hiz(mt
, level
));
2529 return mt
->aux_state
[level
][layer
];
2533 intel_miptree_set_aux_state(struct brw_context
*brw
,
2534 struct intel_mipmap_tree
*mt
, uint32_t level
,
2535 uint32_t start_layer
, uint32_t num_layers
,
2536 enum isl_aux_state aux_state
)
2538 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2540 if (_mesa_is_format_color_format(mt
->format
)) {
2541 assert(mt
->mcs_buf
!= NULL
);
2542 assert(mt
->surf
.samples
== 1 ||
2543 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2544 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2545 unreachable("Cannot get aux state for stencil");
2547 assert(intel_miptree_level_has_hiz(mt
, level
));
2550 for (unsigned a
= 0; a
< num_layers
; a
++)
2551 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2554 /* On Gen9 color buffers may be compressed by the hardware (lossless
2555 * compression). There are, however, format restrictions and care needs to be
2556 * taken that the sampler engine is capable for re-interpreting a buffer with
2557 * format different the buffer was originally written with.
2559 * For example, SRGB formats are not compressible and the sampler engine isn't
2560 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2561 * color buffer needs to be resolved so that the sampling surface can be
2562 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2566 can_texture_with_ccs(struct brw_context
*brw
,
2567 struct intel_mipmap_tree
*mt
,
2568 enum isl_format view_format
)
2570 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2573 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2574 mt
->surf
.format
, view_format
)) {
2575 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2576 isl_format_get_layout(view_format
)->name
,
2577 _mesa_get_format_name(mt
->format
));
2585 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2586 struct intel_mipmap_tree
*mt
,
2587 enum isl_format view_format
)
2589 switch (mt
->aux_usage
) {
2590 case ISL_AUX_USAGE_HIZ
:
2591 if (intel_miptree_sample_with_hiz(brw
, mt
))
2592 return ISL_AUX_USAGE_HIZ
;
2595 case ISL_AUX_USAGE_MCS
:
2596 return ISL_AUX_USAGE_MCS
;
2598 case ISL_AUX_USAGE_CCS_D
:
2599 case ISL_AUX_USAGE_CCS_E
:
2601 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2602 return ISL_AUX_USAGE_NONE
;
2605 /* If we don't have any unresolved color, report an aux usage of
2606 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
2607 * aux surface and we can save some bandwidth.
2609 if (!intel_miptree_has_color_unresolved(mt
, 0, INTEL_REMAINING_LEVELS
,
2610 0, INTEL_REMAINING_LAYERS
))
2611 return ISL_AUX_USAGE_NONE
;
2613 if (can_texture_with_ccs(brw
, mt
, view_format
))
2614 return ISL_AUX_USAGE_CCS_E
;
2621 return ISL_AUX_USAGE_NONE
;
2625 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2627 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2628 * values so sRGB curve application was a no-op for all fast-clearable
2631 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2632 * values, the hardware interprets the floats, not as what would be
2633 * returned from the sampler (or written by the shader), but as being
2634 * between format conversion and sRGB curve application. This means that
2635 * we can switch between sRGB and UNORM without having to whack the clear
2638 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2642 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2643 struct intel_mipmap_tree
*mt
,
2644 enum isl_format view_format
,
2645 uint32_t start_level
, uint32_t num_levels
,
2646 uint32_t start_layer
, uint32_t num_layers
,
2647 bool *aux_supported_out
)
2649 enum isl_aux_usage aux_usage
=
2650 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2651 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2653 /* Clear color is specified as ints or floats and the conversion is done by
2654 * the sampler. If we have a texture view, we would have to perform the
2655 * clear color conversion manually. Just disable clear color.
2657 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2658 clear_supported
= false;
2660 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2661 start_layer
, num_layers
,
2662 aux_usage
, clear_supported
);
2663 if (aux_supported_out
)
2664 *aux_supported_out
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2668 intel_miptree_prepare_texture(struct brw_context
*brw
,
2669 struct intel_mipmap_tree
*mt
,
2670 enum isl_format view_format
,
2671 bool *aux_supported_out
)
2673 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2674 0, INTEL_REMAINING_LEVELS
,
2675 0, INTEL_REMAINING_LAYERS
,
2680 intel_miptree_prepare_image(struct brw_context
*brw
,
2681 struct intel_mipmap_tree
*mt
)
2683 /* The data port doesn't understand any compression */
2684 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2685 0, INTEL_REMAINING_LAYERS
,
2686 ISL_AUX_USAGE_NONE
, false);
2690 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2691 struct intel_mipmap_tree
*mt
, uint32_t level
,
2692 uint32_t start_layer
, uint32_t num_layers
)
2694 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->surf
.format
, level
, 1,
2695 start_layer
, num_layers
, NULL
);
2699 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2700 struct intel_mipmap_tree
*mt
,
2701 bool srgb_enabled
, bool blend_enabled
)
2703 switch (mt
->aux_usage
) {
2704 case ISL_AUX_USAGE_MCS
:
2705 assert(mt
->mcs_buf
);
2706 return ISL_AUX_USAGE_MCS
;
2708 case ISL_AUX_USAGE_CCS_D
:
2709 return mt
->mcs_buf
? ISL_AUX_USAGE_CCS_D
: ISL_AUX_USAGE_NONE
;
2711 case ISL_AUX_USAGE_CCS_E
: {
2712 mesa_format mesa_format
=
2713 srgb_enabled
? mt
->format
:_mesa_get_srgb_format_linear(mt
->format
);
2714 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
2716 /* If the format supports CCS_E, then we can just use it */
2717 if (isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
))
2718 return ISL_AUX_USAGE_CCS_E
;
2720 /* Otherwise, we have to fall back to CCS_D */
2722 /* gen9 hardware technically supports non-0/1 clear colors with sRGB
2723 * formats. However, there are issues with blending where it doesn't
2724 * properly apply the sRGB curve to the clear color when blending.
2726 if (blend_enabled
&& isl_format_is_srgb(isl_format
) &&
2727 !isl_color_value_is_zero_one(mt
->fast_clear_color
, isl_format
))
2728 return ISL_AUX_USAGE_NONE
;
2730 return ISL_AUX_USAGE_CCS_D
;
2734 return ISL_AUX_USAGE_NONE
;
2739 intel_miptree_prepare_render(struct brw_context
*brw
,
2740 struct intel_mipmap_tree
*mt
, uint32_t level
,
2741 uint32_t start_layer
, uint32_t layer_count
,
2742 bool srgb_enabled
, bool blend_enabled
)
2744 enum isl_aux_usage aux_usage
=
2745 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
, blend_enabled
);
2746 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2747 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2751 intel_miptree_finish_render(struct brw_context
*brw
,
2752 struct intel_mipmap_tree
*mt
, uint32_t level
,
2753 uint32_t start_layer
, uint32_t layer_count
,
2754 bool srgb_enabled
, bool blend_enabled
)
2756 assert(_mesa_is_format_color_format(mt
->format
));
2758 enum isl_aux_usage aux_usage
=
2759 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
, blend_enabled
);
2760 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2765 intel_miptree_prepare_depth(struct brw_context
*brw
,
2766 struct intel_mipmap_tree
*mt
, uint32_t level
,
2767 uint32_t start_layer
, uint32_t layer_count
)
2769 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2770 mt
->aux_usage
, mt
->hiz_buf
!= NULL
);
2774 intel_miptree_finish_depth(struct brw_context
*brw
,
2775 struct intel_mipmap_tree
*mt
, uint32_t level
,
2776 uint32_t start_layer
, uint32_t layer_count
,
2779 if (depth_written
) {
2780 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2781 mt
->hiz_buf
!= NULL
);
2786 intel_miptree_prepare_external(struct brw_context
*brw
,
2787 struct intel_mipmap_tree
*mt
)
2789 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
2790 bool supports_fast_clear
= false;
2792 const struct isl_drm_modifier_info
*mod_info
=
2793 isl_drm_modifier_get_info(mt
->drm_modifier
);
2795 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
2796 /* CCS_E is the only supported aux for external images and it's only
2797 * supported on very simple images.
2799 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
2800 assert(_mesa_is_format_color_format(mt
->format
));
2801 assert(mt
->first_level
== 0 && mt
->last_level
== 0);
2802 assert(mt
->surf
.logical_level0_px
.depth
== 1);
2803 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
2804 assert(mt
->surf
.samples
== 1);
2805 assert(mt
->mcs_buf
!= NULL
);
2807 aux_usage
= mod_info
->aux_usage
;
2808 supports_fast_clear
= mod_info
->supports_clear_color
;
2811 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2812 0, INTEL_REMAINING_LAYERS
,
2813 aux_usage
, supports_fast_clear
);
2817 * Make it possible to share the BO backing the given miptree with another
2818 * process or another miptree.
2820 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2821 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2822 * ensure that no MCS buffer gets allocated in the future.
2824 * HiZ is similarly unsafe with shared buffers.
2827 intel_miptree_make_shareable(struct brw_context
*brw
,
2828 struct intel_mipmap_tree
*mt
)
2830 /* MCS buffers are also used for multisample buffers, but we can't resolve
2831 * away a multisample MCS buffer because it's an integral part of how the
2832 * pixel data is stored. Fortunately this code path should never be
2833 * reached for multisample buffers.
2835 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2836 mt
->surf
.samples
== 1);
2838 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2839 0, INTEL_REMAINING_LAYERS
,
2840 ISL_AUX_USAGE_NONE
, false);
2843 brw_bo_unreference(mt
->mcs_buf
->bo
);
2847 /* Any pending MCS/CCS operations are no longer needed. Trying to
2848 * execute any will likely crash due to the missing aux buffer. So let's
2849 * delete all pending ops.
2851 free(mt
->aux_state
);
2852 mt
->aux_state
= NULL
;
2856 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2859 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2860 mt
->level
[l
].has_hiz
= false;
2863 /* Any pending HiZ operations are no longer needed. Trying to execute
2864 * any will likely crash due to the missing aux buffer. So let's delete
2867 free(mt
->aux_state
);
2868 mt
->aux_state
= NULL
;
2871 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2872 mt
->supports_fast_clear
= false;
2877 * \brief Get pointer offset into stencil buffer.
2879 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2880 * must decode the tile's layout in software.
2883 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2885 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2887 * Even though the returned offset is always positive, the return type is
2889 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2890 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2893 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2895 uint32_t tile_size
= 4096;
2896 uint32_t tile_width
= 64;
2897 uint32_t tile_height
= 64;
2898 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2900 uint32_t tile_x
= x
/ tile_width
;
2901 uint32_t tile_y
= y
/ tile_height
;
2903 /* The byte's address relative to the tile's base addres. */
2904 uint32_t byte_x
= x
% tile_width
;
2905 uint32_t byte_y
= y
% tile_height
;
2907 uintptr_t u
= tile_y
* row_size
2908 + tile_x
* tile_size
2909 + 512 * (byte_x
/ 8)
2911 + 32 * ((byte_y
/ 4) % 2)
2912 + 16 * ((byte_x
/ 4) % 2)
2913 + 8 * ((byte_y
/ 2) % 2)
2914 + 4 * ((byte_x
/ 2) % 2)
2919 /* adjust for bit6 swizzling */
2920 if (((byte_x
/ 8) % 2) == 1) {
2921 if (((byte_y
/ 8) % 2) == 0) {
2933 intel_miptree_updownsample(struct brw_context
*brw
,
2934 struct intel_mipmap_tree
*src
,
2935 struct intel_mipmap_tree
*dst
)
2937 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2938 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2939 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2940 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2942 brw_blorp_blit_miptrees(brw
,
2943 src
, 0 /* level */, 0 /* layer */,
2944 src
->format
, SWIZZLE_XYZW
,
2945 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2948 GL_NEAREST
, false, false /*mirror x, y*/,
2951 if (src
->stencil_mt
) {
2952 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2953 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2954 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2955 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2957 brw_blorp_blit_miptrees(brw
,
2958 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2959 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2960 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2961 dst
->stencil_mt
->format
,
2964 GL_NEAREST
, false, false /*mirror x, y*/,
2965 false, false /* decode/encode srgb */);
2970 intel_update_r8stencil(struct brw_context
*brw
,
2971 struct intel_mipmap_tree
*mt
)
2973 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2975 assert(devinfo
->gen
>= 7);
2976 struct intel_mipmap_tree
*src
=
2977 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2978 if (!src
|| devinfo
->gen
>= 8 || !src
->r8stencil_needs_update
)
2981 assert(src
->surf
.size
> 0);
2983 if (!mt
->r8stencil_mt
) {
2984 assert(devinfo
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2985 mt
->r8stencil_mt
= make_surface(
2988 MESA_FORMAT_R_UINT8
,
2989 src
->first_level
, src
->last_level
,
2990 src
->surf
.logical_level0_px
.width
,
2991 src
->surf
.logical_level0_px
.height
,
2992 src
->surf
.dim
== ISL_SURF_DIM_3D
?
2993 src
->surf
.logical_level0_px
.depth
:
2994 src
->surf
.logical_level0_px
.array_len
,
2997 ISL_SURF_USAGE_TEXTURE_BIT
,
2998 BO_ALLOC_BUSY
, 0, NULL
);
2999 assert(mt
->r8stencil_mt
);
3002 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
3004 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
3005 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
3006 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
3007 src
->surf
.phys_level0_sa
.array_len
;
3009 for (unsigned layer
= 0; layer
< depth
; layer
++) {
3010 brw_blorp_copy_miptrees(brw
,
3014 minify(src
->surf
.logical_level0_px
.width
,
3016 minify(src
->surf
.logical_level0_px
.height
,
3021 brw_render_cache_set_check_flush(brw
, dst
->bo
);
3022 src
->r8stencil_needs_update
= false;
3026 intel_miptree_map_raw(struct brw_context
*brw
,
3027 struct intel_mipmap_tree
*mt
,
3030 struct brw_bo
*bo
= mt
->bo
;
3032 if (brw_batch_references(&brw
->batch
, bo
))
3033 intel_batchbuffer_flush(brw
);
3035 return brw_bo_map(brw
, bo
, mode
);
3039 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3041 brw_bo_unmap(mt
->bo
);
3045 intel_miptree_map_gtt(struct brw_context
*brw
,
3046 struct intel_mipmap_tree
*mt
,
3047 struct intel_miptree_map
*map
,
3048 unsigned int level
, unsigned int slice
)
3050 unsigned int bw
, bh
;
3052 unsigned int image_x
, image_y
;
3053 intptr_t x
= map
->x
;
3054 intptr_t y
= map
->y
;
3056 /* For compressed formats, the stride is the number of bytes per
3057 * row of blocks. intel_miptree_get_image_offset() already does
3060 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3061 assert(y
% bh
== 0);
3062 assert(x
% bw
== 0);
3066 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3073 /* Note that in the case of cube maps, the caller must have passed the
3074 * slice number referencing the face.
3076 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3080 map
->stride
= mt
->surf
.row_pitch
;
3081 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3084 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3085 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3086 map
->x
, map
->y
, map
->w
, map
->h
,
3087 mt
, _mesa_get_format_name(mt
->format
),
3088 x
, y
, map
->ptr
, map
->stride
);
3092 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3094 intel_miptree_unmap_raw(mt
);
3098 intel_miptree_map_blit(struct brw_context
*brw
,
3099 struct intel_mipmap_tree
*mt
,
3100 struct intel_miptree_map
*map
,
3101 unsigned int level
, unsigned int slice
)
3103 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3104 /* first_level */ 0,
3108 MIPTREE_CREATE_LINEAR
);
3110 if (!map
->linear_mt
) {
3111 fprintf(stderr
, "Failed to allocate blit temporary\n");
3114 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3116 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3117 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3118 * invalidate is set, since we'll be writing the whole rectangle from our
3119 * temporary buffer back out.
3121 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3122 if (!intel_miptree_copy(brw
,
3123 mt
, level
, slice
, map
->x
, map
->y
,
3124 map
->linear_mt
, 0, 0, 0, 0,
3126 fprintf(stderr
, "Failed to blit\n");
3131 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3133 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3134 map
->x
, map
->y
, map
->w
, map
->h
,
3135 mt
, _mesa_get_format_name(mt
->format
),
3136 level
, slice
, map
->ptr
, map
->stride
);
3141 intel_miptree_release(&map
->linear_mt
);
3147 intel_miptree_unmap_blit(struct brw_context
*brw
,
3148 struct intel_mipmap_tree
*mt
,
3149 struct intel_miptree_map
*map
,
3153 struct gl_context
*ctx
= &brw
->ctx
;
3155 intel_miptree_unmap_raw(map
->linear_mt
);
3157 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3158 bool ok
= intel_miptree_copy(brw
,
3159 map
->linear_mt
, 0, 0, 0, 0,
3160 mt
, level
, slice
, map
->x
, map
->y
,
3162 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3165 intel_miptree_release(&map
->linear_mt
);
3169 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3171 #if defined(USE_SSE41)
3173 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3174 struct intel_mipmap_tree
*mt
,
3175 struct intel_miptree_map
*map
,
3176 unsigned int level
, unsigned int slice
)
3178 assert(map
->mode
& GL_MAP_READ_BIT
);
3179 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3181 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3182 map
->x
, map
->y
, map
->w
, map
->h
,
3183 mt
, _mesa_get_format_name(mt
->format
),
3184 level
, slice
, map
->ptr
, map
->stride
);
3186 /* Map the original image */
3189 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3193 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3199 src
+= image_y
* mt
->surf
.row_pitch
;
3200 src
+= image_x
* mt
->cpp
;
3202 /* Due to the pixel offsets for the particular image being mapped, our
3203 * src pointer may not be 16-byte aligned. However, if the pitch is
3204 * divisible by 16, then the amount by which it's misaligned will remain
3205 * consistent from row to row.
3207 assert((mt
->surf
.row_pitch
% 16) == 0);
3208 const int misalignment
= ((uintptr_t) src
) & 15;
3210 /* Create an untiled temporary buffer for the mapping. */
3211 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3213 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3215 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3216 /* Offset the destination so it has the same misalignment as src. */
3217 map
->ptr
= map
->buffer
+ misalignment
;
3219 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3221 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3222 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3223 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3225 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3228 intel_miptree_unmap_raw(mt
);
3232 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3233 struct intel_mipmap_tree
*mt
,
3234 struct intel_miptree_map
*map
,
3238 _mesa_align_free(map
->buffer
);
3245 intel_miptree_map_s8(struct brw_context
*brw
,
3246 struct intel_mipmap_tree
*mt
,
3247 struct intel_miptree_map
*map
,
3248 unsigned int level
, unsigned int slice
)
3250 map
->stride
= map
->w
;
3251 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3255 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3256 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3257 * invalidate is set, since we'll be writing the whole rectangle from our
3258 * temporary buffer back out.
3260 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3261 uint8_t *untiled_s8_map
= map
->ptr
;
3262 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3263 unsigned int image_x
, image_y
;
3265 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3267 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3268 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3269 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3270 x
+ image_x
+ map
->x
,
3271 y
+ image_y
+ map
->y
,
3272 brw
->has_swizzling
);
3273 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3277 intel_miptree_unmap_raw(mt
);
3279 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3280 map
->x
, map
->y
, map
->w
, map
->h
,
3281 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3283 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3284 map
->x
, map
->y
, map
->w
, map
->h
,
3285 mt
, map
->ptr
, map
->stride
);
3290 intel_miptree_unmap_s8(struct brw_context
*brw
,
3291 struct intel_mipmap_tree
*mt
,
3292 struct intel_miptree_map
*map
,
3296 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3297 unsigned int image_x
, image_y
;
3298 uint8_t *untiled_s8_map
= map
->ptr
;
3299 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3301 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3303 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3304 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3305 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3306 image_x
+ x
+ map
->x
,
3307 image_y
+ y
+ map
->y
,
3308 brw
->has_swizzling
);
3309 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3313 intel_miptree_unmap_raw(mt
);
3320 intel_miptree_map_etc(struct brw_context
*brw
,
3321 struct intel_mipmap_tree
*mt
,
3322 struct intel_miptree_map
*map
,
3326 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3327 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3328 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3331 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3332 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3334 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3335 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3336 map
->w
, map
->h
, 1));
3337 map
->ptr
= map
->buffer
;
3341 intel_miptree_unmap_etc(struct brw_context
*brw
,
3342 struct intel_mipmap_tree
*mt
,
3343 struct intel_miptree_map
*map
,
3349 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3354 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3355 + image_y
* mt
->surf
.row_pitch
3356 + image_x
* mt
->cpp
;
3358 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3359 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3360 map
->ptr
, map
->stride
,
3363 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3364 map
->ptr
, map
->stride
,
3365 map
->w
, map
->h
, mt
->etc_format
);
3367 intel_miptree_unmap_raw(mt
);
3372 * Mapping function for packed depth/stencil miptrees backed by real separate
3373 * miptrees for depth and stencil.
3375 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3376 * separate from the depth buffer. Yet at the GL API level, we have to expose
3377 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3378 * be able to map that memory for texture storage and glReadPixels-type
3379 * operations. We give Mesa core that access by mallocing a temporary and
3380 * copying the data between the actual backing store and the temporary.
3383 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3384 struct intel_mipmap_tree
*mt
,
3385 struct intel_miptree_map
*map
,
3386 unsigned int level
, unsigned int slice
)
3388 struct intel_mipmap_tree
*z_mt
= mt
;
3389 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3390 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3391 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3393 map
->stride
= map
->w
* packed_bpp
;
3394 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3398 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3399 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3400 * invalidate is set, since we'll be writing the whole rectangle from our
3401 * temporary buffer back out.
3403 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3404 uint32_t *packed_map
= map
->ptr
;
3405 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3406 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3407 unsigned int s_image_x
, s_image_y
;
3408 unsigned int z_image_x
, z_image_y
;
3410 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3411 &s_image_x
, &s_image_y
);
3412 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3413 &z_image_x
, &z_image_y
);
3415 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3416 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3417 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3418 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3421 brw
->has_swizzling
);
3422 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3423 (z_mt
->surf
.row_pitch
/ 4) +
3424 (map_x
+ z_image_x
));
3425 uint8_t s
= s_map
[s_offset
];
3426 uint32_t z
= z_map
[z_offset
];
3428 if (map_z32f_x24s8
) {
3429 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3430 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3432 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3437 intel_miptree_unmap_raw(s_mt
);
3438 intel_miptree_unmap_raw(z_mt
);
3440 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3442 map
->x
, map
->y
, map
->w
, map
->h
,
3443 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3444 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3445 map
->ptr
, map
->stride
);
3447 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3448 map
->x
, map
->y
, map
->w
, map
->h
,
3449 mt
, map
->ptr
, map
->stride
);
3454 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3455 struct intel_mipmap_tree
*mt
,
3456 struct intel_miptree_map
*map
,
3460 struct intel_mipmap_tree
*z_mt
= mt
;
3461 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3462 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3464 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3465 uint32_t *packed_map
= map
->ptr
;
3466 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3467 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3468 unsigned int s_image_x
, s_image_y
;
3469 unsigned int z_image_x
, z_image_y
;
3471 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3472 &s_image_x
, &s_image_y
);
3473 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3474 &z_image_x
, &z_image_y
);
3476 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3477 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3478 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3479 x
+ s_image_x
+ map
->x
,
3480 y
+ s_image_y
+ map
->y
,
3481 brw
->has_swizzling
);
3482 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3483 (z_mt
->surf
.row_pitch
/ 4) +
3484 (x
+ z_image_x
+ map
->x
));
3486 if (map_z32f_x24s8
) {
3487 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3488 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3490 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3491 s_map
[s_offset
] = packed
>> 24;
3492 z_map
[z_offset
] = packed
;
3497 intel_miptree_unmap_raw(s_mt
);
3498 intel_miptree_unmap_raw(z_mt
);
3500 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3502 map
->x
, map
->y
, map
->w
, map
->h
,
3503 z_mt
, _mesa_get_format_name(z_mt
->format
),
3504 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3505 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3506 map
->ptr
, map
->stride
);
3513 * Create and attach a map to the miptree at (level, slice). Return the
3516 static struct intel_miptree_map
*
3517 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3526 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3531 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3532 mt
->level
[level
].slice
[slice
].map
= map
;
3544 * Release the map at (level, slice).
3547 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3551 struct intel_miptree_map
**map
;
3553 map
= &mt
->level
[level
].slice
[slice
].map
;
3559 can_blit_slice(struct intel_mipmap_tree
*mt
,
3560 unsigned int level
, unsigned int slice
)
3562 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3563 if (mt
->surf
.row_pitch
>= 32768)
3570 use_intel_mipree_map_blit(struct brw_context
*brw
,
3571 struct intel_mipmap_tree
*mt
,
3576 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3578 if (devinfo
->has_llc
&&
3579 /* It's probably not worth swapping to the blit ring because of
3580 * all the overhead involved.
3582 !(mode
& GL_MAP_WRITE_BIT
) &&
3584 (mt
->surf
.tiling
== ISL_TILING_X
||
3585 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3586 (devinfo
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3587 /* Fast copy blit on skl+ supports all tiling formats. */
3588 devinfo
->gen
>= 9) &&
3589 can_blit_slice(mt
, level
, slice
))
3592 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3593 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3594 assert(can_blit_slice(mt
, level
, slice
));
3602 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3603 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3604 * arithmetic overflow.
3606 * If you call this function and use \a out_stride, then you're doing pointer
3607 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3608 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3609 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3610 * which usually have type uint32_t or GLuint.
3613 intel_miptree_map(struct brw_context
*brw
,
3614 struct intel_mipmap_tree
*mt
,
3623 ptrdiff_t *out_stride
)
3625 struct intel_miptree_map
*map
;
3627 assert(mt
->surf
.samples
== 1);
3629 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3636 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3637 map
->mode
& GL_MAP_WRITE_BIT
);
3639 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3640 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3641 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3642 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3643 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3644 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3645 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3646 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3647 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3648 #if defined(USE_SSE41)
3649 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3650 !mt
->compressed
&& cpu_has_sse4_1
&&
3651 (mt
->surf
.row_pitch
% 16 == 0)) {
3652 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3655 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3658 *out_ptr
= map
->ptr
;
3659 *out_stride
= map
->stride
;
3661 if (map
->ptr
== NULL
)
3662 intel_miptree_release_map(mt
, level
, slice
);
3666 intel_miptree_unmap(struct brw_context
*brw
,
3667 struct intel_mipmap_tree
*mt
,
3671 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3673 assert(mt
->surf
.samples
== 1);
3678 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3679 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3681 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3682 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3683 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3684 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3685 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3686 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3687 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3688 } else if (map
->linear_mt
) {
3689 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3690 #if defined(USE_SSE41)
3691 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3692 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3695 intel_miptree_unmap_gtt(mt
);
3698 intel_miptree_release_map(mt
, level
, slice
);
3702 get_isl_surf_dim(GLenum target
)
3706 case GL_TEXTURE_1D_ARRAY
:
3707 return ISL_SURF_DIM_1D
;
3710 case GL_TEXTURE_2D_ARRAY
:
3711 case GL_TEXTURE_RECTANGLE
:
3712 case GL_TEXTURE_CUBE_MAP
:
3713 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3714 case GL_TEXTURE_2D_MULTISAMPLE
:
3715 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3716 case GL_TEXTURE_EXTERNAL_OES
:
3717 return ISL_SURF_DIM_2D
;
3720 return ISL_SURF_DIM_3D
;
3723 unreachable("Invalid texture target");
3727 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3728 enum isl_tiling tiling
, GLenum target
)
3732 case GL_TEXTURE_1D_ARRAY
:
3733 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3734 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3737 case GL_TEXTURE_2D_ARRAY
:
3738 case GL_TEXTURE_RECTANGLE
:
3739 case GL_TEXTURE_2D_MULTISAMPLE
:
3740 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3741 case GL_TEXTURE_EXTERNAL_OES
:
3742 return ISL_DIM_LAYOUT_GEN4_2D
;
3744 case GL_TEXTURE_CUBE_MAP
:
3745 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3746 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3747 ISL_DIM_LAYOUT_GEN4_2D
);
3750 return (devinfo
->gen
>= 9 ?
3751 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3754 unreachable("Invalid texture target");
3758 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3759 const struct intel_mipmap_tree
*mt
)
3762 return ISL_AUX_USAGE_HIZ
;
3765 return ISL_AUX_USAGE_NONE
;
3767 return mt
->aux_usage
;