2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
28 #include <drm_fourcc.h>
30 #include "intel_batchbuffer.h"
31 #include "intel_image.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_tex.h"
34 #include "intel_blit.h"
35 #include "intel_fbo.h"
37 #include "brw_blorp.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
49 #include "util/format_srgb.h"
51 #include "x86/common_x86_asm.h"
53 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
55 static void *intel_miptree_map_raw(struct brw_context
*brw
,
56 struct intel_mipmap_tree
*mt
,
59 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
62 intel_miptree_supports_mcs(struct brw_context
*brw
,
63 const struct intel_mipmap_tree
*mt
)
65 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
67 /* MCS compression only applies to multisampled miptrees */
68 if (mt
->surf
.samples
<= 1)
71 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
75 /* See isl_surf_get_mcs_surf for details. */
76 if (mt
->surf
.samples
== 16 && mt
->surf
.logical_level0_px
.width
> 8192)
79 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
80 switch (_mesa_get_format_base_format(mt
->format
)) {
81 case GL_DEPTH_COMPONENT
:
82 case GL_STENCIL_INDEX
:
83 case GL_DEPTH_STENCIL
:
86 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
88 * This field must be set to 0 for all SINT MSRTs when all RT channels
91 * In practice this means that we have to disable MCS for all signed
92 * integer MSAA buffers. The alternative, to disable MCS only when one
93 * of the render target channels is disabled, is impractical because it
94 * would require converting between CMS and UMS MSAA layouts on the fly,
97 if (devinfo
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
106 intel_tiling_supports_ccs(const struct brw_context
*brw
,
107 enum isl_tiling tiling
)
109 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
111 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
112 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
114 * - Support is limited to tiled render targets.
116 * Gen9 changes the restriction to Y-tile only.
118 if (devinfo
->gen
>= 9)
119 return tiling
== ISL_TILING_Y0
;
120 else if (devinfo
->gen
>= 7)
121 return tiling
!= ISL_TILING_LINEAR
;
127 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
128 * can be used. This doesn't (and should not) inspect any of the properties of
131 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
132 * beneath the "Fast Color Clear" bullet (p326):
134 * - Support is for non-mip-mapped and non-array surface types only.
136 * And then later, on p327:
138 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
141 * From the Skylake documentation, it is made clear that X-tiling is no longer
144 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
148 intel_miptree_supports_ccs(struct brw_context
*brw
,
149 const struct intel_mipmap_tree
*mt
)
151 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
153 /* MCS support does not exist prior to Gen7 */
154 if (devinfo
->gen
< 7)
157 /* This function applies only to non-multisampled render targets. */
158 if (mt
->surf
.samples
> 1)
161 /* MCS is only supported for color buffers */
162 switch (_mesa_get_format_base_format(mt
->format
)) {
163 case GL_DEPTH_COMPONENT
:
164 case GL_DEPTH_STENCIL
:
165 case GL_STENCIL_INDEX
:
169 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
172 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
173 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
174 mt
->surf
.logical_level0_px
.depth
> 1;
177 /* Multisample surfaces with the CMS layout are not layered surfaces,
178 * yet still have physical_depth0 > 1. Assert that we don't
179 * accidentally reject a multisampled surface here. We should have
180 * rejected it earlier by explicitly checking the sample count.
182 assert(mt
->surf
.samples
== 1);
185 /* Handle the hardware restrictions...
187 * All GENs have the following restriction: "MCS buffer for non-MSRT is
188 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
190 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
191 * Non-MultiSampler Render Target Restrictions) Support is for
192 * non-mip-mapped and non-array surface types only.
194 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
195 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
196 * surfaces are supported with MCS buffer layout with these alignments in
197 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
199 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
200 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
201 * surfaces are supported with MCS buffer layout with these alignments in
202 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
204 if (devinfo
->gen
< 8 && (mip_mapped
|| arrayed
))
207 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
208 * work for 3D textures until gen9 where the layout of 3D textures changes
209 * to match 2D array textures.
211 if (devinfo
->gen
<= 8 && mt
->surf
.dim
!= ISL_SURF_DIM_2D
)
214 /* There's no point in using an MCS buffer if the surface isn't in a
217 if (!brw
->mesa_format_supports_render
[mt
->format
])
224 intel_tiling_supports_hiz(const struct brw_context
*brw
,
225 enum isl_tiling tiling
)
227 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
229 if (devinfo
->gen
< 6)
232 return tiling
== ISL_TILING_Y0
;
236 intel_miptree_supports_hiz(const struct brw_context
*brw
,
237 const struct intel_mipmap_tree
*mt
)
242 switch (mt
->format
) {
243 case MESA_FORMAT_Z_FLOAT32
:
244 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
245 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
246 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
247 case MESA_FORMAT_Z_UNORM16
:
255 * Return true if the format that will be used to access the miptree is
256 * CCS_E-compatible with the miptree's linear/non-sRGB format.
258 * Why use the linear format? Well, although the miptree may be specified with
259 * an sRGB format, the usage of that color space/format can be toggled. Since
260 * our HW tends to support more linear formats than sRGB ones, we use this
261 * format variant for check for CCS_E compatibility.
264 format_ccs_e_compat_with_miptree(const struct gen_device_info
*devinfo
,
265 const struct intel_mipmap_tree
*mt
,
266 enum isl_format access_format
)
268 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
270 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
271 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
272 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
276 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
277 const struct intel_mipmap_tree
*mt
)
279 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
281 if (devinfo
->gen
< 9)
284 /* For now compression is only enabled for integer formats even though
285 * there exist supported floating point formats also. This is a heuristic
286 * decision based on current public benchmarks. In none of the cases these
287 * formats provided any improvement but a few cases were seen to regress.
288 * Hence these are left to to be enabled in the future when they are known
291 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
294 if (!intel_miptree_supports_ccs(brw
, mt
))
297 /* Many window system buffers are sRGB even if they are never rendered as
298 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
299 * surface is used as sRGB, we fall back to CCS_D.
301 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
302 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
303 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
307 * Determine depth format corresponding to a depth+stencil format,
308 * for separate stencil.
311 intel_depth_format_for_depthstencil_format(mesa_format format
) {
313 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
314 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
315 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
316 return MESA_FORMAT_Z_FLOAT32
;
323 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
324 unsigned depth0
, struct intel_mipmap_level
*table
)
326 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
328 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
330 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
331 if (!table
[level
].slice
)
338 for (unsigned level
= first_level
; level
<= last_level
; level
++)
339 free(table
[level
].slice
);
345 needs_separate_stencil(const struct brw_context
*brw
,
346 struct intel_mipmap_tree
*mt
,
349 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
351 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
354 if (devinfo
->must_use_separate_stencil
)
357 return brw
->has_separate_stencil
&&
358 intel_miptree_supports_hiz(brw
, mt
);
362 * Choose the aux usage for this miptree. This function must be called fairly
363 * late in the miptree create process after we have a tiling.
366 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
367 struct intel_mipmap_tree
*mt
)
369 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
371 if (intel_miptree_supports_mcs(brw
, mt
)) {
372 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
373 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
374 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
375 intel_miptree_supports_ccs(brw
, mt
)) {
376 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
377 intel_miptree_supports_ccs_e(brw
, mt
)) {
378 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
380 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
382 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
383 intel_miptree_supports_hiz(brw
, mt
)) {
384 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
387 /* We can do fast-clear on all auxiliary surface types that are
388 * allocated through the normal texture creation paths.
390 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
391 mt
->supports_fast_clear
= true;
396 * Choose an appropriate uncompressed format for a requested
397 * compressed format, if unsupported.
400 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
402 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
404 /* No need to lower ETC formats on these platforms,
405 * they are supported natively.
407 if (devinfo
->gen
>= 8 || devinfo
->is_baytrail
)
411 case MESA_FORMAT_ETC1_RGB8
:
412 return MESA_FORMAT_R8G8B8X8_UNORM
;
413 case MESA_FORMAT_ETC2_RGB8
:
414 return MESA_FORMAT_R8G8B8X8_UNORM
;
415 case MESA_FORMAT_ETC2_SRGB8
:
416 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
417 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
418 return MESA_FORMAT_B8G8R8A8_SRGB
;
419 case MESA_FORMAT_ETC2_RGBA8_EAC
:
420 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
421 return MESA_FORMAT_R8G8B8A8_UNORM
;
422 case MESA_FORMAT_ETC2_R11_EAC
:
423 return MESA_FORMAT_R_UNORM16
;
424 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
425 return MESA_FORMAT_R_SNORM16
;
426 case MESA_FORMAT_ETC2_RG11_EAC
:
427 return MESA_FORMAT_R16G16_UNORM
;
428 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
429 return MESA_FORMAT_R16G16_SNORM
;
431 /* Non ETC1 / ETC2 format */
437 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
439 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
440 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
442 return mt
->surf
.logical_level0_px
.array_len
;
445 UNUSED
static unsigned
446 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
448 /* In case of physical dimensions one needs to consider also the layout.
449 * See isl_calc_phys_level0_extent_sa().
451 if (surf
->dim
!= ISL_SURF_DIM_3D
)
452 return surf
->phys_level0_sa
.array_len
;
454 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
455 return minify(surf
->phys_level0_sa
.array_len
, level
);
457 return minify(surf
->phys_level0_sa
.depth
, level
);
460 /** \brief Assert that the level and layer are valid for the miptree. */
462 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
470 assert(level
>= mt
->first_level
);
471 assert(level
<= mt
->last_level
);
472 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
475 static enum isl_aux_state
**
476 create_aux_state_map(struct intel_mipmap_tree
*mt
,
477 enum isl_aux_state initial
)
479 const uint32_t levels
= mt
->last_level
+ 1;
481 uint32_t total_slices
= 0;
482 for (uint32_t level
= 0; level
< levels
; level
++)
483 total_slices
+= brw_get_num_logical_layers(mt
, level
);
485 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
487 /* We're going to allocate a single chunk of data for both the per-level
488 * reference array and the arrays of aux_state. This makes cleanup
489 * significantly easier.
491 const size_t total_size
= per_level_array_size
+
492 total_slices
* sizeof(enum isl_aux_state
);
493 void *data
= malloc(total_size
);
497 enum isl_aux_state
**per_level_arr
= data
;
498 enum isl_aux_state
*s
= data
+ per_level_array_size
;
499 for (uint32_t level
= 0; level
< levels
; level
++) {
500 per_level_arr
[level
] = s
;
501 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
502 for (uint32_t a
= 0; a
< level_layers
; a
++)
505 assert((void *)s
== data
+ total_size
);
507 return per_level_arr
;
511 free_aux_state_map(enum isl_aux_state
**state
)
517 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
518 enum isl_tiling tiling
, unsigned samples
)
523 if (tiling
== ISL_TILING_LINEAR
)
526 /* If the width is much smaller than a tile, don't bother tiling. */
530 if (ALIGN(row_pitch
, 512) >= 32768) {
531 perf_debug("row pitch %u too large to blit, falling back to untiled",
540 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
541 enum isl_tiling tiling
)
543 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
545 /* If the BO is too large to fit in the aperture, we need to use the
546 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
547 * handle Y-tiling, so we need to fall back to X.
549 if (devinfo
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
550 tiling
== ISL_TILING_Y0
)
556 static struct intel_mipmap_tree
*
557 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
558 unsigned first_level
, unsigned last_level
,
559 unsigned width0
, unsigned height0
, unsigned depth0
,
560 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
561 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
562 unsigned row_pitch
, struct brw_bo
*bo
)
564 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
568 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
576 if (target
== GL_TEXTURE_CUBE_MAP
||
577 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
578 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
580 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
582 _mesa_enum_to_string(target
),
583 _mesa_get_format_name(format
),
584 num_samples
, width0
, height0
, depth0
,
585 first_level
, last_level
, mt
);
587 struct isl_surf_init_info init_info
= {
588 .dim
= get_isl_surf_dim(target
),
589 .format
= translate_tex_format(brw
, format
, false),
592 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
593 .levels
= last_level
- first_level
+ 1,
594 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
595 .samples
= num_samples
,
596 .row_pitch
= row_pitch
,
597 .usage
= isl_usage_flags
,
598 .tiling_flags
= tiling_flags
,
601 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
604 /* Depth surfaces are always Y-tiled and stencil is always W-tiled, although
605 * on gen7 platforms we also need to create Y-tiled copies of stencil for
606 * texturing since the hardware can't sample from W-tiled surfaces. For
607 * everything else, check for corner cases needing special treatment.
609 bool is_depth_stencil
=
610 mt
->surf
.usage
& (ISL_SURF_USAGE_STENCIL_BIT
| ISL_SURF_USAGE_DEPTH_BIT
);
611 if (!is_depth_stencil
) {
612 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
613 mt
->surf
.tiling
, mt
->surf
.samples
)) {
614 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
615 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
617 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
618 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
619 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
624 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
625 * the size may not be multiple of row_pitch.
626 * See isl_apply_surface_padding().
628 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
629 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
632 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
634 isl_tiling_to_i915_tiling(
636 mt
->surf
.row_pitch
, alloc_flags
);
643 mt
->first_level
= first_level
;
644 mt
->last_level
= last_level
;
647 mt
->aux_state
= NULL
;
648 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
649 mt
->compressed
= _mesa_is_format_compressed(format
);
650 mt
->drm_modifier
= DRM_FORMAT_MOD_INVALID
;
655 intel_miptree_release(&mt
);
660 make_separate_stencil_surface(struct brw_context
*brw
,
661 struct intel_mipmap_tree
*mt
)
663 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
664 0, mt
->surf
.levels
- 1,
665 mt
->surf
.logical_level0_px
.width
,
666 mt
->surf
.logical_level0_px
.height
,
667 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
668 mt
->surf
.logical_level0_px
.depth
:
669 mt
->surf
.logical_level0_px
.array_len
,
670 mt
->surf
.samples
, ISL_TILING_W_BIT
,
671 ISL_SURF_USAGE_STENCIL_BIT
|
672 ISL_SURF_USAGE_TEXTURE_BIT
,
673 BO_ALLOC_BUSY
, 0, NULL
);
678 mt
->stencil_mt
->r8stencil_needs_update
= true;
683 static struct intel_mipmap_tree
*
684 miptree_create(struct brw_context
*brw
,
693 enum intel_miptree_create_flags flags
)
695 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
697 if (format
== MESA_FORMAT_S_UINT8
)
698 return make_surface(brw
, target
, format
, first_level
, last_level
,
699 width0
, height0
, depth0
, num_samples
,
701 ISL_SURF_USAGE_STENCIL_BIT
|
702 ISL_SURF_USAGE_TEXTURE_BIT
,
707 const GLenum base_format
= _mesa_get_format_base_format(format
);
708 if ((base_format
== GL_DEPTH_COMPONENT
||
709 base_format
== GL_DEPTH_STENCIL
) &&
710 !(flags
& MIPTREE_CREATE_LINEAR
)) {
711 /* Fix up the Z miptree format for how we're splitting out separate
712 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
714 const mesa_format depth_only_format
=
715 intel_depth_format_for_depthstencil_format(format
);
716 struct intel_mipmap_tree
*mt
= make_surface(
717 brw
, target
, devinfo
->gen
>= 6 ? depth_only_format
: format
,
718 first_level
, last_level
,
719 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
720 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
721 BO_ALLOC_BUSY
, 0, NULL
);
723 if (needs_separate_stencil(brw
, mt
, format
) &&
724 !make_separate_stencil_surface(brw
, mt
)) {
725 intel_miptree_release(&mt
);
729 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
730 intel_miptree_choose_aux_usage(brw
, mt
);
735 mesa_format tex_format
= format
;
736 mesa_format etc_format
= MESA_FORMAT_NONE
;
737 uint32_t alloc_flags
= 0;
739 format
= intel_lower_compressed_format(brw
, format
);
741 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
743 if (flags
& MIPTREE_CREATE_BUSY
)
744 alloc_flags
|= BO_ALLOC_BUSY
;
746 isl_tiling_flags_t tiling_flags
= (flags
& MIPTREE_CREATE_LINEAR
) ?
747 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
749 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
750 if (devinfo
->gen
< 6)
751 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
753 struct intel_mipmap_tree
*mt
= make_surface(
755 first_level
, last_level
,
756 width0
, height0
, depth0
,
757 num_samples
, tiling_flags
,
758 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
759 ISL_SURF_USAGE_TEXTURE_BIT
,
760 alloc_flags
, 0, NULL
);
764 mt
->etc_format
= etc_format
;
766 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
767 intel_miptree_choose_aux_usage(brw
, mt
);
772 struct intel_mipmap_tree
*
773 intel_miptree_create(struct brw_context
*brw
,
782 enum intel_miptree_create_flags flags
)
784 assert(num_samples
> 0);
786 struct intel_mipmap_tree
*mt
= miptree_create(
788 first_level
, last_level
,
789 width0
, height0
, depth0
, num_samples
,
796 /* Create the auxiliary surface up-front. CCS_D, on the other hand, can only
797 * compress clear color so we wait until an actual fast-clear to allocate
800 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
801 !intel_miptree_alloc_aux(brw
, mt
)) {
802 intel_miptree_release(&mt
);
809 struct intel_mipmap_tree
*
810 intel_miptree_create_for_bo(struct brw_context
*brw
,
818 enum isl_tiling tiling
,
819 enum intel_miptree_create_flags flags
)
821 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
822 struct intel_mipmap_tree
*mt
;
823 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
824 const GLenum base_format
= _mesa_get_format_base_format(format
);
826 if ((base_format
== GL_DEPTH_COMPONENT
||
827 base_format
== GL_DEPTH_STENCIL
)) {
828 const mesa_format depth_only_format
=
829 intel_depth_format_for_depthstencil_format(format
);
830 mt
= make_surface(brw
, target
,
831 devinfo
->gen
>= 6 ? depth_only_format
: format
,
832 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
833 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
838 brw_bo_reference(bo
);
840 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
841 intel_miptree_choose_aux_usage(brw
, mt
);
844 } else if (format
== MESA_FORMAT_S_UINT8
) {
845 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
846 0, 0, width
, height
, depth
, 1,
848 ISL_SURF_USAGE_STENCIL_BIT
|
849 ISL_SURF_USAGE_TEXTURE_BIT
,
854 assert(bo
->size
>= mt
->surf
.size
);
856 brw_bo_reference(bo
);
860 /* Nothing will be able to use this miptree with the BO if the offset isn't
863 if (tiling
!= ISL_TILING_LINEAR
)
864 assert(offset
% 4096 == 0);
866 /* miptrees can't handle negative pitch. If you need flipping of images,
867 * that's outside of the scope of the mt.
871 /* The BO already has a tiling format and we shouldn't confuse the lower
872 * layers by making it try to find a tiling format again.
874 assert((flags
& MIPTREE_CREATE_LINEAR
) == 0);
876 mt
= make_surface(brw
, target
, format
,
877 0, 0, width
, height
, depth
, 1,
879 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
880 ISL_SURF_USAGE_TEXTURE_BIT
,
885 brw_bo_reference(bo
);
889 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
890 intel_miptree_choose_aux_usage(brw
, mt
);
892 /* Create the auxiliary surface up-front. CCS_D, on the other hand, can
893 * only compress clear color so we wait until an actual fast-clear to
896 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
897 !intel_miptree_alloc_aux(brw
, mt
)) {
898 intel_miptree_release(&mt
);
906 static struct intel_mipmap_tree
*
907 miptree_create_for_planar_image(struct brw_context
*brw
,
908 __DRIimage
*image
, GLenum target
,
909 enum isl_tiling tiling
)
911 const struct intel_image_format
*f
= image
->planar_format
;
912 struct intel_mipmap_tree
*planar_mt
= NULL
;
914 for (int i
= 0; i
< f
->nplanes
; i
++) {
915 const int index
= f
->planes
[i
].buffer_index
;
916 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
917 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
918 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
919 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
921 /* Disable creation of the texture's aux buffers because the driver
922 * exposes no EGL API to manage them. That is, there is no API for
923 * resolving the aux buffer's content to the main buffer nor for
924 * invalidating the aux buffer's content.
926 struct intel_mipmap_tree
*mt
=
927 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
928 image
->offsets
[index
],
930 image
->strides
[index
],
932 MIPTREE_CREATE_NO_AUX
);
941 planar_mt
->plane
[i
- 1] = mt
;
944 planar_mt
->drm_modifier
= image
->modifier
;
950 create_ccs_buf_for_image(struct brw_context
*brw
,
952 struct intel_mipmap_tree
*mt
,
953 enum isl_aux_state initial_state
)
955 struct isl_surf temp_ccs_surf
;
957 /* CCS is only supported for very simple miptrees */
958 assert(image
->aux_offset
!= 0 && image
->aux_pitch
!= 0);
959 assert(image
->tile_x
== 0 && image
->tile_y
== 0);
960 assert(mt
->surf
.samples
== 1);
961 assert(mt
->surf
.levels
== 1);
962 assert(mt
->surf
.logical_level0_px
.depth
== 1);
963 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
964 assert(mt
->first_level
== 0);
965 assert(mt
->last_level
== 0);
967 /* We shouldn't already have a CCS */
968 assert(!mt
->aux_buf
);
970 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
,
974 assert(image
->aux_offset
< image
->bo
->size
);
975 assert(temp_ccs_surf
.size
<= image
->bo
->size
- image
->aux_offset
);
977 mt
->aux_buf
= calloc(sizeof(*mt
->aux_buf
), 1);
978 if (mt
->aux_buf
== NULL
)
981 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
982 if (!mt
->aux_state
) {
988 /* On gen10+ we start using an extra space in the aux buffer to store the
989 * indirect clear color. However, if we imported an image from the window
990 * system with CCS, we don't have the extra space at the end of the aux
991 * buffer. So create a new bo here that will store that clear color.
993 if (brw
->isl_dev
.ss
.clear_color_state_size
> 0) {
994 mt
->aux_buf
->clear_color_bo
=
995 brw_bo_alloc_tiled(brw
->bufmgr
, "clear_color_bo",
996 brw
->isl_dev
.ss
.clear_color_state_size
,
997 I915_TILING_NONE
, 0, BO_ALLOC_ZEROED
);
998 if (!mt
->aux_buf
->clear_color_bo
) {
1005 mt
->aux_buf
->bo
= image
->bo
;
1006 brw_bo_reference(image
->bo
);
1008 mt
->aux_buf
->offset
= image
->aux_offset
;
1009 mt
->aux_buf
->surf
= temp_ccs_surf
;
1014 struct intel_mipmap_tree
*
1015 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
1016 __DRIimage
*image
, GLenum target
,
1018 bool is_winsys_image
)
1020 uint32_t bo_tiling
, bo_swizzle
;
1021 brw_bo_get_tiling(image
->bo
, &bo_tiling
, &bo_swizzle
);
1023 const struct isl_drm_modifier_info
*mod_info
=
1024 isl_drm_modifier_get_info(image
->modifier
);
1026 const enum isl_tiling tiling
=
1027 mod_info
? mod_info
->tiling
: isl_tiling_from_i915_tiling(bo_tiling
);
1029 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1)
1030 return miptree_create_for_planar_image(brw
, image
, target
, tiling
);
1032 if (image
->planar_format
)
1033 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
1035 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1036 /* The texture storage paths in core Mesa detect if the driver does not
1037 * support the user-requested format, and then searches for a
1038 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1039 * do the fallbacks here for important formats.
1041 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1042 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1043 * the Chrome OS compositor consumes as dma_buf EGLImages.
1045 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1048 if (!brw
->ctx
.TextureFormatSupported
[format
])
1051 enum intel_miptree_create_flags mt_create_flags
= 0;
1053 /* If this image comes in from a window system, we have different
1054 * requirements than if it comes in via an EGL import operation. Window
1055 * system images can use any form of auxiliary compression we wish because
1056 * they get "flushed" before being handed off to the window system and we
1057 * have the opportunity to do resolves. Non window-system images, on the
1058 * other hand, have no resolve point so we can't have aux without a
1061 if (!is_winsys_image
)
1062 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1064 /* If we have a modifier which specifies aux, don't create one yet */
1065 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
1066 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1068 /* Disable creation of the texture's aux buffers because the driver exposes
1069 * no EGL API to manage them. That is, there is no API for resolving the aux
1070 * buffer's content to the main buffer nor for invalidating the aux buffer's
1073 struct intel_mipmap_tree
*mt
=
1074 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1075 image
->offset
, image
->width
, image
->height
, 1,
1076 image
->pitch
, tiling
, mt_create_flags
);
1080 mt
->target
= target
;
1081 mt
->level
[0].level_x
= image
->tile_x
;
1082 mt
->level
[0].level_y
= image
->tile_y
;
1083 mt
->drm_modifier
= image
->modifier
;
1085 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1086 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1087 * trouble resolving back to destination image due to alignment issues.
1089 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1090 if (!devinfo
->has_surface_tile_offset
) {
1091 uint32_t draw_x
, draw_y
;
1092 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1094 if (draw_x
!= 0 || draw_y
!= 0) {
1095 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1096 intel_miptree_release(&mt
);
1101 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1102 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1104 mt
->aux_usage
= mod_info
->aux_usage
;
1105 /* If we are a window system buffer, then we can support fast-clears
1106 * even if the modifier doesn't support them by doing a partial resolve
1107 * as part of the flush operation.
1109 mt
->supports_fast_clear
=
1110 is_winsys_image
|| mod_info
->supports_clear_color
;
1112 /* We don't know the actual state of the surface when we get it but we
1113 * can make a pretty good guess based on the modifier. What we do know
1114 * for sure is that it isn't in the AUX_INVALID state, so we just assume
1115 * a worst case of compression.
1117 enum isl_aux_state initial_state
=
1118 isl_drm_modifier_get_default_aux_state(image
->modifier
);
1120 if (!create_ccs_buf_for_image(brw
, image
, mt
, initial_state
)) {
1121 intel_miptree_release(&mt
);
1126 /* Don't assume coherency for imported EGLimages. We don't know what
1127 * external clients are going to do with it. They may scan it out.
1129 image
->bo
->cache_coherent
= false;
1135 * For a singlesample renderbuffer, this simply wraps the given BO with a
1138 * For a multisample renderbuffer, this wraps the window system's
1139 * (singlesample) BO with a singlesample miptree attached to the
1140 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1141 * that will contain the actual rendering (which is lazily resolved to
1142 * irb->singlesample_mt).
1145 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1146 struct intel_renderbuffer
*irb
,
1147 struct intel_mipmap_tree
*singlesample_mt
,
1148 uint32_t width
, uint32_t height
,
1151 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1152 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1153 mesa_format format
= rb
->Format
;
1154 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1156 /* Only the front and back buffers, which are color buffers, are allocated
1157 * through the image loader.
1159 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1160 _mesa_get_format_base_format(format
) == GL_RGBA
);
1162 assert(singlesample_mt
);
1164 if (num_samples
== 1) {
1165 intel_miptree_release(&irb
->mt
);
1166 irb
->mt
= singlesample_mt
;
1168 assert(!irb
->singlesample_mt
);
1170 intel_miptree_release(&irb
->singlesample_mt
);
1171 irb
->singlesample_mt
= singlesample_mt
;
1174 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1175 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1176 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1181 if (!multisample_mt
)
1184 irb
->need_downsample
= false;
1185 intel_miptree_release(&irb
->mt
);
1186 irb
->mt
= multisample_mt
;
1192 intel_miptree_release(&irb
->mt
);
1196 struct intel_mipmap_tree
*
1197 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1201 uint32_t num_samples
)
1203 struct intel_mipmap_tree
*mt
;
1205 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1207 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1208 width
, height
, depth
, num_samples
,
1209 MIPTREE_CREATE_BUSY
);
1216 intel_miptree_release(&mt
);
1221 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1222 struct intel_mipmap_tree
*src
)
1227 intel_miptree_release(dst
);
1231 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1238 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1240 if (aux_buf
== NULL
)
1243 brw_bo_unreference(aux_buf
->bo
);
1244 brw_bo_unreference(aux_buf
->clear_color_bo
);
1250 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1255 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1256 if (--(*mt
)->refcount
<= 0) {
1259 DBG("%s deleting %p\n", __func__
, *mt
);
1261 brw_bo_unreference((*mt
)->bo
);
1262 intel_miptree_release(&(*mt
)->stencil_mt
);
1263 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1264 intel_miptree_aux_buffer_free((*mt
)->aux_buf
);
1265 free_aux_state_map((*mt
)->aux_state
);
1267 intel_miptree_release(&(*mt
)->plane
[0]);
1268 intel_miptree_release(&(*mt
)->plane
[1]);
1270 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1271 free((*mt
)->level
[i
].slice
);
1281 intel_get_image_dims(struct gl_texture_image
*image
,
1282 int *width
, int *height
, int *depth
)
1284 switch (image
->TexObject
->Target
) {
1285 case GL_TEXTURE_1D_ARRAY
:
1286 /* For a 1D Array texture the OpenGL API will treat the image height as
1287 * the number of array slices. For Intel hardware, we treat the 1D array
1288 * as a 2D Array with a height of 1. So, here we want to swap image
1291 assert(image
->Depth
== 1);
1292 *width
= image
->Width
;
1294 *depth
= image
->Height
;
1296 case GL_TEXTURE_CUBE_MAP
:
1297 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1298 * though we really have 6 slices.
1300 assert(image
->Depth
== 1);
1301 *width
= image
->Width
;
1302 *height
= image
->Height
;
1306 *width
= image
->Width
;
1307 *height
= image
->Height
;
1308 *depth
= image
->Depth
;
1314 * Can the image be pulled into a unified mipmap tree? This mirrors
1315 * the completeness test in a lot of ways.
1317 * Not sure whether I want to pass gl_texture_image here.
1320 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1321 struct gl_texture_image
*image
)
1323 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1324 GLuint level
= intelImage
->base
.Base
.Level
;
1325 int width
, height
, depth
;
1327 /* glTexImage* choose the texture object based on the target passed in, and
1328 * objects can't change targets over their lifetimes, so this should be
1331 assert(image
->TexObject
->Target
== mt
->target
);
1333 mesa_format mt_format
= mt
->format
;
1334 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1335 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1336 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1337 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1338 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1339 mt_format
= mt
->etc_format
;
1341 if (_mesa_get_srgb_format_linear(image
->TexFormat
) !=
1342 _mesa_get_srgb_format_linear(mt_format
))
1345 intel_get_image_dims(image
, &width
, &height
, &depth
);
1347 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1350 if (level
>= mt
->surf
.levels
)
1353 const unsigned level_depth
=
1354 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1355 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1356 mt
->surf
.logical_level0_px
.array_len
;
1358 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1359 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1360 depth
== level_depth
&&
1361 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1365 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1366 GLuint level
, GLuint slice
,
1367 GLuint
*x
, GLuint
*y
)
1369 if (level
== 0 && slice
== 0) {
1370 *x
= mt
->level
[0].level_x
;
1371 *y
= mt
->level
[0].level_y
;
1375 uint32_t x_offset_sa
, y_offset_sa
;
1377 /* Miptree itself can have an offset only if it represents a single
1378 * slice in an imported buffer object.
1379 * See intel_miptree_create_for_dri_image().
1381 assert(mt
->level
[0].level_x
== 0);
1382 assert(mt
->level
[0].level_y
== 0);
1384 /* Given level is relative to level zero while the miptree may be
1385 * represent just a subset of all levels starting from 'first_level'.
1387 assert(level
>= mt
->first_level
);
1388 level
-= mt
->first_level
;
1390 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1391 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1392 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1393 &x_offset_sa
, &y_offset_sa
);
1401 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1402 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1403 * and tile_h is set to 1.
1406 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1407 uint32_t *tile_w
, uint32_t *tile_h
)
1418 case ISL_TILING_LINEAR
:
1423 unreachable("not reached");
1429 * This function computes masks that may be used to select the bits of the X
1430 * and Y coordinates that indicate the offset within a tile. If the BO is
1431 * untiled, the masks are set to 0.
1434 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1435 uint32_t *mask_x
, uint32_t *mask_y
)
1437 uint32_t tile_w_bytes
, tile_h
;
1439 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1441 *mask_x
= tile_w_bytes
/ cpp
- 1;
1442 *mask_y
= tile_h
- 1;
1446 * Compute the offset (in bytes) from the start of the BO to the given x
1447 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1448 * multiples of the tile size.
1451 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1452 uint32_t x
, uint32_t y
)
1455 uint32_t pitch
= mt
->surf
.row_pitch
;
1457 switch (mt
->surf
.tiling
) {
1459 unreachable("not reached");
1460 case ISL_TILING_LINEAR
:
1461 return y
* pitch
+ x
* cpp
;
1463 assert((x
% (512 / cpp
)) == 0);
1464 assert((y
% 8) == 0);
1465 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1467 assert((x
% (128 / cpp
)) == 0);
1468 assert((y
% 32) == 0);
1469 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1474 * Rendering with tiled buffers requires that the base address of the buffer
1475 * be aligned to a page boundary. For renderbuffers, and sometimes with
1476 * textures, we may want the surface to point at a texture image level that
1477 * isn't at a page boundary.
1479 * This function returns an appropriately-aligned base offset
1480 * according to the tiling restrictions, plus any required x/y offset
1484 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1485 GLuint level
, GLuint slice
,
1490 uint32_t mask_x
, mask_y
;
1492 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1493 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1495 *tile_x
= x
& mask_x
;
1496 *tile_y
= y
& mask_y
;
1498 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1502 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1503 struct intel_mipmap_tree
*src_mt
,
1504 unsigned src_level
, unsigned src_layer
,
1505 struct intel_mipmap_tree
*dst_mt
,
1506 unsigned dst_level
, unsigned dst_layer
,
1507 unsigned width
, unsigned height
)
1510 ptrdiff_t src_stride
, dst_stride
;
1511 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1513 intel_miptree_map(brw
, src_mt
,
1514 src_level
, src_layer
,
1517 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1520 intel_miptree_map(brw
, dst_mt
,
1521 dst_level
, dst_layer
,
1524 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1528 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1529 _mesa_get_format_name(src_mt
->format
),
1530 src_mt
, src
, src_stride
,
1531 _mesa_get_format_name(dst_mt
->format
),
1532 dst_mt
, dst
, dst_stride
,
1535 int row_size
= cpp
* width
;
1536 if (src_stride
== row_size
&&
1537 dst_stride
== row_size
) {
1538 memcpy(dst
, src
, row_size
* height
);
1540 for (int i
= 0; i
< height
; i
++) {
1541 memcpy(dst
, src
, row_size
);
1547 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1548 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1550 /* Don't forget to copy the stencil data over, too. We could have skipped
1551 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1552 * shuffling the two data sources in/out of temporary storage instead of
1553 * the direct mapping we get this way.
1555 if (dst_mt
->stencil_mt
) {
1556 assert(src_mt
->stencil_mt
);
1557 intel_miptree_copy_slice_sw(brw
,
1558 src_mt
->stencil_mt
, src_level
, src_layer
,
1559 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1565 intel_miptree_copy_slice(struct brw_context
*brw
,
1566 struct intel_mipmap_tree
*src_mt
,
1567 unsigned src_level
, unsigned src_layer
,
1568 struct intel_mipmap_tree
*dst_mt
,
1569 unsigned dst_level
, unsigned dst_layer
)
1572 mesa_format format
= src_mt
->format
;
1573 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1574 src_level
- src_mt
->first_level
);
1575 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1576 src_level
- src_mt
->first_level
);
1578 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1579 src_level
- src_mt
->first_level
));
1581 assert(_mesa_get_srgb_format_linear(src_mt
->format
) ==
1582 _mesa_get_srgb_format_linear(dst_mt
->format
));
1584 if (dst_mt
->compressed
) {
1586 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1587 height
= ALIGN_NPOT(height
, j
) / j
;
1588 width
= ALIGN_NPOT(width
, i
) / i
;
1591 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1592 * below won't apply since we can't do the depth's Y tiling or the
1593 * stencil's W tiling in the blitter.
1595 if (src_mt
->stencil_mt
) {
1596 intel_miptree_copy_slice_sw(brw
,
1597 src_mt
, src_level
, src_layer
,
1598 dst_mt
, dst_level
, dst_layer
,
1603 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1604 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1606 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1609 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1610 _mesa_get_format_name(src_mt
->format
),
1611 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1612 _mesa_get_format_name(dst_mt
->format
),
1613 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1616 if (!intel_miptree_blit(brw
,
1617 src_mt
, src_level
, src_layer
, 0, 0, false,
1618 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1619 width
, height
, COLOR_LOGICOP_COPY
)) {
1620 perf_debug("miptree validate blit for %s failed\n",
1621 _mesa_get_format_name(format
));
1623 intel_miptree_copy_slice_sw(brw
,
1624 src_mt
, src_level
, src_layer
,
1625 dst_mt
, dst_level
, dst_layer
,
1631 * Copies the image's current data to the given miptree, and associates that
1632 * miptree with the image.
1635 intel_miptree_copy_teximage(struct brw_context
*brw
,
1636 struct intel_texture_image
*intelImage
,
1637 struct intel_mipmap_tree
*dst_mt
)
1639 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1640 struct intel_texture_object
*intel_obj
=
1641 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1642 int level
= intelImage
->base
.Base
.Level
;
1643 const unsigned face
= intelImage
->base
.Base
.Face
;
1644 unsigned start_layer
, end_layer
;
1646 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1648 assert(intelImage
->base
.Base
.Height
);
1650 end_layer
= intelImage
->base
.Base
.Height
- 1;
1651 } else if (face
> 0) {
1655 assert(intelImage
->base
.Base
.Depth
);
1657 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1660 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1661 intel_miptree_copy_slice(brw
,
1666 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1667 intel_obj
->needs_validate
= true;
1670 static struct intel_miptree_aux_buffer
*
1671 intel_alloc_aux_buffer(struct brw_context
*brw
,
1672 const struct isl_surf
*aux_surf
,
1674 uint8_t memset_value
)
1676 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1680 uint64_t size
= aux_surf
->size
;
1682 const bool has_indirect_clear
= brw
->isl_dev
.ss
.clear_color_state_size
> 0;
1683 if (has_indirect_clear
) {
1684 /* On CNL+, instead of setting the clear color in the SURFACE_STATE, we
1685 * will set a pointer to a dword somewhere that contains the color. So,
1686 * allocate the space for the clear color value here on the aux buffer.
1688 buf
->clear_color_offset
= size
;
1689 size
+= brw
->isl_dev
.ss
.clear_color_state_size
;
1692 /* If the buffer needs to be initialised (requiring the buffer to be
1693 * immediately mapped to cpu space for writing), do not use the gpu access
1694 * flag which can cause an unnecessary delay if the backing pages happened
1695 * to be just used by the GPU.
1697 const bool alloc_zeroed
= wants_memset
&& memset_value
== 0;
1698 const bool needs_memset
=
1699 !alloc_zeroed
&& (wants_memset
|| has_indirect_clear
);
1700 const uint32_t alloc_flags
=
1701 alloc_zeroed
? BO_ALLOC_ZEROED
: (needs_memset
? 0 : BO_ALLOC_BUSY
);
1703 /* ISL has stricter set of alignment rules then the drm allocator.
1704 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1705 * trying to recalculate based on different format block sizes.
1707 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "aux-miptree", size
,
1708 I915_TILING_Y
, aux_surf
->row_pitch
,
1715 /* Initialize the bo to the desired value */
1717 assert(!(alloc_flags
& BO_ALLOC_BUSY
));
1719 void *map
= brw_bo_map(brw
, buf
->bo
, MAP_WRITE
| MAP_RAW
);
1721 intel_miptree_aux_buffer_free(buf
);
1725 /* Memset the aux_surf portion of the BO. */
1727 memset(map
, memset_value
, aux_surf
->size
);
1729 /* Zero the indirect clear color to match ::fast_clear_color. */
1730 if (has_indirect_clear
) {
1731 memset((char *)map
+ buf
->clear_color_offset
, 0,
1732 brw
->isl_dev
.ss
.clear_color_state_size
);
1735 brw_bo_unmap(buf
->bo
);
1738 if (has_indirect_clear
) {
1739 buf
->clear_color_bo
= buf
->bo
;
1740 brw_bo_reference(buf
->clear_color_bo
);
1743 buf
->surf
= *aux_surf
;
1750 * Helper for intel_miptree_alloc_aux() that sets
1751 * \c mt->level[level].has_hiz. Return true if and only if
1752 * \c has_hiz was set.
1755 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1756 struct intel_mipmap_tree
*mt
,
1759 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1761 assert(mt
->aux_buf
);
1762 assert(mt
->surf
.size
> 0);
1764 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
1765 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1766 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1768 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1769 * and the height is 4 aligned. This allows our HiZ support
1770 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1771 * we can grow the width & height to allow the HiZ op to
1772 * force the proper size alignments.
1774 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1775 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1780 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1781 mt
->level
[level
].has_hiz
= true;
1787 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1789 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1790 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1791 * compress clear color so we wait until an actual fast-clear to allocate it.
1794 intel_miptree_alloc_aux(struct brw_context
*brw
,
1795 struct intel_mipmap_tree
*mt
)
1797 assert(mt
->aux_buf
== NULL
);
1799 /* Get the aux buf allocation parameters for this miptree. */
1800 enum isl_aux_state initial_state
;
1801 uint8_t memset_value
;
1802 struct isl_surf aux_surf
;
1803 MAYBE_UNUSED
bool aux_surf_ok
;
1805 switch (mt
->aux_usage
) {
1806 case ISL_AUX_USAGE_NONE
:
1810 case ISL_AUX_USAGE_HIZ
:
1811 assert(!_mesa_is_format_color_format(mt
->format
));
1813 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
1814 aux_surf_ok
= isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &aux_surf
);
1816 case ISL_AUX_USAGE_MCS
:
1817 assert(_mesa_is_format_color_format(mt
->format
));
1818 assert(brw
->screen
->devinfo
.gen
>= 7); /* MCS only used on Gen7+ */
1820 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1822 * When MCS buffer is enabled and bound to MSRT, it is required that
1823 * it is cleared prior to any rendering.
1825 * Since we don't use the MCS buffer for any purpose other than
1826 * rendering, it makes sense to just clear it immediately upon
1829 * Note: the clear value for MCS buffers is all 1's, so we memset to
1832 initial_state
= ISL_AUX_STATE_CLEAR
;
1833 memset_value
= 0xFF;
1834 aux_surf_ok
= isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &aux_surf
);
1836 case ISL_AUX_USAGE_CCS_D
:
1837 case ISL_AUX_USAGE_CCS_E
:
1838 assert(_mesa_is_format_color_format(mt
->format
));
1840 /* When CCS_E is used, we need to ensure that the CCS starts off in a
1841 * valid state. From the Sky Lake PRM, "MCS Buffer for Render
1844 * "If Software wants to enable Color Compression without Fast
1845 * clear, Software needs to initialize MCS with zeros."
1847 * A CCS value of 0 indicates that the corresponding block is in the
1848 * pass-through state which is what we want.
1850 * For CCS_D, do the same thing. On gen9+, this avoids having any
1851 * undefined bits in the aux buffer.
1853 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
1856 isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &aux_surf
, 0);
1860 /* We should have a valid aux_surf. */
1861 assert(aux_surf_ok
);
1863 /* No work is needed for a zero-sized auxiliary buffer. */
1864 if (aux_surf
.size
== 0)
1867 /* Create the aux_state for the auxiliary buffer. */
1868 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
1869 if (mt
->aux_state
== NULL
)
1872 /* Allocate the auxiliary buffer. */
1873 const bool needs_memset
= initial_state
!= ISL_AUX_STATE_AUX_INVALID
;
1874 mt
->aux_buf
= intel_alloc_aux_buffer(brw
, &aux_surf
, needs_memset
,
1876 if (mt
->aux_buf
== NULL
) {
1877 free_aux_state_map(mt
->aux_state
);
1878 mt
->aux_state
= NULL
;
1882 /* Perform aux_usage-specific initialization. */
1883 if (mt
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
1884 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1885 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1893 * Can the miptree sample using the hiz buffer?
1896 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1897 struct intel_mipmap_tree
*mt
)
1899 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1901 if (!devinfo
->has_sample_with_hiz
) {
1909 /* It seems the hardware won't fallback to the depth buffer if some of the
1910 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1911 * of the texture to be HiZ enabled.
1913 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1914 if (!intel_miptree_level_has_hiz(mt
, level
))
1918 /* If compressed multisampling is enabled, then we use it for the auxiliary
1921 * From the BDW PRM (Volume 2d: Command Reference: Structures
1922 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1924 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1925 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1927 * There is no such blurb for 1D textures, but there is sufficient evidence
1928 * that this is broken on SKL+.
1930 return (mt
->surf
.samples
== 1 &&
1931 mt
->target
!= GL_TEXTURE_3D
&&
1932 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1936 * Does the miptree slice have hiz enabled?
1939 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1941 intel_miptree_check_level_layer(mt
, level
, 0);
1942 return mt
->level
[level
].has_hiz
;
1945 static inline uint32_t
1946 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1947 uint32_t start_level
, uint32_t num_levels
)
1949 assert(start_level
>= mt
->first_level
);
1950 assert(start_level
<= mt
->last_level
);
1952 if (num_levels
== INTEL_REMAINING_LAYERS
)
1953 num_levels
= mt
->last_level
- start_level
+ 1;
1954 /* Check for overflow */
1955 assert(start_level
+ num_levels
>= start_level
);
1956 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
1961 static inline uint32_t
1962 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
1963 uint32_t start_layer
, uint32_t num_layers
)
1965 assert(level
<= mt
->last_level
);
1967 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
1968 assert(start_layer
< total_num_layers
);
1969 if (num_layers
== INTEL_REMAINING_LAYERS
)
1970 num_layers
= total_num_layers
- start_layer
;
1971 /* Check for overflow */
1972 assert(start_layer
+ num_layers
>= start_layer
);
1973 assert(start_layer
+ num_layers
<= total_num_layers
);
1979 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1980 unsigned start_level
, unsigned num_levels
,
1981 unsigned start_layer
, unsigned num_layers
)
1983 assert(_mesa_is_format_color_format(mt
->format
));
1988 /* Clamp the level range to fit the miptree */
1989 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
1991 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1992 const uint32_t level
= start_level
+ l
;
1993 const uint32_t level_layers
=
1994 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
1995 for (unsigned a
= 0; a
< level_layers
; a
++) {
1996 enum isl_aux_state aux_state
=
1997 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
1998 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
1999 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2008 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2009 const struct intel_mipmap_tree
*mt
,
2010 unsigned level
, unsigned layer
)
2015 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2016 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2017 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2019 /* Compression of arrayed msaa surfaces is supported. */
2020 if (mt
->surf
.samples
> 1)
2023 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2024 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2026 mt
->surf
.logical_level0_px
.depth
== 1 &&
2027 mt
->surf
.logical_level0_px
.array_len
== 1));
2033 static enum isl_aux_op
2034 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2035 enum isl_aux_usage aux_usage
,
2036 bool fast_clear_supported
)
2038 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
2040 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
2042 assert(ccs_supported
== fast_clear_supported
);
2044 switch (aux_state
) {
2045 case ISL_AUX_STATE_CLEAR
:
2046 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2048 return ISL_AUX_OP_FULL_RESOLVE
;
2050 return ISL_AUX_OP_NONE
;
2052 case ISL_AUX_STATE_PASS_THROUGH
:
2053 return ISL_AUX_OP_NONE
;
2055 case ISL_AUX_STATE_RESOLVED
:
2056 case ISL_AUX_STATE_AUX_INVALID
:
2057 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2058 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2062 unreachable("Invalid aux state for CCS_D");
2065 static enum isl_aux_op
2066 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2067 enum isl_aux_usage aux_usage
,
2068 bool fast_clear_supported
)
2070 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
2071 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2072 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2073 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2075 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
2076 assert(fast_clear_supported
);
2078 switch (aux_state
) {
2079 case ISL_AUX_STATE_CLEAR
:
2080 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2081 if (fast_clear_supported
)
2082 return ISL_AUX_OP_NONE
;
2083 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
2084 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2086 return ISL_AUX_OP_FULL_RESOLVE
;
2088 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2089 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2090 return ISL_AUX_OP_FULL_RESOLVE
;
2091 else if (!fast_clear_supported
)
2092 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2094 return ISL_AUX_OP_NONE
;
2096 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2097 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2098 return ISL_AUX_OP_FULL_RESOLVE
;
2100 return ISL_AUX_OP_NONE
;
2102 case ISL_AUX_STATE_PASS_THROUGH
:
2103 return ISL_AUX_OP_NONE
;
2105 case ISL_AUX_STATE_RESOLVED
:
2106 case ISL_AUX_STATE_AUX_INVALID
:
2110 unreachable("Invalid aux state for CCS_E");
2114 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2115 struct intel_mipmap_tree
*mt
,
2116 uint32_t level
, uint32_t layer
,
2117 enum isl_aux_usage aux_usage
,
2118 bool fast_clear_supported
)
2120 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2122 enum isl_aux_op resolve_op
;
2123 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2124 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2125 fast_clear_supported
);
2127 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2128 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2129 fast_clear_supported
);
2132 if (resolve_op
!= ISL_AUX_OP_NONE
) {
2133 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2134 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2136 switch (resolve_op
) {
2137 case ISL_AUX_OP_FULL_RESOLVE
:
2138 /* The CCS full resolve operation destroys the CCS and sets it to the
2139 * pass-through state. (You can also think of this as being both a
2140 * resolve and an ambiguate in one operation.)
2142 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2143 ISL_AUX_STATE_PASS_THROUGH
);
2146 case ISL_AUX_OP_PARTIAL_RESOLVE
:
2147 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2148 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2152 unreachable("Invalid resolve op");
2158 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2159 struct intel_mipmap_tree
*mt
,
2160 uint32_t level
, uint32_t layer
,
2161 enum isl_aux_usage aux_usage
)
2163 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2164 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2165 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2167 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2169 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2170 switch (aux_state
) {
2171 case ISL_AUX_STATE_CLEAR
:
2172 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2173 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2174 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2176 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2177 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2178 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2179 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2180 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2181 ISL_AUX_STATE_PARTIAL_CLEAR
);
2185 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2186 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2187 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2188 break; /* Nothing to do */
2190 case ISL_AUX_STATE_PASS_THROUGH
:
2191 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2192 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2193 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2199 case ISL_AUX_STATE_RESOLVED
:
2200 case ISL_AUX_STATE_AUX_INVALID
:
2201 unreachable("Invalid aux state for CCS_E");
2204 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2205 /* CCS_D is a bit simpler */
2206 switch (aux_state
) {
2207 case ISL_AUX_STATE_CLEAR
:
2208 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2209 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2210 ISL_AUX_STATE_PARTIAL_CLEAR
);
2213 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2214 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2215 break; /* Nothing to do */
2217 case ISL_AUX_STATE_PASS_THROUGH
:
2221 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2222 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2223 case ISL_AUX_STATE_RESOLVED
:
2224 case ISL_AUX_STATE_AUX_INVALID
:
2225 unreachable("Invalid aux state for CCS_D");
2231 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2232 struct intel_mipmap_tree
*mt
,
2234 enum isl_aux_usage aux_usage
,
2235 bool fast_clear_supported
)
2237 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2239 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2240 case ISL_AUX_STATE_CLEAR
:
2241 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2242 if (!fast_clear_supported
) {
2243 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2244 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2245 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2249 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2250 break; /* Nothing to do */
2252 case ISL_AUX_STATE_RESOLVED
:
2253 case ISL_AUX_STATE_PASS_THROUGH
:
2254 case ISL_AUX_STATE_AUX_INVALID
:
2255 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2256 unreachable("Invalid aux state for MCS");
2261 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2262 struct intel_mipmap_tree
*mt
,
2264 enum isl_aux_usage aux_usage
)
2266 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2268 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2269 case ISL_AUX_STATE_CLEAR
:
2270 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2271 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2274 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2275 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2276 break; /* Nothing to do */
2278 case ISL_AUX_STATE_RESOLVED
:
2279 case ISL_AUX_STATE_PASS_THROUGH
:
2280 case ISL_AUX_STATE_AUX_INVALID
:
2281 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2282 unreachable("Invalid aux state for MCS");
2287 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2288 struct intel_mipmap_tree
*mt
,
2289 uint32_t level
, uint32_t layer
,
2290 enum isl_aux_usage aux_usage
,
2291 bool fast_clear_supported
)
2293 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2295 enum isl_aux_op hiz_op
= ISL_AUX_OP_NONE
;
2296 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2297 case ISL_AUX_STATE_CLEAR
:
2298 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2299 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2300 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2303 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2304 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2305 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2308 case ISL_AUX_STATE_PASS_THROUGH
:
2309 case ISL_AUX_STATE_RESOLVED
:
2312 case ISL_AUX_STATE_AUX_INVALID
:
2313 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2314 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
2317 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2318 unreachable("Invalid HiZ state");
2321 if (hiz_op
!= ISL_AUX_OP_NONE
) {
2322 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2325 case ISL_AUX_OP_FULL_RESOLVE
:
2326 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2327 ISL_AUX_STATE_RESOLVED
);
2330 case ISL_AUX_OP_AMBIGUATE
:
2331 /* The HiZ resolve operation is actually an ambiguate */
2332 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2333 ISL_AUX_STATE_PASS_THROUGH
);
2337 unreachable("Invalid HiZ op");
2343 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2344 struct intel_mipmap_tree
*mt
,
2345 uint32_t level
, uint32_t layer
,
2346 enum isl_aux_usage aux_usage
)
2348 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2350 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2351 case ISL_AUX_STATE_CLEAR
:
2352 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2353 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2354 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2357 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2358 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2359 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2360 break; /* Nothing to do */
2362 case ISL_AUX_STATE_RESOLVED
:
2363 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2364 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2365 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2367 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2368 ISL_AUX_STATE_AUX_INVALID
);
2372 case ISL_AUX_STATE_PASS_THROUGH
:
2373 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2374 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2375 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2379 case ISL_AUX_STATE_AUX_INVALID
:
2380 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2383 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2384 unreachable("Invalid HiZ state");
2389 intel_miptree_prepare_access(struct brw_context
*brw
,
2390 struct intel_mipmap_tree
*mt
,
2391 uint32_t start_level
, uint32_t num_levels
,
2392 uint32_t start_layer
, uint32_t num_layers
,
2393 enum isl_aux_usage aux_usage
,
2394 bool fast_clear_supported
)
2396 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2398 switch (mt
->aux_usage
) {
2399 case ISL_AUX_USAGE_NONE
:
2403 case ISL_AUX_USAGE_MCS
:
2404 assert(mt
->aux_buf
);
2405 assert(start_level
== 0 && num_levels
== 1);
2406 const uint32_t level_layers
=
2407 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2408 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2409 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2410 aux_usage
, fast_clear_supported
);
2414 case ISL_AUX_USAGE_CCS_D
:
2415 case ISL_AUX_USAGE_CCS_E
:
2419 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2420 const uint32_t level
= start_level
+ l
;
2421 const uint32_t level_layers
=
2422 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2423 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2424 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2426 aux_usage
, fast_clear_supported
);
2431 case ISL_AUX_USAGE_HIZ
:
2432 assert(mt
->aux_buf
);
2433 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2434 const uint32_t level
= start_level
+ l
;
2435 if (!intel_miptree_level_has_hiz(mt
, level
))
2438 const uint32_t level_layers
=
2439 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2440 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2441 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2442 aux_usage
, fast_clear_supported
);
2448 unreachable("Invalid aux usage");
2453 intel_miptree_finish_write(struct brw_context
*brw
,
2454 struct intel_mipmap_tree
*mt
, uint32_t level
,
2455 uint32_t start_layer
, uint32_t num_layers
,
2456 enum isl_aux_usage aux_usage
)
2458 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2460 switch (mt
->aux_usage
) {
2461 case ISL_AUX_USAGE_NONE
:
2465 case ISL_AUX_USAGE_MCS
:
2466 assert(mt
->aux_buf
);
2467 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2468 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2473 case ISL_AUX_USAGE_CCS_D
:
2474 case ISL_AUX_USAGE_CCS_E
:
2478 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2479 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2484 case ISL_AUX_USAGE_HIZ
:
2485 if (!intel_miptree_level_has_hiz(mt
, level
))
2488 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2489 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2495 unreachable("Invavlid aux usage");
2500 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2501 uint32_t level
, uint32_t layer
)
2503 intel_miptree_check_level_layer(mt
, level
, layer
);
2505 if (_mesa_is_format_color_format(mt
->format
)) {
2506 assert(mt
->aux_buf
!= NULL
);
2507 assert(mt
->surf
.samples
== 1 ||
2508 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2509 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2510 unreachable("Cannot get aux state for stencil");
2512 assert(intel_miptree_level_has_hiz(mt
, level
));
2515 return mt
->aux_state
[level
][layer
];
2519 intel_miptree_set_aux_state(struct brw_context
*brw
,
2520 struct intel_mipmap_tree
*mt
, uint32_t level
,
2521 uint32_t start_layer
, uint32_t num_layers
,
2522 enum isl_aux_state aux_state
)
2524 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2526 if (_mesa_is_format_color_format(mt
->format
)) {
2527 assert(mt
->aux_buf
!= NULL
);
2528 assert(mt
->surf
.samples
== 1 ||
2529 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2530 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2531 unreachable("Cannot get aux state for stencil");
2533 assert(intel_miptree_level_has_hiz(mt
, level
));
2536 for (unsigned a
= 0; a
< num_layers
; a
++) {
2537 if (mt
->aux_state
[level
][start_layer
+ a
] != aux_state
) {
2538 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2539 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2544 /* On Gen9 color buffers may be compressed by the hardware (lossless
2545 * compression). There are, however, format restrictions and care needs to be
2546 * taken that the sampler engine is capable for re-interpreting a buffer with
2547 * format different the buffer was originally written with.
2549 * For example, SRGB formats are not compressible and the sampler engine isn't
2550 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2551 * color buffer needs to be resolved so that the sampling surface can be
2552 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2556 can_texture_with_ccs(struct brw_context
*brw
,
2557 struct intel_mipmap_tree
*mt
,
2558 enum isl_format view_format
)
2560 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2563 if (!format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2565 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2566 isl_format_get_layout(view_format
)->name
,
2567 _mesa_get_format_name(mt
->format
));
2575 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2576 struct intel_mipmap_tree
*mt
,
2577 enum isl_format view_format
)
2579 switch (mt
->aux_usage
) {
2580 case ISL_AUX_USAGE_HIZ
:
2581 if (intel_miptree_sample_with_hiz(brw
, mt
))
2582 return ISL_AUX_USAGE_HIZ
;
2585 case ISL_AUX_USAGE_MCS
:
2586 return ISL_AUX_USAGE_MCS
;
2588 case ISL_AUX_USAGE_CCS_D
:
2589 case ISL_AUX_USAGE_CCS_E
:
2591 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2592 return ISL_AUX_USAGE_NONE
;
2595 /* If we don't have any unresolved color, report an aux usage of
2596 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
2597 * aux surface and we can save some bandwidth.
2599 if (!intel_miptree_has_color_unresolved(mt
, 0, INTEL_REMAINING_LEVELS
,
2600 0, INTEL_REMAINING_LAYERS
))
2601 return ISL_AUX_USAGE_NONE
;
2603 if (can_texture_with_ccs(brw
, mt
, view_format
))
2604 return ISL_AUX_USAGE_CCS_E
;
2611 return ISL_AUX_USAGE_NONE
;
2615 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2617 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2618 * values so sRGB curve application was a no-op for all fast-clearable
2621 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2622 * values, the hardware interprets the floats, not as what would be
2623 * returned from the sampler (or written by the shader), but as being
2624 * between format conversion and sRGB curve application. This means that
2625 * we can switch between sRGB and UNORM without having to whack the clear
2628 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2632 intel_miptree_prepare_texture(struct brw_context
*brw
,
2633 struct intel_mipmap_tree
*mt
,
2634 enum isl_format view_format
,
2635 uint32_t start_level
, uint32_t num_levels
,
2636 uint32_t start_layer
, uint32_t num_layers
)
2638 enum isl_aux_usage aux_usage
=
2639 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2640 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2642 /* Clear color is specified as ints or floats and the conversion is done by
2643 * the sampler. If we have a texture view, we would have to perform the
2644 * clear color conversion manually. Just disable clear color.
2646 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2647 clear_supported
= false;
2649 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2650 start_layer
, num_layers
,
2651 aux_usage
, clear_supported
);
2655 intel_miptree_prepare_image(struct brw_context
*brw
,
2656 struct intel_mipmap_tree
*mt
)
2658 /* The data port doesn't understand any compression */
2659 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2660 0, INTEL_REMAINING_LAYERS
,
2661 ISL_AUX_USAGE_NONE
, false);
2665 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2666 struct intel_mipmap_tree
*mt
,
2667 enum isl_format render_format
,
2669 bool draw_aux_disabled
)
2671 struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2673 if (draw_aux_disabled
)
2674 return ISL_AUX_USAGE_NONE
;
2676 switch (mt
->aux_usage
) {
2677 case ISL_AUX_USAGE_MCS
:
2678 assert(mt
->aux_buf
);
2679 return ISL_AUX_USAGE_MCS
;
2681 case ISL_AUX_USAGE_CCS_D
:
2682 case ISL_AUX_USAGE_CCS_E
:
2684 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2685 return ISL_AUX_USAGE_NONE
;
2688 /* gen9+ hardware technically supports non-0/1 clear colors with sRGB
2689 * formats. However, there are issues with blending where it doesn't
2690 * properly apply the sRGB curve to the clear color when blending.
2692 if (devinfo
->gen
>= 9 && blend_enabled
&&
2693 isl_format_is_srgb(render_format
) &&
2694 !isl_color_value_is_zero_one(mt
->fast_clear_color
, render_format
))
2695 return ISL_AUX_USAGE_NONE
;
2697 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
&&
2698 format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2700 return ISL_AUX_USAGE_CCS_E
;
2702 /* Otherwise, we have to fall back to CCS_D */
2703 return ISL_AUX_USAGE_CCS_D
;
2706 return ISL_AUX_USAGE_NONE
;
2711 intel_miptree_prepare_render(struct brw_context
*brw
,
2712 struct intel_mipmap_tree
*mt
, uint32_t level
,
2713 uint32_t start_layer
, uint32_t layer_count
,
2714 enum isl_aux_usage aux_usage
)
2716 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2717 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2721 intel_miptree_finish_render(struct brw_context
*brw
,
2722 struct intel_mipmap_tree
*mt
, uint32_t level
,
2723 uint32_t start_layer
, uint32_t layer_count
,
2724 enum isl_aux_usage aux_usage
)
2726 assert(_mesa_is_format_color_format(mt
->format
));
2728 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2733 intel_miptree_prepare_depth(struct brw_context
*brw
,
2734 struct intel_mipmap_tree
*mt
, uint32_t level
,
2735 uint32_t start_layer
, uint32_t layer_count
)
2737 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2738 mt
->aux_usage
, mt
->aux_buf
!= NULL
);
2742 intel_miptree_finish_depth(struct brw_context
*brw
,
2743 struct intel_mipmap_tree
*mt
, uint32_t level
,
2744 uint32_t start_layer
, uint32_t layer_count
,
2747 if (depth_written
) {
2748 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2749 mt
->aux_buf
!= NULL
);
2754 intel_miptree_prepare_external(struct brw_context
*brw
,
2755 struct intel_mipmap_tree
*mt
)
2757 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
2758 bool supports_fast_clear
= false;
2760 const struct isl_drm_modifier_info
*mod_info
=
2761 isl_drm_modifier_get_info(mt
->drm_modifier
);
2763 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
2764 /* CCS_E is the only supported aux for external images and it's only
2765 * supported on very simple images.
2767 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
2768 assert(_mesa_is_format_color_format(mt
->format
));
2769 assert(mt
->first_level
== 0 && mt
->last_level
== 0);
2770 assert(mt
->surf
.logical_level0_px
.depth
== 1);
2771 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
2772 assert(mt
->surf
.samples
== 1);
2773 assert(mt
->aux_buf
!= NULL
);
2775 aux_usage
= mod_info
->aux_usage
;
2776 supports_fast_clear
= mod_info
->supports_clear_color
;
2779 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2780 0, INTEL_REMAINING_LAYERS
,
2781 aux_usage
, supports_fast_clear
);
2785 intel_miptree_finish_external(struct brw_context
*brw
,
2786 struct intel_mipmap_tree
*mt
)
2791 /* We don't know the actual aux state of the aux surface. The previous
2792 * owner could have given it to us in a number of different states.
2793 * Because we don't know the aux state, we reset the aux state to the
2794 * least common denominator of possible valid states.
2796 enum isl_aux_state default_aux_state
=
2797 isl_drm_modifier_get_default_aux_state(mt
->drm_modifier
);
2798 assert(mt
->last_level
== mt
->first_level
);
2799 intel_miptree_set_aux_state(brw
, mt
, 0, 0, INTEL_REMAINING_LAYERS
,
2804 * Make it possible to share the BO backing the given miptree with another
2805 * process or another miptree.
2807 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2808 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2809 * ensure that no MCS buffer gets allocated in the future.
2811 * HiZ is similarly unsafe with shared buffers.
2814 intel_miptree_make_shareable(struct brw_context
*brw
,
2815 struct intel_mipmap_tree
*mt
)
2817 /* MCS buffers are also used for multisample buffers, but we can't resolve
2818 * away a multisample MCS buffer because it's an integral part of how the
2819 * pixel data is stored. Fortunately this code path should never be
2820 * reached for multisample buffers.
2822 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2823 mt
->surf
.samples
== 1);
2825 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2826 0, INTEL_REMAINING_LAYERS
,
2827 ISL_AUX_USAGE_NONE
, false);
2830 intel_miptree_aux_buffer_free(mt
->aux_buf
);
2833 /* Make future calls of intel_miptree_level_has_hiz() return false. */
2834 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2835 mt
->level
[l
].has_hiz
= false;
2838 free(mt
->aux_state
);
2839 mt
->aux_state
= NULL
;
2840 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2843 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2844 mt
->supports_fast_clear
= false;
2849 * \brief Get pointer offset into stencil buffer.
2851 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2852 * must decode the tile's layout in software.
2855 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2857 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2859 * Even though the returned offset is always positive, the return type is
2861 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2862 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2865 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2867 uint32_t tile_size
= 4096;
2868 uint32_t tile_width
= 64;
2869 uint32_t tile_height
= 64;
2870 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2872 uint32_t tile_x
= x
/ tile_width
;
2873 uint32_t tile_y
= y
/ tile_height
;
2875 /* The byte's address relative to the tile's base addres. */
2876 uint32_t byte_x
= x
% tile_width
;
2877 uint32_t byte_y
= y
% tile_height
;
2879 uintptr_t u
= tile_y
* row_size
2880 + tile_x
* tile_size
2881 + 512 * (byte_x
/ 8)
2883 + 32 * ((byte_y
/ 4) % 2)
2884 + 16 * ((byte_x
/ 4) % 2)
2885 + 8 * ((byte_y
/ 2) % 2)
2886 + 4 * ((byte_x
/ 2) % 2)
2891 /* adjust for bit6 swizzling */
2892 if (((byte_x
/ 8) % 2) == 1) {
2893 if (((byte_y
/ 8) % 2) == 0) {
2905 intel_miptree_updownsample(struct brw_context
*brw
,
2906 struct intel_mipmap_tree
*src
,
2907 struct intel_mipmap_tree
*dst
)
2909 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2910 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2911 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2912 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2914 brw_blorp_blit_miptrees(brw
,
2915 src
, 0 /* level */, 0 /* layer */,
2916 src
->format
, SWIZZLE_XYZW
,
2917 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2920 GL_NEAREST
, false, false /*mirror x, y*/,
2923 if (src
->stencil_mt
) {
2924 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2925 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2926 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2927 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2929 brw_blorp_blit_miptrees(brw
,
2930 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2931 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2932 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2933 dst
->stencil_mt
->format
,
2936 GL_NEAREST
, false, false /*mirror x, y*/,
2937 false, false /* decode/encode srgb */);
2942 intel_update_r8stencil(struct brw_context
*brw
,
2943 struct intel_mipmap_tree
*mt
)
2945 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2947 assert(devinfo
->gen
>= 7);
2948 struct intel_mipmap_tree
*src
=
2949 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2950 if (!src
|| devinfo
->gen
>= 8 || !src
->r8stencil_needs_update
)
2953 assert(src
->surf
.size
> 0);
2955 if (!mt
->r8stencil_mt
) {
2956 assert(devinfo
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2957 mt
->r8stencil_mt
= make_surface(
2960 MESA_FORMAT_R_UINT8
,
2961 src
->first_level
, src
->last_level
,
2962 src
->surf
.logical_level0_px
.width
,
2963 src
->surf
.logical_level0_px
.height
,
2964 src
->surf
.dim
== ISL_SURF_DIM_3D
?
2965 src
->surf
.logical_level0_px
.depth
:
2966 src
->surf
.logical_level0_px
.array_len
,
2969 ISL_SURF_USAGE_TEXTURE_BIT
,
2970 BO_ALLOC_BUSY
, 0, NULL
);
2971 assert(mt
->r8stencil_mt
);
2974 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2976 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2977 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
2978 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
2979 src
->surf
.phys_level0_sa
.array_len
;
2981 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2982 brw_blorp_copy_miptrees(brw
,
2986 minify(src
->surf
.logical_level0_px
.width
,
2988 minify(src
->surf
.logical_level0_px
.height
,
2993 brw_cache_flush_for_read(brw
, dst
->bo
);
2994 src
->r8stencil_needs_update
= false;
2998 intel_miptree_map_raw(struct brw_context
*brw
,
2999 struct intel_mipmap_tree
*mt
,
3002 struct brw_bo
*bo
= mt
->bo
;
3004 if (brw_batch_references(&brw
->batch
, bo
))
3005 intel_batchbuffer_flush(brw
);
3007 return brw_bo_map(brw
, bo
, mode
);
3011 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3013 brw_bo_unmap(mt
->bo
);
3017 intel_miptree_unmap_gtt(struct brw_context
*brw
,
3018 struct intel_mipmap_tree
*mt
,
3019 struct intel_miptree_map
*map
,
3020 unsigned int level
, unsigned int slice
)
3022 intel_miptree_unmap_raw(mt
);
3026 intel_miptree_map_gtt(struct brw_context
*brw
,
3027 struct intel_mipmap_tree
*mt
,
3028 struct intel_miptree_map
*map
,
3029 unsigned int level
, unsigned int slice
)
3031 unsigned int bw
, bh
;
3033 unsigned int image_x
, image_y
;
3034 intptr_t x
= map
->x
;
3035 intptr_t y
= map
->y
;
3037 /* For compressed formats, the stride is the number of bytes per
3038 * row of blocks. intel_miptree_get_image_offset() already does
3041 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3042 assert(y
% bh
== 0);
3043 assert(x
% bw
== 0);
3047 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3054 /* Note that in the case of cube maps, the caller must have passed the
3055 * slice number referencing the face.
3057 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3061 map
->stride
= mt
->surf
.row_pitch
;
3062 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3065 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3066 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3067 map
->x
, map
->y
, map
->w
, map
->h
,
3068 mt
, _mesa_get_format_name(mt
->format
),
3069 x
, y
, map
->ptr
, map
->stride
);
3071 map
->unmap
= intel_miptree_unmap_gtt
;
3075 intel_miptree_unmap_blit(struct brw_context
*brw
,
3076 struct intel_mipmap_tree
*mt
,
3077 struct intel_miptree_map
*map
,
3081 struct gl_context
*ctx
= &brw
->ctx
;
3083 intel_miptree_unmap_raw(map
->linear_mt
);
3085 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3086 bool ok
= intel_miptree_copy(brw
,
3087 map
->linear_mt
, 0, 0, 0, 0,
3088 mt
, level
, slice
, map
->x
, map
->y
,
3090 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3093 intel_miptree_release(&map
->linear_mt
);
3097 intel_miptree_map_blit(struct brw_context
*brw
,
3098 struct intel_mipmap_tree
*mt
,
3099 struct intel_miptree_map
*map
,
3100 unsigned int level
, unsigned int slice
)
3102 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3103 /* first_level */ 0,
3107 MIPTREE_CREATE_LINEAR
);
3109 if (!map
->linear_mt
) {
3110 fprintf(stderr
, "Failed to allocate blit temporary\n");
3113 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3115 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3116 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3117 * invalidate is set, since we'll be writing the whole rectangle from our
3118 * temporary buffer back out.
3120 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3121 if (!intel_miptree_copy(brw
,
3122 mt
, level
, slice
, map
->x
, map
->y
,
3123 map
->linear_mt
, 0, 0, 0, 0,
3125 fprintf(stderr
, "Failed to blit\n");
3130 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3132 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3133 map
->x
, map
->y
, map
->w
, map
->h
,
3134 mt
, _mesa_get_format_name(mt
->format
),
3135 level
, slice
, map
->ptr
, map
->stride
);
3137 map
->unmap
= intel_miptree_unmap_blit
;
3141 intel_miptree_release(&map
->linear_mt
);
3147 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3149 #if defined(USE_SSE41)
3151 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3152 struct intel_mipmap_tree
*mt
,
3153 struct intel_miptree_map
*map
,
3157 _mesa_align_free(map
->buffer
);
3163 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3164 struct intel_mipmap_tree
*mt
,
3165 struct intel_miptree_map
*map
,
3166 unsigned int level
, unsigned int slice
)
3168 assert(map
->mode
& GL_MAP_READ_BIT
);
3169 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3171 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3172 map
->x
, map
->y
, map
->w
, map
->h
,
3173 mt
, _mesa_get_format_name(mt
->format
),
3174 level
, slice
, map
->ptr
, map
->stride
);
3176 /* Map the original image */
3179 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3183 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3189 src
+= image_y
* mt
->surf
.row_pitch
;
3190 src
+= image_x
* mt
->cpp
;
3192 /* Due to the pixel offsets for the particular image being mapped, our
3193 * src pointer may not be 16-byte aligned. However, if the pitch is
3194 * divisible by 16, then the amount by which it's misaligned will remain
3195 * consistent from row to row.
3197 assert((mt
->surf
.row_pitch
% 16) == 0);
3198 const int misalignment
= ((uintptr_t) src
) & 15;
3200 /* Create an untiled temporary buffer for the mapping. */
3201 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3203 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3205 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3206 /* Offset the destination so it has the same misalignment as src. */
3207 map
->ptr
= map
->buffer
+ misalignment
;
3209 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3211 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3212 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3213 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3215 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3218 intel_miptree_unmap_raw(mt
);
3220 map
->unmap
= intel_miptree_unmap_movntdqa
;
3225 intel_miptree_unmap_s8(struct brw_context
*brw
,
3226 struct intel_mipmap_tree
*mt
,
3227 struct intel_miptree_map
*map
,
3231 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3232 unsigned int image_x
, image_y
;
3233 uint8_t *untiled_s8_map
= map
->ptr
;
3234 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3236 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3238 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3239 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3240 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3241 image_x
+ x
+ map
->x
,
3242 image_y
+ y
+ map
->y
,
3243 brw
->has_swizzling
);
3244 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3248 intel_miptree_unmap_raw(mt
);
3255 intel_miptree_map_s8(struct brw_context
*brw
,
3256 struct intel_mipmap_tree
*mt
,
3257 struct intel_miptree_map
*map
,
3258 unsigned int level
, unsigned int slice
)
3260 map
->stride
= map
->w
;
3261 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3265 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3266 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3267 * invalidate is set, since we'll be writing the whole rectangle from our
3268 * temporary buffer back out.
3270 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3271 uint8_t *untiled_s8_map
= map
->ptr
;
3272 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3273 unsigned int image_x
, image_y
;
3275 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3277 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3278 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3279 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3280 x
+ image_x
+ map
->x
,
3281 y
+ image_y
+ map
->y
,
3282 brw
->has_swizzling
);
3283 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3287 intel_miptree_unmap_raw(mt
);
3289 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3290 map
->x
, map
->y
, map
->w
, map
->h
,
3291 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3293 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3294 map
->x
, map
->y
, map
->w
, map
->h
,
3295 mt
, map
->ptr
, map
->stride
);
3298 map
->unmap
= intel_miptree_unmap_s8
;
3302 intel_miptree_unmap_etc(struct brw_context
*brw
,
3303 struct intel_mipmap_tree
*mt
,
3304 struct intel_miptree_map
*map
,
3310 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3315 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3316 + image_y
* mt
->surf
.row_pitch
3317 + image_x
* mt
->cpp
;
3319 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3320 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3321 map
->ptr
, map
->stride
,
3324 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3325 map
->ptr
, map
->stride
,
3326 map
->w
, map
->h
, mt
->etc_format
);
3328 intel_miptree_unmap_raw(mt
);
3333 intel_miptree_map_etc(struct brw_context
*brw
,
3334 struct intel_mipmap_tree
*mt
,
3335 struct intel_miptree_map
*map
,
3339 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3340 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3341 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3344 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3345 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3347 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3348 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3349 map
->w
, map
->h
, 1));
3350 map
->ptr
= map
->buffer
;
3351 map
->unmap
= intel_miptree_unmap_etc
;
3355 * Mapping functions for packed depth/stencil miptrees backed by real separate
3356 * miptrees for depth and stencil.
3358 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3359 * separate from the depth buffer. Yet at the GL API level, we have to expose
3360 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3361 * be able to map that memory for texture storage and glReadPixels-type
3362 * operations. We give Mesa core that access by mallocing a temporary and
3363 * copying the data between the actual backing store and the temporary.
3366 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3367 struct intel_mipmap_tree
*mt
,
3368 struct intel_miptree_map
*map
,
3372 struct intel_mipmap_tree
*z_mt
= mt
;
3373 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3374 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3376 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3377 uint32_t *packed_map
= map
->ptr
;
3378 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3379 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3380 unsigned int s_image_x
, s_image_y
;
3381 unsigned int z_image_x
, z_image_y
;
3383 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3384 &s_image_x
, &s_image_y
);
3385 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3386 &z_image_x
, &z_image_y
);
3388 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3389 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3390 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3391 x
+ s_image_x
+ map
->x
,
3392 y
+ s_image_y
+ map
->y
,
3393 brw
->has_swizzling
);
3394 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3395 (z_mt
->surf
.row_pitch
/ 4) +
3396 (x
+ z_image_x
+ map
->x
));
3398 if (map_z32f_x24s8
) {
3399 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3400 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3402 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3403 s_map
[s_offset
] = packed
>> 24;
3404 z_map
[z_offset
] = packed
;
3409 intel_miptree_unmap_raw(s_mt
);
3410 intel_miptree_unmap_raw(z_mt
);
3412 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3414 map
->x
, map
->y
, map
->w
, map
->h
,
3415 z_mt
, _mesa_get_format_name(z_mt
->format
),
3416 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3417 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3418 map
->ptr
, map
->stride
);
3425 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3426 struct intel_mipmap_tree
*mt
,
3427 struct intel_miptree_map
*map
,
3428 unsigned int level
, unsigned int slice
)
3430 struct intel_mipmap_tree
*z_mt
= mt
;
3431 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3432 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3433 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3435 map
->stride
= map
->w
* packed_bpp
;
3436 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3440 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3441 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3442 * invalidate is set, since we'll be writing the whole rectangle from our
3443 * temporary buffer back out.
3445 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3446 uint32_t *packed_map
= map
->ptr
;
3447 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3448 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3449 unsigned int s_image_x
, s_image_y
;
3450 unsigned int z_image_x
, z_image_y
;
3452 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3453 &s_image_x
, &s_image_y
);
3454 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3455 &z_image_x
, &z_image_y
);
3457 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3458 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3459 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3460 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3463 brw
->has_swizzling
);
3464 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3465 (z_mt
->surf
.row_pitch
/ 4) +
3466 (map_x
+ z_image_x
));
3467 uint8_t s
= s_map
[s_offset
];
3468 uint32_t z
= z_map
[z_offset
];
3470 if (map_z32f_x24s8
) {
3471 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3472 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3474 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3479 intel_miptree_unmap_raw(s_mt
);
3480 intel_miptree_unmap_raw(z_mt
);
3482 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3484 map
->x
, map
->y
, map
->w
, map
->h
,
3485 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3486 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3487 map
->ptr
, map
->stride
);
3489 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3490 map
->x
, map
->y
, map
->w
, map
->h
,
3491 mt
, map
->ptr
, map
->stride
);
3494 map
->unmap
= intel_miptree_unmap_depthstencil
;
3498 * Create and attach a map to the miptree at (level, slice). Return the
3501 static struct intel_miptree_map
*
3502 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3511 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3516 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3517 mt
->level
[level
].slice
[slice
].map
= map
;
3529 * Release the map at (level, slice).
3532 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3536 struct intel_miptree_map
**map
;
3538 map
= &mt
->level
[level
].slice
[slice
].map
;
3544 can_blit_slice(struct intel_mipmap_tree
*mt
,
3545 unsigned int level
, unsigned int slice
)
3547 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3548 if (mt
->surf
.row_pitch
>= 32768)
3555 use_intel_mipree_map_blit(struct brw_context
*brw
,
3556 struct intel_mipmap_tree
*mt
,
3561 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3563 if (devinfo
->has_llc
&&
3564 /* It's probably not worth swapping to the blit ring because of
3565 * all the overhead involved.
3567 !(mode
& GL_MAP_WRITE_BIT
) &&
3569 (mt
->surf
.tiling
== ISL_TILING_X
||
3570 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3571 (devinfo
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3572 /* Fast copy blit on skl+ supports all tiling formats. */
3573 devinfo
->gen
>= 9) &&
3574 can_blit_slice(mt
, level
, slice
))
3577 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3578 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3579 assert(can_blit_slice(mt
, level
, slice
));
3587 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3588 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3589 * arithmetic overflow.
3591 * If you call this function and use \a out_stride, then you're doing pointer
3592 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3593 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3594 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3595 * which usually have type uint32_t or GLuint.
3598 intel_miptree_map(struct brw_context
*brw
,
3599 struct intel_mipmap_tree
*mt
,
3608 ptrdiff_t *out_stride
)
3610 struct intel_miptree_map
*map
;
3612 assert(mt
->surf
.samples
== 1);
3614 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3621 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3622 map
->mode
& GL_MAP_WRITE_BIT
);
3624 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3625 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3626 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3627 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3628 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3629 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3630 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3631 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3632 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3633 #if defined(USE_SSE41)
3634 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3635 !mt
->compressed
&& cpu_has_sse4_1
&&
3636 (mt
->surf
.row_pitch
% 16 == 0)) {
3637 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3640 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3643 *out_ptr
= map
->ptr
;
3644 *out_stride
= map
->stride
;
3646 if (map
->ptr
== NULL
)
3647 intel_miptree_release_map(mt
, level
, slice
);
3651 intel_miptree_unmap(struct brw_context
*brw
,
3652 struct intel_mipmap_tree
*mt
,
3656 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3658 assert(mt
->surf
.samples
== 1);
3663 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3664 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3667 map
->unmap(brw
, mt
, map
, level
, slice
);
3669 intel_miptree_release_map(mt
, level
, slice
);
3673 get_isl_surf_dim(GLenum target
)
3677 case GL_TEXTURE_1D_ARRAY
:
3678 return ISL_SURF_DIM_1D
;
3681 case GL_TEXTURE_2D_ARRAY
:
3682 case GL_TEXTURE_RECTANGLE
:
3683 case GL_TEXTURE_CUBE_MAP
:
3684 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3685 case GL_TEXTURE_2D_MULTISAMPLE
:
3686 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3687 case GL_TEXTURE_EXTERNAL_OES
:
3688 return ISL_SURF_DIM_2D
;
3691 return ISL_SURF_DIM_3D
;
3694 unreachable("Invalid texture target");
3698 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3699 enum isl_tiling tiling
, GLenum target
)
3703 case GL_TEXTURE_1D_ARRAY
:
3704 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3705 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3708 case GL_TEXTURE_2D_ARRAY
:
3709 case GL_TEXTURE_RECTANGLE
:
3710 case GL_TEXTURE_2D_MULTISAMPLE
:
3711 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3712 case GL_TEXTURE_EXTERNAL_OES
:
3713 return ISL_DIM_LAYOUT_GEN4_2D
;
3715 case GL_TEXTURE_CUBE_MAP
:
3716 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3717 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3718 ISL_DIM_LAYOUT_GEN4_2D
);
3721 return (devinfo
->gen
>= 9 ?
3722 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3725 unreachable("Invalid texture target");
3729 intel_miptree_set_clear_color(struct brw_context
*brw
,
3730 struct intel_mipmap_tree
*mt
,
3731 union isl_color_value clear_color
)
3733 if (memcmp(&mt
->fast_clear_color
, &clear_color
, sizeof(clear_color
)) != 0) {
3734 mt
->fast_clear_color
= clear_color
;
3735 if (mt
->aux_buf
->clear_color_bo
) {
3736 /* We can't update the clear color while the hardware is still using
3737 * the previous one for a resolve or sampling from it. Make sure that
3738 * there are no pending commands at this point.
3740 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
);
3741 for (int i
= 0; i
< 4; i
++) {
3742 brw_store_data_imm32(brw
, mt
->aux_buf
->clear_color_bo
,
3743 mt
->aux_buf
->clear_color_offset
+ i
* 4,
3744 mt
->fast_clear_color
.u32
[i
]);
3746 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
3748 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
3754 union isl_color_value
3755 intel_miptree_get_clear_color(const struct gen_device_info
*devinfo
,
3756 const struct intel_mipmap_tree
*mt
,
3757 enum isl_format view_format
, bool sampling
,
3758 struct brw_bo
**clear_color_bo
,
3759 uint32_t *clear_color_offset
)
3761 assert(mt
->aux_buf
);
3763 if (devinfo
->gen
== 10 && isl_format_is_srgb(view_format
) && sampling
) {
3764 /* The gen10 sampler doesn't gamma-correct the clear color. In this case,
3765 * we switch to using the inline clear color and do the sRGB color
3766 * conversion process defined in the OpenGL spec. The red, green, and
3767 * blue channels take part in gamma correction, while the alpha channel
3770 union isl_color_value srgb_decoded_value
= mt
->fast_clear_color
;
3771 for (unsigned i
= 0; i
< 3; i
++) {
3772 srgb_decoded_value
.f32
[i
] =
3773 util_format_srgb_to_linear_float(mt
->fast_clear_color
.f32
[i
]);
3775 *clear_color_bo
= 0;
3776 *clear_color_offset
= 0;
3777 return srgb_decoded_value
;
3779 *clear_color_bo
= mt
->aux_buf
->clear_color_bo
;
3780 *clear_color_offset
= mt
->aux_buf
->clear_color_offset
;
3781 return mt
->fast_clear_color
;