2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
28 #include "drm-uapi/drm_fourcc.h"
30 #include "intel_batchbuffer.h"
31 #include "intel_image.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_tex.h"
34 #include "intel_blit.h"
35 #include "intel_fbo.h"
37 #include "brw_blorp.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
49 #include "util/format_srgb.h"
51 #include "x86/common_x86_asm.h"
53 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
55 static void *intel_miptree_map_raw(struct brw_context
*brw
,
56 struct intel_mipmap_tree
*mt
,
59 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
62 intel_miptree_supports_mcs(struct brw_context
*brw
,
63 const struct intel_mipmap_tree
*mt
)
65 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
67 /* MCS compression only applies to multisampled miptrees */
68 if (mt
->surf
.samples
<= 1)
71 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
75 /* See isl_surf_get_mcs_surf for details. */
76 if (mt
->surf
.samples
== 16 && mt
->surf
.logical_level0_px
.width
> 8192)
79 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
80 switch (_mesa_get_format_base_format(mt
->format
)) {
81 case GL_DEPTH_COMPONENT
:
82 case GL_STENCIL_INDEX
:
83 case GL_DEPTH_STENCIL
:
86 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
88 * This field must be set to 0 for all SINT MSRTs when all RT channels
91 * In practice this means that we have to disable MCS for all signed
92 * integer MSAA buffers. The alternative, to disable MCS only when one
93 * of the render target channels is disabled, is impractical because it
94 * would require converting between CMS and UMS MSAA layouts on the fly,
97 if (devinfo
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
106 intel_tiling_supports_ccs(const struct brw_context
*brw
,
107 enum isl_tiling tiling
)
109 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
111 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
112 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
114 * - Support is limited to tiled render targets.
116 * Gen9 changes the restriction to Y-tile only.
118 if (devinfo
->gen
>= 9)
119 return tiling
== ISL_TILING_Y0
;
120 else if (devinfo
->gen
>= 7)
121 return tiling
!= ISL_TILING_LINEAR
;
127 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
128 * can be used. This doesn't (and should not) inspect any of the properties of
131 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
132 * beneath the "Fast Color Clear" bullet (p326):
134 * - Support is for non-mip-mapped and non-array surface types only.
136 * And then later, on p327:
138 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
141 * From the Skylake documentation, it is made clear that X-tiling is no longer
144 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
148 intel_miptree_supports_ccs(struct brw_context
*brw
,
149 const struct intel_mipmap_tree
*mt
)
151 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
153 /* MCS support does not exist prior to Gen7 */
154 if (devinfo
->gen
< 7)
157 /* This function applies only to non-multisampled render targets. */
158 if (mt
->surf
.samples
> 1)
161 /* MCS is only supported for color buffers */
162 if (!_mesa_is_format_color_format(mt
->format
))
165 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
168 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
169 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
170 mt
->surf
.logical_level0_px
.depth
> 1;
173 /* Multisample surfaces with the CMS layout are not layered surfaces,
174 * yet still have physical_depth0 > 1. Assert that we don't
175 * accidentally reject a multisampled surface here. We should have
176 * rejected it earlier by explicitly checking the sample count.
178 assert(mt
->surf
.samples
== 1);
181 /* Handle the hardware restrictions...
183 * All GENs have the following restriction: "MCS buffer for non-MSRT is
184 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
186 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
187 * Non-MultiSampler Render Target Restrictions) Support is for
188 * non-mip-mapped and non-array surface types only.
190 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
191 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
192 * surfaces are supported with MCS buffer layout with these alignments in
193 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
195 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
196 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
197 * surfaces are supported with MCS buffer layout with these alignments in
198 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
200 if (devinfo
->gen
< 8 && (mip_mapped
|| arrayed
))
203 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
204 * work for 3D textures until gen9 where the layout of 3D textures changes
205 * to match 2D array textures.
207 if (devinfo
->gen
<= 8 && mt
->surf
.dim
!= ISL_SURF_DIM_2D
)
210 /* There's no point in using an MCS buffer if the surface isn't in a
213 if (!brw
->mesa_format_supports_render
[mt
->format
])
220 intel_tiling_supports_hiz(const struct brw_context
*brw
,
221 enum isl_tiling tiling
)
223 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
225 if (devinfo
->gen
< 6)
228 return tiling
== ISL_TILING_Y0
;
232 intel_miptree_supports_hiz(const struct brw_context
*brw
,
233 const struct intel_mipmap_tree
*mt
)
238 switch (mt
->format
) {
239 case MESA_FORMAT_Z_FLOAT32
:
240 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
241 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
242 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
243 case MESA_FORMAT_Z_UNORM16
:
251 * Return true if the format that will be used to access the miptree is
252 * CCS_E-compatible with the miptree's linear/non-sRGB format.
254 * Why use the linear format? Well, although the miptree may be specified with
255 * an sRGB format, the usage of that color space/format can be toggled. Since
256 * our HW tends to support more linear formats than sRGB ones, we use this
257 * format variant for check for CCS_E compatibility.
260 format_ccs_e_compat_with_miptree(const struct gen_device_info
*devinfo
,
261 const struct intel_mipmap_tree
*mt
,
262 enum isl_format access_format
)
264 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
266 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
267 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
268 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
272 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
273 const struct intel_mipmap_tree
*mt
)
275 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
277 if (devinfo
->gen
< 9)
280 /* For now compression is only enabled for integer formats even though
281 * there exist supported floating point formats also. This is a heuristic
282 * decision based on current public benchmarks. In none of the cases these
283 * formats provided any improvement but a few cases were seen to regress.
284 * Hence these are left to to be enabled in the future when they are known
287 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
290 if (!intel_miptree_supports_ccs(brw
, mt
))
293 /* Many window system buffers are sRGB even if they are never rendered as
294 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
295 * surface is used as sRGB, we fall back to CCS_D.
297 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
298 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
299 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
303 * Determine depth format corresponding to a depth+stencil format,
304 * for separate stencil.
307 intel_depth_format_for_depthstencil_format(mesa_format format
) {
309 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
310 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
311 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
312 return MESA_FORMAT_Z_FLOAT32
;
319 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
320 unsigned depth0
, struct intel_mipmap_level
*table
)
322 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
324 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
326 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
327 if (!table
[level
].slice
)
334 for (unsigned level
= first_level
; level
<= last_level
; level
++)
335 free(table
[level
].slice
);
341 needs_separate_stencil(const struct brw_context
*brw
,
342 struct intel_mipmap_tree
*mt
,
345 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
347 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
350 if (devinfo
->must_use_separate_stencil
)
353 return brw
->has_separate_stencil
&&
354 intel_miptree_supports_hiz(brw
, mt
);
358 * Choose the aux usage for this miptree. This function must be called fairly
359 * late in the miptree create process after we have a tiling.
362 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
363 struct intel_mipmap_tree
*mt
)
365 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
367 if (intel_miptree_supports_mcs(brw
, mt
)) {
368 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
369 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
370 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
371 intel_miptree_supports_ccs(brw
, mt
)) {
372 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
373 intel_miptree_supports_ccs_e(brw
, mt
)) {
374 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
376 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
378 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
379 intel_miptree_supports_hiz(brw
, mt
)) {
380 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
383 /* We can do fast-clear on all auxiliary surface types that are
384 * allocated through the normal texture creation paths.
386 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
387 mt
->supports_fast_clear
= true;
392 * Choose an appropriate uncompressed format for a requested
393 * compressed format, if unsupported.
396 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
398 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
400 /* No need to lower ETC formats on these platforms,
401 * they are supported natively.
403 if (devinfo
->gen
>= 8 || devinfo
->is_baytrail
)
407 case MESA_FORMAT_ETC1_RGB8
:
408 return MESA_FORMAT_R8G8B8X8_UNORM
;
409 case MESA_FORMAT_ETC2_RGB8
:
410 return MESA_FORMAT_R8G8B8X8_UNORM
;
411 case MESA_FORMAT_ETC2_SRGB8
:
412 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
413 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
414 return MESA_FORMAT_B8G8R8A8_SRGB
;
415 case MESA_FORMAT_ETC2_RGBA8_EAC
:
416 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
417 return MESA_FORMAT_R8G8B8A8_UNORM
;
418 case MESA_FORMAT_ETC2_R11_EAC
:
419 return MESA_FORMAT_R_UNORM16
;
420 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
421 return MESA_FORMAT_R_SNORM16
;
422 case MESA_FORMAT_ETC2_RG11_EAC
:
423 return MESA_FORMAT_R16G16_UNORM
;
424 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
425 return MESA_FORMAT_R16G16_SNORM
;
427 /* Non ETC1 / ETC2 format */
433 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
435 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
436 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
438 return mt
->surf
.logical_level0_px
.array_len
;
441 UNUSED
static unsigned
442 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
444 /* In case of physical dimensions one needs to consider also the layout.
445 * See isl_calc_phys_level0_extent_sa().
447 if (surf
->dim
!= ISL_SURF_DIM_3D
)
448 return surf
->phys_level0_sa
.array_len
;
450 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
451 return minify(surf
->phys_level0_sa
.array_len
, level
);
453 return minify(surf
->phys_level0_sa
.depth
, level
);
456 /** \brief Assert that the level and layer are valid for the miptree. */
458 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
466 assert(level
>= mt
->first_level
);
467 assert(level
<= mt
->last_level
);
468 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
471 static enum isl_aux_state
**
472 create_aux_state_map(struct intel_mipmap_tree
*mt
,
473 enum isl_aux_state initial
)
475 const uint32_t levels
= mt
->last_level
+ 1;
477 uint32_t total_slices
= 0;
478 for (uint32_t level
= 0; level
< levels
; level
++)
479 total_slices
+= brw_get_num_logical_layers(mt
, level
);
481 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
483 /* We're going to allocate a single chunk of data for both the per-level
484 * reference array and the arrays of aux_state. This makes cleanup
485 * significantly easier.
487 const size_t total_size
= per_level_array_size
+
488 total_slices
* sizeof(enum isl_aux_state
);
489 void *data
= malloc(total_size
);
493 enum isl_aux_state
**per_level_arr
= data
;
494 enum isl_aux_state
*s
= data
+ per_level_array_size
;
495 for (uint32_t level
= 0; level
< levels
; level
++) {
496 per_level_arr
[level
] = s
;
497 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
498 for (uint32_t a
= 0; a
< level_layers
; a
++)
501 assert((void *)s
== data
+ total_size
);
503 return per_level_arr
;
507 free_aux_state_map(enum isl_aux_state
**state
)
513 need_to_retile_as_linear(struct brw_context
*brw
, unsigned blt_pitch
,
514 enum isl_tiling tiling
, unsigned samples
)
519 if (tiling
== ISL_TILING_LINEAR
)
522 if (blt_pitch
>= 32768) {
523 perf_debug("blt pitch %u too large to blit, falling back to untiled",
532 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
533 enum isl_tiling tiling
)
535 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
537 /* If the BO is too large to fit in the aperture, we need to use the
538 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
539 * handle Y-tiling, so we need to fall back to X.
541 if (devinfo
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
542 tiling
== ISL_TILING_Y0
)
548 static struct intel_mipmap_tree
*
549 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
550 unsigned first_level
, unsigned last_level
,
551 unsigned width0
, unsigned height0
, unsigned depth0
,
552 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
553 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
554 unsigned row_pitch_B
, struct brw_bo
*bo
)
556 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
560 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
568 if (target
== GL_TEXTURE_CUBE_MAP
||
569 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
570 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
572 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
574 _mesa_enum_to_string(target
),
575 _mesa_get_format_name(format
),
576 num_samples
, width0
, height0
, depth0
,
577 first_level
, last_level
, mt
);
579 struct isl_surf_init_info init_info
= {
580 .dim
= get_isl_surf_dim(target
),
581 .format
= translate_tex_format(brw
, format
, false),
584 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
585 .levels
= last_level
- first_level
+ 1,
586 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
587 .samples
= num_samples
,
588 .row_pitch_B
= row_pitch_B
,
589 .usage
= isl_usage_flags
,
590 .tiling_flags
= tiling_flags
,
593 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
596 /* Depth surfaces are always Y-tiled and stencil is always W-tiled, although
597 * on gen7 platforms we also need to create Y-tiled copies of stencil for
598 * texturing since the hardware can't sample from W-tiled surfaces. For
599 * everything else, check for corner cases needing special treatment.
601 bool is_depth_stencil
=
602 mt
->surf
.usage
& (ISL_SURF_USAGE_STENCIL_BIT
| ISL_SURF_USAGE_DEPTH_BIT
);
603 if (!is_depth_stencil
) {
604 if (need_to_retile_as_linear(brw
, intel_miptree_blt_pitch(mt
),
605 mt
->surf
.tiling
, mt
->surf
.samples
)) {
606 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
607 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
609 } else if (need_to_retile_as_x(brw
, mt
->surf
.size_B
, mt
->surf
.tiling
)) {
610 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
611 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
616 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
617 * the size may not be multiple of row_pitch.
618 * See isl_apply_surface_padding().
620 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
621 assert(mt
->surf
.size_B
% mt
->surf
.row_pitch_B
== 0);
624 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
627 isl_tiling_to_i915_tiling(
629 mt
->surf
.row_pitch_B
, alloc_flags
);
636 mt
->first_level
= first_level
;
637 mt
->last_level
= last_level
;
640 mt
->aux_state
= NULL
;
641 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
642 mt
->compressed
= _mesa_is_format_compressed(format
);
643 mt
->drm_modifier
= DRM_FORMAT_MOD_INVALID
;
648 intel_miptree_release(&mt
);
652 /* Return the usual surface usage flags for the given format. */
653 static isl_surf_usage_flags_t
654 mt_surf_usage(mesa_format format
)
656 switch(_mesa_get_format_base_format(format
)) {
657 case GL_DEPTH_COMPONENT
:
658 return ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
659 case GL_DEPTH_STENCIL
:
660 return ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
661 ISL_SURF_USAGE_TEXTURE_BIT
;
662 case GL_STENCIL_INDEX
:
663 return ISL_SURF_USAGE_STENCIL_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
665 return ISL_SURF_USAGE_RENDER_TARGET_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
669 static struct intel_mipmap_tree
*
670 miptree_create(struct brw_context
*brw
,
679 enum intel_miptree_create_flags flags
)
681 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
682 const uint32_t alloc_flags
=
683 (flags
& MIPTREE_CREATE_BUSY
|| num_samples
> 1) ? BO_ALLOC_BUSY
: 0;
684 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
686 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
687 if (devinfo
->gen
< 6 && _mesa_is_format_color_format(format
))
688 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
690 mesa_format mt_fmt
= format
;
691 if (!_mesa_is_format_color_format(format
) && devinfo
->gen
>= 6) {
692 /* Fix up the Z miptree format for how we're splitting out separate
693 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
695 mt_fmt
= intel_depth_format_for_depthstencil_format(format
);
698 struct intel_mipmap_tree
*mt
=
699 make_surface(brw
, target
, mt_fmt
, first_level
, last_level
,
700 width0
, height0
, depth0
, num_samples
,
701 tiling_flags
, mt_surf_usage(mt_fmt
),
702 alloc_flags
, 0, NULL
);
707 if (intel_miptree_needs_fake_etc(brw
, mt
)) {
708 mesa_format decomp_format
= intel_lower_compressed_format(brw
, format
);
709 mt
->etc_format
= format
;
710 mt
->shadow_mt
= make_surface(brw
, target
, decomp_format
, first_level
,
711 last_level
, width0
, height0
, depth0
,
712 num_samples
, tiling_flags
,
713 mt_surf_usage(decomp_format
),
714 alloc_flags
, 0, NULL
);
716 if (mt
->shadow_mt
== NULL
) {
717 intel_miptree_release(&mt
);
721 mt
->shadow_mt
->etc_format
= MESA_FORMAT_NONE
;
723 mt
->etc_format
= MESA_FORMAT_NONE
;
726 if (needs_separate_stencil(brw
, mt
, format
)) {
728 make_surface(brw
, target
, MESA_FORMAT_S_UINT8
, first_level
, last_level
,
729 width0
, height0
, depth0
, num_samples
,
730 ISL_TILING_W_BIT
, mt_surf_usage(MESA_FORMAT_S_UINT8
),
731 alloc_flags
, 0, NULL
);
732 if (mt
->stencil_mt
== NULL
) {
733 intel_miptree_release(&mt
);
738 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
739 intel_miptree_choose_aux_usage(brw
, mt
);
744 struct intel_mipmap_tree
*
745 intel_miptree_create(struct brw_context
*brw
,
754 enum intel_miptree_create_flags flags
)
756 assert(num_samples
> 0);
758 struct intel_mipmap_tree
*mt
= miptree_create(
760 first_level
, last_level
,
761 width0
, height0
, depth0
, num_samples
,
768 /* Create the auxiliary surface up-front. CCS_D, on the other hand, can only
769 * compress clear color so we wait until an actual fast-clear to allocate
772 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
773 !intel_miptree_alloc_aux(brw
, mt
)) {
774 intel_miptree_release(&mt
);
781 struct intel_mipmap_tree
*
782 intel_miptree_create_for_bo(struct brw_context
*brw
,
790 enum isl_tiling tiling
,
791 enum intel_miptree_create_flags flags
)
793 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
794 struct intel_mipmap_tree
*mt
;
795 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
796 const GLenum base_format
= _mesa_get_format_base_format(format
);
798 if ((base_format
== GL_DEPTH_COMPONENT
||
799 base_format
== GL_DEPTH_STENCIL
)) {
800 const mesa_format mt_fmt
= (devinfo
->gen
< 6) ? format
:
801 intel_depth_format_for_depthstencil_format(format
);
802 mt
= make_surface(brw
, target
, mt_fmt
,
803 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
804 mt_surf_usage(mt_fmt
),
809 brw_bo_reference(bo
);
811 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
812 intel_miptree_choose_aux_usage(brw
, mt
);
815 } else if (format
== MESA_FORMAT_S_UINT8
) {
816 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
817 0, 0, width
, height
, depth
, 1,
819 mt_surf_usage(MESA_FORMAT_S_UINT8
),
824 assert(bo
->size
>= mt
->surf
.size_B
);
826 brw_bo_reference(bo
);
830 /* Nothing will be able to use this miptree with the BO if the offset isn't
833 if (tiling
!= ISL_TILING_LINEAR
)
834 assert(offset
% 4096 == 0);
836 /* miptrees can't handle negative pitch. If you need flipping of images,
837 * that's outside of the scope of the mt.
841 mt
= make_surface(brw
, target
, format
,
842 0, 0, width
, height
, depth
, 1,
844 mt_surf_usage(format
),
849 brw_bo_reference(bo
);
853 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
854 intel_miptree_choose_aux_usage(brw
, mt
);
856 /* Create the auxiliary surface up-front. CCS_D, on the other hand, can
857 * only compress clear color so we wait until an actual fast-clear to
860 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
861 !intel_miptree_alloc_aux(brw
, mt
)) {
862 intel_miptree_release(&mt
);
870 static struct intel_mipmap_tree
*
871 miptree_create_for_planar_image(struct brw_context
*brw
,
872 __DRIimage
*image
, GLenum target
,
873 enum isl_tiling tiling
)
875 const struct intel_image_format
*f
= image
->planar_format
;
876 struct intel_mipmap_tree
*planar_mt
= NULL
;
878 for (int i
= 0; i
< f
->nplanes
; i
++) {
879 const int index
= f
->planes
[i
].buffer_index
;
880 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
881 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
882 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
883 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
885 /* Disable creation of the texture's aux buffers because the driver
886 * exposes no EGL API to manage them. That is, there is no API for
887 * resolving the aux buffer's content to the main buffer nor for
888 * invalidating the aux buffer's content.
890 struct intel_mipmap_tree
*mt
=
891 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
892 image
->offsets
[index
],
894 image
->strides
[index
],
896 MIPTREE_CREATE_NO_AUX
);
898 intel_miptree_release(&planar_mt
);
907 planar_mt
->plane
[i
- 1] = mt
;
910 planar_mt
->drm_modifier
= image
->modifier
;
916 create_ccs_buf_for_image(struct brw_context
*brw
,
918 struct intel_mipmap_tree
*mt
,
919 enum isl_aux_state initial_state
)
921 struct isl_surf temp_ccs_surf
;
923 /* CCS is only supported for very simple miptrees */
924 assert(image
->aux_offset
!= 0 && image
->aux_pitch
!= 0);
925 assert(image
->tile_x
== 0 && image
->tile_y
== 0);
926 assert(mt
->surf
.samples
== 1);
927 assert(mt
->surf
.levels
== 1);
928 assert(mt
->surf
.logical_level0_px
.depth
== 1);
929 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
930 assert(mt
->first_level
== 0);
931 assert(mt
->last_level
== 0);
933 /* We shouldn't already have a CCS */
934 assert(!mt
->aux_buf
);
936 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
,
940 assert(image
->aux_offset
< image
->bo
->size
);
941 assert(temp_ccs_surf
.size_B
<= image
->bo
->size
- image
->aux_offset
);
943 mt
->aux_buf
= calloc(sizeof(*mt
->aux_buf
), 1);
944 if (mt
->aux_buf
== NULL
)
947 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
948 if (!mt
->aux_state
) {
954 /* On gen10+ we start using an extra space in the aux buffer to store the
955 * indirect clear color. However, if we imported an image from the window
956 * system with CCS, we don't have the extra space at the end of the aux
957 * buffer. So create a new bo here that will store that clear color.
959 if (brw
->isl_dev
.ss
.clear_color_state_size
> 0) {
960 mt
->aux_buf
->clear_color_bo
=
961 brw_bo_alloc_tiled(brw
->bufmgr
, "clear_color_bo",
962 brw
->isl_dev
.ss
.clear_color_state_size
,
963 BRW_MEMZONE_OTHER
, I915_TILING_NONE
, 0,
965 if (!mt
->aux_buf
->clear_color_bo
) {
972 mt
->aux_buf
->bo
= image
->bo
;
973 brw_bo_reference(image
->bo
);
975 mt
->aux_buf
->offset
= image
->aux_offset
;
976 mt
->aux_buf
->surf
= temp_ccs_surf
;
981 struct intel_mipmap_tree
*
982 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
983 __DRIimage
*image
, GLenum target
,
985 bool allow_internal_aux
)
987 uint32_t bo_tiling
, bo_swizzle
;
988 brw_bo_get_tiling(image
->bo
, &bo_tiling
, &bo_swizzle
);
990 const struct isl_drm_modifier_info
*mod_info
=
991 isl_drm_modifier_get_info(image
->modifier
);
993 const enum isl_tiling tiling
=
994 mod_info
? mod_info
->tiling
: isl_tiling_from_i915_tiling(bo_tiling
);
996 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1)
997 return miptree_create_for_planar_image(brw
, image
, target
, tiling
);
999 if (image
->planar_format
)
1000 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
1002 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1003 /* The texture storage paths in core Mesa detect if the driver does not
1004 * support the user-requested format, and then searches for a
1005 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1006 * do the fallbacks here for important formats.
1008 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1009 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1010 * the Chrome OS compositor consumes as dma_buf EGLImages.
1012 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1015 if (!brw
->ctx
.TextureFormatSupported
[format
])
1018 enum intel_miptree_create_flags mt_create_flags
= 0;
1020 /* If this image comes in from a window system, we have different
1021 * requirements than if it comes in via an EGL import operation. Window
1022 * system images can use any form of auxiliary compression we wish because
1023 * they get "flushed" before being handed off to the window system and we
1024 * have the opportunity to do resolves. Non window-system images, on the
1025 * other hand, have no resolve point so we can't have aux without a
1028 if (!allow_internal_aux
)
1029 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1031 /* If we have a modifier which specifies aux, don't create one yet */
1032 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
1033 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1035 /* Disable creation of the texture's aux buffers because the driver exposes
1036 * no EGL API to manage them. That is, there is no API for resolving the aux
1037 * buffer's content to the main buffer nor for invalidating the aux buffer's
1040 struct intel_mipmap_tree
*mt
=
1041 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1042 image
->offset
, image
->width
, image
->height
, 1,
1043 image
->pitch
, tiling
, mt_create_flags
);
1047 mt
->target
= target
;
1048 mt
->level
[0].level_x
= image
->tile_x
;
1049 mt
->level
[0].level_y
= image
->tile_y
;
1050 mt
->drm_modifier
= image
->modifier
;
1052 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1053 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1054 * trouble resolving back to destination image due to alignment issues.
1056 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1057 if (!devinfo
->has_surface_tile_offset
) {
1058 uint32_t draw_x
, draw_y
;
1059 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1061 if (draw_x
!= 0 || draw_y
!= 0) {
1062 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1063 intel_miptree_release(&mt
);
1068 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1069 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1071 mt
->aux_usage
= mod_info
->aux_usage
;
1072 /* If we are a window system buffer, then we can support fast-clears
1073 * even if the modifier doesn't support them by doing a partial resolve
1074 * as part of the flush operation.
1076 mt
->supports_fast_clear
=
1077 allow_internal_aux
|| mod_info
->supports_clear_color
;
1079 /* We don't know the actual state of the surface when we get it but we
1080 * can make a pretty good guess based on the modifier. What we do know
1081 * for sure is that it isn't in the AUX_INVALID state, so we just assume
1082 * a worst case of compression.
1084 enum isl_aux_state initial_state
=
1085 isl_drm_modifier_get_default_aux_state(image
->modifier
);
1087 if (!create_ccs_buf_for_image(brw
, image
, mt
, initial_state
)) {
1088 intel_miptree_release(&mt
);
1093 /* Don't assume coherency for imported EGLimages. We don't know what
1094 * external clients are going to do with it. They may scan it out.
1096 image
->bo
->cache_coherent
= false;
1102 * For a singlesample renderbuffer, this simply wraps the given BO with a
1105 * For a multisample renderbuffer, this wraps the window system's
1106 * (singlesample) BO with a singlesample miptree attached to the
1107 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1108 * that will contain the actual rendering (which is lazily resolved to
1109 * irb->singlesample_mt).
1112 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1113 struct intel_renderbuffer
*irb
,
1114 struct intel_mipmap_tree
*singlesample_mt
,
1115 uint32_t width
, uint32_t height
,
1118 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1119 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1120 mesa_format format
= rb
->Format
;
1121 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1123 /* Only the front and back buffers, which are color buffers, are allocated
1124 * through the image loader.
1126 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1127 _mesa_get_format_base_format(format
) == GL_RGBA
);
1129 assert(singlesample_mt
);
1131 if (num_samples
== 1) {
1132 intel_miptree_release(&irb
->mt
);
1133 irb
->mt
= singlesample_mt
;
1135 assert(!irb
->singlesample_mt
);
1137 intel_miptree_release(&irb
->singlesample_mt
);
1138 irb
->singlesample_mt
= singlesample_mt
;
1141 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1142 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1143 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1148 if (!multisample_mt
)
1151 irb
->need_downsample
= false;
1152 intel_miptree_release(&irb
->mt
);
1153 irb
->mt
= multisample_mt
;
1159 intel_miptree_release(&irb
->mt
);
1163 struct intel_mipmap_tree
*
1164 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1168 uint32_t num_samples
)
1170 struct intel_mipmap_tree
*mt
;
1172 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1174 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1175 width
, height
, depth
, num_samples
,
1176 MIPTREE_CREATE_BUSY
);
1183 intel_miptree_release(&mt
);
1188 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1189 struct intel_mipmap_tree
*src
)
1194 intel_miptree_release(dst
);
1198 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1205 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1207 if (aux_buf
== NULL
)
1210 brw_bo_unreference(aux_buf
->bo
);
1211 brw_bo_unreference(aux_buf
->clear_color_bo
);
1217 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1222 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1223 if (--(*mt
)->refcount
<= 0) {
1226 DBG("%s deleting %p\n", __func__
, *mt
);
1228 brw_bo_unreference((*mt
)->bo
);
1229 intel_miptree_release(&(*mt
)->stencil_mt
);
1230 intel_miptree_release(&(*mt
)->shadow_mt
);
1231 intel_miptree_aux_buffer_free((*mt
)->aux_buf
);
1232 free_aux_state_map((*mt
)->aux_state
);
1234 intel_miptree_release(&(*mt
)->plane
[0]);
1235 intel_miptree_release(&(*mt
)->plane
[1]);
1237 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1238 free((*mt
)->level
[i
].slice
);
1248 intel_get_image_dims(struct gl_texture_image
*image
,
1249 int *width
, int *height
, int *depth
)
1251 switch (image
->TexObject
->Target
) {
1252 case GL_TEXTURE_1D_ARRAY
:
1253 /* For a 1D Array texture the OpenGL API will treat the image height as
1254 * the number of array slices. For Intel hardware, we treat the 1D array
1255 * as a 2D Array with a height of 1. So, here we want to swap image
1258 assert(image
->Depth
== 1);
1259 *width
= image
->Width
;
1261 *depth
= image
->Height
;
1263 case GL_TEXTURE_CUBE_MAP
:
1264 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1265 * though we really have 6 slices.
1267 assert(image
->Depth
== 1);
1268 *width
= image
->Width
;
1269 *height
= image
->Height
;
1273 *width
= image
->Width
;
1274 *height
= image
->Height
;
1275 *depth
= image
->Depth
;
1281 * Can the image be pulled into a unified mipmap tree? This mirrors
1282 * the completeness test in a lot of ways.
1284 * Not sure whether I want to pass gl_texture_image here.
1287 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1288 struct gl_texture_image
*image
)
1290 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1291 GLuint level
= intelImage
->base
.Base
.Level
;
1292 int width
, height
, depth
;
1294 /* glTexImage* choose the texture object based on the target passed in, and
1295 * objects can't change targets over their lifetimes, so this should be
1298 assert(image
->TexObject
->Target
== mt
->target
);
1300 mesa_format mt_format
= mt
->format
;
1301 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1302 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1303 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1304 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1305 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1306 mt_format
= mt
->etc_format
;
1308 if (_mesa_get_srgb_format_linear(image
->TexFormat
) !=
1309 _mesa_get_srgb_format_linear(mt_format
))
1312 intel_get_image_dims(image
, &width
, &height
, &depth
);
1314 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1317 if (level
>= mt
->surf
.levels
)
1320 const unsigned level_depth
=
1321 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1322 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1323 mt
->surf
.logical_level0_px
.array_len
;
1325 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1326 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1327 depth
== level_depth
&&
1328 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1332 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1333 GLuint level
, GLuint slice
,
1334 GLuint
*x
, GLuint
*y
)
1336 if (level
== 0 && slice
== 0) {
1337 *x
= mt
->level
[0].level_x
;
1338 *y
= mt
->level
[0].level_y
;
1342 uint32_t x_offset_sa
, y_offset_sa
;
1344 /* Miptree itself can have an offset only if it represents a single
1345 * slice in an imported buffer object.
1346 * See intel_miptree_create_for_dri_image().
1348 assert(mt
->level
[0].level_x
== 0);
1349 assert(mt
->level
[0].level_y
== 0);
1351 /* Given level is relative to level zero while the miptree may be
1352 * represent just a subset of all levels starting from 'first_level'.
1354 assert(level
>= mt
->first_level
);
1355 level
-= mt
->first_level
;
1357 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1358 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1359 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1360 &x_offset_sa
, &y_offset_sa
);
1368 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1369 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1370 * and tile_h is set to 1.
1373 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1374 uint32_t *tile_w
, uint32_t *tile_h
)
1385 case ISL_TILING_LINEAR
:
1390 unreachable("not reached");
1396 * This function computes masks that may be used to select the bits of the X
1397 * and Y coordinates that indicate the offset within a tile. If the BO is
1398 * untiled, the masks are set to 0.
1401 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1402 uint32_t *mask_x
, uint32_t *mask_y
)
1404 uint32_t tile_w_bytes
, tile_h
;
1406 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1408 *mask_x
= tile_w_bytes
/ cpp
- 1;
1409 *mask_y
= tile_h
- 1;
1413 * Compute the offset (in bytes) from the start of the BO to the given x
1414 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1415 * multiples of the tile size.
1418 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1419 uint32_t x
, uint32_t y
)
1422 uint32_t pitch
= mt
->surf
.row_pitch_B
;
1424 switch (mt
->surf
.tiling
) {
1426 unreachable("not reached");
1427 case ISL_TILING_LINEAR
:
1428 return y
* pitch
+ x
* cpp
;
1430 assert((x
% (512 / cpp
)) == 0);
1431 assert((y
% 8) == 0);
1432 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1434 assert((x
% (128 / cpp
)) == 0);
1435 assert((y
% 32) == 0);
1436 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1441 * Rendering with tiled buffers requires that the base address of the buffer
1442 * be aligned to a page boundary. For renderbuffers, and sometimes with
1443 * textures, we may want the surface to point at a texture image level that
1444 * isn't at a page boundary.
1446 * This function returns an appropriately-aligned base offset
1447 * according to the tiling restrictions, plus any required x/y offset
1451 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1452 GLuint level
, GLuint slice
,
1457 uint32_t mask_x
, mask_y
;
1459 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1460 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1462 *tile_x
= x
& mask_x
;
1463 *tile_y
= y
& mask_y
;
1465 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1469 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1470 struct intel_mipmap_tree
*src_mt
,
1471 unsigned src_level
, unsigned src_layer
,
1472 struct intel_mipmap_tree
*dst_mt
,
1473 unsigned dst_level
, unsigned dst_layer
,
1474 unsigned width
, unsigned height
)
1477 ptrdiff_t src_stride
, dst_stride
;
1478 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1480 intel_miptree_map(brw
, src_mt
,
1481 src_level
, src_layer
,
1484 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1487 intel_miptree_map(brw
, dst_mt
,
1488 dst_level
, dst_layer
,
1491 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1495 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1496 _mesa_get_format_name(src_mt
->format
),
1497 src_mt
, src
, src_stride
,
1498 _mesa_get_format_name(dst_mt
->format
),
1499 dst_mt
, dst
, dst_stride
,
1502 int row_size
= cpp
* width
;
1503 if (src_stride
== row_size
&&
1504 dst_stride
== row_size
) {
1505 memcpy(dst
, src
, row_size
* height
);
1507 for (int i
= 0; i
< height
; i
++) {
1508 memcpy(dst
, src
, row_size
);
1514 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1515 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1517 /* Don't forget to copy the stencil data over, too. We could have skipped
1518 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1519 * shuffling the two data sources in/out of temporary storage instead of
1520 * the direct mapping we get this way.
1522 if (dst_mt
->stencil_mt
) {
1523 assert(src_mt
->stencil_mt
);
1524 intel_miptree_copy_slice_sw(brw
,
1525 src_mt
->stencil_mt
, src_level
, src_layer
,
1526 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1532 intel_miptree_copy_slice(struct brw_context
*brw
,
1533 struct intel_mipmap_tree
*src_mt
,
1534 unsigned src_level
, unsigned src_layer
,
1535 struct intel_mipmap_tree
*dst_mt
,
1536 unsigned dst_level
, unsigned dst_layer
)
1539 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1540 mesa_format format
= src_mt
->format
;
1541 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1542 src_level
- src_mt
->first_level
);
1543 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1544 src_level
- src_mt
->first_level
);
1546 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1547 src_level
- src_mt
->first_level
));
1549 assert(_mesa_get_srgb_format_linear(src_mt
->format
) ==
1550 _mesa_get_srgb_format_linear(dst_mt
->format
));
1552 DBG("validate blit mt %s %p %d,%d -> mt %s %p %d,%d (%dx%d)\n",
1553 _mesa_get_format_name(src_mt
->format
),
1554 src_mt
, src_level
, src_layer
,
1555 _mesa_get_format_name(dst_mt
->format
),
1556 dst_mt
, dst_level
, dst_layer
,
1559 if (devinfo
->gen
>= 6) {
1560 /* On gen6 and above, we just use blorp. It's faster than the blitter
1561 * and can handle everything without software fallbacks.
1563 brw_blorp_copy_miptrees(brw
,
1564 src_mt
, src_level
, src_layer
,
1565 dst_mt
, dst_level
, dst_layer
,
1566 0, 0, 0, 0, width
, height
);
1568 if (src_mt
->stencil_mt
) {
1569 assert(dst_mt
->stencil_mt
);
1570 brw_blorp_copy_miptrees(brw
,
1571 src_mt
->stencil_mt
, src_level
, src_layer
,
1572 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1573 0, 0, 0, 0, width
, height
);
1578 if (dst_mt
->compressed
) {
1580 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1581 height
= ALIGN_NPOT(height
, j
) / j
;
1582 width
= ALIGN_NPOT(width
, i
) / i
;
1585 /* Gen4-5 doesn't support separate stencil */
1586 assert(!src_mt
->stencil_mt
);
1588 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1589 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1591 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1594 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1595 _mesa_get_format_name(src_mt
->format
),
1596 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch_B
,
1597 _mesa_get_format_name(dst_mt
->format
),
1598 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch_B
,
1601 if (!intel_miptree_blit(brw
,
1602 src_mt
, src_level
, src_layer
, 0, 0, false,
1603 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1604 width
, height
, COLOR_LOGICOP_COPY
)) {
1605 perf_debug("miptree validate blit for %s failed\n",
1606 _mesa_get_format_name(format
));
1608 intel_miptree_copy_slice_sw(brw
,
1609 src_mt
, src_level
, src_layer
,
1610 dst_mt
, dst_level
, dst_layer
,
1616 * Copies the image's current data to the given miptree, and associates that
1617 * miptree with the image.
1620 intel_miptree_copy_teximage(struct brw_context
*brw
,
1621 struct intel_texture_image
*intelImage
,
1622 struct intel_mipmap_tree
*dst_mt
)
1624 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1625 struct intel_texture_object
*intel_obj
=
1626 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1627 int level
= intelImage
->base
.Base
.Level
;
1628 const unsigned face
= intelImage
->base
.Base
.Face
;
1629 unsigned start_layer
, end_layer
;
1631 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1633 assert(intelImage
->base
.Base
.Height
);
1635 end_layer
= intelImage
->base
.Base
.Height
- 1;
1636 } else if (face
> 0) {
1640 assert(intelImage
->base
.Base
.Depth
);
1642 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1645 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1646 intel_miptree_copy_slice(brw
,
1651 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1652 intel_obj
->needs_validate
= true;
1655 static struct intel_miptree_aux_buffer
*
1656 intel_alloc_aux_buffer(struct brw_context
*brw
,
1657 const struct isl_surf
*aux_surf
,
1659 uint8_t memset_value
)
1661 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1665 uint64_t size
= aux_surf
->size_B
;
1667 const bool has_indirect_clear
= brw
->isl_dev
.ss
.clear_color_state_size
> 0;
1668 if (has_indirect_clear
) {
1669 /* On CNL+, instead of setting the clear color in the SURFACE_STATE, we
1670 * will set a pointer to a dword somewhere that contains the color. So,
1671 * allocate the space for the clear color value here on the aux buffer.
1673 buf
->clear_color_offset
= size
;
1674 size
+= brw
->isl_dev
.ss
.clear_color_state_size
;
1677 /* If the buffer needs to be initialised (requiring the buffer to be
1678 * immediately mapped to cpu space for writing), do not use the gpu access
1679 * flag which can cause an unnecessary delay if the backing pages happened
1680 * to be just used by the GPU.
1682 const bool alloc_zeroed
= wants_memset
&& memset_value
== 0;
1683 const bool needs_memset
=
1684 !alloc_zeroed
&& (wants_memset
|| has_indirect_clear
);
1685 const uint32_t alloc_flags
=
1686 alloc_zeroed
? BO_ALLOC_ZEROED
: (needs_memset
? 0 : BO_ALLOC_BUSY
);
1688 /* ISL has stricter set of alignment rules then the drm allocator.
1689 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1690 * trying to recalculate based on different format block sizes.
1692 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "aux-miptree", size
,
1693 BRW_MEMZONE_OTHER
, I915_TILING_Y
,
1694 aux_surf
->row_pitch_B
, alloc_flags
);
1700 /* Initialize the bo to the desired value */
1702 assert(!(alloc_flags
& BO_ALLOC_BUSY
));
1704 void *map
= brw_bo_map(brw
, buf
->bo
, MAP_WRITE
| MAP_RAW
);
1706 intel_miptree_aux_buffer_free(buf
);
1710 /* Memset the aux_surf portion of the BO. */
1712 memset(map
, memset_value
, aux_surf
->size_B
);
1714 /* Zero the indirect clear color to match ::fast_clear_color. */
1715 if (has_indirect_clear
) {
1716 memset((char *)map
+ buf
->clear_color_offset
, 0,
1717 brw
->isl_dev
.ss
.clear_color_state_size
);
1720 brw_bo_unmap(buf
->bo
);
1723 if (has_indirect_clear
) {
1724 buf
->clear_color_bo
= buf
->bo
;
1725 brw_bo_reference(buf
->clear_color_bo
);
1728 buf
->surf
= *aux_surf
;
1735 * Helper for intel_miptree_alloc_aux() that sets
1736 * \c mt->level[level].has_hiz. Return true if and only if
1737 * \c has_hiz was set.
1740 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1741 struct intel_mipmap_tree
*mt
,
1744 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1746 assert(mt
->aux_buf
);
1747 assert(mt
->surf
.size_B
> 0);
1749 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
1750 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1751 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1753 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1754 * and the height is 4 aligned. This allows our HiZ support
1755 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1756 * we can grow the width & height to allow the HiZ op to
1757 * force the proper size alignments.
1759 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1760 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1765 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1766 mt
->level
[level
].has_hiz
= true;
1772 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1774 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1775 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1776 * compress clear color so we wait until an actual fast-clear to allocate it.
1779 intel_miptree_alloc_aux(struct brw_context
*brw
,
1780 struct intel_mipmap_tree
*mt
)
1782 assert(mt
->aux_buf
== NULL
);
1784 /* Get the aux buf allocation parameters for this miptree. */
1785 enum isl_aux_state initial_state
;
1786 uint8_t memset_value
;
1787 struct isl_surf aux_surf
;
1788 MAYBE_UNUSED
bool aux_surf_ok
= false;
1790 switch (mt
->aux_usage
) {
1791 case ISL_AUX_USAGE_NONE
:
1792 aux_surf
.size_B
= 0;
1795 case ISL_AUX_USAGE_HIZ
:
1796 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
1798 aux_surf_ok
= isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &aux_surf
);
1800 case ISL_AUX_USAGE_MCS
:
1801 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1803 * When MCS buffer is enabled and bound to MSRT, it is required that
1804 * it is cleared prior to any rendering.
1806 * Since we don't use the MCS buffer for any purpose other than
1807 * rendering, it makes sense to just clear it immediately upon
1810 * Note: the clear value for MCS buffers is all 1's, so we memset to
1813 initial_state
= ISL_AUX_STATE_CLEAR
;
1814 memset_value
= 0xFF;
1815 aux_surf_ok
= isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &aux_surf
);
1817 case ISL_AUX_USAGE_CCS_D
:
1818 case ISL_AUX_USAGE_CCS_E
:
1819 /* When CCS_E is used, we need to ensure that the CCS starts off in a
1820 * valid state. From the Sky Lake PRM, "MCS Buffer for Render
1823 * "If Software wants to enable Color Compression without Fast
1824 * clear, Software needs to initialize MCS with zeros."
1826 * A CCS value of 0 indicates that the corresponding block is in the
1827 * pass-through state which is what we want.
1829 * For CCS_D, do the same thing. On gen9+, this avoids having any
1830 * undefined bits in the aux buffer.
1832 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
1835 isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &aux_surf
, 0);
1839 /* We should have a valid aux_surf. */
1840 assert(aux_surf_ok
);
1842 /* No work is needed for a zero-sized auxiliary buffer. */
1843 if (aux_surf
.size_B
== 0)
1846 /* Create the aux_state for the auxiliary buffer. */
1847 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
1848 if (mt
->aux_state
== NULL
)
1851 /* Allocate the auxiliary buffer. */
1852 const bool needs_memset
= initial_state
!= ISL_AUX_STATE_AUX_INVALID
;
1853 mt
->aux_buf
= intel_alloc_aux_buffer(brw
, &aux_surf
, needs_memset
,
1855 if (mt
->aux_buf
== NULL
) {
1856 free_aux_state_map(mt
->aux_state
);
1857 mt
->aux_state
= NULL
;
1861 /* Perform aux_usage-specific initialization. */
1862 if (mt
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
1863 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1864 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1872 * Can the miptree sample using the hiz buffer?
1875 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1876 struct intel_mipmap_tree
*mt
)
1878 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1880 if (!devinfo
->has_sample_with_hiz
) {
1888 /* It seems the hardware won't fallback to the depth buffer if some of the
1889 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1890 * of the texture to be HiZ enabled.
1892 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1893 if (!intel_miptree_level_has_hiz(mt
, level
))
1897 /* If compressed multisampling is enabled, then we use it for the auxiliary
1900 * From the BDW PRM (Volume 2d: Command Reference: Structures
1901 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1903 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1904 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1906 * There is no such blurb for 1D textures, but there is sufficient evidence
1907 * that this is broken on SKL+.
1909 return (mt
->surf
.samples
== 1 &&
1910 mt
->target
!= GL_TEXTURE_3D
&&
1911 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1915 * Does the miptree slice have hiz enabled?
1918 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1920 intel_miptree_check_level_layer(mt
, level
, 0);
1921 return mt
->level
[level
].has_hiz
;
1924 static inline uint32_t
1925 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1926 uint32_t start_level
, uint32_t num_levels
)
1928 assert(start_level
>= mt
->first_level
);
1929 assert(start_level
<= mt
->last_level
);
1931 if (num_levels
== INTEL_REMAINING_LAYERS
)
1932 num_levels
= mt
->last_level
- start_level
+ 1;
1933 /* Check for overflow */
1934 assert(start_level
+ num_levels
>= start_level
);
1935 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
1940 static inline uint32_t
1941 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
1942 uint32_t start_layer
, uint32_t num_layers
)
1944 assert(level
<= mt
->last_level
);
1946 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
1947 assert(start_layer
< total_num_layers
);
1948 if (num_layers
== INTEL_REMAINING_LAYERS
)
1949 num_layers
= total_num_layers
- start_layer
;
1950 /* Check for overflow */
1951 assert(start_layer
+ num_layers
>= start_layer
);
1952 assert(start_layer
+ num_layers
<= total_num_layers
);
1958 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1959 unsigned start_level
, unsigned num_levels
,
1960 unsigned start_layer
, unsigned num_layers
)
1962 assert(_mesa_is_format_color_format(mt
->format
));
1967 /* Clamp the level range to fit the miptree */
1968 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
1970 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1971 const uint32_t level
= start_level
+ l
;
1972 const uint32_t level_layers
=
1973 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
1974 for (unsigned a
= 0; a
< level_layers
; a
++) {
1975 enum isl_aux_state aux_state
=
1976 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
1977 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
1978 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
1987 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
1988 const struct intel_mipmap_tree
*mt
,
1989 unsigned level
, unsigned layer
)
1994 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
1995 assert(brw
->screen
->devinfo
.gen
>= 8 ||
1996 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
1998 /* Compression of arrayed msaa surfaces is supported. */
1999 if (mt
->surf
.samples
> 1)
2002 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2003 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2005 mt
->surf
.logical_level0_px
.depth
== 1 &&
2006 mt
->surf
.logical_level0_px
.array_len
== 1));
2012 static enum isl_aux_op
2013 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2014 enum isl_aux_usage aux_usage
,
2015 bool fast_clear_supported
)
2017 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
2019 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
2021 assert(ccs_supported
== fast_clear_supported
);
2023 switch (aux_state
) {
2024 case ISL_AUX_STATE_CLEAR
:
2025 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2027 return ISL_AUX_OP_FULL_RESOLVE
;
2029 return ISL_AUX_OP_NONE
;
2031 case ISL_AUX_STATE_PASS_THROUGH
:
2032 return ISL_AUX_OP_NONE
;
2034 case ISL_AUX_STATE_RESOLVED
:
2035 case ISL_AUX_STATE_AUX_INVALID
:
2036 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2037 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2041 unreachable("Invalid aux state for CCS_D");
2044 static enum isl_aux_op
2045 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2046 enum isl_aux_usage aux_usage
,
2047 bool fast_clear_supported
)
2049 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
2050 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2051 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2052 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2054 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
2055 assert(fast_clear_supported
);
2057 switch (aux_state
) {
2058 case ISL_AUX_STATE_CLEAR
:
2059 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2060 if (fast_clear_supported
)
2061 return ISL_AUX_OP_NONE
;
2062 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
2063 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2065 return ISL_AUX_OP_FULL_RESOLVE
;
2067 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2068 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2069 return ISL_AUX_OP_FULL_RESOLVE
;
2070 else if (!fast_clear_supported
)
2071 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2073 return ISL_AUX_OP_NONE
;
2075 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2076 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2077 return ISL_AUX_OP_FULL_RESOLVE
;
2079 return ISL_AUX_OP_NONE
;
2081 case ISL_AUX_STATE_PASS_THROUGH
:
2082 return ISL_AUX_OP_NONE
;
2084 case ISL_AUX_STATE_RESOLVED
:
2085 case ISL_AUX_STATE_AUX_INVALID
:
2089 unreachable("Invalid aux state for CCS_E");
2093 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2094 struct intel_mipmap_tree
*mt
,
2095 uint32_t level
, uint32_t layer
,
2096 enum isl_aux_usage aux_usage
,
2097 bool fast_clear_supported
)
2099 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2101 enum isl_aux_op resolve_op
;
2102 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2103 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2104 fast_clear_supported
);
2106 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2107 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2108 fast_clear_supported
);
2111 if (resolve_op
!= ISL_AUX_OP_NONE
) {
2112 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2113 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2115 switch (resolve_op
) {
2116 case ISL_AUX_OP_FULL_RESOLVE
:
2117 /* The CCS full resolve operation destroys the CCS and sets it to the
2118 * pass-through state. (You can also think of this as being both a
2119 * resolve and an ambiguate in one operation.)
2121 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2122 ISL_AUX_STATE_PASS_THROUGH
);
2125 case ISL_AUX_OP_PARTIAL_RESOLVE
:
2126 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2127 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2131 unreachable("Invalid resolve op");
2137 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2138 struct intel_mipmap_tree
*mt
,
2139 uint32_t level
, uint32_t layer
,
2140 enum isl_aux_usage aux_usage
)
2142 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2143 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2144 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2146 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2148 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2149 switch (aux_state
) {
2150 case ISL_AUX_STATE_CLEAR
:
2151 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2152 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2153 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2155 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2156 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2157 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2158 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2159 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2160 ISL_AUX_STATE_PARTIAL_CLEAR
);
2164 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2165 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2166 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2167 break; /* Nothing to do */
2169 case ISL_AUX_STATE_PASS_THROUGH
:
2170 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2171 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2172 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2178 case ISL_AUX_STATE_RESOLVED
:
2179 case ISL_AUX_STATE_AUX_INVALID
:
2180 unreachable("Invalid aux state for CCS_E");
2183 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2184 /* CCS_D is a bit simpler */
2185 switch (aux_state
) {
2186 case ISL_AUX_STATE_CLEAR
:
2187 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2188 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2189 ISL_AUX_STATE_PARTIAL_CLEAR
);
2192 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2193 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2194 break; /* Nothing to do */
2196 case ISL_AUX_STATE_PASS_THROUGH
:
2200 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2201 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2202 case ISL_AUX_STATE_RESOLVED
:
2203 case ISL_AUX_STATE_AUX_INVALID
:
2204 unreachable("Invalid aux state for CCS_D");
2210 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2211 struct intel_mipmap_tree
*mt
,
2213 enum isl_aux_usage aux_usage
,
2214 bool fast_clear_supported
)
2216 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2218 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2219 case ISL_AUX_STATE_CLEAR
:
2220 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2221 if (!fast_clear_supported
) {
2222 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2223 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2224 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2228 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2229 break; /* Nothing to do */
2231 case ISL_AUX_STATE_RESOLVED
:
2232 case ISL_AUX_STATE_PASS_THROUGH
:
2233 case ISL_AUX_STATE_AUX_INVALID
:
2234 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2235 unreachable("Invalid aux state for MCS");
2240 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2241 struct intel_mipmap_tree
*mt
,
2243 enum isl_aux_usage aux_usage
)
2245 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2247 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2248 case ISL_AUX_STATE_CLEAR
:
2249 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2250 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2253 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2254 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2255 break; /* Nothing to do */
2257 case ISL_AUX_STATE_RESOLVED
:
2258 case ISL_AUX_STATE_PASS_THROUGH
:
2259 case ISL_AUX_STATE_AUX_INVALID
:
2260 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2261 unreachable("Invalid aux state for MCS");
2266 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2267 struct intel_mipmap_tree
*mt
,
2268 uint32_t level
, uint32_t layer
,
2269 enum isl_aux_usage aux_usage
,
2270 bool fast_clear_supported
)
2272 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2274 enum isl_aux_op hiz_op
= ISL_AUX_OP_NONE
;
2275 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2276 case ISL_AUX_STATE_CLEAR
:
2277 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2278 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2279 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2282 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2283 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2284 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2287 case ISL_AUX_STATE_PASS_THROUGH
:
2288 case ISL_AUX_STATE_RESOLVED
:
2291 case ISL_AUX_STATE_AUX_INVALID
:
2292 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2293 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
2296 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2297 unreachable("Invalid HiZ state");
2300 if (hiz_op
!= ISL_AUX_OP_NONE
) {
2301 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2304 case ISL_AUX_OP_FULL_RESOLVE
:
2305 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2306 ISL_AUX_STATE_RESOLVED
);
2309 case ISL_AUX_OP_AMBIGUATE
:
2310 /* The HiZ resolve operation is actually an ambiguate */
2311 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2312 ISL_AUX_STATE_PASS_THROUGH
);
2316 unreachable("Invalid HiZ op");
2322 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2323 struct intel_mipmap_tree
*mt
,
2324 uint32_t level
, uint32_t layer
,
2325 enum isl_aux_usage aux_usage
)
2327 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2329 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2330 case ISL_AUX_STATE_CLEAR
:
2331 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2332 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2333 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2336 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2337 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2338 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2339 break; /* Nothing to do */
2341 case ISL_AUX_STATE_RESOLVED
:
2342 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2343 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2344 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2346 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2347 ISL_AUX_STATE_AUX_INVALID
);
2351 case ISL_AUX_STATE_PASS_THROUGH
:
2352 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2353 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2354 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2358 case ISL_AUX_STATE_AUX_INVALID
:
2359 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2362 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2363 unreachable("Invalid HiZ state");
2368 intel_miptree_prepare_access(struct brw_context
*brw
,
2369 struct intel_mipmap_tree
*mt
,
2370 uint32_t start_level
, uint32_t num_levels
,
2371 uint32_t start_layer
, uint32_t num_layers
,
2372 enum isl_aux_usage aux_usage
,
2373 bool fast_clear_supported
)
2375 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2377 switch (mt
->aux_usage
) {
2378 case ISL_AUX_USAGE_NONE
:
2382 case ISL_AUX_USAGE_MCS
:
2383 assert(mt
->aux_buf
);
2384 assert(start_level
== 0 && num_levels
== 1);
2385 const uint32_t level_layers
=
2386 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2387 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2388 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2389 aux_usage
, fast_clear_supported
);
2393 case ISL_AUX_USAGE_CCS_D
:
2394 case ISL_AUX_USAGE_CCS_E
:
2398 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2399 const uint32_t level
= start_level
+ l
;
2400 const uint32_t level_layers
=
2401 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2402 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2403 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2405 aux_usage
, fast_clear_supported
);
2410 case ISL_AUX_USAGE_HIZ
:
2411 assert(mt
->aux_buf
);
2412 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2413 const uint32_t level
= start_level
+ l
;
2414 if (!intel_miptree_level_has_hiz(mt
, level
))
2417 const uint32_t level_layers
=
2418 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2419 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2420 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2421 aux_usage
, fast_clear_supported
);
2427 unreachable("Invalid aux usage");
2432 intel_miptree_finish_write(struct brw_context
*brw
,
2433 struct intel_mipmap_tree
*mt
, uint32_t level
,
2434 uint32_t start_layer
, uint32_t num_layers
,
2435 enum isl_aux_usage aux_usage
)
2437 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2438 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2440 switch (mt
->aux_usage
) {
2441 case ISL_AUX_USAGE_NONE
:
2442 if (mt
->format
== MESA_FORMAT_S_UINT8
&& devinfo
->gen
<= 7) {
2443 mt
->shadow_needs_update
= true;
2444 } else if (intel_miptree_has_etc_shadow(brw
, mt
)) {
2445 mt
->shadow_needs_update
= true;
2449 case ISL_AUX_USAGE_MCS
:
2450 assert(mt
->aux_buf
);
2451 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2452 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2457 case ISL_AUX_USAGE_CCS_D
:
2458 case ISL_AUX_USAGE_CCS_E
:
2462 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2463 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2468 case ISL_AUX_USAGE_HIZ
:
2469 if (!intel_miptree_level_has_hiz(mt
, level
))
2472 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2473 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2479 unreachable("Invavlid aux usage");
2484 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2485 uint32_t level
, uint32_t layer
)
2487 intel_miptree_check_level_layer(mt
, level
, layer
);
2489 if (_mesa_is_format_color_format(mt
->format
)) {
2490 assert(mt
->aux_buf
!= NULL
);
2491 assert(mt
->surf
.samples
== 1 ||
2492 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2493 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2494 unreachable("Cannot get aux state for stencil");
2496 assert(intel_miptree_level_has_hiz(mt
, level
));
2499 return mt
->aux_state
[level
][layer
];
2503 intel_miptree_set_aux_state(struct brw_context
*brw
,
2504 struct intel_mipmap_tree
*mt
, uint32_t level
,
2505 uint32_t start_layer
, uint32_t num_layers
,
2506 enum isl_aux_state aux_state
)
2508 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2510 if (_mesa_is_format_color_format(mt
->format
)) {
2511 assert(mt
->aux_buf
!= NULL
);
2512 assert(mt
->surf
.samples
== 1 ||
2513 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2514 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2515 unreachable("Cannot get aux state for stencil");
2517 assert(intel_miptree_level_has_hiz(mt
, level
));
2520 for (unsigned a
= 0; a
< num_layers
; a
++) {
2521 if (mt
->aux_state
[level
][start_layer
+ a
] != aux_state
) {
2522 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2523 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2528 /* On Gen9 color buffers may be compressed by the hardware (lossless
2529 * compression). There are, however, format restrictions and care needs to be
2530 * taken that the sampler engine is capable for re-interpreting a buffer with
2531 * format different the buffer was originally written with.
2533 * For example, SRGB formats are not compressible and the sampler engine isn't
2534 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2535 * color buffer needs to be resolved so that the sampling surface can be
2536 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2540 can_texture_with_ccs(struct brw_context
*brw
,
2541 struct intel_mipmap_tree
*mt
,
2542 enum isl_format view_format
)
2544 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2547 if (!format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2549 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2550 isl_format_get_layout(view_format
)->name
,
2551 _mesa_get_format_name(mt
->format
));
2559 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2560 struct intel_mipmap_tree
*mt
,
2561 enum isl_format view_format
,
2562 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
)
2564 assert(brw
->screen
->devinfo
.gen
== 9 || astc5x5_wa_bits
== 0);
2566 /* On gen9, ASTC 5x5 textures cannot live in the sampler cache along side
2567 * CCS or HiZ compressed textures. See gen9_apply_astc5x5_wa_flush() for
2570 if ((astc5x5_wa_bits
& GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
) &&
2571 mt
->aux_usage
!= ISL_AUX_USAGE_MCS
)
2572 return ISL_AUX_USAGE_NONE
;
2574 switch (mt
->aux_usage
) {
2575 case ISL_AUX_USAGE_HIZ
:
2576 if (intel_miptree_sample_with_hiz(brw
, mt
))
2577 return ISL_AUX_USAGE_HIZ
;
2580 case ISL_AUX_USAGE_MCS
:
2581 return ISL_AUX_USAGE_MCS
;
2583 case ISL_AUX_USAGE_CCS_D
:
2584 case ISL_AUX_USAGE_CCS_E
:
2586 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2587 return ISL_AUX_USAGE_NONE
;
2590 /* If we don't have any unresolved color, report an aux usage of
2591 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
2592 * aux surface and we can save some bandwidth.
2594 if (!intel_miptree_has_color_unresolved(mt
, 0, INTEL_REMAINING_LEVELS
,
2595 0, INTEL_REMAINING_LAYERS
))
2596 return ISL_AUX_USAGE_NONE
;
2598 if (can_texture_with_ccs(brw
, mt
, view_format
))
2599 return ISL_AUX_USAGE_CCS_E
;
2606 return ISL_AUX_USAGE_NONE
;
2610 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2612 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2613 * values so sRGB curve application was a no-op for all fast-clearable
2616 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2617 * values, the hardware interprets the floats, not as what would be
2618 * returned from the sampler (or written by the shader), but as being
2619 * between format conversion and sRGB curve application. This means that
2620 * we can switch between sRGB and UNORM without having to whack the clear
2623 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2627 intel_miptree_prepare_texture(struct brw_context
*brw
,
2628 struct intel_mipmap_tree
*mt
,
2629 enum isl_format view_format
,
2630 uint32_t start_level
, uint32_t num_levels
,
2631 uint32_t start_layer
, uint32_t num_layers
,
2632 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
)
2634 enum isl_aux_usage aux_usage
=
2635 intel_miptree_texture_aux_usage(brw
, mt
, view_format
, astc5x5_wa_bits
);
2637 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2639 /* Clear color is specified as ints or floats and the conversion is done by
2640 * the sampler. If we have a texture view, we would have to perform the
2641 * clear color conversion manually. Just disable clear color.
2643 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2644 clear_supported
= false;
2646 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2647 start_layer
, num_layers
,
2648 aux_usage
, clear_supported
);
2652 intel_miptree_prepare_image(struct brw_context
*brw
,
2653 struct intel_mipmap_tree
*mt
)
2655 /* The data port doesn't understand any compression */
2656 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2657 0, INTEL_REMAINING_LAYERS
,
2658 ISL_AUX_USAGE_NONE
, false);
2662 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2663 struct intel_mipmap_tree
*mt
,
2664 enum isl_format render_format
,
2666 bool draw_aux_disabled
)
2668 struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2670 if (draw_aux_disabled
)
2671 return ISL_AUX_USAGE_NONE
;
2673 switch (mt
->aux_usage
) {
2674 case ISL_AUX_USAGE_MCS
:
2675 assert(mt
->aux_buf
);
2676 return ISL_AUX_USAGE_MCS
;
2678 case ISL_AUX_USAGE_CCS_D
:
2679 case ISL_AUX_USAGE_CCS_E
:
2681 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2682 return ISL_AUX_USAGE_NONE
;
2685 /* gen9+ hardware technically supports non-0/1 clear colors with sRGB
2686 * formats. However, there are issues with blending where it doesn't
2687 * properly apply the sRGB curve to the clear color when blending.
2689 if (devinfo
->gen
>= 9 && blend_enabled
&&
2690 isl_format_is_srgb(render_format
) &&
2691 !isl_color_value_is_zero_one(mt
->fast_clear_color
, render_format
))
2692 return ISL_AUX_USAGE_NONE
;
2694 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
&&
2695 format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2697 return ISL_AUX_USAGE_CCS_E
;
2699 /* Otherwise, we have to fall back to CCS_D */
2700 return ISL_AUX_USAGE_CCS_D
;
2703 return ISL_AUX_USAGE_NONE
;
2708 intel_miptree_prepare_render(struct brw_context
*brw
,
2709 struct intel_mipmap_tree
*mt
, uint32_t level
,
2710 uint32_t start_layer
, uint32_t layer_count
,
2711 enum isl_aux_usage aux_usage
)
2713 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2714 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2718 intel_miptree_finish_render(struct brw_context
*brw
,
2719 struct intel_mipmap_tree
*mt
, uint32_t level
,
2720 uint32_t start_layer
, uint32_t layer_count
,
2721 enum isl_aux_usage aux_usage
)
2723 assert(_mesa_is_format_color_format(mt
->format
));
2725 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2730 intel_miptree_prepare_depth(struct brw_context
*brw
,
2731 struct intel_mipmap_tree
*mt
, uint32_t level
,
2732 uint32_t start_layer
, uint32_t layer_count
)
2734 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2735 mt
->aux_usage
, mt
->aux_buf
!= NULL
);
2739 intel_miptree_finish_depth(struct brw_context
*brw
,
2740 struct intel_mipmap_tree
*mt
, uint32_t level
,
2741 uint32_t start_layer
, uint32_t layer_count
,
2744 if (depth_written
) {
2745 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2751 intel_miptree_prepare_external(struct brw_context
*brw
,
2752 struct intel_mipmap_tree
*mt
)
2754 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
2755 bool supports_fast_clear
= false;
2757 const struct isl_drm_modifier_info
*mod_info
=
2758 isl_drm_modifier_get_info(mt
->drm_modifier
);
2760 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
2761 /* CCS_E is the only supported aux for external images and it's only
2762 * supported on very simple images.
2764 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
2765 assert(_mesa_is_format_color_format(mt
->format
));
2766 assert(mt
->first_level
== 0 && mt
->last_level
== 0);
2767 assert(mt
->surf
.logical_level0_px
.depth
== 1);
2768 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
2769 assert(mt
->surf
.samples
== 1);
2770 assert(mt
->aux_buf
!= NULL
);
2772 aux_usage
= mod_info
->aux_usage
;
2773 supports_fast_clear
= mod_info
->supports_clear_color
;
2776 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2777 0, INTEL_REMAINING_LAYERS
,
2778 aux_usage
, supports_fast_clear
);
2782 intel_miptree_finish_external(struct brw_context
*brw
,
2783 struct intel_mipmap_tree
*mt
)
2788 /* We don't know the actual aux state of the aux surface. The previous
2789 * owner could have given it to us in a number of different states.
2790 * Because we don't know the aux state, we reset the aux state to the
2791 * least common denominator of possible valid states.
2793 enum isl_aux_state default_aux_state
=
2794 isl_drm_modifier_get_default_aux_state(mt
->drm_modifier
);
2795 assert(mt
->last_level
== mt
->first_level
);
2796 intel_miptree_set_aux_state(brw
, mt
, 0, 0, INTEL_REMAINING_LAYERS
,
2801 * Make it possible to share the BO backing the given miptree with another
2802 * process or another miptree.
2804 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2805 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2806 * ensure that no MCS buffer gets allocated in the future.
2808 * HiZ is similarly unsafe with shared buffers.
2811 intel_miptree_make_shareable(struct brw_context
*brw
,
2812 struct intel_mipmap_tree
*mt
)
2814 /* MCS buffers are also used for multisample buffers, but we can't resolve
2815 * away a multisample MCS buffer because it's an integral part of how the
2816 * pixel data is stored. Fortunately this code path should never be
2817 * reached for multisample buffers.
2819 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2820 mt
->surf
.samples
== 1);
2822 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2823 0, INTEL_REMAINING_LAYERS
,
2824 ISL_AUX_USAGE_NONE
, false);
2827 intel_miptree_aux_buffer_free(mt
->aux_buf
);
2830 /* Make future calls of intel_miptree_level_has_hiz() return false. */
2831 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2832 mt
->level
[l
].has_hiz
= false;
2835 free(mt
->aux_state
);
2836 mt
->aux_state
= NULL
;
2837 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2840 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2841 mt
->supports_fast_clear
= false;
2846 * \brief Get pointer offset into stencil buffer.
2848 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2849 * must decode the tile's layout in software.
2852 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2854 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2856 * Even though the returned offset is always positive, the return type is
2858 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2859 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2862 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2864 uint32_t tile_size
= 4096;
2865 uint32_t tile_width
= 64;
2866 uint32_t tile_height
= 64;
2867 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2869 uint32_t tile_x
= x
/ tile_width
;
2870 uint32_t tile_y
= y
/ tile_height
;
2872 /* The byte's address relative to the tile's base addres. */
2873 uint32_t byte_x
= x
% tile_width
;
2874 uint32_t byte_y
= y
% tile_height
;
2876 uintptr_t u
= tile_y
* row_size
2877 + tile_x
* tile_size
2878 + 512 * (byte_x
/ 8)
2880 + 32 * ((byte_y
/ 4) % 2)
2881 + 16 * ((byte_x
/ 4) % 2)
2882 + 8 * ((byte_y
/ 2) % 2)
2883 + 4 * ((byte_x
/ 2) % 2)
2888 /* adjust for bit6 swizzling */
2889 if (((byte_x
/ 8) % 2) == 1) {
2890 if (((byte_y
/ 8) % 2) == 0) {
2902 intel_miptree_updownsample(struct brw_context
*brw
,
2903 struct intel_mipmap_tree
*src
,
2904 struct intel_mipmap_tree
*dst
)
2906 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2907 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2908 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2909 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2911 brw_blorp_blit_miptrees(brw
,
2912 src
, 0 /* level */, 0 /* layer */,
2913 src
->format
, SWIZZLE_XYZW
,
2914 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2917 GL_NEAREST
, false, false /*mirror x, y*/,
2920 if (src
->stencil_mt
) {
2921 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2922 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2923 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2924 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2926 brw_blorp_blit_miptrees(brw
,
2927 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2928 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2929 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2930 dst
->stencil_mt
->format
,
2933 GL_NEAREST
, false, false /*mirror x, y*/,
2934 false, false /* decode/encode srgb */);
2939 intel_update_r8stencil(struct brw_context
*brw
,
2940 struct intel_mipmap_tree
*mt
)
2942 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2944 assert(devinfo
->gen
>= 7);
2945 struct intel_mipmap_tree
*src
=
2946 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2947 if (!src
|| devinfo
->gen
>= 8)
2950 assert(src
->surf
.size_B
> 0);
2952 if (!mt
->shadow_mt
) {
2953 assert(devinfo
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2954 mt
->shadow_mt
= make_surface(
2957 MESA_FORMAT_R_UINT8
,
2958 src
->first_level
, src
->last_level
,
2959 src
->surf
.logical_level0_px
.width
,
2960 src
->surf
.logical_level0_px
.height
,
2961 src
->surf
.dim
== ISL_SURF_DIM_3D
?
2962 src
->surf
.logical_level0_px
.depth
:
2963 src
->surf
.logical_level0_px
.array_len
,
2966 ISL_SURF_USAGE_TEXTURE_BIT
,
2967 BO_ALLOC_BUSY
, 0, NULL
);
2968 assert(mt
->shadow_mt
);
2971 if (src
->shadow_needs_update
== false)
2974 struct intel_mipmap_tree
*dst
= mt
->shadow_mt
;
2976 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2977 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
2978 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
2979 src
->surf
.phys_level0_sa
.array_len
;
2981 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2982 brw_blorp_copy_miptrees(brw
,
2986 minify(src
->surf
.logical_level0_px
.width
,
2988 minify(src
->surf
.logical_level0_px
.height
,
2993 brw_cache_flush_for_read(brw
, dst
->bo
);
2994 src
->shadow_needs_update
= false;
2998 intel_miptree_map_raw(struct brw_context
*brw
,
2999 struct intel_mipmap_tree
*mt
,
3002 struct brw_bo
*bo
= mt
->bo
;
3004 if (brw_batch_references(&brw
->batch
, bo
))
3005 intel_batchbuffer_flush(brw
);
3007 return brw_bo_map(brw
, bo
, mode
);
3011 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3013 brw_bo_unmap(mt
->bo
);
3017 intel_miptree_unmap_map(struct brw_context
*brw
,
3018 struct intel_mipmap_tree
*mt
,
3019 struct intel_miptree_map
*map
,
3020 unsigned int level
, unsigned int slice
)
3022 intel_miptree_unmap_raw(mt
);
3026 intel_miptree_map_map(struct brw_context
*brw
,
3027 struct intel_mipmap_tree
*mt
,
3028 struct intel_miptree_map
*map
,
3029 unsigned int level
, unsigned int slice
)
3031 unsigned int bw
, bh
;
3033 unsigned int image_x
, image_y
;
3034 intptr_t x
= map
->x
;
3035 intptr_t y
= map
->y
;
3037 /* For compressed formats, the stride is the number of bytes per
3038 * row of blocks. intel_miptree_get_image_offset() already does
3041 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3042 assert(y
% bh
== 0);
3043 assert(x
% bw
== 0);
3047 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3048 map
->mode
& GL_MAP_WRITE_BIT
);
3050 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3057 /* Note that in the case of cube maps, the caller must have passed the
3058 * slice number referencing the face.
3060 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3064 map
->stride
= mt
->surf
.row_pitch_B
;
3065 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3068 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3069 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3070 map
->x
, map
->y
, map
->w
, map
->h
,
3071 mt
, _mesa_get_format_name(mt
->format
),
3072 x
, y
, map
->ptr
, map
->stride
);
3074 map
->unmap
= intel_miptree_unmap_map
;
3078 intel_miptree_unmap_blit(struct brw_context
*brw
,
3079 struct intel_mipmap_tree
*mt
,
3080 struct intel_miptree_map
*map
,
3084 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3085 struct gl_context
*ctx
= &brw
->ctx
;
3087 intel_miptree_unmap_raw(map
->linear_mt
);
3089 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3090 if (devinfo
->gen
>= 6) {
3091 brw_blorp_copy_miptrees(brw
, map
->linear_mt
, 0, 0,
3093 0, 0, map
->x
, map
->y
, map
->w
, map
->h
);
3095 bool ok
= intel_miptree_copy(brw
,
3096 map
->linear_mt
, 0, 0, 0, 0,
3097 mt
, level
, slice
, map
->x
, map
->y
,
3099 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3103 intel_miptree_release(&map
->linear_mt
);
3106 /* Compute extent parameters for use with tiled_memcpy functions.
3107 * xs are in units of bytes and ys are in units of strides.
3110 tile_extents(struct intel_mipmap_tree
*mt
, struct intel_miptree_map
*map
,
3111 unsigned int level
, unsigned int slice
, unsigned int *x1_B
,
3112 unsigned int *x2_B
, unsigned int *y1_el
, unsigned int *y2_el
)
3114 unsigned int block_width
, block_height
;
3115 unsigned int x0_el
, y0_el
;
3117 _mesa_get_format_block_size(mt
->format
, &block_width
, &block_height
);
3119 assert(map
->x
% block_width
== 0);
3120 assert(map
->y
% block_height
== 0);
3122 intel_miptree_get_image_offset(mt
, level
, slice
, &x0_el
, &y0_el
);
3123 *x1_B
= (map
->x
/ block_width
+ x0_el
) * mt
->cpp
;
3124 *y1_el
= map
->y
/ block_height
+ y0_el
;
3125 *x2_B
= (DIV_ROUND_UP(map
->x
+ map
->w
, block_width
) + x0_el
) * mt
->cpp
;
3126 *y2_el
= DIV_ROUND_UP(map
->y
+ map
->h
, block_height
) + y0_el
;
3130 intel_miptree_unmap_tiled_memcpy(struct brw_context
*brw
,
3131 struct intel_mipmap_tree
*mt
,
3132 struct intel_miptree_map
*map
,
3136 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3137 unsigned int x1
, x2
, y1
, y2
;
3138 tile_extents(mt
, map
, level
, slice
, &x1
, &x2
, &y1
, &y2
);
3140 char *dst
= intel_miptree_map_raw(brw
, mt
, map
->mode
| MAP_RAW
);
3143 isl_memcpy_linear_to_tiled(
3144 x1
, x2
, y1
, y2
, dst
, map
->ptr
, mt
->surf
.row_pitch_B
, map
->stride
,
3145 brw
->has_swizzling
, mt
->surf
.tiling
, ISL_MEMCPY
);
3147 intel_miptree_unmap_raw(mt
);
3149 _mesa_align_free(map
->buffer
);
3150 map
->buffer
= map
->ptr
= NULL
;
3154 * Determine which copy function to use for the given format combination
3156 * The only two possible copy functions which are ever returned are a
3157 * direct memcpy and a RGBA <-> BGRA copy function. Since RGBA -> BGRA and
3158 * BGRA -> RGBA are exactly the same operation (and memcpy is obviously
3159 * symmetric), it doesn't matter whether the copy is from the tiled image
3160 * to the untiled or vice versa. The copy function required is the same in
3161 * either case so this function can be used.
3163 * \param[in] tiledFormat The format of the tiled image
3164 * \param[in] format The GL format of the client data
3165 * \param[in] type The GL type of the client data
3166 * \param[out] mem_copy Will be set to one of either the standard
3167 * library's memcpy or a different copy function
3168 * that performs an RGBA to BGRA conversion
3169 * \param[out] cpp Number of bytes per channel
3171 * \return true if the format and type combination are valid
3173 MAYBE_UNUSED isl_memcpy_type
3174 intel_miptree_get_memcpy_type(mesa_format tiledFormat
, GLenum format
, GLenum type
,
3177 if (type
== GL_UNSIGNED_INT_8_8_8_8_REV
&&
3178 !(format
== GL_RGBA
|| format
== GL_BGRA
))
3179 return ISL_MEMCPY_INVALID
; /* Invalid type/format combination */
3181 if ((tiledFormat
== MESA_FORMAT_L_UNORM8
&& format
== GL_LUMINANCE
) ||
3182 (tiledFormat
== MESA_FORMAT_A_UNORM8
&& format
== GL_ALPHA
)) {
3185 } else if ((tiledFormat
== MESA_FORMAT_B8G8R8A8_UNORM
) ||
3186 (tiledFormat
== MESA_FORMAT_B8G8R8X8_UNORM
) ||
3187 (tiledFormat
== MESA_FORMAT_B8G8R8A8_SRGB
) ||
3188 (tiledFormat
== MESA_FORMAT_B8G8R8X8_SRGB
)) {
3190 if (format
== GL_BGRA
) {
3192 } else if (format
== GL_RGBA
) {
3193 return ISL_MEMCPY_BGRA8
;
3195 } else if ((tiledFormat
== MESA_FORMAT_R8G8B8A8_UNORM
) ||
3196 (tiledFormat
== MESA_FORMAT_R8G8B8X8_UNORM
) ||
3197 (tiledFormat
== MESA_FORMAT_R8G8B8A8_SRGB
) ||
3198 (tiledFormat
== MESA_FORMAT_R8G8B8X8_SRGB
)) {
3200 if (format
== GL_BGRA
) {
3201 /* Copying from RGBA to BGRA is the same as BGRA to RGBA so we can
3202 * use the same function.
3204 return ISL_MEMCPY_BGRA8
;
3205 } else if (format
== GL_RGBA
) {
3210 return ISL_MEMCPY_INVALID
;
3214 intel_miptree_map_tiled_memcpy(struct brw_context
*brw
,
3215 struct intel_mipmap_tree
*mt
,
3216 struct intel_miptree_map
*map
,
3217 unsigned int level
, unsigned int slice
)
3219 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3220 map
->mode
& GL_MAP_WRITE_BIT
);
3222 unsigned int x1
, x2
, y1
, y2
;
3223 tile_extents(mt
, map
, level
, slice
, &x1
, &x2
, &y1
, &y2
);
3224 map
->stride
= ALIGN(_mesa_format_row_stride(mt
->format
, map
->w
), 16);
3226 /* The tiling and detiling functions require that the linear buffer
3227 * has proper 16-byte alignment (that is, its `x0` is 16-byte
3228 * aligned). Here we over-allocate the linear buffer by enough
3229 * bytes to get the proper alignment.
3231 map
->buffer
= _mesa_align_malloc(map
->stride
* (y2
- y1
) + (x1
& 0xf), 16);
3232 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
3233 assert(map
->buffer
);
3235 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3236 char *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
| MAP_RAW
);
3239 const isl_memcpy_type copy_type
=
3240 #if defined(USE_SSE41)
3241 cpu_has_sse4_1
? ISL_MEMCPY_STREAMING_LOAD
:
3245 isl_memcpy_tiled_to_linear(
3246 x1
, x2
, y1
, y2
, map
->ptr
, src
, map
->stride
,
3247 mt
->surf
.row_pitch_B
, brw
->has_swizzling
, mt
->surf
.tiling
,
3250 intel_miptree_unmap_raw(mt
);
3253 map
->unmap
= intel_miptree_unmap_tiled_memcpy
;
3257 intel_miptree_map_blit(struct brw_context
*brw
,
3258 struct intel_mipmap_tree
*mt
,
3259 struct intel_miptree_map
*map
,
3260 unsigned int level
, unsigned int slice
)
3262 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3263 map
->linear_mt
= make_surface(brw
, GL_TEXTURE_2D
, mt
->format
,
3264 0, 0, map
->w
, map
->h
, 1, 1,
3265 ISL_TILING_LINEAR_BIT
,
3266 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
3267 ISL_SURF_USAGE_TEXTURE_BIT
,
3270 if (!map
->linear_mt
) {
3271 fprintf(stderr
, "Failed to allocate blit temporary\n");
3274 map
->stride
= map
->linear_mt
->surf
.row_pitch_B
;
3276 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3277 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3278 * invalidate is set, since we'll be writing the whole rectangle from our
3279 * temporary buffer back out.
3281 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3282 if (devinfo
->gen
>= 6) {
3283 brw_blorp_copy_miptrees(brw
, mt
, level
, slice
,
3284 map
->linear_mt
, 0, 0,
3285 map
->x
, map
->y
, 0, 0, map
->w
, map
->h
);
3287 if (!intel_miptree_copy(brw
,
3288 mt
, level
, slice
, map
->x
, map
->y
,
3289 map
->linear_mt
, 0, 0, 0, 0,
3291 fprintf(stderr
, "Failed to blit\n");
3297 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3299 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3300 map
->x
, map
->y
, map
->w
, map
->h
,
3301 mt
, _mesa_get_format_name(mt
->format
),
3302 level
, slice
, map
->ptr
, map
->stride
);
3304 map
->unmap
= intel_miptree_unmap_blit
;
3308 intel_miptree_release(&map
->linear_mt
);
3314 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3316 #if defined(USE_SSE41)
3318 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3319 struct intel_mipmap_tree
*mt
,
3320 struct intel_miptree_map
*map
,
3324 _mesa_align_free(map
->buffer
);
3330 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3331 struct intel_mipmap_tree
*mt
,
3332 struct intel_miptree_map
*map
,
3333 unsigned int level
, unsigned int slice
)
3335 assert(map
->mode
& GL_MAP_READ_BIT
);
3336 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3338 intel_miptree_access_raw(brw
, mt
, level
, slice
, false);
3340 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3341 map
->x
, map
->y
, map
->w
, map
->h
,
3342 mt
, _mesa_get_format_name(mt
->format
),
3343 level
, slice
, map
->ptr
, map
->stride
);
3345 /* Map the original image */
3348 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3352 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3358 src
+= image_y
* mt
->surf
.row_pitch_B
;
3359 src
+= image_x
* mt
->cpp
;
3361 /* Due to the pixel offsets for the particular image being mapped, our
3362 * src pointer may not be 16-byte aligned. However, if the pitch is
3363 * divisible by 16, then the amount by which it's misaligned will remain
3364 * consistent from row to row.
3366 assert((mt
->surf
.row_pitch_B
% 16) == 0);
3367 const int misalignment
= ((uintptr_t) src
) & 15;
3369 /* Create an untiled temporary buffer for the mapping. */
3370 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3372 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3374 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3375 /* Offset the destination so it has the same misalignment as src. */
3376 map
->ptr
= map
->buffer
+ misalignment
;
3378 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3380 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3381 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3382 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch_B
;
3384 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3387 intel_miptree_unmap_raw(mt
);
3389 map
->unmap
= intel_miptree_unmap_movntdqa
;
3394 intel_miptree_unmap_s8(struct brw_context
*brw
,
3395 struct intel_mipmap_tree
*mt
,
3396 struct intel_miptree_map
*map
,
3400 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3401 unsigned int image_x
, image_y
;
3402 uint8_t *untiled_s8_map
= map
->ptr
;
3403 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3405 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3407 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3408 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3409 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch_B
,
3410 image_x
+ x
+ map
->x
,
3411 image_y
+ y
+ map
->y
,
3412 brw
->has_swizzling
);
3413 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3417 intel_miptree_unmap_raw(mt
);
3424 intel_miptree_map_s8(struct brw_context
*brw
,
3425 struct intel_mipmap_tree
*mt
,
3426 struct intel_miptree_map
*map
,
3427 unsigned int level
, unsigned int slice
)
3429 map
->stride
= map
->w
;
3430 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3434 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3435 map
->mode
& GL_MAP_WRITE_BIT
);
3437 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3438 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3439 * invalidate is set, since we'll be writing the whole rectangle from our
3440 * temporary buffer back out.
3442 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3443 uint8_t *untiled_s8_map
= map
->ptr
;
3444 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3445 unsigned int image_x
, image_y
;
3447 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3449 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3450 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3451 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch_B
,
3452 x
+ image_x
+ map
->x
,
3453 y
+ image_y
+ map
->y
,
3454 brw
->has_swizzling
);
3455 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3459 intel_miptree_unmap_raw(mt
);
3461 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3462 map
->x
, map
->y
, map
->w
, map
->h
,
3463 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3465 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3466 map
->x
, map
->y
, map
->w
, map
->h
,
3467 mt
, map
->ptr
, map
->stride
);
3470 map
->unmap
= intel_miptree_unmap_s8
;
3474 * Mapping functions for packed depth/stencil miptrees backed by real separate
3475 * miptrees for depth and stencil.
3477 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3478 * separate from the depth buffer. Yet at the GL API level, we have to expose
3479 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3480 * be able to map that memory for texture storage and glReadPixels-type
3481 * operations. We give Mesa core that access by mallocing a temporary and
3482 * copying the data between the actual backing store and the temporary.
3485 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3486 struct intel_mipmap_tree
*mt
,
3487 struct intel_miptree_map
*map
,
3491 struct intel_mipmap_tree
*z_mt
= mt
;
3492 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3493 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3495 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3496 uint32_t *packed_map
= map
->ptr
;
3497 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3498 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3499 unsigned int s_image_x
, s_image_y
;
3500 unsigned int z_image_x
, z_image_y
;
3502 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3503 &s_image_x
, &s_image_y
);
3504 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3505 &z_image_x
, &z_image_y
);
3507 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3508 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3509 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch_B
,
3510 x
+ s_image_x
+ map
->x
,
3511 y
+ s_image_y
+ map
->y
,
3512 brw
->has_swizzling
);
3513 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3514 (z_mt
->surf
.row_pitch_B
/ 4) +
3515 (x
+ z_image_x
+ map
->x
));
3517 if (map_z32f_x24s8
) {
3518 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3519 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3521 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3522 s_map
[s_offset
] = packed
>> 24;
3523 z_map
[z_offset
] = packed
;
3528 intel_miptree_unmap_raw(s_mt
);
3529 intel_miptree_unmap_raw(z_mt
);
3531 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3533 map
->x
, map
->y
, map
->w
, map
->h
,
3534 z_mt
, _mesa_get_format_name(z_mt
->format
),
3535 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3536 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3537 map
->ptr
, map
->stride
);
3544 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3545 struct intel_mipmap_tree
*mt
,
3546 struct intel_miptree_map
*map
,
3547 unsigned int level
, unsigned int slice
)
3549 struct intel_mipmap_tree
*z_mt
= mt
;
3550 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3551 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3552 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3554 map
->stride
= map
->w
* packed_bpp
;
3555 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3559 intel_miptree_access_raw(brw
, z_mt
, level
, slice
,
3560 map
->mode
& GL_MAP_WRITE_BIT
);
3561 intel_miptree_access_raw(brw
, s_mt
, level
, slice
,
3562 map
->mode
& GL_MAP_WRITE_BIT
);
3564 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3565 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3566 * invalidate is set, since we'll be writing the whole rectangle from our
3567 * temporary buffer back out.
3569 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3570 uint32_t *packed_map
= map
->ptr
;
3571 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3572 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3573 unsigned int s_image_x
, s_image_y
;
3574 unsigned int z_image_x
, z_image_y
;
3576 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3577 &s_image_x
, &s_image_y
);
3578 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3579 &z_image_x
, &z_image_y
);
3581 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3582 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3583 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3584 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch_B
,
3587 brw
->has_swizzling
);
3588 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3589 (z_mt
->surf
.row_pitch_B
/ 4) +
3590 (map_x
+ z_image_x
));
3591 uint8_t s
= s_map
[s_offset
];
3592 uint32_t z
= z_map
[z_offset
];
3594 if (map_z32f_x24s8
) {
3595 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3596 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3598 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3603 intel_miptree_unmap_raw(s_mt
);
3604 intel_miptree_unmap_raw(z_mt
);
3606 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3608 map
->x
, map
->y
, map
->w
, map
->h
,
3609 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3610 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3611 map
->ptr
, map
->stride
);
3613 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3614 map
->x
, map
->y
, map
->w
, map
->h
,
3615 mt
, map
->ptr
, map
->stride
);
3618 map
->unmap
= intel_miptree_unmap_depthstencil
;
3622 * Create and attach a map to the miptree at (level, slice). Return the
3625 static struct intel_miptree_map
*
3626 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3635 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3640 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3641 mt
->level
[level
].slice
[slice
].map
= map
;
3653 * Release the map at (level, slice).
3656 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3660 struct intel_miptree_map
**map
;
3662 map
= &mt
->level
[level
].slice
[slice
].map
;
3668 can_blit_slice(struct intel_mipmap_tree
*mt
,
3669 const struct intel_miptree_map
*map
)
3671 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3672 const unsigned src_blt_pitch
= intel_miptree_blt_pitch(mt
);
3673 const unsigned dst_blt_pitch
= ALIGN(map
->w
* mt
->cpp
, 64);
3674 return src_blt_pitch
< 32768 && dst_blt_pitch
< 32768;
3678 use_intel_mipree_map_blit(struct brw_context
*brw
,
3679 struct intel_mipmap_tree
*mt
,
3680 const struct intel_miptree_map
*map
)
3682 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3684 if (devinfo
->has_llc
&&
3685 /* It's probably not worth swapping to the blit ring because of
3686 * all the overhead involved.
3688 !(map
->mode
& GL_MAP_WRITE_BIT
) &&
3690 (mt
->surf
.tiling
== ISL_TILING_X
||
3691 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3692 (devinfo
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3693 /* Fast copy blit on skl+ supports all tiling formats. */
3694 devinfo
->gen
>= 9) &&
3695 can_blit_slice(mt
, map
))
3698 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3699 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3700 assert(can_blit_slice(mt
, map
));
3708 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3709 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3710 * arithmetic overflow.
3712 * If you call this function and use \a out_stride, then you're doing pointer
3713 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3714 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3715 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3716 * which usually have type uint32_t or GLuint.
3719 intel_miptree_map(struct brw_context
*brw
,
3720 struct intel_mipmap_tree
*mt
,
3729 ptrdiff_t *out_stride
)
3731 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3732 struct intel_miptree_map
*map
;
3734 assert(mt
->surf
.samples
== 1);
3736 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3743 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3744 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3745 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3746 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3747 } else if (use_intel_mipree_map_blit(brw
, mt
, map
)) {
3748 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3749 } else if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&& devinfo
->gen
> 4) {
3750 intel_miptree_map_tiled_memcpy(brw
, mt
, map
, level
, slice
);
3751 #if defined(USE_SSE41)
3752 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3753 !mt
->compressed
&& cpu_has_sse4_1
&&
3754 (mt
->surf
.row_pitch_B
% 16 == 0)) {
3755 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3758 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
3759 perf_debug("intel_miptree_map: mapping via gtt");
3760 intel_miptree_map_map(brw
, mt
, map
, level
, slice
);
3763 *out_ptr
= map
->ptr
;
3764 *out_stride
= map
->stride
;
3766 if (map
->ptr
== NULL
)
3767 intel_miptree_release_map(mt
, level
, slice
);
3771 intel_miptree_unmap(struct brw_context
*brw
,
3772 struct intel_mipmap_tree
*mt
,
3776 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3778 assert(mt
->surf
.samples
== 1);
3783 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3784 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3787 map
->unmap(brw
, mt
, map
, level
, slice
);
3789 intel_miptree_release_map(mt
, level
, slice
);
3793 get_isl_surf_dim(GLenum target
)
3797 case GL_TEXTURE_1D_ARRAY
:
3798 return ISL_SURF_DIM_1D
;
3801 case GL_TEXTURE_2D_ARRAY
:
3802 case GL_TEXTURE_RECTANGLE
:
3803 case GL_TEXTURE_CUBE_MAP
:
3804 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3805 case GL_TEXTURE_2D_MULTISAMPLE
:
3806 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3807 case GL_TEXTURE_EXTERNAL_OES
:
3808 return ISL_SURF_DIM_2D
;
3811 return ISL_SURF_DIM_3D
;
3814 unreachable("Invalid texture target");
3818 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3819 enum isl_tiling tiling
, GLenum target
)
3823 case GL_TEXTURE_1D_ARRAY
:
3824 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3825 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3828 case GL_TEXTURE_2D_ARRAY
:
3829 case GL_TEXTURE_RECTANGLE
:
3830 case GL_TEXTURE_2D_MULTISAMPLE
:
3831 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3832 case GL_TEXTURE_EXTERNAL_OES
:
3833 return ISL_DIM_LAYOUT_GEN4_2D
;
3835 case GL_TEXTURE_CUBE_MAP
:
3836 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3837 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3838 ISL_DIM_LAYOUT_GEN4_2D
);
3841 return (devinfo
->gen
>= 9 ?
3842 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3845 unreachable("Invalid texture target");
3849 intel_miptree_set_clear_color(struct brw_context
*brw
,
3850 struct intel_mipmap_tree
*mt
,
3851 union isl_color_value clear_color
)
3853 if (memcmp(&mt
->fast_clear_color
, &clear_color
, sizeof(clear_color
)) != 0) {
3854 mt
->fast_clear_color
= clear_color
;
3855 if (mt
->aux_buf
->clear_color_bo
) {
3856 /* We can't update the clear color while the hardware is still using
3857 * the previous one for a resolve or sampling from it. Make sure that
3858 * there are no pending commands at this point.
3860 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
);
3861 for (int i
= 0; i
< 4; i
++) {
3862 brw_store_data_imm32(brw
, mt
->aux_buf
->clear_color_bo
,
3863 mt
->aux_buf
->clear_color_offset
+ i
* 4,
3864 mt
->fast_clear_color
.u32
[i
]);
3866 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
3868 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
3874 union isl_color_value
3875 intel_miptree_get_clear_color(const struct gen_device_info
*devinfo
,
3876 const struct intel_mipmap_tree
*mt
,
3877 enum isl_format view_format
, bool sampling
,
3878 struct brw_bo
**clear_color_bo
,
3879 uint64_t *clear_color_offset
)
3881 assert(mt
->aux_buf
);
3883 if (devinfo
->gen
== 10 && isl_format_is_srgb(view_format
) && sampling
) {
3884 /* The gen10 sampler doesn't gamma-correct the clear color. In this case,
3885 * we switch to using the inline clear color and do the sRGB color
3886 * conversion process defined in the OpenGL spec. The red, green, and
3887 * blue channels take part in gamma correction, while the alpha channel
3890 union isl_color_value srgb_decoded_value
= mt
->fast_clear_color
;
3891 for (unsigned i
= 0; i
< 3; i
++) {
3892 srgb_decoded_value
.f32
[i
] =
3893 util_format_srgb_to_linear_float(mt
->fast_clear_color
.f32
[i
]);
3895 *clear_color_bo
= 0;
3896 *clear_color_offset
= 0;
3897 return srgb_decoded_value
;
3899 *clear_color_bo
= mt
->aux_buf
->clear_color_bo
;
3900 *clear_color_offset
= mt
->aux_buf
->clear_color_offset
;
3901 return mt
->fast_clear_color
;
3906 intel_miptree_update_etc_shadow(struct brw_context
*brw
,
3907 struct intel_mipmap_tree
*mt
,
3913 ptrdiff_t etc_stride
, shadow_stride
;
3915 struct intel_mipmap_tree
*smt
= mt
->shadow_mt
;
3917 assert(intel_miptree_has_etc_shadow(brw
, mt
));
3919 intel_miptree_map(brw
, mt
, level
, slice
, 0, 0, level_w
, level_h
,
3920 GL_MAP_READ_BIT
, &mptr
, &etc_stride
);
3921 intel_miptree_map(brw
, smt
, level
, slice
, 0, 0, level_w
, level_h
,
3922 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
,
3923 &sptr
, &shadow_stride
);
3925 if (mt
->format
== MESA_FORMAT_ETC1_RGB8
) {
3926 _mesa_etc1_unpack_rgba8888(sptr
, shadow_stride
, mptr
, etc_stride
,
3929 /* destination and source images must have the same swizzle */
3930 bool is_bgra
= (smt
->format
== MESA_FORMAT_B8G8R8A8_SRGB
);
3931 _mesa_unpack_etc2_format(sptr
, shadow_stride
, mptr
, etc_stride
,
3932 level_w
, level_h
, mt
->format
, is_bgra
);
3935 intel_miptree_unmap(brw
, mt
, level
, slice
);
3936 intel_miptree_unmap(brw
, smt
, level
, slice
);
3940 intel_miptree_update_etc_shadow_levels(struct brw_context
*brw
,
3941 struct intel_mipmap_tree
*mt
)
3943 struct intel_mipmap_tree
*smt
;
3947 assert(mt
->surf
.size_B
> 0);
3948 assert(intel_miptree_has_etc_shadow(brw
, mt
));
3950 smt
= mt
->shadow_mt
;
3951 num_slices
= smt
->surf
.logical_level0_px
.array_len
;
3953 for (int level
= smt
->first_level
; level
<= smt
->last_level
; level
++) {
3954 int level_w
= minify(smt
->surf
.logical_level0_px
.width
,
3955 level
- smt
->first_level
);
3956 int level_h
= minify(smt
->surf
.logical_level0_px
.height
,
3957 level
- smt
->first_level
);
3959 for (unsigned int slice
= 0; slice
< num_slices
; slice
++) {
3960 intel_miptree_update_etc_shadow(brw
, mt
, level
, slice
, level_w
,
3965 mt
->shadow_needs_update
= false;