2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_resolve_map.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
);
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 enum intel_aux_disable aux_disable
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (aux_disable
& INTEL_AUX_DISABLE_MCS
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
105 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
108 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
109 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
111 * - Support is limited to tiled render targets.
113 * Gen9 changes the restriction to Y-tile only.
116 return tiling
== I915_TILING_Y
;
117 else if (brw
->gen
>= 7)
118 return tiling
!= I915_TILING_NONE
;
124 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
125 * can be used. This doesn't (and should not) inspect any of the properties of
128 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
129 * beneath the "Fast Color Clear" bullet (p326):
131 * - Support is for non-mip-mapped and non-array surface types only.
133 * And then later, on p327:
135 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
138 * From the Skylake documentation, it is made clear that X-tiling is no longer
141 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
145 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
146 const struct intel_mipmap_tree
*mt
)
148 /* MCS support does not exist prior to Gen7 */
152 if (mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
)
155 /* This function applies only to non-multisampled render targets. */
156 if (mt
->num_samples
> 1)
159 /* MCS is only supported for color buffers */
160 switch (_mesa_get_format_base_format(mt
->format
)) {
161 case GL_DEPTH_COMPONENT
:
162 case GL_DEPTH_STENCIL
:
163 case GL_STENCIL_INDEX
:
167 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
170 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
171 const bool arrayed
= mt
->physical_depth0
!= 1;
174 /* Multisample surfaces with the CMS layout are not layered surfaces,
175 * yet still have physical_depth0 > 1. Assert that we don't
176 * accidentally reject a multisampled surface here. We should have
177 * rejected it earlier by explicitly checking the sample count.
179 assert(mt
->num_samples
<= 1);
182 /* Handle the hardware restrictions...
184 * All GENs have the following restriction: "MCS buffer for non-MSRT is
185 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
187 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
188 * Non-MultiSampler Render Target Restrictions) Support is for
189 * non-mip-mapped and non-array surface types only.
191 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
192 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
193 * surfaces are supported with MCS buffer layout with these alignments in
194 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
196 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
197 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
198 * surfaces are supported with MCS buffer layout with these alignments in
199 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
201 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
204 /* There's no point in using an MCS buffer if the surface isn't in a
207 if (!brw
->format_supported_as_render_target
[mt
->format
])
211 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
212 const uint32_t brw_format
= brw_isl_format_for_mesa_format(linear_format
);
213 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, brw_format
);
218 /* On Gen9 support for color buffer compression was extended to single
219 * sampled surfaces. This is a helper considering both auxiliary buffer
220 * type and number of samples telling if the given miptree represents
221 * the new single sampled case - also called lossless compression.
224 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
225 const struct intel_mipmap_tree
*mt
)
227 /* Only available from Gen9 onwards. */
231 /* Compression always requires auxiliary buffer. */
235 /* Single sample compression is represented re-using msaa compression
236 * layout type: "Compressed Multisampled Surfaces".
238 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
241 /* And finally distinguish between msaa and single sample case. */
242 return mt
->num_samples
<= 1;
246 intel_miptree_supports_lossless_compressed(struct brw_context
*brw
,
247 const struct intel_mipmap_tree
*mt
)
249 /* For now compression is only enabled for integer formats even though
250 * there exist supported floating point formats also. This is a heuristic
251 * decision based on current public benchmarks. In none of the cases these
252 * formats provided any improvement but a few cases were seen to regress.
253 * Hence these are left to to be enabled in the future when they are known
256 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
259 /* Fast clear mechanism and lossless compression go hand in hand. */
260 if (!intel_miptree_supports_non_msrt_fast_clear(brw
, mt
))
263 /* Fast clear can be also used to clear srgb surfaces by using equivalent
264 * linear format. This trick, however, can't be extended to be used with
265 * lossless compression and therefore a check is needed to see if the format
268 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
272 * Determine depth format corresponding to a depth+stencil format,
273 * for separate stencil.
276 intel_depth_format_for_depthstencil_format(mesa_format format
) {
278 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
279 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
280 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
281 return MESA_FORMAT_Z_FLOAT32
;
289 * @param for_bo Indicates that the caller is
290 * intel_miptree_create_for_bo(). If true, then do not create
293 static struct intel_mipmap_tree
*
294 intel_miptree_create_layout(struct brw_context
*brw
,
303 uint32_t layout_flags
)
305 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
309 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
310 _mesa_enum_to_string(target
),
311 _mesa_get_format_name(format
),
312 first_level
, last_level
, depth0
, mt
);
314 if (target
== GL_TEXTURE_1D_ARRAY
)
315 assert(height0
== 1);
319 mt
->first_level
= first_level
;
320 mt
->last_level
= last_level
;
321 mt
->logical_width0
= width0
;
322 mt
->logical_height0
= height0
;
323 mt
->logical_depth0
= depth0
;
324 mt
->aux_disable
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0 ?
325 INTEL_AUX_DISABLE_ALL
: INTEL_AUX_DISABLE_NONE
;
326 mt
->aux_disable
|= INTEL_AUX_DISABLE_CCS
;
327 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
328 exec_list_make_empty(&mt
->hiz_map
);
329 exec_list_make_empty(&mt
->color_resolve_map
);
330 mt
->cpp
= _mesa_get_format_bytes(format
);
331 mt
->num_samples
= num_samples
;
332 mt
->compressed
= _mesa_is_format_compressed(format
);
333 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
336 int depth_multiply
= 1;
337 if (num_samples
> 1) {
338 /* Adjust width/height/depth for MSAA */
339 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->aux_disable
);
340 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
341 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
342 * "If the surface is multisampled and it is a depth or stencil
343 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
344 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
347 * +----------------------------------------------------------------+
348 * | Num Multisamples | W_l = | H_l = |
349 * +----------------------------------------------------------------+
350 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
351 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
352 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
353 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
354 * +----------------------------------------------------------------+
357 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
358 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
359 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
361 * Another more complicated explanation for these adjustments comes
362 * from the Sandybridge PRM, volume 4, part 1, page 31:
364 * "Any of the other messages (sample*, LOD, load4) used with a
365 * (4x) multisampled surface will in-effect sample a surface with
366 * double the height and width as that indicated in the surface
367 * state. Each pixel position on the original-sized surface is
368 * replaced with a 2x2 of samples with the following arrangement:
373 * Thus, when sampling from a multisampled texture, it behaves as
374 * though the layout in memory for (x,y,sample) is:
376 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
377 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
379 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
380 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
382 * However, the actual layout of multisampled data in memory is:
384 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
385 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
387 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
388 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
390 * This pattern repeats for each 2x2 pixel block.
392 * As a result, when calculating the size of our 4-sample buffer for
393 * an odd width or height, we have to align before scaling up because
394 * sample 3 is in that bottom right 2x2 block.
396 switch (num_samples
) {
398 assert(brw
->gen
>= 8);
399 width0
= ALIGN(width0
, 2) * 2;
400 height0
= ALIGN(height0
, 2);
403 width0
= ALIGN(width0
, 2) * 2;
404 height0
= ALIGN(height0
, 2) * 2;
407 width0
= ALIGN(width0
, 2) * 4;
408 height0
= ALIGN(height0
, 2) * 2;
411 width0
= ALIGN(width0
, 2) * 4;
412 height0
= ALIGN(height0
, 2) * 4;
415 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
418 unreachable("not reached");
421 /* Non-interleaved */
422 depth_multiply
= num_samples
;
423 depth0
*= depth_multiply
;
427 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
428 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
429 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
430 * used on Gen8 to make it pick a qpitch value which doesn't include space
431 * for the mipmaps. On Gen9 this is not necessary because it will
432 * automatically pick a packed qpitch value whenever mt->first_level ==
434 * TODO: can we use it elsewhere?
435 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
438 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
440 switch (mt
->msaa_layout
) {
441 case INTEL_MSAA_LAYOUT_NONE
:
442 case INTEL_MSAA_LAYOUT_IMS
:
443 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
445 case INTEL_MSAA_LAYOUT_UMS
:
446 case INTEL_MSAA_LAYOUT_CMS
:
447 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
452 if (target
== GL_TEXTURE_CUBE_MAP
)
453 assert(depth0
== 6 * depth_multiply
);
455 mt
->physical_width0
= width0
;
456 mt
->physical_height0
= height0
;
457 mt
->physical_depth0
= depth0
;
459 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
460 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
461 (brw
->must_use_separate_stencil
||
462 (brw
->has_separate_stencil
&&
463 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
464 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
466 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
|
467 MIPTREE_LAYOUT_TILING_ANY
;
470 mt
->stencil_mt
= intel_miptree_create(brw
,
481 if (!mt
->stencil_mt
) {
482 intel_miptree_release(&mt
);
485 mt
->stencil_mt
->r8stencil_needs_update
= true;
487 /* Fix up the Z miptree format for how we're splitting out separate
488 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
490 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
493 if (format
== mt
->format
) {
494 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
495 _mesa_get_format_name(mt
->format
));
499 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
500 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
503 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
504 * multisampled or have an AUX buffer attached to it.
506 * GEN | MSRT | AUX_CCS_* or AUX_MCS
507 * -------------------------------------------
508 * 9 | HALIGN_16 | HALIGN_16
509 * 8 | HALIGN_ANY | HALIGN_16
513 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
514 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
515 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
516 } else if (brw
->gen
>= 9 && num_samples
> 1) {
517 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
519 const UNUSED
bool is_lossless_compressed_aux
=
520 brw
->gen
>= 9 && num_samples
== 1 &&
521 mt
->format
== MESA_FORMAT_R_UINT32
;
523 /* For now, nothing else has this requirement */
524 assert(is_lossless_compressed_aux
||
525 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
528 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
529 intel_miptree_release(&mt
);
533 if (mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
)
534 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
541 * Choose an appropriate uncompressed format for a requested
542 * compressed format, if unsupported.
545 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
547 /* No need to lower ETC formats on these platforms,
548 * they are supported natively.
550 if (brw
->gen
>= 8 || brw
->is_baytrail
)
554 case MESA_FORMAT_ETC1_RGB8
:
555 return MESA_FORMAT_R8G8B8X8_UNORM
;
556 case MESA_FORMAT_ETC2_RGB8
:
557 return MESA_FORMAT_R8G8B8X8_UNORM
;
558 case MESA_FORMAT_ETC2_SRGB8
:
559 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
560 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
561 return MESA_FORMAT_B8G8R8A8_SRGB
;
562 case MESA_FORMAT_ETC2_RGBA8_EAC
:
563 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
564 return MESA_FORMAT_R8G8B8A8_UNORM
;
565 case MESA_FORMAT_ETC2_R11_EAC
:
566 return MESA_FORMAT_R_UNORM16
;
567 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
568 return MESA_FORMAT_R_SNORM16
;
569 case MESA_FORMAT_ETC2_RG11_EAC
:
570 return MESA_FORMAT_R16G16_UNORM
;
571 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
572 return MESA_FORMAT_R16G16_SNORM
;
574 /* Non ETC1 / ETC2 format */
579 static struct intel_mipmap_tree
*
580 miptree_create(struct brw_context
*brw
,
589 uint32_t layout_flags
)
591 struct intel_mipmap_tree
*mt
;
592 mesa_format tex_format
= format
;
593 mesa_format etc_format
= MESA_FORMAT_NONE
;
594 uint32_t alloc_flags
= 0;
596 format
= intel_lower_compressed_format(brw
, format
);
598 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
600 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
601 mt
= intel_miptree_create_layout(brw
, target
, format
,
602 first_level
, last_level
, width0
,
603 height0
, depth0
, num_samples
,
608 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
609 mt
->tiling
= I915_TILING_Y
;
611 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
612 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
615 mt
->etc_format
= etc_format
;
617 if (format
== MESA_FORMAT_S_UINT8
) {
618 /* Align to size of W tile, 64x64. */
619 mt
->bo
= drm_bacon_bo_alloc_tiled(brw
->bufmgr
, "miptree",
620 ALIGN(mt
->total_width
, 64),
621 ALIGN(mt
->total_height
, 64),
622 mt
->cpp
, &mt
->tiling
, &pitch
,
625 mt
->bo
= drm_bacon_bo_alloc_tiled(brw
->bufmgr
, "miptree",
626 mt
->total_width
, mt
->total_height
,
627 mt
->cpp
, &mt
->tiling
, &pitch
,
636 struct intel_mipmap_tree
*
637 intel_miptree_create(struct brw_context
*brw
,
646 uint32_t layout_flags
)
648 struct intel_mipmap_tree
*mt
= miptree_create(
650 first_level
, last_level
,
651 width0
, height0
, depth0
, num_samples
,
654 /* If the BO is too large to fit in the aperture, we need to use the
655 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
656 * handle Y-tiling, so we need to fall back to X.
658 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
659 mt
->tiling
== I915_TILING_Y
) {
660 unsigned long pitch
= mt
->pitch
;
661 const uint32_t alloc_flags
=
662 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
663 BO_ALLOC_FOR_RENDER
: 0;
664 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
665 mt
->total_width
, mt
->total_height
);
667 mt
->tiling
= I915_TILING_X
;
668 drm_bacon_bo_unreference(mt
->bo
);
669 mt
->bo
= drm_bacon_bo_alloc_tiled(brw
->bufmgr
, "miptree",
670 mt
->total_width
, mt
->total_height
, mt
->cpp
,
671 &mt
->tiling
, &pitch
, alloc_flags
);
678 intel_miptree_release(&mt
);
683 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
684 assert(mt
->num_samples
> 1);
685 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
686 intel_miptree_release(&mt
);
691 /* If this miptree is capable of supporting fast color clears, set
692 * fast_clear_state appropriately to ensure that fast clears will occur.
693 * Allocation of the MCS miptree will be deferred until the first fast
694 * clear actually occurs or when compressed single sampled buffer is
695 * written by the GPU for the first time.
697 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
698 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
699 mt
->aux_disable
&= ~INTEL_AUX_DISABLE_CCS
;
700 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
702 /* On Gen9+ clients are not currently capable of consuming compressed
703 * single-sampled buffers. Disabling compression allows us to skip
706 const bool lossless_compression_disabled
= INTEL_DEBUG
& DEBUG_NO_RBC
;
707 const bool is_lossless_compressed
=
708 unlikely(!lossless_compression_disabled
) &&
709 brw
->gen
>= 9 && !mt
->is_scanout
&&
710 intel_miptree_supports_lossless_compressed(brw
, mt
);
712 if (is_lossless_compressed
) {
713 intel_miptree_alloc_non_msrt_mcs(brw
, mt
, is_lossless_compressed
);
720 struct intel_mipmap_tree
*
721 intel_miptree_create_for_bo(struct brw_context
*brw
,
729 uint32_t layout_flags
)
731 struct intel_mipmap_tree
*mt
;
732 uint32_t tiling
, swizzle
;
735 drm_bacon_bo_get_tiling(bo
, &tiling
, &swizzle
);
737 /* Nothing will be able to use this miptree with the BO if the offset isn't
740 if (tiling
!= I915_TILING_NONE
)
741 assert(offset
% 4096 == 0);
743 /* miptrees can't handle negative pitch. If you need flipping of images,
744 * that's outside of the scope of the mt.
748 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
750 /* The BO already has a tiling format and we shouldn't confuse the lower
751 * layers by making it try to find a tiling format again.
753 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
754 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
756 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
757 mt
= intel_miptree_create_layout(brw
, target
, format
,
759 width
, height
, depth
, 0,
764 drm_bacon_bo_reference(bo
);
774 * For a singlesample renderbuffer, this simply wraps the given BO with a
777 * For a multisample renderbuffer, this wraps the window system's
778 * (singlesample) BO with a singlesample miptree attached to the
779 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
780 * that will contain the actual rendering (which is lazily resolved to
781 * irb->singlesample_mt).
784 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
785 struct intel_renderbuffer
*irb
,
787 uint32_t width
, uint32_t height
,
790 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
791 struct intel_mipmap_tree
*multisample_mt
= NULL
;
792 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
793 mesa_format format
= rb
->Format
;
794 int num_samples
= rb
->NumSamples
;
796 /* Only the front and back buffers, which are color buffers, are allocated
797 * through the image loader.
799 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
800 _mesa_get_format_base_format(format
) == GL_RGBA
);
802 singlesample_mt
= intel_miptree_create_for_bo(intel
,
810 MIPTREE_LAYOUT_FOR_SCANOUT
);
811 if (!singlesample_mt
)
814 /* If this miptree is capable of supporting fast color clears, set
815 * mcs_state appropriately to ensure that fast clears will occur.
816 * Allocation of the MCS miptree will be deferred until the first fast
817 * clear actually occurs.
819 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
820 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
821 singlesample_mt
->aux_disable
&= ~INTEL_AUX_DISABLE_CCS
;
824 if (num_samples
== 0) {
825 intel_miptree_release(&irb
->mt
);
826 irb
->mt
= singlesample_mt
;
828 assert(!irb
->singlesample_mt
);
830 intel_miptree_release(&irb
->singlesample_mt
);
831 irb
->singlesample_mt
= singlesample_mt
;
834 irb
->mt
->logical_width0
!= width
||
835 irb
->mt
->logical_height0
!= height
) {
836 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
844 irb
->need_downsample
= false;
845 intel_miptree_release(&irb
->mt
);
846 irb
->mt
= multisample_mt
;
852 intel_miptree_release(&irb
->singlesample_mt
);
853 intel_miptree_release(&irb
->mt
);
857 struct intel_mipmap_tree
*
858 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
862 uint32_t num_samples
)
864 struct intel_mipmap_tree
*mt
;
867 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
868 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
869 MIPTREE_LAYOUT_TILING_ANY
|
870 MIPTREE_LAYOUT_FOR_SCANOUT
;
872 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
873 width
, height
, depth
, num_samples
,
878 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
879 ok
= intel_miptree_alloc_hiz(brw
, mt
);
887 intel_miptree_release(&mt
);
892 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
893 struct intel_mipmap_tree
*src
)
898 intel_miptree_release(dst
);
902 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
909 intel_miptree_hiz_buffer_free(struct intel_miptree_hiz_buffer
*hiz_buf
)
915 intel_miptree_release(&hiz_buf
->mt
);
917 drm_bacon_bo_unreference(hiz_buf
->aux_base
.bo
);
923 intel_miptree_release(struct intel_mipmap_tree
**mt
)
928 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
929 if (--(*mt
)->refcount
<= 0) {
932 DBG("%s deleting %p\n", __func__
, *mt
);
934 drm_bacon_bo_unreference((*mt
)->bo
);
935 intel_miptree_release(&(*mt
)->stencil_mt
);
936 intel_miptree_release(&(*mt
)->r8stencil_mt
);
937 intel_miptree_hiz_buffer_free((*mt
)->hiz_buf
);
938 if ((*mt
)->mcs_buf
) {
939 drm_bacon_bo_unreference((*mt
)->mcs_buf
->bo
);
940 free((*mt
)->mcs_buf
);
942 intel_resolve_map_clear(&(*mt
)->hiz_map
);
943 intel_resolve_map_clear(&(*mt
)->color_resolve_map
);
945 intel_miptree_release(&(*mt
)->plane
[0]);
946 intel_miptree_release(&(*mt
)->plane
[1]);
948 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
949 free((*mt
)->level
[i
].slice
);
959 intel_get_image_dims(struct gl_texture_image
*image
,
960 int *width
, int *height
, int *depth
)
962 switch (image
->TexObject
->Target
) {
963 case GL_TEXTURE_1D_ARRAY
:
964 /* For a 1D Array texture the OpenGL API will treat the image height as
965 * the number of array slices. For Intel hardware, we treat the 1D array
966 * as a 2D Array with a height of 1. So, here we want to swap image
969 assert(image
->Depth
== 1);
970 *width
= image
->Width
;
972 *depth
= image
->Height
;
974 case GL_TEXTURE_CUBE_MAP
:
975 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
976 * though we really have 6 slices.
978 assert(image
->Depth
== 1);
979 *width
= image
->Width
;
980 *height
= image
->Height
;
984 *width
= image
->Width
;
985 *height
= image
->Height
;
986 *depth
= image
->Depth
;
992 * Can the image be pulled into a unified mipmap tree? This mirrors
993 * the completeness test in a lot of ways.
995 * Not sure whether I want to pass gl_texture_image here.
998 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
999 struct gl_texture_image
*image
)
1001 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1002 GLuint level
= intelImage
->base
.Base
.Level
;
1003 int width
, height
, depth
;
1005 /* glTexImage* choose the texture object based on the target passed in, and
1006 * objects can't change targets over their lifetimes, so this should be
1009 assert(image
->TexObject
->Target
== mt
->target
);
1011 mesa_format mt_format
= mt
->format
;
1012 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1013 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1014 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1015 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1016 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1017 mt_format
= mt
->etc_format
;
1019 if (image
->TexFormat
!= mt_format
)
1022 intel_get_image_dims(image
, &width
, &height
, &depth
);
1024 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1027 int level_depth
= mt
->level
[level
].depth
;
1028 if (mt
->num_samples
> 1) {
1029 switch (mt
->msaa_layout
) {
1030 case INTEL_MSAA_LAYOUT_NONE
:
1031 case INTEL_MSAA_LAYOUT_IMS
:
1033 case INTEL_MSAA_LAYOUT_UMS
:
1034 case INTEL_MSAA_LAYOUT_CMS
:
1035 level_depth
/= mt
->num_samples
;
1040 /* Test image dimensions against the base level image adjusted for
1041 * minification. This will also catch images not present in the
1042 * tree, changed targets, etc.
1044 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1045 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1046 depth
!= level_depth
) {
1050 if (image
->NumSamples
!= mt
->num_samples
)
1058 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1060 GLuint x
, GLuint y
, GLuint d
)
1062 mt
->level
[level
].depth
= d
;
1063 mt
->level
[level
].level_x
= x
;
1064 mt
->level
[level
].level_y
= y
;
1066 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1069 assert(mt
->level
[level
].slice
== NULL
);
1071 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1072 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1073 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1078 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1079 GLuint level
, GLuint img
,
1082 if (img
== 0 && level
== 0)
1083 assert(x
== 0 && y
== 0);
1085 assert(img
< mt
->level
[level
].depth
);
1087 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1088 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1090 DBG("%s level %d img %d pos %d,%d\n",
1091 __func__
, level
, img
,
1092 mt
->level
[level
].slice
[img
].x_offset
,
1093 mt
->level
[level
].slice
[img
].y_offset
);
1097 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1098 GLuint level
, GLuint slice
,
1099 GLuint
*x
, GLuint
*y
)
1101 assert(slice
< mt
->level
[level
].depth
);
1103 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1104 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1109 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1110 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1111 * and tile_h is set to 1.
1114 intel_get_tile_dims(uint32_t tiling
, uint32_t cpp
,
1115 uint32_t *tile_w
, uint32_t *tile_h
)
1126 case I915_TILING_NONE
:
1131 unreachable("not reached");
1137 * This function computes masks that may be used to select the bits of the X
1138 * and Y coordinates that indicate the offset within a tile. If the BO is
1139 * untiled, the masks are set to 0.
1142 intel_get_tile_masks(uint32_t tiling
, uint32_t cpp
,
1143 uint32_t *mask_x
, uint32_t *mask_y
)
1145 uint32_t tile_w_bytes
, tile_h
;
1147 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1149 *mask_x
= tile_w_bytes
/ cpp
- 1;
1150 *mask_y
= tile_h
- 1;
1154 * Compute the offset (in bytes) from the start of the BO to the given x
1155 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1156 * multiples of the tile size.
1159 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1160 uint32_t x
, uint32_t y
)
1163 uint32_t pitch
= mt
->pitch
;
1164 uint32_t tiling
= mt
->tiling
;
1168 unreachable("not reached");
1169 case I915_TILING_NONE
:
1170 return y
* pitch
+ x
* cpp
;
1172 assert((x
% (512 / cpp
)) == 0);
1173 assert((y
% 8) == 0);
1174 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1176 assert((x
% (128 / cpp
)) == 0);
1177 assert((y
% 32) == 0);
1178 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1183 * Rendering with tiled buffers requires that the base address of the buffer
1184 * be aligned to a page boundary. For renderbuffers, and sometimes with
1185 * textures, we may want the surface to point at a texture image level that
1186 * isn't at a page boundary.
1188 * This function returns an appropriately-aligned base offset
1189 * according to the tiling restrictions, plus any required x/y offset
1193 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1194 GLuint level
, GLuint slice
,
1199 uint32_t mask_x
, mask_y
;
1201 intel_get_tile_masks(mt
->tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1202 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1204 *tile_x
= x
& mask_x
;
1205 *tile_y
= y
& mask_y
;
1207 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1211 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1212 struct intel_mipmap_tree
*dst_mt
,
1213 struct intel_mipmap_tree
*src_mt
,
1220 ptrdiff_t src_stride
, dst_stride
;
1221 int cpp
= dst_mt
->cpp
;
1223 intel_miptree_map(brw
, src_mt
,
1227 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1230 intel_miptree_map(brw
, dst_mt
,
1234 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1238 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1239 _mesa_get_format_name(src_mt
->format
),
1240 src_mt
, src
, src_stride
,
1241 _mesa_get_format_name(dst_mt
->format
),
1242 dst_mt
, dst
, dst_stride
,
1245 int row_size
= cpp
* width
;
1246 if (src_stride
== row_size
&&
1247 dst_stride
== row_size
) {
1248 memcpy(dst
, src
, row_size
* height
);
1250 for (int i
= 0; i
< height
; i
++) {
1251 memcpy(dst
, src
, row_size
);
1257 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1258 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1260 /* Don't forget to copy the stencil data over, too. We could have skipped
1261 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1262 * shuffling the two data sources in/out of temporary storage instead of
1263 * the direct mapping we get this way.
1265 if (dst_mt
->stencil_mt
) {
1266 assert(src_mt
->stencil_mt
);
1267 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1268 level
, slice
, width
, height
);
1273 intel_miptree_copy_slice(struct brw_context
*brw
,
1274 struct intel_mipmap_tree
*dst_mt
,
1275 struct intel_mipmap_tree
*src_mt
,
1281 mesa_format format
= src_mt
->format
;
1282 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1283 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1291 assert(depth
< src_mt
->level
[level
].depth
);
1292 assert(src_mt
->format
== dst_mt
->format
);
1294 if (dst_mt
->compressed
) {
1296 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1297 height
= ALIGN_NPOT(height
, j
) / j
;
1298 width
= ALIGN_NPOT(width
, i
) / i
;
1301 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1302 * below won't apply since we can't do the depth's Y tiling or the
1303 * stencil's W tiling in the blitter.
1305 if (src_mt
->stencil_mt
) {
1306 intel_miptree_copy_slice_sw(brw
,
1313 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1314 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1315 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1317 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1318 _mesa_get_format_name(src_mt
->format
),
1319 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1320 _mesa_get_format_name(dst_mt
->format
),
1321 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1324 if (!intel_miptree_blit(brw
,
1325 src_mt
, level
, slice
, 0, 0, false,
1326 dst_mt
, level
, slice
, 0, 0, false,
1327 width
, height
, GL_COPY
)) {
1328 perf_debug("miptree validate blit for %s failed\n",
1329 _mesa_get_format_name(format
));
1331 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1337 * Copies the image's current data to the given miptree, and associates that
1338 * miptree with the image.
1340 * If \c invalidate is true, then the actual image data does not need to be
1341 * copied, but the image still needs to be associated to the new miptree (this
1342 * is set to true if we're about to clear the image).
1345 intel_miptree_copy_teximage(struct brw_context
*brw
,
1346 struct intel_texture_image
*intelImage
,
1347 struct intel_mipmap_tree
*dst_mt
,
1350 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1351 struct intel_texture_object
*intel_obj
=
1352 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1353 int level
= intelImage
->base
.Base
.Level
;
1354 int face
= intelImage
->base
.Base
.Face
;
1357 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1358 depth
= intelImage
->base
.Base
.Height
;
1360 depth
= intelImage
->base
.Base
.Depth
;
1363 for (int slice
= 0; slice
< depth
; slice
++) {
1364 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1368 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1369 intel_obj
->needs_validate
= true;
1373 intel_miptree_init_mcs(struct brw_context
*brw
,
1374 struct intel_mipmap_tree
*mt
,
1377 assert(mt
->mcs_buf
!= NULL
);
1379 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1381 * When MCS buffer is enabled and bound to MSRT, it is required that it
1382 * is cleared prior to any rendering.
1384 * Since we don't use the MCS buffer for any purpose other than rendering,
1385 * it makes sense to just clear it immediately upon allocation.
1387 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1389 const int ret
= drm_bacon_gem_bo_map_gtt(mt
->mcs_buf
->bo
);
1390 if (unlikely(ret
)) {
1391 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1392 drm_bacon_bo_unreference(mt
->mcs_buf
->bo
);
1396 void *data
= mt
->mcs_buf
->bo
->virtual;
1397 memset(data
, init_value
, mt
->mcs_buf
->size
);
1398 drm_bacon_bo_unmap(mt
->mcs_buf
->bo
);
1401 static struct intel_miptree_aux_buffer
*
1402 intel_mcs_miptree_buf_create(struct brw_context
*brw
,
1403 struct intel_mipmap_tree
*mt
,
1406 unsigned mcs_height
,
1407 uint32_t layout_flags
)
1409 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1410 struct intel_mipmap_tree
*temp_mt
;
1415 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1417 * "The MCS surface must be stored as Tile Y."
1419 layout_flags
|= MIPTREE_LAYOUT_TILING_Y
;
1420 temp_mt
= miptree_create(brw
,
1428 0 /* num_samples */,
1435 buf
->bo
= temp_mt
->bo
;
1436 buf
->offset
= temp_mt
->offset
;
1437 buf
->size
= temp_mt
->total_height
* temp_mt
->pitch
;
1438 buf
->pitch
= temp_mt
->pitch
;
1439 buf
->qpitch
= temp_mt
->qpitch
;
1441 /* Just hang on to the BO which backs the AUX buffer; the rest of the miptree
1442 * structure should go away. We use miptree create simply as a means to make
1443 * sure all the constraints for the buffer are satisfied.
1445 drm_bacon_bo_reference(temp_mt
->bo
);
1446 intel_miptree_release(&temp_mt
);
1452 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1453 struct intel_mipmap_tree
*mt
,
1456 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1457 assert(mt
->mcs_buf
== NULL
);
1458 assert((mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
) == 0);
1460 /* Choose the correct format for the MCS buffer. All that really matters
1461 * is that we allocate the right buffer size, since we'll always be
1462 * accessing this miptree using MCS-specific hardware mechanisms, which
1463 * infer the correct format based on num_samples.
1466 switch (num_samples
) {
1469 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1472 format
= MESA_FORMAT_R_UNORM8
;
1475 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1476 * for each sample, plus 8 padding bits).
1478 format
= MESA_FORMAT_R_UINT32
;
1481 /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
1484 format
= MESA_FORMAT_RG_UINT32
;
1487 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1491 intel_mcs_miptree_buf_create(brw
, mt
,
1494 mt
->logical_height0
,
1495 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
);
1499 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1501 /* Multisampled miptrees are only supported for single level. */
1502 assert(mt
->first_level
== 0);
1503 intel_miptree_set_fast_clear_state(brw
, mt
, mt
->first_level
, 0,
1505 INTEL_FAST_CLEAR_STATE_CLEAR
);
1512 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1513 struct intel_mipmap_tree
*mt
,
1514 bool is_lossless_compressed
)
1516 assert(mt
->mcs_buf
== NULL
);
1517 assert(!(mt
->aux_disable
& (INTEL_AUX_DISABLE_MCS
| INTEL_AUX_DISABLE_CCS
)));
1519 struct isl_surf temp_main_surf
;
1520 struct isl_surf temp_ccs_surf
;
1522 /* Create first an ISL presentation for the main color surface and let ISL
1523 * calculate equivalent CCS surface against it.
1525 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1526 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_ccs_surf
))
1529 assert(temp_ccs_surf
.size
&&
1530 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1532 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1536 buf
->size
= temp_ccs_surf
.size
;
1537 buf
->pitch
= temp_ccs_surf
.row_pitch
;
1538 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(&temp_ccs_surf
);
1540 /* In case of compression mcs buffer needs to be initialised requiring the
1541 * buffer to be immediately mapped to cpu space for writing. Therefore do
1542 * not use the gpu access flag which can cause an unnecessary delay if the
1543 * backing pages happened to be just used by the GPU.
1545 const uint32_t alloc_flags
=
1546 is_lossless_compressed
? 0 : BO_ALLOC_FOR_RENDER
;
1547 uint32_t tiling
= I915_TILING_Y
;
1548 unsigned long pitch
;
1550 /* ISL has stricter set of alignment rules then the drm allocator.
1551 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1552 * trying to recalculate based on different format block sizes.
1554 buf
->bo
= drm_bacon_bo_alloc_tiled(brw
->bufmgr
, "ccs-miptree",
1555 buf
->pitch
, buf
->size
/ buf
->pitch
,
1556 1, &tiling
, &pitch
, alloc_flags
);
1558 assert(pitch
== buf
->pitch
);
1559 assert(tiling
== I915_TILING_Y
);
1567 /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
1568 * used for lossless compression which requires similar initialisation
1569 * as multi-sample compression.
1571 if (is_lossless_compressed
) {
1572 /* Hardware sets the auxiliary buffer to all zeroes when it does full
1573 * resolve. Initialize it accordingly in case the first renderer is
1574 * cpu (or other none compression aware party).
1576 * This is also explicitly stated in the spec (MCS Buffer for Render
1578 * "If Software wants to enable Color Compression without Fast clear,
1579 * Software needs to initialize MCS with zeros."
1581 intel_miptree_init_mcs(brw
, mt
, 0);
1582 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_CMS
;
1589 * Helper for intel_miptree_alloc_hiz() that sets
1590 * \c mt->level[level].has_hiz. Return true if and only if
1591 * \c has_hiz was set.
1594 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1595 struct intel_mipmap_tree
*mt
,
1598 assert(mt
->hiz_buf
);
1600 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1601 uint32_t width
= minify(mt
->physical_width0
, level
);
1602 uint32_t height
= minify(mt
->physical_height0
, level
);
1604 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1605 * and the height is 4 aligned. This allows our HiZ support
1606 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1607 * we can grow the width & height to allow the HiZ op to
1608 * force the proper size alignments.
1610 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1611 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1616 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1617 mt
->level
[level
].has_hiz
= true;
1623 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1624 * buffer dimensions and allocates a bo for the hiz buffer.
1626 static struct intel_miptree_hiz_buffer
*
1627 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1628 struct intel_mipmap_tree
*mt
)
1630 unsigned z_width
= mt
->logical_width0
;
1631 unsigned z_height
= mt
->logical_height0
;
1632 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1633 unsigned hz_width
, hz_height
;
1634 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1639 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1640 * adjustments required for Z_Height and Z_Width based on multisampling.
1642 switch (mt
->num_samples
) {
1656 unreachable("unsupported sample count");
1659 const unsigned vertical_align
= 8; /* 'j' in the docs */
1660 const unsigned H0
= z_height
;
1661 const unsigned h0
= ALIGN(H0
, vertical_align
);
1662 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1663 const unsigned Z0
= z_depth
;
1665 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1666 hz_width
= ALIGN(z_width
, 16);
1668 if (mt
->target
== GL_TEXTURE_3D
) {
1672 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1673 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1674 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1675 hz_height
+= h_i
* Z_i
;
1676 H_i
= minify(H_i
, 1);
1677 Z_i
= minify(Z_i
, 1);
1680 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1682 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1684 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1685 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1686 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1689 unsigned long pitch
;
1690 uint32_t tiling
= I915_TILING_Y
;
1691 buf
->aux_base
.bo
= drm_bacon_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1692 hz_width
, hz_height
, 1,
1694 BO_ALLOC_FOR_RENDER
);
1695 if (!buf
->aux_base
.bo
) {
1698 } else if (tiling
!= I915_TILING_Y
) {
1699 drm_bacon_bo_unreference(buf
->aux_base
.bo
);
1704 buf
->aux_base
.size
= hz_width
* hz_height
;
1705 buf
->aux_base
.pitch
= pitch
;
1712 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1713 * buffer dimensions and allocates a bo for the hiz buffer.
1715 static struct intel_miptree_hiz_buffer
*
1716 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1717 struct intel_mipmap_tree
*mt
)
1719 unsigned z_width
= mt
->logical_width0
;
1720 unsigned z_height
= mt
->logical_height0
;
1721 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1722 unsigned hz_width
, hz_height
;
1723 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1728 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1729 * adjustments required for Z_Height and Z_Width based on multisampling.
1732 switch (mt
->num_samples
) {
1746 unreachable("unsupported sample count");
1750 const unsigned vertical_align
= 8; /* 'j' in the docs */
1751 const unsigned H0
= z_height
;
1752 const unsigned h0
= ALIGN(H0
, vertical_align
);
1753 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1754 const unsigned Z0
= z_depth
;
1756 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1757 hz_width
= ALIGN(z_width
, 16);
1761 unsigned sum_h_i
= 0;
1762 unsigned hz_height_3d_sum
= 0;
1763 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1764 unsigned i
= level
- mt
->first_level
;
1765 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1766 /* sum(i=2 to m; h_i) */
1770 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1771 hz_height_3d_sum
+= h_i
* Z_i
;
1772 H_i
= minify(H_i
, 1);
1773 Z_i
= minify(Z_i
, 1);
1775 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1776 buf
->aux_base
.qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1778 if (mt
->target
== GL_TEXTURE_3D
) {
1779 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1780 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1782 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1783 hz_height
= DIV_ROUND_UP(buf
->aux_base
.qpitch
, 2 * 8) * 8 * Z0
;
1786 unsigned long pitch
;
1787 uint32_t tiling
= I915_TILING_Y
;
1788 buf
->aux_base
.bo
= drm_bacon_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1789 hz_width
, hz_height
, 1,
1791 BO_ALLOC_FOR_RENDER
);
1792 if (!buf
->aux_base
.bo
) {
1795 } else if (tiling
!= I915_TILING_Y
) {
1796 drm_bacon_bo_unreference(buf
->aux_base
.bo
);
1801 buf
->aux_base
.size
= hz_width
* hz_height
;
1802 buf
->aux_base
.pitch
= pitch
;
1808 static struct intel_miptree_hiz_buffer
*
1809 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1810 struct intel_mipmap_tree
*mt
)
1812 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1813 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1816 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1821 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1822 buf
->mt
= intel_miptree_create(brw
,
1828 mt
->logical_height0
,
1837 buf
->aux_base
.bo
= buf
->mt
->bo
;
1838 buf
->aux_base
.size
= buf
->mt
->total_height
* buf
->mt
->pitch
;
1839 buf
->aux_base
.pitch
= buf
->mt
->pitch
;
1841 /* On gen6 hiz is unconditionally laid out packing all slices
1842 * at each level-of-detail (LOD). This means there is no valid qpitch
1843 * setting. In fact, this is ignored when hardware is setup - there is no
1844 * hardware qpitch setting of hiz on gen6.
1846 buf
->aux_base
.qpitch
= 0;
1852 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1853 struct intel_mipmap_tree
*mt
)
1858 if (mt
->hiz_buf
!= NULL
)
1861 if (mt
->aux_disable
& INTEL_AUX_DISABLE_HIZ
)
1864 switch (mt
->format
) {
1865 case MESA_FORMAT_Z_FLOAT32
:
1866 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1867 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1868 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1869 case MESA_FORMAT_Z_UNORM16
:
1877 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1878 struct intel_mipmap_tree
*mt
)
1880 assert(mt
->hiz_buf
== NULL
);
1881 assert((mt
->aux_disable
& INTEL_AUX_DISABLE_HIZ
) == 0);
1883 if (brw
->gen
== 7) {
1884 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1885 } else if (brw
->gen
>= 8) {
1886 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1888 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1894 /* Mark that all slices need a HiZ resolve. */
1895 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1896 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1899 for (unsigned layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1900 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1901 exec_node_init(&m
->link
);
1904 m
->need
= BLORP_HIZ_OP_HIZ_RESOLVE
;
1906 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1914 * Can the miptree sample using the hiz buffer?
1917 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1918 struct intel_mipmap_tree
*mt
)
1920 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1921 * so keep things conservative for now and never enable it unless we're SKL+.
1931 /* It seems the hardware won't fallback to the depth buffer if some of the
1932 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1933 * of the texture to be HiZ enabled.
1935 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1936 if (!intel_miptree_level_has_hiz(mt
, level
))
1940 /* If compressed multisampling is enabled, then we use it for the auxiliary
1943 * From the BDW PRM (Volume 2d: Command Reference: Structures
1944 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1946 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1947 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1949 * There is no such blurb for 1D textures, but there is sufficient evidence
1950 * that this is broken on SKL+.
1952 return (mt
->num_samples
<= 1 &&
1953 mt
->target
!= GL_TEXTURE_3D
&&
1954 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1958 * Does the miptree slice have hiz enabled?
1961 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1963 intel_miptree_check_level_layer(mt
, level
, 0);
1964 return mt
->level
[level
].has_hiz
;
1968 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1972 if (!intel_miptree_level_has_hiz(mt
, level
))
1975 intel_resolve_map_set(&mt
->hiz_map
,
1976 level
, layer
, BLORP_HIZ_OP_HIZ_RESOLVE
);
1981 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1985 if (!intel_miptree_level_has_hiz(mt
, level
))
1988 intel_resolve_map_set(&mt
->hiz_map
,
1989 level
, layer
, BLORP_HIZ_OP_DEPTH_RESOLVE
);
1993 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1997 uint32_t end_layer
= mt
->level
[level
].depth
;
1999 for (layer
= 0; layer
< end_layer
; layer
++) {
2000 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
2005 intel_miptree_slice_resolve(struct brw_context
*brw
,
2006 struct intel_mipmap_tree
*mt
,
2009 enum blorp_hiz_op need
)
2011 intel_miptree_check_level_layer(mt
, level
, layer
);
2013 struct intel_resolve_map
*item
=
2014 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
2016 if (!item
|| item
->need
!= need
)
2019 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
2020 intel_resolve_map_remove(item
);
2025 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
2026 struct intel_mipmap_tree
*mt
,
2030 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2031 BLORP_HIZ_OP_HIZ_RESOLVE
);
2035 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
2036 struct intel_mipmap_tree
*mt
,
2040 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2041 BLORP_HIZ_OP_DEPTH_RESOLVE
);
2045 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
2046 struct intel_mipmap_tree
*mt
,
2047 enum blorp_hiz_op need
)
2049 bool did_resolve
= false;
2051 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
2052 if (map
->need
!= need
)
2055 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
2056 intel_resolve_map_remove(map
);
2064 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
2065 struct intel_mipmap_tree
*mt
)
2067 return intel_miptree_all_slices_resolve(brw
, mt
,
2068 BLORP_HIZ_OP_HIZ_RESOLVE
);
2072 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
2073 struct intel_mipmap_tree
*mt
)
2075 return intel_miptree_all_slices_resolve(brw
, mt
,
2076 BLORP_HIZ_OP_DEPTH_RESOLVE
);
2079 enum intel_fast_clear_state
2080 intel_miptree_get_fast_clear_state(const struct intel_mipmap_tree
*mt
,
2081 unsigned level
, unsigned layer
)
2083 intel_miptree_check_level_layer(mt
, level
, layer
);
2085 const struct intel_resolve_map
*item
=
2086 intel_resolve_map_const_get(&mt
->color_resolve_map
, level
, layer
);
2089 return INTEL_FAST_CLEAR_STATE_RESOLVED
;
2091 return item
->fast_clear_state
;
2095 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2096 const struct intel_mipmap_tree
*mt
,
2097 unsigned level
, unsigned layer
)
2100 if ((mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) || !mt
->mcs_buf
)
2103 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2104 assert(brw
->gen
>= 8 ||
2105 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2107 /* Compression of arrayed msaa surfaces is supported. */
2108 if (mt
->num_samples
> 1)
2111 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2112 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
2119 intel_miptree_set_fast_clear_state(const struct brw_context
*brw
,
2120 struct intel_mipmap_tree
*mt
,
2122 unsigned first_layer
,
2123 unsigned num_layers
,
2124 enum intel_fast_clear_state new_state
)
2126 /* Setting the state to resolved means removing the item from the list
2129 assert(new_state
!= INTEL_FAST_CLEAR_STATE_RESOLVED
);
2131 intel_miptree_check_color_resolve(brw
, mt
, level
, first_layer
);
2133 assert(first_layer
+ num_layers
<= mt
->physical_depth0
);
2135 for (unsigned i
= 0; i
< num_layers
; i
++)
2136 intel_resolve_map_set(&mt
->color_resolve_map
, level
,
2137 first_layer
+ i
, new_state
);
2141 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2142 unsigned start_level
, unsigned num_levels
,
2143 unsigned start_layer
, unsigned num_layers
)
2145 return intel_resolve_map_find_any(&mt
->color_resolve_map
,
2146 start_level
, num_levels
,
2147 start_layer
, num_layers
) != NULL
;
2151 intel_miptree_used_for_rendering(const struct brw_context
*brw
,
2152 struct intel_mipmap_tree
*mt
, unsigned level
,
2153 unsigned start_layer
, unsigned num_layers
)
2155 const bool is_lossless_compressed
=
2156 intel_miptree_is_lossless_compressed(brw
, mt
);
2158 for (unsigned i
= 0; i
< num_layers
; ++i
) {
2159 const enum intel_fast_clear_state fast_clear_state
=
2160 intel_miptree_get_fast_clear_state(mt
, level
, start_layer
+ i
);
2162 /* If the buffer was previously in fast clear state, change it to
2163 * unresolved state, since it won't be guaranteed to be clear after
2166 if (is_lossless_compressed
||
2167 fast_clear_state
== INTEL_FAST_CLEAR_STATE_CLEAR
) {
2168 intel_miptree_set_fast_clear_state(
2169 brw
, mt
, level
, start_layer
+ i
, 1,
2170 INTEL_FAST_CLEAR_STATE_UNRESOLVED
);
2176 intel_miptree_needs_color_resolve(const struct brw_context
*brw
,
2177 const struct intel_mipmap_tree
*mt
,
2180 if (mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
)
2183 const bool is_lossless_compressed
=
2184 intel_miptree_is_lossless_compressed(brw
, mt
);
2186 /* From gen9 onwards there is new compression scheme for single sampled
2187 * surfaces called "lossless compressed". These don't need to be always
2190 if ((flags
& INTEL_MIPTREE_IGNORE_CCS_E
) && is_lossless_compressed
)
2193 /* Fast color clear resolves only make sense for non-MSAA buffers. */
2194 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_NONE
&& !is_lossless_compressed
)
2201 intel_miptree_resolve_color(struct brw_context
*brw
,
2202 struct intel_mipmap_tree
*mt
, unsigned level
,
2203 unsigned start_layer
, unsigned num_layers
,
2206 intel_miptree_check_color_resolve(brw
, mt
, level
, start_layer
);
2208 if (!intel_miptree_needs_color_resolve(brw
, mt
, flags
))
2211 /* Arrayed fast clear is only supported for gen8+. */
2212 assert(brw
->gen
>= 8 || num_layers
== 1);
2214 bool resolved
= false;
2215 for (unsigned i
= 0; i
< num_layers
; ++i
) {
2216 intel_miptree_check_level_layer(mt
, level
, start_layer
+ i
);
2218 struct intel_resolve_map
*item
=
2219 intel_resolve_map_get(&mt
->color_resolve_map
, level
,
2223 assert(item
->fast_clear_state
!= INTEL_FAST_CLEAR_STATE_RESOLVED
);
2225 brw_blorp_resolve_color(brw
, mt
, level
, start_layer
);
2226 intel_resolve_map_remove(item
);
2235 intel_miptree_all_slices_resolve_color(struct brw_context
*brw
,
2236 struct intel_mipmap_tree
*mt
,
2239 if (!intel_miptree_needs_color_resolve(brw
, mt
, flags
))
2242 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
,
2243 &mt
->color_resolve_map
) {
2244 assert(map
->fast_clear_state
!= INTEL_FAST_CLEAR_STATE_RESOLVED
);
2246 brw_blorp_resolve_color(brw
, mt
, map
->level
, map
->layer
);
2247 intel_resolve_map_remove(map
);
2252 * Make it possible to share the BO backing the given miptree with another
2253 * process or another miptree.
2255 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2256 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2257 * ensure that no MCS buffer gets allocated in the future.
2259 * HiZ is similarly unsafe with shared buffers.
2262 intel_miptree_make_shareable(struct brw_context
*brw
,
2263 struct intel_mipmap_tree
*mt
)
2265 /* MCS buffers are also used for multisample buffers, but we can't resolve
2266 * away a multisample MCS buffer because it's an integral part of how the
2267 * pixel data is stored. Fortunately this code path should never be
2268 * reached for multisample buffers.
2270 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
|| mt
->num_samples
<= 1);
2273 intel_miptree_all_slices_resolve_color(brw
, mt
, 0);
2274 mt
->aux_disable
|= (INTEL_AUX_DISABLE_CCS
| INTEL_AUX_DISABLE_MCS
);
2275 drm_bacon_bo_unreference(mt
->mcs_buf
->bo
);
2279 /* Any pending MCS/CCS operations are no longer needed. Trying to
2280 * execute any will likely crash due to the missing aux buffer. So let's
2281 * delete all pending ops.
2283 exec_list_make_empty(&mt
->color_resolve_map
);
2287 mt
->aux_disable
|= INTEL_AUX_DISABLE_HIZ
;
2288 intel_miptree_all_slices_resolve_depth(brw
, mt
);
2289 intel_miptree_hiz_buffer_free(mt
->hiz_buf
);
2292 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2293 mt
->level
[l
].has_hiz
= false;
2296 /* Any pending HiZ operations are no longer needed. Trying to execute
2297 * any will likely crash due to the missing aux buffer. So let's delete
2300 exec_list_make_empty(&mt
->hiz_map
);
2306 * \brief Get pointer offset into stencil buffer.
2308 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2309 * must decode the tile's layout in software.
2312 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2314 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2316 * Even though the returned offset is always positive, the return type is
2318 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2319 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2322 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2324 uint32_t tile_size
= 4096;
2325 uint32_t tile_width
= 64;
2326 uint32_t tile_height
= 64;
2327 uint32_t row_size
= 64 * stride
;
2329 uint32_t tile_x
= x
/ tile_width
;
2330 uint32_t tile_y
= y
/ tile_height
;
2332 /* The byte's address relative to the tile's base addres. */
2333 uint32_t byte_x
= x
% tile_width
;
2334 uint32_t byte_y
= y
% tile_height
;
2336 uintptr_t u
= tile_y
* row_size
2337 + tile_x
* tile_size
2338 + 512 * (byte_x
/ 8)
2340 + 32 * ((byte_y
/ 4) % 2)
2341 + 16 * ((byte_x
/ 4) % 2)
2342 + 8 * ((byte_y
/ 2) % 2)
2343 + 4 * ((byte_x
/ 2) % 2)
2348 /* adjust for bit6 swizzling */
2349 if (((byte_x
/ 8) % 2) == 1) {
2350 if (((byte_y
/ 8) % 2) == 0) {
2362 intel_miptree_updownsample(struct brw_context
*brw
,
2363 struct intel_mipmap_tree
*src
,
2364 struct intel_mipmap_tree
*dst
)
2366 brw_blorp_blit_miptrees(brw
,
2367 src
, 0 /* level */, 0 /* layer */,
2368 src
->format
, SWIZZLE_XYZW
,
2369 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2371 src
->logical_width0
, src
->logical_height0
,
2373 dst
->logical_width0
, dst
->logical_height0
,
2374 GL_NEAREST
, false, false /*mirror x, y*/,
2377 if (src
->stencil_mt
) {
2378 brw_blorp_blit_miptrees(brw
,
2379 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2380 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2381 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2382 dst
->stencil_mt
->format
,
2384 src
->logical_width0
, src
->logical_height0
,
2386 dst
->logical_width0
, dst
->logical_height0
,
2387 GL_NEAREST
, false, false /*mirror x, y*/,
2388 false, false /* decode/encode srgb */);
2393 intel_update_r8stencil(struct brw_context
*brw
,
2394 struct intel_mipmap_tree
*mt
)
2396 assert(brw
->gen
>= 7);
2397 struct intel_mipmap_tree
*src
=
2398 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2399 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2402 if (!mt
->r8stencil_mt
) {
2403 const uint32_t r8stencil_flags
=
2404 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2405 MIPTREE_LAYOUT_DISABLE_AUX
;
2406 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD */
2407 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2409 MESA_FORMAT_R_UINT8
,
2412 src
->logical_width0
,
2413 src
->logical_height0
,
2414 src
->logical_depth0
,
2417 assert(mt
->r8stencil_mt
);
2420 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2422 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2423 const unsigned depth
= src
->level
[level
].depth
;
2424 const int layers_per_blit
=
2425 (dst
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
2426 dst
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) ?
2427 dst
->num_samples
: 1;
2429 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2430 brw_blorp_blit_miptrees(brw
,
2432 src
->format
, SWIZZLE_X
,
2433 dst
, level
, layers_per_blit
* layer
,
2434 MESA_FORMAT_R_UNORM8
,
2436 minify(src
->logical_width0
, level
),
2437 minify(src
->logical_height0
, level
),
2439 minify(dst
->logical_width0
, level
),
2440 minify(dst
->logical_height0
, level
),
2441 GL_NEAREST
, false, false /*mirror x, y*/,
2442 false, false /* decode/encode srgb */);
2446 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2447 src
->r8stencil_needs_update
= false;
2451 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2453 /* CPU accesses to color buffers don't understand fast color clears, so
2454 * resolve any pending fast color clears before we map.
2456 intel_miptree_all_slices_resolve_color(brw
, mt
, 0);
2458 drm_bacon_bo
*bo
= mt
->bo
;
2460 if (brw_batch_references(&brw
->batch
, bo
))
2461 intel_batchbuffer_flush(brw
);
2463 /* brw_bo_map() uses a WB mmaping of the buffer's backing storage. It
2464 * will utilize the CPU cache even if the buffer is incoherent with the
2465 * GPU (i.e. any writes will be stored in the cache and not flushed to
2466 * memory and so will be invisible to the GPU or display engine). This
2467 * is the majority of buffers on a !llc machine, but even on a llc
2468 * almost all scanouts are incoherent with the CPU. A WB write into the
2469 * backing storage of the current scanout will not be immediately
2470 * visible on the screen. The transfer from cache to screen is slow and
2471 * indeterministic causing visible glitching on the screen. Never use
2472 * this WB mapping for writes to an active scanout (reads are fine, so
2473 * long as cache consistency is maintained).
2475 if (mt
->tiling
!= I915_TILING_NONE
|| mt
->is_scanout
)
2476 drm_bacon_gem_bo_map_gtt(bo
);
2478 drm_bacon_bo_map(bo
, true);
2484 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2486 drm_bacon_bo_unmap(mt
->bo
);
2490 intel_miptree_map_gtt(struct brw_context
*brw
,
2491 struct intel_mipmap_tree
*mt
,
2492 struct intel_miptree_map
*map
,
2493 unsigned int level
, unsigned int slice
)
2495 unsigned int bw
, bh
;
2497 unsigned int image_x
, image_y
;
2498 intptr_t x
= map
->x
;
2499 intptr_t y
= map
->y
;
2501 /* For compressed formats, the stride is the number of bytes per
2502 * row of blocks. intel_miptree_get_image_offset() already does
2505 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2506 assert(y
% bh
== 0);
2507 assert(x
% bw
== 0);
2511 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2516 /* Note that in the case of cube maps, the caller must have passed the
2517 * slice number referencing the face.
2519 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2523 map
->stride
= mt
->pitch
;
2524 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2527 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2528 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2529 map
->x
, map
->y
, map
->w
, map
->h
,
2530 mt
, _mesa_get_format_name(mt
->format
),
2531 x
, y
, map
->ptr
, map
->stride
);
2535 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2537 intel_miptree_unmap_raw(mt
);
2541 intel_miptree_map_blit(struct brw_context
*brw
,
2542 struct intel_mipmap_tree
*mt
,
2543 struct intel_miptree_map
*map
,
2544 unsigned int level
, unsigned int slice
)
2546 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2547 /* first_level */ 0,
2551 MIPTREE_LAYOUT_TILING_NONE
);
2553 if (!map
->linear_mt
) {
2554 fprintf(stderr
, "Failed to allocate blit temporary\n");
2557 map
->stride
= map
->linear_mt
->pitch
;
2559 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2560 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2561 * invalidate is set, since we'll be writing the whole rectangle from our
2562 * temporary buffer back out.
2564 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2565 if (!intel_miptree_copy(brw
,
2566 mt
, level
, slice
, map
->x
, map
->y
,
2567 map
->linear_mt
, 0, 0, 0, 0,
2569 fprintf(stderr
, "Failed to blit\n");
2574 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
);
2576 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2577 map
->x
, map
->y
, map
->w
, map
->h
,
2578 mt
, _mesa_get_format_name(mt
->format
),
2579 level
, slice
, map
->ptr
, map
->stride
);
2584 intel_miptree_release(&map
->linear_mt
);
2590 intel_miptree_unmap_blit(struct brw_context
*brw
,
2591 struct intel_mipmap_tree
*mt
,
2592 struct intel_miptree_map
*map
,
2596 struct gl_context
*ctx
= &brw
->ctx
;
2598 intel_miptree_unmap_raw(map
->linear_mt
);
2600 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2601 bool ok
= intel_miptree_copy(brw
,
2602 map
->linear_mt
, 0, 0, 0, 0,
2603 mt
, level
, slice
, map
->x
, map
->y
,
2605 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2608 intel_miptree_release(&map
->linear_mt
);
2612 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2614 #if defined(USE_SSE41)
2616 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2617 struct intel_mipmap_tree
*mt
,
2618 struct intel_miptree_map
*map
,
2619 unsigned int level
, unsigned int slice
)
2621 assert(map
->mode
& GL_MAP_READ_BIT
);
2622 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2624 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2625 map
->x
, map
->y
, map
->w
, map
->h
,
2626 mt
, _mesa_get_format_name(mt
->format
),
2627 level
, slice
, map
->ptr
, map
->stride
);
2629 /* Map the original image */
2632 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2636 void *src
= intel_miptree_map_raw(brw
, mt
);
2642 src
+= image_y
* mt
->pitch
;
2643 src
+= image_x
* mt
->cpp
;
2645 /* Due to the pixel offsets for the particular image being mapped, our
2646 * src pointer may not be 16-byte aligned. However, if the pitch is
2647 * divisible by 16, then the amount by which it's misaligned will remain
2648 * consistent from row to row.
2650 assert((mt
->pitch
% 16) == 0);
2651 const int misalignment
= ((uintptr_t) src
) & 15;
2653 /* Create an untiled temporary buffer for the mapping. */
2654 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2656 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2658 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2659 /* Offset the destination so it has the same misalignment as src. */
2660 map
->ptr
= map
->buffer
+ misalignment
;
2662 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2664 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2665 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2666 void *src_ptr
= src
+ y
* mt
->pitch
;
2668 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2671 intel_miptree_unmap_raw(mt
);
2675 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2676 struct intel_mipmap_tree
*mt
,
2677 struct intel_miptree_map
*map
,
2681 _mesa_align_free(map
->buffer
);
2688 intel_miptree_map_s8(struct brw_context
*brw
,
2689 struct intel_mipmap_tree
*mt
,
2690 struct intel_miptree_map
*map
,
2691 unsigned int level
, unsigned int slice
)
2693 map
->stride
= map
->w
;
2694 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2698 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2699 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2700 * invalidate is set, since we'll be writing the whole rectangle from our
2701 * temporary buffer back out.
2703 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2704 uint8_t *untiled_s8_map
= map
->ptr
;
2705 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2706 unsigned int image_x
, image_y
;
2708 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2710 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2711 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2712 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2713 x
+ image_x
+ map
->x
,
2714 y
+ image_y
+ map
->y
,
2715 brw
->has_swizzling
);
2716 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2720 intel_miptree_unmap_raw(mt
);
2722 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2723 map
->x
, map
->y
, map
->w
, map
->h
,
2724 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2726 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2727 map
->x
, map
->y
, map
->w
, map
->h
,
2728 mt
, map
->ptr
, map
->stride
);
2733 intel_miptree_unmap_s8(struct brw_context
*brw
,
2734 struct intel_mipmap_tree
*mt
,
2735 struct intel_miptree_map
*map
,
2739 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2740 unsigned int image_x
, image_y
;
2741 uint8_t *untiled_s8_map
= map
->ptr
;
2742 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2744 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2746 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2747 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2748 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2749 image_x
+ x
+ map
->x
,
2750 image_y
+ y
+ map
->y
,
2751 brw
->has_swizzling
);
2752 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2756 intel_miptree_unmap_raw(mt
);
2763 intel_miptree_map_etc(struct brw_context
*brw
,
2764 struct intel_mipmap_tree
*mt
,
2765 struct intel_miptree_map
*map
,
2769 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2770 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2771 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2774 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2775 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2777 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2778 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2779 map
->w
, map
->h
, 1));
2780 map
->ptr
= map
->buffer
;
2784 intel_miptree_unmap_etc(struct brw_context
*brw
,
2785 struct intel_mipmap_tree
*mt
,
2786 struct intel_miptree_map
*map
,
2792 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2797 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2798 + image_y
* mt
->pitch
2799 + image_x
* mt
->cpp
;
2801 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2802 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2803 map
->ptr
, map
->stride
,
2806 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2807 map
->ptr
, map
->stride
,
2808 map
->w
, map
->h
, mt
->etc_format
);
2810 intel_miptree_unmap_raw(mt
);
2815 * Mapping function for packed depth/stencil miptrees backed by real separate
2816 * miptrees for depth and stencil.
2818 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2819 * separate from the depth buffer. Yet at the GL API level, we have to expose
2820 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2821 * be able to map that memory for texture storage and glReadPixels-type
2822 * operations. We give Mesa core that access by mallocing a temporary and
2823 * copying the data between the actual backing store and the temporary.
2826 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2827 struct intel_mipmap_tree
*mt
,
2828 struct intel_miptree_map
*map
,
2829 unsigned int level
, unsigned int slice
)
2831 struct intel_mipmap_tree
*z_mt
= mt
;
2832 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2833 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2834 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2836 map
->stride
= map
->w
* packed_bpp
;
2837 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2841 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2842 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2843 * invalidate is set, since we'll be writing the whole rectangle from our
2844 * temporary buffer back out.
2846 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2847 uint32_t *packed_map
= map
->ptr
;
2848 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2849 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2850 unsigned int s_image_x
, s_image_y
;
2851 unsigned int z_image_x
, z_image_y
;
2853 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2854 &s_image_x
, &s_image_y
);
2855 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2856 &z_image_x
, &z_image_y
);
2858 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2859 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2860 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2861 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2864 brw
->has_swizzling
);
2865 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2867 (map_x
+ z_image_x
));
2868 uint8_t s
= s_map
[s_offset
];
2869 uint32_t z
= z_map
[z_offset
];
2871 if (map_z32f_x24s8
) {
2872 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2873 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2875 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2880 intel_miptree_unmap_raw(s_mt
);
2881 intel_miptree_unmap_raw(z_mt
);
2883 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2885 map
->x
, map
->y
, map
->w
, map
->h
,
2886 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2887 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2888 map
->ptr
, map
->stride
);
2890 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2891 map
->x
, map
->y
, map
->w
, map
->h
,
2892 mt
, map
->ptr
, map
->stride
);
2897 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2898 struct intel_mipmap_tree
*mt
,
2899 struct intel_miptree_map
*map
,
2903 struct intel_mipmap_tree
*z_mt
= mt
;
2904 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2905 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2907 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2908 uint32_t *packed_map
= map
->ptr
;
2909 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2910 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2911 unsigned int s_image_x
, s_image_y
;
2912 unsigned int z_image_x
, z_image_y
;
2914 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2915 &s_image_x
, &s_image_y
);
2916 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2917 &z_image_x
, &z_image_y
);
2919 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2920 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2921 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2922 x
+ s_image_x
+ map
->x
,
2923 y
+ s_image_y
+ map
->y
,
2924 brw
->has_swizzling
);
2925 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2927 (x
+ z_image_x
+ map
->x
));
2929 if (map_z32f_x24s8
) {
2930 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2931 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2933 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2934 s_map
[s_offset
] = packed
>> 24;
2935 z_map
[z_offset
] = packed
;
2940 intel_miptree_unmap_raw(s_mt
);
2941 intel_miptree_unmap_raw(z_mt
);
2943 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2945 map
->x
, map
->y
, map
->w
, map
->h
,
2946 z_mt
, _mesa_get_format_name(z_mt
->format
),
2947 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2948 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2949 map
->ptr
, map
->stride
);
2956 * Create and attach a map to the miptree at (level, slice). Return the
2959 static struct intel_miptree_map
*
2960 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2969 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2974 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2975 mt
->level
[level
].slice
[slice
].map
= map
;
2987 * Release the map at (level, slice).
2990 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2994 struct intel_miptree_map
**map
;
2996 map
= &mt
->level
[level
].slice
[slice
].map
;
3002 can_blit_slice(struct intel_mipmap_tree
*mt
,
3003 unsigned int level
, unsigned int slice
)
3005 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3006 if (mt
->pitch
>= 32768)
3013 use_intel_mipree_map_blit(struct brw_context
*brw
,
3014 struct intel_mipmap_tree
*mt
,
3020 /* It's probably not worth swapping to the blit ring because of
3021 * all the overhead involved.
3023 !(mode
& GL_MAP_WRITE_BIT
) &&
3025 (mt
->tiling
== I915_TILING_X
||
3026 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3027 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
3028 /* Fast copy blit on skl+ supports all tiling formats. */
3030 can_blit_slice(mt
, level
, slice
))
3033 if (mt
->tiling
!= I915_TILING_NONE
&&
3034 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3035 assert(can_blit_slice(mt
, level
, slice
));
3043 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3044 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3045 * arithmetic overflow.
3047 * If you call this function and use \a out_stride, then you're doing pointer
3048 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3049 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3050 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3051 * which usually have type uint32_t or GLuint.
3054 intel_miptree_map(struct brw_context
*brw
,
3055 struct intel_mipmap_tree
*mt
,
3064 ptrdiff_t *out_stride
)
3066 struct intel_miptree_map
*map
;
3068 assert(mt
->num_samples
<= 1);
3070 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3077 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
3078 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3079 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
3082 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3083 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3084 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3085 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3086 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3087 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3088 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3089 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3090 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3091 #if defined(USE_SSE41)
3092 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3093 !mt
->compressed
&& cpu_has_sse4_1
&&
3094 (mt
->pitch
% 16 == 0)) {
3095 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3098 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3101 *out_ptr
= map
->ptr
;
3102 *out_stride
= map
->stride
;
3104 if (map
->ptr
== NULL
)
3105 intel_miptree_release_map(mt
, level
, slice
);
3109 intel_miptree_unmap(struct brw_context
*brw
,
3110 struct intel_mipmap_tree
*mt
,
3114 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3116 assert(mt
->num_samples
<= 1);
3121 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3122 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3124 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3125 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3126 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3127 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3128 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3129 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3130 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3131 } else if (map
->linear_mt
) {
3132 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3133 #if defined(USE_SSE41)
3134 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3135 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3138 intel_miptree_unmap_gtt(mt
);
3141 intel_miptree_release_map(mt
, level
, slice
);
3145 get_isl_surf_dim(GLenum target
)
3149 case GL_TEXTURE_1D_ARRAY
:
3150 return ISL_SURF_DIM_1D
;
3153 case GL_TEXTURE_2D_ARRAY
:
3154 case GL_TEXTURE_RECTANGLE
:
3155 case GL_TEXTURE_CUBE_MAP
:
3156 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3157 case GL_TEXTURE_2D_MULTISAMPLE
:
3158 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3159 case GL_TEXTURE_EXTERNAL_OES
:
3160 return ISL_SURF_DIM_2D
;
3163 return ISL_SURF_DIM_3D
;
3166 unreachable("Invalid texture target");
3170 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3175 case GL_TEXTURE_1D_ARRAY
:
3176 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3177 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3180 case GL_TEXTURE_2D_ARRAY
:
3181 case GL_TEXTURE_RECTANGLE
:
3182 case GL_TEXTURE_2D_MULTISAMPLE
:
3183 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3184 case GL_TEXTURE_EXTERNAL_OES
:
3185 return ISL_DIM_LAYOUT_GEN4_2D
;
3187 case GL_TEXTURE_CUBE_MAP
:
3188 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3189 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3190 ISL_DIM_LAYOUT_GEN4_2D
);
3193 return (devinfo
->gen
>= 9 ?
3194 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3197 unreachable("Invalid texture target");
3201 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3203 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3204 return ISL_TILING_W
;
3206 switch (mt
->tiling
) {
3207 case I915_TILING_NONE
:
3208 return ISL_TILING_LINEAR
;
3210 return ISL_TILING_X
;
3212 return ISL_TILING_Y0
;
3214 unreachable("Invalid tiling mode");
3220 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3221 const struct intel_mipmap_tree
*mt
,
3222 struct isl_surf
*surf
)
3224 surf
->dim
= get_isl_surf_dim(mt
->target
);
3225 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3226 mt
->tiling
, mt
->target
);
3228 if (mt
->num_samples
> 1) {
3229 switch (mt
->msaa_layout
) {
3230 case INTEL_MSAA_LAYOUT_IMS
:
3231 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3233 case INTEL_MSAA_LAYOUT_UMS
:
3234 case INTEL_MSAA_LAYOUT_CMS
:
3235 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3238 unreachable("Invalid MSAA layout");
3241 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3244 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3246 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3247 /* The ISL definition of row_pitch matches the surface state pitch field
3248 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3249 * the factor of 2 for W-tiling in row_pitch.
3251 surf
->row_pitch
= 2 * mt
->pitch
;
3253 surf
->row_pitch
= mt
->pitch
;
3256 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3258 if (brw
->gen
>= 9) {
3259 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3260 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3261 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3263 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3264 * alignment in terms of surface elements like we want.
3266 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3269 /* On earlier gens it's stored in pixels. */
3271 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3272 surf
->image_alignment_el
=
3273 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3276 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3277 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3278 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3279 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3280 surf
->logical_level0_px
.array_len
= 1;
3282 surf
->logical_level0_px
.depth
= 1;
3283 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3286 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3287 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3288 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3289 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3290 surf
->phys_level0_sa
.array_len
= 1;
3292 surf
->phys_level0_sa
.depth
= 1;
3293 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3296 surf
->levels
= mt
->last_level
+ 1;
3297 surf
->samples
= MAX2(mt
->num_samples
, 1);
3299 surf
->size
= 0; /* TODO */
3300 surf
->alignment
= 0; /* TODO */
3302 switch (surf
->dim_layout
) {
3303 case ISL_DIM_LAYOUT_GEN4_2D
:
3304 case ISL_DIM_LAYOUT_GEN4_3D
:
3305 if (brw
->gen
>= 9) {
3306 surf
->array_pitch_el_rows
= mt
->qpitch
;
3309 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3310 assert(mt
->qpitch
% bh
== 0);
3311 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3314 case ISL_DIM_LAYOUT_GEN9_1D
:
3315 surf
->array_pitch_el_rows
= 1;
3319 switch (mt
->array_layout
) {
3320 case ALL_LOD_IN_EACH_SLICE
:
3321 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3323 case ALL_SLICES_AT_EACH_LOD
:
3324 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3327 unreachable("Invalid array layout");
3330 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3331 switch (base_format
) {
3332 case GL_DEPTH_COMPONENT
:
3333 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3335 case GL_STENCIL_INDEX
:
3336 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3338 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3340 case GL_DEPTH_STENCIL
:
3341 /* In this case we only texture from the depth part */
3342 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3343 ISL_SURF_USAGE_TEXTURE_BIT
;
3346 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3347 if (brw
->format_supported_as_render_target
[mt
->format
])
3348 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3352 if (_mesa_is_cube_map_texture(mt
->target
))
3353 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3356 /* WARNING: THE SURFACE CREATED BY THIS FUNCTION IS NOT COMPLETE AND CANNOT BE
3357 * USED FOR ANY REAL CALCULATIONS. THE ONLY VALID USE OF SUCH A SURFACE IS TO
3358 * PASS IT INTO isl_surf_fill_state.
3361 intel_miptree_get_aux_isl_surf(struct brw_context
*brw
,
3362 const struct intel_mipmap_tree
*mt
,
3363 struct isl_surf
*surf
,
3364 enum isl_aux_usage
*usage
)
3366 uint32_t aux_pitch
, aux_qpitch
;
3368 aux_pitch
= mt
->mcs_buf
->pitch
;
3369 aux_qpitch
= mt
->mcs_buf
->qpitch
;
3371 if (mt
->num_samples
> 1) {
3372 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
3373 *usage
= ISL_AUX_USAGE_MCS
;
3374 } else if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
3375 assert(brw
->gen
>= 9);
3376 *usage
= ISL_AUX_USAGE_CCS_E
;
3377 } else if ((mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) == 0) {
3378 *usage
= ISL_AUX_USAGE_CCS_D
;
3380 unreachable("Invalid MCS miptree");
3382 } else if (mt
->hiz_buf
) {
3383 aux_pitch
= mt
->hiz_buf
->aux_base
.pitch
;
3384 aux_qpitch
= mt
->hiz_buf
->aux_base
.qpitch
;
3386 *usage
= ISL_AUX_USAGE_HIZ
;
3388 *usage
= ISL_AUX_USAGE_NONE
;
3392 /* Start with a copy of the original surface. */
3393 intel_miptree_get_isl_surf(brw
, mt
, surf
);
3395 /* Figure out the format and tiling of the auxiliary surface */
3397 case ISL_AUX_USAGE_NONE
:
3398 unreachable("Invalid auxiliary usage");
3400 case ISL_AUX_USAGE_HIZ
:
3401 isl_surf_get_hiz_surf(&brw
->isl_dev
, surf
, surf
);
3404 case ISL_AUX_USAGE_MCS
:
3407 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3408 * HALIGN 16 must be used."
3411 assert(mt
->halign
== 16);
3413 isl_surf_get_mcs_surf(&brw
->isl_dev
, surf
, surf
);
3416 case ISL_AUX_USAGE_CCS_D
:
3417 case ISL_AUX_USAGE_CCS_E
:
3419 * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
3421 * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
3423 * From the hardware spec for GEN9:
3425 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3426 * HALIGN 16 must be used."
3428 assert(mt
->num_samples
<= 1);
3430 assert(mt
->halign
== 16);
3432 isl_surf_get_ccs_surf(&brw
->isl_dev
, surf
, surf
);
3436 /* We want the pitch of the actual aux buffer. */
3437 surf
->row_pitch
= aux_pitch
;
3439 /* Auxiliary surfaces in ISL have compressed formats and array_pitch_el_rows
3440 * is in elements. This doesn't match intel_mipmap_tree::qpitch which is
3441 * in elements of the primary color surface so we have to divide by the
3442 * compression block height.
3444 surf
->array_pitch_el_rows
=
3445 aux_qpitch
/ isl_format_get_layout(surf
->format
)->bh
;
3448 union isl_color_value
3449 intel_miptree_get_isl_clear_color(struct brw_context
*brw
,
3450 const struct intel_mipmap_tree
*mt
)
3452 union isl_color_value clear_color
;
3454 if (_mesa_get_format_base_format(mt
->format
) == GL_DEPTH_COMPONENT
) {
3455 clear_color
.i32
[0] = mt
->depth_clear_value
;
3456 clear_color
.i32
[1] = 0;
3457 clear_color
.i32
[2] = 0;
3458 clear_color
.i32
[3] = 0;
3459 } else if (brw
->gen
>= 9) {
3460 clear_color
.i32
[0] = mt
->gen9_fast_clear_color
.i
[0];
3461 clear_color
.i32
[1] = mt
->gen9_fast_clear_color
.i
[1];
3462 clear_color
.i32
[2] = mt
->gen9_fast_clear_color
.i
[2];
3463 clear_color
.i32
[3] = mt
->gen9_fast_clear_color
.i
[3];
3464 } else if (_mesa_is_format_integer(mt
->format
)) {
3465 clear_color
.i32
[0] = (mt
->fast_clear_color_value
& (1u << 31)) != 0;
3466 clear_color
.i32
[1] = (mt
->fast_clear_color_value
& (1u << 30)) != 0;
3467 clear_color
.i32
[2] = (mt
->fast_clear_color_value
& (1u << 29)) != 0;
3468 clear_color
.i32
[3] = (mt
->fast_clear_color_value
& (1u << 28)) != 0;
3470 clear_color
.f32
[0] = (mt
->fast_clear_color_value
& (1u << 31)) != 0;
3471 clear_color
.f32
[1] = (mt
->fast_clear_color_value
& (1u << 30)) != 0;
3472 clear_color
.f32
[2] = (mt
->fast_clear_color_value
& (1u << 29)) != 0;
3473 clear_color
.f32
[3] = (mt
->fast_clear_color_value
& (1u << 28)) != 0;