2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_image.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
,
55 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
58 intel_miptree_alloc_aux(struct brw_context
*brw
,
59 struct intel_mipmap_tree
*mt
);
62 intel_miptree_supports_mcs(struct brw_context
*brw
,
63 const struct intel_mipmap_tree
*mt
)
65 /* MCS compression only applies to multisampled miptrees */
66 if (mt
->surf
.samples
<= 1)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(mt
->format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
100 intel_tiling_supports_ccs(const struct brw_context
*brw
,
101 enum isl_tiling tiling
)
103 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
104 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
106 * - Support is limited to tiled render targets.
108 * Gen9 changes the restriction to Y-tile only.
111 return tiling
== ISL_TILING_Y0
;
112 else if (brw
->gen
>= 7)
113 return tiling
!= ISL_TILING_LINEAR
;
119 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
120 * can be used. This doesn't (and should not) inspect any of the properties of
123 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
124 * beneath the "Fast Color Clear" bullet (p326):
126 * - Support is for non-mip-mapped and non-array surface types only.
128 * And then later, on p327:
130 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
133 * From the Skylake documentation, it is made clear that X-tiling is no longer
136 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
140 intel_miptree_supports_ccs(struct brw_context
*brw
,
141 const struct intel_mipmap_tree
*mt
)
143 /* MCS support does not exist prior to Gen7 */
147 /* This function applies only to non-multisampled render targets. */
148 if (mt
->surf
.samples
> 1)
151 /* MCS is only supported for color buffers */
152 switch (_mesa_get_format_base_format(mt
->format
)) {
153 case GL_DEPTH_COMPONENT
:
154 case GL_DEPTH_STENCIL
:
155 case GL_STENCIL_INDEX
:
159 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
162 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
163 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
164 mt
->surf
.logical_level0_px
.depth
> 1;
167 /* Multisample surfaces with the CMS layout are not layered surfaces,
168 * yet still have physical_depth0 > 1. Assert that we don't
169 * accidentally reject a multisampled surface here. We should have
170 * rejected it earlier by explicitly checking the sample count.
172 assert(mt
->surf
.samples
== 1);
175 /* Handle the hardware restrictions...
177 * All GENs have the following restriction: "MCS buffer for non-MSRT is
178 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
180 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
181 * Non-MultiSampler Render Target Restrictions) Support is for
182 * non-mip-mapped and non-array surface types only.
184 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
185 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
186 * surfaces are supported with MCS buffer layout with these alignments in
187 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
189 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
190 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
191 * surfaces are supported with MCS buffer layout with these alignments in
192 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
194 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
197 /* There's no point in using an MCS buffer if the surface isn't in a
200 if (!brw
->mesa_format_supports_render
[mt
->format
])
207 intel_tiling_supports_hiz(const struct brw_context
*brw
,
208 enum isl_tiling tiling
)
213 return tiling
== ISL_TILING_Y0
;
217 intel_miptree_supports_hiz(const struct brw_context
*brw
,
218 const struct intel_mipmap_tree
*mt
)
223 switch (mt
->format
) {
224 case MESA_FORMAT_Z_FLOAT32
:
225 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
226 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
227 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
228 case MESA_FORMAT_Z_UNORM16
:
236 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
237 const struct intel_mipmap_tree
*mt
)
242 /* For now compression is only enabled for integer formats even though
243 * there exist supported floating point formats also. This is a heuristic
244 * decision based on current public benchmarks. In none of the cases these
245 * formats provided any improvement but a few cases were seen to regress.
246 * Hence these are left to to be enabled in the future when they are known
249 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
252 if (!intel_miptree_supports_ccs(brw
, mt
))
255 /* Many window system buffers are sRGB even if they are never rendered as
256 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
257 * surface is used as sRGB, we fall back to CCS_D.
259 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
260 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
261 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
265 * Determine depth format corresponding to a depth+stencil format,
266 * for separate stencil.
269 intel_depth_format_for_depthstencil_format(mesa_format format
) {
271 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
272 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
273 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
274 return MESA_FORMAT_Z_FLOAT32
;
281 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
282 unsigned depth0
, struct intel_mipmap_level
*table
)
284 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
286 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
288 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
289 if (!table
[level
].slice
)
296 for (unsigned level
= first_level
; level
<= last_level
; level
++)
297 free(table
[level
].slice
);
303 needs_separate_stencil(const struct brw_context
*brw
,
304 struct intel_mipmap_tree
*mt
,
307 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
310 if (brw
->must_use_separate_stencil
)
313 return brw
->has_separate_stencil
&&
314 intel_miptree_supports_hiz(brw
, mt
);
318 * Choose the aux usage for this miptree. This function must be called fairly
319 * late in the miptree create process after we have a tiling.
322 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
323 struct intel_mipmap_tree
*mt
)
325 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
327 if (intel_miptree_supports_mcs(brw
, mt
)) {
328 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
329 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
330 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
331 intel_miptree_supports_ccs(brw
, mt
)) {
332 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
333 intel_miptree_supports_ccs_e(brw
, mt
)) {
334 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
336 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
338 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
339 intel_miptree_supports_hiz(brw
, mt
)) {
340 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
343 /* We can do fast-clear on all auxiliary surface types that are
344 * allocated through the normal texture creation paths.
346 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
347 mt
->supports_fast_clear
= true;
352 * Choose an appropriate uncompressed format for a requested
353 * compressed format, if unsupported.
356 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
358 /* No need to lower ETC formats on these platforms,
359 * they are supported natively.
361 if (brw
->gen
>= 8 || brw
->is_baytrail
)
365 case MESA_FORMAT_ETC1_RGB8
:
366 return MESA_FORMAT_R8G8B8X8_UNORM
;
367 case MESA_FORMAT_ETC2_RGB8
:
368 return MESA_FORMAT_R8G8B8X8_UNORM
;
369 case MESA_FORMAT_ETC2_SRGB8
:
370 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
371 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
372 return MESA_FORMAT_B8G8R8A8_SRGB
;
373 case MESA_FORMAT_ETC2_RGBA8_EAC
:
374 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
375 return MESA_FORMAT_R8G8B8A8_UNORM
;
376 case MESA_FORMAT_ETC2_R11_EAC
:
377 return MESA_FORMAT_R_UNORM16
;
378 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
379 return MESA_FORMAT_R_SNORM16
;
380 case MESA_FORMAT_ETC2_RG11_EAC
:
381 return MESA_FORMAT_R16G16_UNORM
;
382 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
383 return MESA_FORMAT_R16G16_SNORM
;
385 /* Non ETC1 / ETC2 format */
391 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
393 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
394 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
396 return mt
->surf
.logical_level0_px
.array_len
;
400 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
402 /* In case of physical dimensions one needs to consider also the layout.
403 * See isl_calc_phys_level0_extent_sa().
405 if (surf
->dim
!= ISL_SURF_DIM_3D
)
406 return surf
->phys_level0_sa
.array_len
;
408 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
409 return minify(surf
->phys_level0_sa
.array_len
, level
);
411 return minify(surf
->phys_level0_sa
.depth
, level
);
414 /** \brief Assert that the level and layer are valid for the miptree. */
416 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
424 assert(level
>= mt
->first_level
);
425 assert(level
<= mt
->last_level
);
426 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
429 static enum isl_aux_state
**
430 create_aux_state_map(struct intel_mipmap_tree
*mt
,
431 enum isl_aux_state initial
)
433 const uint32_t levels
= mt
->last_level
+ 1;
435 uint32_t total_slices
= 0;
436 for (uint32_t level
= 0; level
< levels
; level
++)
437 total_slices
+= brw_get_num_logical_layers(mt
, level
);
439 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
441 /* We're going to allocate a single chunk of data for both the per-level
442 * reference array and the arrays of aux_state. This makes cleanup
443 * significantly easier.
445 const size_t total_size
= per_level_array_size
+
446 total_slices
* sizeof(enum isl_aux_state
);
447 void *data
= malloc(total_size
);
451 enum isl_aux_state
**per_level_arr
= data
;
452 enum isl_aux_state
*s
= data
+ per_level_array_size
;
453 for (uint32_t level
= 0; level
< levels
; level
++) {
454 per_level_arr
[level
] = s
;
455 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
456 for (uint32_t a
= 0; a
< level_layers
; a
++)
459 assert((void *)s
== data
+ total_size
);
461 return per_level_arr
;
465 free_aux_state_map(enum isl_aux_state
**state
)
471 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
472 enum isl_tiling tiling
, unsigned samples
)
477 if (tiling
== ISL_TILING_LINEAR
)
480 /* If the width is much smaller than a tile, don't bother tiling. */
484 if (ALIGN(row_pitch
, 512) >= 32768) {
485 perf_debug("row pitch %u too large to blit, falling back to untiled",
494 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
495 enum isl_tiling tiling
)
497 /* If the BO is too large to fit in the aperture, we need to use the
498 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
499 * handle Y-tiling, so we need to fall back to X.
501 if (brw
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
502 tiling
== ISL_TILING_Y0
)
508 static struct intel_mipmap_tree
*
509 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
510 unsigned first_level
, unsigned last_level
,
511 unsigned width0
, unsigned height0
, unsigned depth0
,
512 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
513 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
514 unsigned row_pitch
, struct brw_bo
*bo
)
516 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
520 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
528 if (target
== GL_TEXTURE_CUBE_MAP
||
529 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
530 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
532 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
534 _mesa_enum_to_string(target
),
535 _mesa_get_format_name(format
),
536 num_samples
, width0
, height0
, depth0
,
537 first_level
, last_level
, mt
);
539 struct isl_surf_init_info init_info
= {
540 .dim
= get_isl_surf_dim(target
),
541 .format
= translate_tex_format(brw
, format
, false),
544 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
545 .levels
= last_level
- first_level
+ 1,
546 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
547 .samples
= num_samples
,
548 .row_pitch
= row_pitch
,
549 .usage
= isl_usage_flags
,
550 .tiling_flags
= tiling_flags
,
553 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
556 /* In case caller doesn't specifically request Y-tiling (needed
557 * unconditionally for depth), check for corner cases needing special
560 if (tiling_flags
& ~ISL_TILING_Y0_BIT
) {
561 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
562 mt
->surf
.tiling
, mt
->surf
.samples
)) {
563 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
564 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
566 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
567 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
568 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
573 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
574 * the size may not be multiple of row_pitch.
575 * See isl_apply_surface_padding().
577 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
578 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
581 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
583 isl_tiling_to_i915_tiling(
585 mt
->surf
.row_pitch
, alloc_flags
);
592 mt
->first_level
= first_level
;
593 mt
->last_level
= last_level
;
596 mt
->aux_state
= NULL
;
597 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
598 mt
->compressed
= _mesa_is_format_compressed(format
);
603 intel_miptree_release(&mt
);
608 make_separate_stencil_surface(struct brw_context
*brw
,
609 struct intel_mipmap_tree
*mt
)
611 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
612 0, mt
->surf
.levels
- 1,
613 mt
->surf
.logical_level0_px
.width
,
614 mt
->surf
.logical_level0_px
.height
,
615 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
616 mt
->surf
.logical_level0_px
.depth
:
617 mt
->surf
.logical_level0_px
.array_len
,
618 mt
->surf
.samples
, ISL_TILING_W_BIT
,
619 ISL_SURF_USAGE_STENCIL_BIT
|
620 ISL_SURF_USAGE_TEXTURE_BIT
,
621 BO_ALLOC_FOR_RENDER
, 0, NULL
);
626 mt
->stencil_mt
->r8stencil_needs_update
= true;
631 static struct intel_mipmap_tree
*
632 miptree_create(struct brw_context
*brw
,
641 enum intel_miptree_create_flags flags
)
643 if (format
== MESA_FORMAT_S_UINT8
)
644 return make_surface(brw
, target
, format
, first_level
, last_level
,
645 width0
, height0
, depth0
, num_samples
,
647 ISL_SURF_USAGE_STENCIL_BIT
|
648 ISL_SURF_USAGE_TEXTURE_BIT
,
653 const GLenum base_format
= _mesa_get_format_base_format(format
);
654 if ((base_format
== GL_DEPTH_COMPONENT
||
655 base_format
== GL_DEPTH_STENCIL
) &&
656 !(flags
& MIPTREE_CREATE_LINEAR
)) {
657 /* Fix up the Z miptree format for how we're splitting out separate
658 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
660 const mesa_format depth_only_format
=
661 intel_depth_format_for_depthstencil_format(format
);
662 struct intel_mipmap_tree
*mt
= make_surface(
663 brw
, target
, brw
->gen
>= 6 ? depth_only_format
: format
,
664 first_level
, last_level
,
665 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
666 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
667 BO_ALLOC_FOR_RENDER
, 0, NULL
);
669 if (needs_separate_stencil(brw
, mt
, format
) &&
670 !make_separate_stencil_surface(brw
, mt
)) {
671 intel_miptree_release(&mt
);
675 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
676 intel_miptree_choose_aux_usage(brw
, mt
);
681 mesa_format tex_format
= format
;
682 mesa_format etc_format
= MESA_FORMAT_NONE
;
683 uint32_t alloc_flags
= 0;
685 format
= intel_lower_compressed_format(brw
, format
);
687 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
689 if (flags
& MIPTREE_CREATE_BUSY
)
690 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
692 isl_tiling_flags_t tiling_flags
= (flags
& MIPTREE_CREATE_LINEAR
) ?
693 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
695 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
697 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
699 struct intel_mipmap_tree
*mt
= make_surface(
701 first_level
, last_level
,
702 width0
, height0
, depth0
,
703 num_samples
, tiling_flags
,
704 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
705 ISL_SURF_USAGE_TEXTURE_BIT
,
706 alloc_flags
, 0, NULL
);
710 mt
->etc_format
= etc_format
;
712 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
713 intel_miptree_choose_aux_usage(brw
, mt
);
718 struct intel_mipmap_tree
*
719 intel_miptree_create(struct brw_context
*brw
,
728 enum intel_miptree_create_flags flags
)
730 assert(num_samples
> 0);
732 struct intel_mipmap_tree
*mt
= miptree_create(
734 first_level
, last_level
,
735 width0
, height0
, depth0
, num_samples
,
742 if (!intel_miptree_alloc_aux(brw
, mt
)) {
743 intel_miptree_release(&mt
);
750 struct intel_mipmap_tree
*
751 intel_miptree_create_for_bo(struct brw_context
*brw
,
759 enum intel_miptree_create_flags flags
)
761 struct intel_mipmap_tree
*mt
;
762 uint32_t tiling
, swizzle
;
763 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
764 const GLenum base_format
= _mesa_get_format_base_format(format
);
766 if ((base_format
== GL_DEPTH_COMPONENT
||
767 base_format
== GL_DEPTH_STENCIL
)) {
768 const mesa_format depth_only_format
=
769 intel_depth_format_for_depthstencil_format(format
);
770 mt
= make_surface(brw
, target
,
771 brw
->gen
>= 6 ? depth_only_format
: format
,
772 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
773 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
774 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
778 brw_bo_reference(bo
);
780 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
781 intel_miptree_choose_aux_usage(brw
, mt
);
784 } else if (format
== MESA_FORMAT_S_UINT8
) {
785 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
786 0, 0, width
, height
, depth
, 1,
788 ISL_SURF_USAGE_STENCIL_BIT
|
789 ISL_SURF_USAGE_TEXTURE_BIT
,
790 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
794 assert(bo
->size
>= mt
->surf
.size
);
796 brw_bo_reference(bo
);
800 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
802 /* Nothing will be able to use this miptree with the BO if the offset isn't
805 if (tiling
!= I915_TILING_NONE
)
806 assert(offset
% 4096 == 0);
808 /* miptrees can't handle negative pitch. If you need flipping of images,
809 * that's outside of the scope of the mt.
813 /* The BO already has a tiling format and we shouldn't confuse the lower
814 * layers by making it try to find a tiling format again.
816 assert((flags
& MIPTREE_CREATE_LINEAR
) == 0);
818 mt
= make_surface(brw
, target
, format
,
819 0, 0, width
, height
, depth
, 1,
820 1lu << isl_tiling_from_i915_tiling(tiling
),
821 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
822 ISL_SURF_USAGE_TEXTURE_BIT
,
827 brw_bo_reference(bo
);
831 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
832 intel_miptree_choose_aux_usage(brw
, mt
);
834 if (!intel_miptree_alloc_aux(brw
, mt
)) {
835 intel_miptree_release(&mt
);
843 static struct intel_mipmap_tree
*
844 miptree_create_for_planar_image(struct brw_context
*brw
,
845 __DRIimage
*image
, GLenum target
)
847 const struct intel_image_format
*f
= image
->planar_format
;
848 struct intel_mipmap_tree
*planar_mt
= NULL
;
850 for (int i
= 0; i
< f
->nplanes
; i
++) {
851 const int index
= f
->planes
[i
].buffer_index
;
852 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
853 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
854 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
855 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
857 /* Disable creation of the texture's aux buffers because the driver
858 * exposes no EGL API to manage them. That is, there is no API for
859 * resolving the aux buffer's content to the main buffer nor for
860 * invalidating the aux buffer's content.
862 struct intel_mipmap_tree
*mt
=
863 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
864 image
->offsets
[index
],
866 image
->strides
[index
],
867 MIPTREE_CREATE_NO_AUX
);
876 planar_mt
->plane
[i
- 1] = mt
;
882 struct intel_mipmap_tree
*
883 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
884 __DRIimage
*image
, GLenum target
,
885 enum isl_colorspace colorspace
,
886 bool is_winsys_image
)
888 if (image
->planar_format
&& image
->planar_format
->nplanes
> 0) {
889 assert(colorspace
== ISL_COLORSPACE_NONE
||
890 colorspace
== ISL_COLORSPACE_YUV
);
891 return miptree_create_for_planar_image(brw
, image
, target
);
894 mesa_format format
= image
->format
;
895 switch (colorspace
) {
896 case ISL_COLORSPACE_NONE
:
897 /* Keep the image format unmodified */
900 case ISL_COLORSPACE_LINEAR
:
901 format
=_mesa_get_srgb_format_linear(format
);
904 case ISL_COLORSPACE_SRGB
:
905 format
=_mesa_get_linear_format_srgb(format
);
909 unreachable("Inalid colorspace for non-planar image");
912 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
913 /* The texture storage paths in core Mesa detect if the driver does not
914 * support the user-requested format, and then searches for a
915 * fallback format. The DRIimage code bypasses core Mesa, though. So we
916 * do the fallbacks here for important formats.
918 * We must support DRM_FOURCC_XBGR8888 textures because the Android
919 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
920 * the Chrome OS compositor consumes as dma_buf EGLImages.
922 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
925 if (!brw
->ctx
.TextureFormatSupported
[format
])
928 /* If this image comes in from a window system, we have different
929 * requirements than if it comes in via an EGL import operation. Window
930 * system images can use any form of auxiliary compression we wish because
931 * they get "flushed" before being handed off to the window system and we
932 * have the opportunity to do resolves. Window system buffers also may be
933 * used for scanout so we need to flag that appropriately.
935 const enum intel_miptree_create_flags mt_create_flags
=
936 is_winsys_image
? 0 : MIPTREE_CREATE_NO_AUX
;
938 /* Disable creation of the texture's aux buffers because the driver exposes
939 * no EGL API to manage them. That is, there is no API for resolving the aux
940 * buffer's content to the main buffer nor for invalidating the aux buffer's
943 struct intel_mipmap_tree
*mt
=
944 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
945 image
->offset
, image
->width
, image
->height
, 1,
946 image
->pitch
, mt_create_flags
);
951 mt
->level
[0].level_x
= image
->tile_x
;
952 mt
->level
[0].level_y
= image
->tile_y
;
954 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
955 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
956 * trouble resolving back to destination image due to alignment issues.
958 if (!brw
->has_surface_tile_offset
) {
959 uint32_t draw_x
, draw_y
;
960 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
962 if (draw_x
!= 0 || draw_y
!= 0) {
963 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
964 intel_miptree_release(&mt
);
969 /* If this is a window-system image, then we can no longer assume it's
970 * cache-coherent because it may suddenly get scanned out which destroys
974 image
->bo
->cache_coherent
= false;
980 * For a singlesample renderbuffer, this simply wraps the given BO with a
983 * For a multisample renderbuffer, this wraps the window system's
984 * (singlesample) BO with a singlesample miptree attached to the
985 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
986 * that will contain the actual rendering (which is lazily resolved to
987 * irb->singlesample_mt).
990 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
991 struct intel_renderbuffer
*irb
,
992 struct intel_mipmap_tree
*singlesample_mt
,
993 uint32_t width
, uint32_t height
,
996 struct intel_mipmap_tree
*multisample_mt
= NULL
;
997 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
998 mesa_format format
= rb
->Format
;
999 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1001 /* Only the front and back buffers, which are color buffers, are allocated
1002 * through the image loader.
1004 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1005 _mesa_get_format_base_format(format
) == GL_RGBA
);
1007 assert(singlesample_mt
);
1009 if (num_samples
== 1) {
1010 intel_miptree_release(&irb
->mt
);
1011 irb
->mt
= singlesample_mt
;
1013 assert(!irb
->singlesample_mt
);
1015 intel_miptree_release(&irb
->singlesample_mt
);
1016 irb
->singlesample_mt
= singlesample_mt
;
1019 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1020 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1021 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1026 if (!multisample_mt
)
1029 irb
->need_downsample
= false;
1030 intel_miptree_release(&irb
->mt
);
1031 irb
->mt
= multisample_mt
;
1037 intel_miptree_release(&irb
->mt
);
1041 struct intel_mipmap_tree
*
1042 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1046 uint32_t num_samples
)
1048 struct intel_mipmap_tree
*mt
;
1050 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1052 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1053 width
, height
, depth
, num_samples
,
1054 MIPTREE_CREATE_BUSY
);
1061 intel_miptree_release(&mt
);
1066 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1067 struct intel_mipmap_tree
*src
)
1072 intel_miptree_release(dst
);
1076 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1083 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1085 if (aux_buf
== NULL
)
1088 brw_bo_unreference(aux_buf
->bo
);
1094 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1099 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1100 if (--(*mt
)->refcount
<= 0) {
1103 DBG("%s deleting %p\n", __func__
, *mt
);
1105 brw_bo_unreference((*mt
)->bo
);
1106 intel_miptree_release(&(*mt
)->stencil_mt
);
1107 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1108 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1109 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1110 free_aux_state_map((*mt
)->aux_state
);
1112 intel_miptree_release(&(*mt
)->plane
[0]);
1113 intel_miptree_release(&(*mt
)->plane
[1]);
1115 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1116 free((*mt
)->level
[i
].slice
);
1126 intel_get_image_dims(struct gl_texture_image
*image
,
1127 int *width
, int *height
, int *depth
)
1129 switch (image
->TexObject
->Target
) {
1130 case GL_TEXTURE_1D_ARRAY
:
1131 /* For a 1D Array texture the OpenGL API will treat the image height as
1132 * the number of array slices. For Intel hardware, we treat the 1D array
1133 * as a 2D Array with a height of 1. So, here we want to swap image
1136 assert(image
->Depth
== 1);
1137 *width
= image
->Width
;
1139 *depth
= image
->Height
;
1141 case GL_TEXTURE_CUBE_MAP
:
1142 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1143 * though we really have 6 slices.
1145 assert(image
->Depth
== 1);
1146 *width
= image
->Width
;
1147 *height
= image
->Height
;
1151 *width
= image
->Width
;
1152 *height
= image
->Height
;
1153 *depth
= image
->Depth
;
1159 * Can the image be pulled into a unified mipmap tree? This mirrors
1160 * the completeness test in a lot of ways.
1162 * Not sure whether I want to pass gl_texture_image here.
1165 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1166 struct gl_texture_image
*image
)
1168 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1169 GLuint level
= intelImage
->base
.Base
.Level
;
1170 int width
, height
, depth
;
1172 /* glTexImage* choose the texture object based on the target passed in, and
1173 * objects can't change targets over their lifetimes, so this should be
1176 assert(image
->TexObject
->Target
== mt
->target
);
1178 mesa_format mt_format
= mt
->format
;
1179 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1180 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1181 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1182 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1183 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1184 mt_format
= mt
->etc_format
;
1186 if (image
->TexFormat
!= mt_format
)
1189 intel_get_image_dims(image
, &width
, &height
, &depth
);
1191 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1194 if (level
>= mt
->surf
.levels
)
1197 const unsigned level_depth
=
1198 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1199 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1200 mt
->surf
.logical_level0_px
.array_len
;
1202 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1203 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1204 depth
== level_depth
&&
1205 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1209 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1210 GLuint level
, GLuint slice
,
1211 GLuint
*x
, GLuint
*y
)
1213 if (level
== 0 && slice
== 0) {
1214 *x
= mt
->level
[0].level_x
;
1215 *y
= mt
->level
[0].level_y
;
1219 uint32_t x_offset_sa
, y_offset_sa
;
1221 /* Miptree itself can have an offset only if it represents a single
1222 * slice in an imported buffer object.
1223 * See intel_miptree_create_for_dri_image().
1225 assert(mt
->level
[0].level_x
== 0);
1226 assert(mt
->level
[0].level_y
== 0);
1228 /* Given level is relative to level zero while the miptree may be
1229 * represent just a subset of all levels starting from 'first_level'.
1231 assert(level
>= mt
->first_level
);
1232 level
-= mt
->first_level
;
1234 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1235 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1236 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1237 &x_offset_sa
, &y_offset_sa
);
1245 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1246 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1247 * and tile_h is set to 1.
1250 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1251 uint32_t *tile_w
, uint32_t *tile_h
)
1262 case ISL_TILING_LINEAR
:
1267 unreachable("not reached");
1273 * This function computes masks that may be used to select the bits of the X
1274 * and Y coordinates that indicate the offset within a tile. If the BO is
1275 * untiled, the masks are set to 0.
1278 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1279 uint32_t *mask_x
, uint32_t *mask_y
)
1281 uint32_t tile_w_bytes
, tile_h
;
1283 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1285 *mask_x
= tile_w_bytes
/ cpp
- 1;
1286 *mask_y
= tile_h
- 1;
1290 * Compute the offset (in bytes) from the start of the BO to the given x
1291 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1292 * multiples of the tile size.
1295 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1296 uint32_t x
, uint32_t y
)
1299 uint32_t pitch
= mt
->surf
.row_pitch
;
1301 switch (mt
->surf
.tiling
) {
1303 unreachable("not reached");
1304 case ISL_TILING_LINEAR
:
1305 return y
* pitch
+ x
* cpp
;
1307 assert((x
% (512 / cpp
)) == 0);
1308 assert((y
% 8) == 0);
1309 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1311 assert((x
% (128 / cpp
)) == 0);
1312 assert((y
% 32) == 0);
1313 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1318 * Rendering with tiled buffers requires that the base address of the buffer
1319 * be aligned to a page boundary. For renderbuffers, and sometimes with
1320 * textures, we may want the surface to point at a texture image level that
1321 * isn't at a page boundary.
1323 * This function returns an appropriately-aligned base offset
1324 * according to the tiling restrictions, plus any required x/y offset
1328 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1329 GLuint level
, GLuint slice
,
1334 uint32_t mask_x
, mask_y
;
1336 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1337 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1339 *tile_x
= x
& mask_x
;
1340 *tile_y
= y
& mask_y
;
1342 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1346 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1347 struct intel_mipmap_tree
*src_mt
,
1348 unsigned src_level
, unsigned src_layer
,
1349 struct intel_mipmap_tree
*dst_mt
,
1350 unsigned dst_level
, unsigned dst_layer
,
1351 unsigned width
, unsigned height
)
1354 ptrdiff_t src_stride
, dst_stride
;
1355 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1357 intel_miptree_map(brw
, src_mt
,
1358 src_level
, src_layer
,
1361 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1364 intel_miptree_map(brw
, dst_mt
,
1365 dst_level
, dst_layer
,
1368 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1372 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1373 _mesa_get_format_name(src_mt
->format
),
1374 src_mt
, src
, src_stride
,
1375 _mesa_get_format_name(dst_mt
->format
),
1376 dst_mt
, dst
, dst_stride
,
1379 int row_size
= cpp
* width
;
1380 if (src_stride
== row_size
&&
1381 dst_stride
== row_size
) {
1382 memcpy(dst
, src
, row_size
* height
);
1384 for (int i
= 0; i
< height
; i
++) {
1385 memcpy(dst
, src
, row_size
);
1391 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1392 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1394 /* Don't forget to copy the stencil data over, too. We could have skipped
1395 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1396 * shuffling the two data sources in/out of temporary storage instead of
1397 * the direct mapping we get this way.
1399 if (dst_mt
->stencil_mt
) {
1400 assert(src_mt
->stencil_mt
);
1401 intel_miptree_copy_slice_sw(brw
,
1402 src_mt
->stencil_mt
, src_level
, src_layer
,
1403 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1409 intel_miptree_copy_slice(struct brw_context
*brw
,
1410 struct intel_mipmap_tree
*src_mt
,
1411 unsigned src_level
, unsigned src_layer
,
1412 struct intel_mipmap_tree
*dst_mt
,
1413 unsigned dst_level
, unsigned dst_layer
)
1416 mesa_format format
= src_mt
->format
;
1417 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1418 src_level
- src_mt
->first_level
);
1419 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1420 src_level
- src_mt
->first_level
);
1422 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1423 src_level
- src_mt
->first_level
));
1425 assert(src_mt
->format
== dst_mt
->format
);
1427 if (dst_mt
->compressed
) {
1429 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1430 height
= ALIGN_NPOT(height
, j
) / j
;
1431 width
= ALIGN_NPOT(width
, i
) / i
;
1434 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1435 * below won't apply since we can't do the depth's Y tiling or the
1436 * stencil's W tiling in the blitter.
1438 if (src_mt
->stencil_mt
) {
1439 intel_miptree_copy_slice_sw(brw
,
1440 src_mt
, src_level
, src_layer
,
1441 dst_mt
, dst_level
, dst_layer
,
1446 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1447 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1449 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1452 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1453 _mesa_get_format_name(src_mt
->format
),
1454 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1455 _mesa_get_format_name(dst_mt
->format
),
1456 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1459 if (!intel_miptree_blit(brw
,
1460 src_mt
, src_level
, src_layer
, 0, 0, false,
1461 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1462 width
, height
, GL_COPY
)) {
1463 perf_debug("miptree validate blit for %s failed\n",
1464 _mesa_get_format_name(format
));
1466 intel_miptree_copy_slice_sw(brw
,
1467 src_mt
, src_level
, src_layer
,
1468 dst_mt
, dst_level
, dst_layer
,
1474 * Copies the image's current data to the given miptree, and associates that
1475 * miptree with the image.
1477 * If \c invalidate is true, then the actual image data does not need to be
1478 * copied, but the image still needs to be associated to the new miptree (this
1479 * is set to true if we're about to clear the image).
1482 intel_miptree_copy_teximage(struct brw_context
*brw
,
1483 struct intel_texture_image
*intelImage
,
1484 struct intel_mipmap_tree
*dst_mt
,
1487 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1488 struct intel_texture_object
*intel_obj
=
1489 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1490 int level
= intelImage
->base
.Base
.Level
;
1491 const unsigned face
= intelImage
->base
.Base
.Face
;
1492 unsigned start_layer
, end_layer
;
1494 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1496 assert(intelImage
->base
.Base
.Height
);
1498 end_layer
= intelImage
->base
.Base
.Height
- 1;
1499 } else if (face
> 0) {
1503 assert(intelImage
->base
.Base
.Depth
);
1505 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1509 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1510 intel_miptree_copy_slice(brw
,
1516 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1517 intel_obj
->needs_validate
= true;
1521 intel_miptree_init_mcs(struct brw_context
*brw
,
1522 struct intel_mipmap_tree
*mt
,
1525 assert(mt
->mcs_buf
!= NULL
);
1527 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1529 * When MCS buffer is enabled and bound to MSRT, it is required that it
1530 * is cleared prior to any rendering.
1532 * Since we don't use the MCS buffer for any purpose other than rendering,
1533 * it makes sense to just clear it immediately upon allocation.
1535 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1537 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1538 if (unlikely(map
== NULL
)) {
1539 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1540 brw_bo_unreference(mt
->mcs_buf
->bo
);
1545 memset(data
, init_value
, mt
->mcs_buf
->size
);
1546 brw_bo_unmap(mt
->mcs_buf
->bo
);
1549 static struct intel_miptree_aux_buffer
*
1550 intel_alloc_aux_buffer(struct brw_context
*brw
,
1552 const struct isl_surf
*aux_surf
,
1553 uint32_t alloc_flags
,
1554 struct intel_mipmap_tree
*mt
)
1556 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1560 buf
->size
= aux_surf
->size
;
1561 buf
->pitch
= aux_surf
->row_pitch
;
1562 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1564 /* ISL has stricter set of alignment rules then the drm allocator.
1565 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1566 * trying to recalculate based on different format block sizes.
1568 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1569 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1575 buf
->surf
= *aux_surf
;
1581 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1582 struct intel_mipmap_tree
*mt
,
1585 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1586 assert(mt
->mcs_buf
== NULL
);
1587 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1589 /* Multisampled miptrees are only supported for single level. */
1590 assert(mt
->first_level
== 0);
1591 enum isl_aux_state
**aux_state
=
1592 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1596 struct isl_surf temp_mcs_surf
;
1598 MAYBE_UNUSED
bool ok
=
1599 isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_mcs_surf
);
1602 /* Buffer needs to be initialised requiring the buffer to be immediately
1603 * mapped to cpu space for writing. Therefore do not use the gpu access
1604 * flag which can cause an unnecessary delay if the backing pages happened
1605 * to be just used by the GPU.
1607 const uint32_t alloc_flags
= 0;
1608 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1609 &temp_mcs_surf
, alloc_flags
, mt
);
1615 mt
->aux_state
= aux_state
;
1617 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1623 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1624 struct intel_mipmap_tree
*mt
)
1626 assert(mt
->mcs_buf
== NULL
);
1627 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1628 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1630 struct isl_surf temp_ccs_surf
;
1632 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
, 0))
1635 assert(temp_ccs_surf
.size
&&
1636 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1638 enum isl_aux_state
**aux_state
=
1639 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1643 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1644 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1646 * "If Software wants to enable Color Compression without Fast clear,
1647 * Software needs to initialize MCS with zeros."
1649 * A CCS value of 0 indicates that the corresponding block is in the
1650 * pass-through state which is what we want.
1652 * For CCS_D, on the other hand, we don't care as we're about to perform a
1653 * fast-clear operation. In that case, being hot in caches more useful.
1655 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1656 BO_ALLOC_ZEROED
: BO_ALLOC_FOR_RENDER
;
1657 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1658 &temp_ccs_surf
, alloc_flags
, mt
);
1664 mt
->aux_state
= aux_state
;
1670 * Helper for intel_miptree_alloc_hiz() that sets
1671 * \c mt->level[level].has_hiz. Return true if and only if
1672 * \c has_hiz was set.
1675 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1676 struct intel_mipmap_tree
*mt
,
1679 assert(mt
->hiz_buf
);
1680 assert(mt
->surf
.size
> 0);
1682 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1683 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1684 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1686 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1687 * and the height is 4 aligned. This allows our HiZ support
1688 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1689 * we can grow the width & height to allow the HiZ op to
1690 * force the proper size alignments.
1692 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1693 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1698 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1699 mt
->level
[level
].has_hiz
= true;
1704 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1705 struct intel_mipmap_tree
*mt
)
1707 assert(mt
->hiz_buf
== NULL
);
1708 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1710 enum isl_aux_state
**aux_state
=
1711 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1715 struct isl_surf temp_hiz_surf
;
1717 MAYBE_UNUSED
bool ok
=
1718 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
1721 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
1722 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1723 &temp_hiz_surf
, alloc_flags
, mt
);
1730 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1731 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1733 mt
->aux_state
= aux_state
;
1740 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1742 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1743 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1744 * compress clear color so we wait until an actual fast-clear to allocate it.
1747 intel_miptree_alloc_aux(struct brw_context
*brw
,
1748 struct intel_mipmap_tree
*mt
)
1750 switch (mt
->aux_usage
) {
1751 case ISL_AUX_USAGE_NONE
:
1754 case ISL_AUX_USAGE_HIZ
:
1755 assert(!_mesa_is_format_color_format(mt
->format
));
1756 if (!intel_miptree_alloc_hiz(brw
, mt
))
1760 case ISL_AUX_USAGE_MCS
:
1761 assert(_mesa_is_format_color_format(mt
->format
));
1762 assert(mt
->surf
.samples
> 1);
1763 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
1767 case ISL_AUX_USAGE_CCS_D
:
1768 /* Since CCS_D can only compress clear color so we wait until an actual
1769 * fast-clear to allocate it.
1773 case ISL_AUX_USAGE_CCS_E
:
1774 assert(_mesa_is_format_color_format(mt
->format
));
1775 assert(mt
->surf
.samples
== 1);
1776 if (!intel_miptree_alloc_ccs(brw
, mt
))
1781 unreachable("Invalid aux usage");
1786 * Can the miptree sample using the hiz buffer?
1789 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1790 struct intel_mipmap_tree
*mt
)
1792 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1793 * so keep things conservative for now and never enable it unless we're SKL+.
1803 /* It seems the hardware won't fallback to the depth buffer if some of the
1804 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1805 * of the texture to be HiZ enabled.
1807 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1808 if (!intel_miptree_level_has_hiz(mt
, level
))
1812 /* If compressed multisampling is enabled, then we use it for the auxiliary
1815 * From the BDW PRM (Volume 2d: Command Reference: Structures
1816 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1818 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1819 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1821 * There is no such blurb for 1D textures, but there is sufficient evidence
1822 * that this is broken on SKL+.
1824 return (mt
->surf
.samples
== 1 &&
1825 mt
->target
!= GL_TEXTURE_3D
&&
1826 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1830 * Does the miptree slice have hiz enabled?
1833 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1835 intel_miptree_check_level_layer(mt
, level
, 0);
1836 return mt
->level
[level
].has_hiz
;
1839 static inline uint32_t
1840 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1841 uint32_t start_level
, uint32_t num_levels
)
1843 assert(start_level
>= mt
->first_level
);
1844 assert(start_level
<= mt
->last_level
);
1846 if (num_levels
== INTEL_REMAINING_LAYERS
)
1847 num_levels
= mt
->last_level
- start_level
+ 1;
1848 /* Check for overflow */
1849 assert(start_level
+ num_levels
>= start_level
);
1850 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
1855 static inline uint32_t
1856 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
1857 uint32_t start_layer
, uint32_t num_layers
)
1859 assert(level
<= mt
->last_level
);
1861 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
1862 assert(start_layer
< total_num_layers
);
1863 if (num_layers
== INTEL_REMAINING_LAYERS
)
1864 num_layers
= total_num_layers
- start_layer
;
1865 /* Check for overflow */
1866 assert(start_layer
+ num_layers
>= start_layer
);
1867 assert(start_layer
+ num_layers
<= total_num_layers
);
1873 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1874 unsigned start_level
, unsigned num_levels
,
1875 unsigned start_layer
, unsigned num_layers
)
1877 assert(_mesa_is_format_color_format(mt
->format
));
1882 /* Clamp the level range to fit the miptree */
1883 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
1885 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1886 const uint32_t level
= start_level
+ l
;
1887 const uint32_t level_layers
=
1888 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
1889 for (unsigned a
= 0; a
< level_layers
; a
++) {
1890 enum isl_aux_state aux_state
=
1891 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
1892 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
1893 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
1902 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
1903 const struct intel_mipmap_tree
*mt
,
1904 unsigned level
, unsigned layer
)
1910 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
1911 assert(brw
->gen
>= 8 ||
1912 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
1914 /* Compression of arrayed msaa surfaces is supported. */
1915 if (mt
->surf
.samples
> 1)
1918 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
1919 assert(brw
->gen
>= 8 ||
1921 mt
->surf
.logical_level0_px
.depth
== 1 &&
1922 mt
->surf
.logical_level0_px
.array_len
== 1));
1928 static enum blorp_fast_clear_op
1929 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
1930 enum isl_aux_usage aux_usage
,
1931 bool fast_clear_supported
)
1933 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
1935 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
1937 assert(ccs_supported
== fast_clear_supported
);
1939 switch (aux_state
) {
1940 case ISL_AUX_STATE_CLEAR
:
1941 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1943 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1945 return BLORP_FAST_CLEAR_OP_NONE
;
1947 case ISL_AUX_STATE_PASS_THROUGH
:
1948 return BLORP_FAST_CLEAR_OP_NONE
;
1950 case ISL_AUX_STATE_RESOLVED
:
1951 case ISL_AUX_STATE_AUX_INVALID
:
1952 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1953 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1957 unreachable("Invalid aux state for CCS_D");
1960 static enum blorp_fast_clear_op
1961 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
1962 enum isl_aux_usage aux_usage
,
1963 bool fast_clear_supported
)
1965 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
1966 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
1967 aux_usage
== ISL_AUX_USAGE_CCS_D
||
1968 aux_usage
== ISL_AUX_USAGE_CCS_E
);
1970 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
1971 assert(fast_clear_supported
);
1973 switch (aux_state
) {
1974 case ISL_AUX_STATE_CLEAR
:
1975 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1976 if (fast_clear_supported
)
1977 return BLORP_FAST_CLEAR_OP_NONE
;
1978 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
1979 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
1981 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1983 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1984 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1985 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1986 else if (!fast_clear_supported
)
1987 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
1989 return BLORP_FAST_CLEAR_OP_NONE
;
1991 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1992 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1993 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1995 return BLORP_FAST_CLEAR_OP_NONE
;
1997 case ISL_AUX_STATE_PASS_THROUGH
:
1998 return BLORP_FAST_CLEAR_OP_NONE
;
2000 case ISL_AUX_STATE_RESOLVED
:
2001 case ISL_AUX_STATE_AUX_INVALID
:
2005 unreachable("Invalid aux state for CCS_E");
2009 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2010 struct intel_mipmap_tree
*mt
,
2011 uint32_t level
, uint32_t layer
,
2012 enum isl_aux_usage aux_usage
,
2013 bool fast_clear_supported
)
2015 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2017 enum blorp_fast_clear_op resolve_op
;
2018 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2019 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2020 fast_clear_supported
);
2022 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2023 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2024 fast_clear_supported
);
2027 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2028 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2029 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2031 switch (resolve_op
) {
2032 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2033 /* The CCS full resolve operation destroys the CCS and sets it to the
2034 * pass-through state. (You can also think of this as being both a
2035 * resolve and an ambiguate in one operation.)
2037 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2038 ISL_AUX_STATE_PASS_THROUGH
);
2041 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2042 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2043 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2047 unreachable("Invalid resolve op");
2053 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2054 struct intel_mipmap_tree
*mt
,
2055 uint32_t level
, uint32_t layer
,
2056 enum isl_aux_usage aux_usage
)
2058 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2059 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2060 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2062 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2064 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2065 switch (aux_state
) {
2066 case ISL_AUX_STATE_CLEAR
:
2067 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2068 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2069 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2071 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2072 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2073 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2074 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2075 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2076 ISL_AUX_STATE_PARTIAL_CLEAR
);
2080 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2081 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2082 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2083 break; /* Nothing to do */
2085 case ISL_AUX_STATE_PASS_THROUGH
:
2086 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2087 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2088 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2094 case ISL_AUX_STATE_RESOLVED
:
2095 case ISL_AUX_STATE_AUX_INVALID
:
2096 unreachable("Invalid aux state for CCS_E");
2099 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2100 /* CCS_D is a bit simpler */
2101 switch (aux_state
) {
2102 case ISL_AUX_STATE_CLEAR
:
2103 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2104 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2105 ISL_AUX_STATE_PARTIAL_CLEAR
);
2108 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2109 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2110 break; /* Nothing to do */
2112 case ISL_AUX_STATE_PASS_THROUGH
:
2116 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2117 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2118 case ISL_AUX_STATE_RESOLVED
:
2119 case ISL_AUX_STATE_AUX_INVALID
:
2120 unreachable("Invalid aux state for CCS_D");
2126 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2127 struct intel_mipmap_tree
*mt
,
2129 enum isl_aux_usage aux_usage
,
2130 bool fast_clear_supported
)
2132 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2134 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2135 case ISL_AUX_STATE_CLEAR
:
2136 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2137 if (!fast_clear_supported
) {
2138 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2139 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2140 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2144 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2145 break; /* Nothing to do */
2147 case ISL_AUX_STATE_RESOLVED
:
2148 case ISL_AUX_STATE_PASS_THROUGH
:
2149 case ISL_AUX_STATE_AUX_INVALID
:
2150 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2151 unreachable("Invalid aux state for MCS");
2156 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2157 struct intel_mipmap_tree
*mt
,
2159 enum isl_aux_usage aux_usage
)
2161 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2163 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2164 case ISL_AUX_STATE_CLEAR
:
2165 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2166 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2169 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2170 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2171 break; /* Nothing to do */
2173 case ISL_AUX_STATE_RESOLVED
:
2174 case ISL_AUX_STATE_PASS_THROUGH
:
2175 case ISL_AUX_STATE_AUX_INVALID
:
2176 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2177 unreachable("Invalid aux state for MCS");
2182 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2183 struct intel_mipmap_tree
*mt
,
2184 uint32_t level
, uint32_t layer
,
2185 enum isl_aux_usage aux_usage
,
2186 bool fast_clear_supported
)
2188 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2190 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2191 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2192 case ISL_AUX_STATE_CLEAR
:
2193 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2194 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2195 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2198 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2199 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2200 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2203 case ISL_AUX_STATE_PASS_THROUGH
:
2204 case ISL_AUX_STATE_RESOLVED
:
2207 case ISL_AUX_STATE_AUX_INVALID
:
2208 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2209 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2212 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2213 unreachable("Invalid HiZ state");
2216 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2217 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2220 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2221 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2222 ISL_AUX_STATE_RESOLVED
);
2225 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2226 /* The HiZ resolve operation is actually an ambiguate */
2227 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2228 ISL_AUX_STATE_PASS_THROUGH
);
2232 unreachable("Invalid HiZ op");
2238 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2239 struct intel_mipmap_tree
*mt
,
2240 uint32_t level
, uint32_t layer
,
2241 enum isl_aux_usage aux_usage
)
2243 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2245 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2246 case ISL_AUX_STATE_CLEAR
:
2247 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2248 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2249 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2252 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2253 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2254 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2255 break; /* Nothing to do */
2257 case ISL_AUX_STATE_RESOLVED
:
2258 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2259 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2260 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2262 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2263 ISL_AUX_STATE_AUX_INVALID
);
2267 case ISL_AUX_STATE_PASS_THROUGH
:
2268 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2269 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2270 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2274 case ISL_AUX_STATE_AUX_INVALID
:
2275 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2278 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2279 unreachable("Invalid HiZ state");
2284 intel_miptree_prepare_access(struct brw_context
*brw
,
2285 struct intel_mipmap_tree
*mt
,
2286 uint32_t start_level
, uint32_t num_levels
,
2287 uint32_t start_layer
, uint32_t num_layers
,
2288 enum isl_aux_usage aux_usage
,
2289 bool fast_clear_supported
)
2291 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2293 switch (mt
->aux_usage
) {
2294 case ISL_AUX_USAGE_NONE
:
2298 case ISL_AUX_USAGE_MCS
:
2299 assert(mt
->mcs_buf
);
2300 assert(start_level
== 0 && num_levels
== 1);
2301 const uint32_t level_layers
=
2302 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2303 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2304 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2305 aux_usage
, fast_clear_supported
);
2309 case ISL_AUX_USAGE_CCS_D
:
2310 case ISL_AUX_USAGE_CCS_E
:
2314 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2315 const uint32_t level
= start_level
+ l
;
2316 const uint32_t level_layers
=
2317 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2318 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2319 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2321 aux_usage
, fast_clear_supported
);
2326 case ISL_AUX_USAGE_HIZ
:
2327 assert(mt
->hiz_buf
);
2328 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2329 const uint32_t level
= start_level
+ l
;
2330 if (!intel_miptree_level_has_hiz(mt
, level
))
2333 const uint32_t level_layers
=
2334 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2335 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2336 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2337 aux_usage
, fast_clear_supported
);
2343 unreachable("Invalid aux usage");
2348 intel_miptree_finish_write(struct brw_context
*brw
,
2349 struct intel_mipmap_tree
*mt
, uint32_t level
,
2350 uint32_t start_layer
, uint32_t num_layers
,
2351 enum isl_aux_usage aux_usage
)
2353 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2355 switch (mt
->aux_usage
) {
2356 case ISL_AUX_USAGE_NONE
:
2360 case ISL_AUX_USAGE_MCS
:
2361 assert(mt
->mcs_buf
);
2362 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2363 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2368 case ISL_AUX_USAGE_CCS_D
:
2369 case ISL_AUX_USAGE_CCS_E
:
2373 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2374 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2379 case ISL_AUX_USAGE_HIZ
:
2380 if (!intel_miptree_level_has_hiz(mt
, level
))
2383 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2384 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2390 unreachable("Invavlid aux usage");
2395 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2396 uint32_t level
, uint32_t layer
)
2398 intel_miptree_check_level_layer(mt
, level
, layer
);
2400 if (_mesa_is_format_color_format(mt
->format
)) {
2401 assert(mt
->mcs_buf
!= NULL
);
2402 assert(mt
->surf
.samples
== 1 ||
2403 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2404 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2405 unreachable("Cannot get aux state for stencil");
2407 assert(intel_miptree_level_has_hiz(mt
, level
));
2410 return mt
->aux_state
[level
][layer
];
2414 intel_miptree_set_aux_state(struct brw_context
*brw
,
2415 struct intel_mipmap_tree
*mt
, uint32_t level
,
2416 uint32_t start_layer
, uint32_t num_layers
,
2417 enum isl_aux_state aux_state
)
2419 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2421 if (_mesa_is_format_color_format(mt
->format
)) {
2422 assert(mt
->mcs_buf
!= NULL
);
2423 assert(mt
->surf
.samples
== 1 ||
2424 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2425 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2426 unreachable("Cannot get aux state for stencil");
2428 assert(intel_miptree_level_has_hiz(mt
, level
));
2431 for (unsigned a
= 0; a
< num_layers
; a
++)
2432 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2435 /* On Gen9 color buffers may be compressed by the hardware (lossless
2436 * compression). There are, however, format restrictions and care needs to be
2437 * taken that the sampler engine is capable for re-interpreting a buffer with
2438 * format different the buffer was originally written with.
2440 * For example, SRGB formats are not compressible and the sampler engine isn't
2441 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2442 * color buffer needs to be resolved so that the sampling surface can be
2443 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2447 can_texture_with_ccs(struct brw_context
*brw
,
2448 struct intel_mipmap_tree
*mt
,
2449 enum isl_format view_format
)
2451 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2454 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2455 mt
->surf
.format
, view_format
)) {
2456 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2457 isl_format_get_layout(view_format
)->name
,
2458 _mesa_get_format_name(mt
->format
));
2466 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2467 struct intel_mipmap_tree
*mt
,
2468 enum isl_format view_format
)
2470 switch (mt
->aux_usage
) {
2471 case ISL_AUX_USAGE_HIZ
:
2472 if (intel_miptree_sample_with_hiz(brw
, mt
))
2473 return ISL_AUX_USAGE_HIZ
;
2476 case ISL_AUX_USAGE_MCS
:
2477 return ISL_AUX_USAGE_MCS
;
2479 case ISL_AUX_USAGE_CCS_D
:
2480 case ISL_AUX_USAGE_CCS_E
:
2481 if (mt
->mcs_buf
&& can_texture_with_ccs(brw
, mt
, view_format
))
2482 return ISL_AUX_USAGE_CCS_E
;
2489 return ISL_AUX_USAGE_NONE
;
2493 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2495 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2496 * values so sRGB curve application was a no-op for all fast-clearable
2499 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2500 * values, the hardware interprets the floats, not as what would be
2501 * returned from the sampler (or written by the shader), but as being
2502 * between format conversion and sRGB curve application. This means that
2503 * we can switch between sRGB and UNORM without having to whack the clear
2506 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2510 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2511 struct intel_mipmap_tree
*mt
,
2512 enum isl_format view_format
,
2513 uint32_t start_level
, uint32_t num_levels
,
2514 uint32_t start_layer
, uint32_t num_layers
,
2515 bool *aux_supported_out
)
2517 enum isl_aux_usage aux_usage
=
2518 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2519 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2521 /* Clear color is specified as ints or floats and the conversion is done by
2522 * the sampler. If we have a texture view, we would have to perform the
2523 * clear color conversion manually. Just disable clear color.
2525 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2526 clear_supported
= false;
2528 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2529 start_layer
, num_layers
,
2530 aux_usage
, clear_supported
);
2531 if (aux_supported_out
)
2532 *aux_supported_out
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2536 intel_miptree_prepare_texture(struct brw_context
*brw
,
2537 struct intel_mipmap_tree
*mt
,
2538 enum isl_format view_format
,
2539 bool *aux_supported_out
)
2541 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2542 0, INTEL_REMAINING_LEVELS
,
2543 0, INTEL_REMAINING_LAYERS
,
2548 intel_miptree_prepare_image(struct brw_context
*brw
,
2549 struct intel_mipmap_tree
*mt
)
2551 /* The data port doesn't understand any compression */
2552 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2553 0, INTEL_REMAINING_LAYERS
,
2554 ISL_AUX_USAGE_NONE
, false);
2558 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2559 struct intel_mipmap_tree
*mt
, uint32_t level
,
2560 uint32_t start_layer
, uint32_t num_layers
)
2562 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->surf
.format
, level
, 1,
2563 start_layer
, num_layers
, NULL
);
2567 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2568 struct intel_mipmap_tree
*mt
,
2569 bool srgb_enabled
, bool blend_enabled
)
2571 switch (mt
->aux_usage
) {
2572 case ISL_AUX_USAGE_MCS
:
2573 assert(mt
->mcs_buf
);
2574 return ISL_AUX_USAGE_MCS
;
2576 case ISL_AUX_USAGE_CCS_D
:
2577 return mt
->mcs_buf
? ISL_AUX_USAGE_CCS_D
: ISL_AUX_USAGE_NONE
;
2579 case ISL_AUX_USAGE_CCS_E
: {
2580 mesa_format mesa_format
=
2581 srgb_enabled
? mt
->format
:_mesa_get_srgb_format_linear(mt
->format
);
2582 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
2584 /* If the format supports CCS_E, then we can just use it */
2585 if (isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
))
2586 return ISL_AUX_USAGE_CCS_E
;
2588 /* Otherwise, we have to fall back to CCS_D */
2590 /* gen9 hardware technically supports non-0/1 clear colors with sRGB
2591 * formats. However, there are issues with blending where it doesn't
2592 * properly apply the sRGB curve to the clear color when blending.
2594 if (blend_enabled
&& isl_format_is_srgb(isl_format
) &&
2595 !isl_color_value_is_zero_one(mt
->fast_clear_color
, isl_format
))
2596 return ISL_AUX_USAGE_NONE
;
2598 return ISL_AUX_USAGE_CCS_D
;
2602 return ISL_AUX_USAGE_NONE
;
2607 intel_miptree_prepare_render(struct brw_context
*brw
,
2608 struct intel_mipmap_tree
*mt
, uint32_t level
,
2609 uint32_t start_layer
, uint32_t layer_count
,
2610 bool srgb_enabled
, bool blend_enabled
)
2612 enum isl_aux_usage aux_usage
=
2613 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
, blend_enabled
);
2614 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2615 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2619 intel_miptree_finish_render(struct brw_context
*brw
,
2620 struct intel_mipmap_tree
*mt
, uint32_t level
,
2621 uint32_t start_layer
, uint32_t layer_count
,
2622 bool srgb_enabled
, bool blend_enabled
)
2624 assert(_mesa_is_format_color_format(mt
->format
));
2626 enum isl_aux_usage aux_usage
=
2627 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
, blend_enabled
);
2628 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2633 intel_miptree_prepare_depth(struct brw_context
*brw
,
2634 struct intel_mipmap_tree
*mt
, uint32_t level
,
2635 uint32_t start_layer
, uint32_t layer_count
)
2637 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2638 mt
->aux_usage
, mt
->hiz_buf
!= NULL
);
2642 intel_miptree_finish_depth(struct brw_context
*brw
,
2643 struct intel_mipmap_tree
*mt
, uint32_t level
,
2644 uint32_t start_layer
, uint32_t layer_count
,
2647 if (depth_written
) {
2648 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2649 mt
->hiz_buf
!= NULL
);
2654 * Make it possible to share the BO backing the given miptree with another
2655 * process or another miptree.
2657 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2658 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2659 * ensure that no MCS buffer gets allocated in the future.
2661 * HiZ is similarly unsafe with shared buffers.
2664 intel_miptree_make_shareable(struct brw_context
*brw
,
2665 struct intel_mipmap_tree
*mt
)
2667 /* MCS buffers are also used for multisample buffers, but we can't resolve
2668 * away a multisample MCS buffer because it's an integral part of how the
2669 * pixel data is stored. Fortunately this code path should never be
2670 * reached for multisample buffers.
2672 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2673 mt
->surf
.samples
== 1);
2675 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2676 0, INTEL_REMAINING_LAYERS
,
2677 ISL_AUX_USAGE_NONE
, false);
2680 brw_bo_unreference(mt
->mcs_buf
->bo
);
2684 /* Any pending MCS/CCS operations are no longer needed. Trying to
2685 * execute any will likely crash due to the missing aux buffer. So let's
2686 * delete all pending ops.
2688 free(mt
->aux_state
);
2689 mt
->aux_state
= NULL
;
2693 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2696 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2697 mt
->level
[l
].has_hiz
= false;
2700 /* Any pending HiZ operations are no longer needed. Trying to execute
2701 * any will likely crash due to the missing aux buffer. So let's delete
2704 free(mt
->aux_state
);
2705 mt
->aux_state
= NULL
;
2708 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2709 mt
->supports_fast_clear
= false;
2714 * \brief Get pointer offset into stencil buffer.
2716 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2717 * must decode the tile's layout in software.
2720 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2722 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2724 * Even though the returned offset is always positive, the return type is
2726 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2727 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2730 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2732 uint32_t tile_size
= 4096;
2733 uint32_t tile_width
= 64;
2734 uint32_t tile_height
= 64;
2735 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2737 uint32_t tile_x
= x
/ tile_width
;
2738 uint32_t tile_y
= y
/ tile_height
;
2740 /* The byte's address relative to the tile's base addres. */
2741 uint32_t byte_x
= x
% tile_width
;
2742 uint32_t byte_y
= y
% tile_height
;
2744 uintptr_t u
= tile_y
* row_size
2745 + tile_x
* tile_size
2746 + 512 * (byte_x
/ 8)
2748 + 32 * ((byte_y
/ 4) % 2)
2749 + 16 * ((byte_x
/ 4) % 2)
2750 + 8 * ((byte_y
/ 2) % 2)
2751 + 4 * ((byte_x
/ 2) % 2)
2756 /* adjust for bit6 swizzling */
2757 if (((byte_x
/ 8) % 2) == 1) {
2758 if (((byte_y
/ 8) % 2) == 0) {
2770 intel_miptree_updownsample(struct brw_context
*brw
,
2771 struct intel_mipmap_tree
*src
,
2772 struct intel_mipmap_tree
*dst
)
2774 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2775 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2776 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2777 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2779 brw_blorp_blit_miptrees(brw
,
2780 src
, 0 /* level */, 0 /* layer */,
2781 src
->format
, SWIZZLE_XYZW
,
2782 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2785 GL_NEAREST
, false, false /*mirror x, y*/,
2788 if (src
->stencil_mt
) {
2789 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2790 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2791 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2792 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2794 brw_blorp_blit_miptrees(brw
,
2795 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2796 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2797 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2798 dst
->stencil_mt
->format
,
2801 GL_NEAREST
, false, false /*mirror x, y*/,
2802 false, false /* decode/encode srgb */);
2807 intel_update_r8stencil(struct brw_context
*brw
,
2808 struct intel_mipmap_tree
*mt
)
2810 assert(brw
->gen
>= 7);
2811 struct intel_mipmap_tree
*src
=
2812 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2813 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2816 assert(src
->surf
.size
> 0);
2818 if (!mt
->r8stencil_mt
) {
2819 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2820 mt
->r8stencil_mt
= make_surface(
2823 MESA_FORMAT_R_UINT8
,
2824 src
->first_level
, src
->last_level
,
2825 src
->surf
.logical_level0_px
.width
,
2826 src
->surf
.logical_level0_px
.height
,
2827 src
->surf
.dim
== ISL_SURF_DIM_3D
?
2828 src
->surf
.logical_level0_px
.depth
:
2829 src
->surf
.logical_level0_px
.array_len
,
2832 ISL_SURF_USAGE_TEXTURE_BIT
,
2833 BO_ALLOC_FOR_RENDER
, 0, NULL
);
2834 assert(mt
->r8stencil_mt
);
2837 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2839 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2840 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
2841 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
2842 src
->surf
.phys_level0_sa
.array_len
;
2844 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2845 brw_blorp_copy_miptrees(brw
,
2849 minify(src
->surf
.logical_level0_px
.width
,
2851 minify(src
->surf
.logical_level0_px
.height
,
2856 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2857 src
->r8stencil_needs_update
= false;
2861 intel_miptree_map_raw(struct brw_context
*brw
,
2862 struct intel_mipmap_tree
*mt
,
2865 struct brw_bo
*bo
= mt
->bo
;
2867 if (brw_batch_references(&brw
->batch
, bo
))
2868 intel_batchbuffer_flush(brw
);
2870 return brw_bo_map(brw
, bo
, mode
);
2874 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2876 brw_bo_unmap(mt
->bo
);
2880 intel_miptree_map_gtt(struct brw_context
*brw
,
2881 struct intel_mipmap_tree
*mt
,
2882 struct intel_miptree_map
*map
,
2883 unsigned int level
, unsigned int slice
)
2885 unsigned int bw
, bh
;
2887 unsigned int image_x
, image_y
;
2888 intptr_t x
= map
->x
;
2889 intptr_t y
= map
->y
;
2891 /* For compressed formats, the stride is the number of bytes per
2892 * row of blocks. intel_miptree_get_image_offset() already does
2895 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2896 assert(y
% bh
== 0);
2897 assert(x
% bw
== 0);
2901 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
2908 /* Note that in the case of cube maps, the caller must have passed the
2909 * slice number referencing the face.
2911 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2915 map
->stride
= mt
->surf
.row_pitch
;
2916 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2919 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2920 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2921 map
->x
, map
->y
, map
->w
, map
->h
,
2922 mt
, _mesa_get_format_name(mt
->format
),
2923 x
, y
, map
->ptr
, map
->stride
);
2927 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2929 intel_miptree_unmap_raw(mt
);
2933 intel_miptree_map_blit(struct brw_context
*brw
,
2934 struct intel_mipmap_tree
*mt
,
2935 struct intel_miptree_map
*map
,
2936 unsigned int level
, unsigned int slice
)
2938 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2939 /* first_level */ 0,
2943 MIPTREE_CREATE_LINEAR
);
2945 if (!map
->linear_mt
) {
2946 fprintf(stderr
, "Failed to allocate blit temporary\n");
2949 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
2951 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2952 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2953 * invalidate is set, since we'll be writing the whole rectangle from our
2954 * temporary buffer back out.
2956 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2957 if (!intel_miptree_copy(brw
,
2958 mt
, level
, slice
, map
->x
, map
->y
,
2959 map
->linear_mt
, 0, 0, 0, 0,
2961 fprintf(stderr
, "Failed to blit\n");
2966 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
2968 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2969 map
->x
, map
->y
, map
->w
, map
->h
,
2970 mt
, _mesa_get_format_name(mt
->format
),
2971 level
, slice
, map
->ptr
, map
->stride
);
2976 intel_miptree_release(&map
->linear_mt
);
2982 intel_miptree_unmap_blit(struct brw_context
*brw
,
2983 struct intel_mipmap_tree
*mt
,
2984 struct intel_miptree_map
*map
,
2988 struct gl_context
*ctx
= &brw
->ctx
;
2990 intel_miptree_unmap_raw(map
->linear_mt
);
2992 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2993 bool ok
= intel_miptree_copy(brw
,
2994 map
->linear_mt
, 0, 0, 0, 0,
2995 mt
, level
, slice
, map
->x
, map
->y
,
2997 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3000 intel_miptree_release(&map
->linear_mt
);
3004 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3006 #if defined(USE_SSE41)
3008 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3009 struct intel_mipmap_tree
*mt
,
3010 struct intel_miptree_map
*map
,
3011 unsigned int level
, unsigned int slice
)
3013 assert(map
->mode
& GL_MAP_READ_BIT
);
3014 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3016 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3017 map
->x
, map
->y
, map
->w
, map
->h
,
3018 mt
, _mesa_get_format_name(mt
->format
),
3019 level
, slice
, map
->ptr
, map
->stride
);
3021 /* Map the original image */
3024 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3028 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3034 src
+= image_y
* mt
->surf
.row_pitch
;
3035 src
+= image_x
* mt
->cpp
;
3037 /* Due to the pixel offsets for the particular image being mapped, our
3038 * src pointer may not be 16-byte aligned. However, if the pitch is
3039 * divisible by 16, then the amount by which it's misaligned will remain
3040 * consistent from row to row.
3042 assert((mt
->surf
.row_pitch
% 16) == 0);
3043 const int misalignment
= ((uintptr_t) src
) & 15;
3045 /* Create an untiled temporary buffer for the mapping. */
3046 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3048 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3050 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3051 /* Offset the destination so it has the same misalignment as src. */
3052 map
->ptr
= map
->buffer
+ misalignment
;
3054 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3056 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3057 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3058 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3060 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3063 intel_miptree_unmap_raw(mt
);
3067 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3068 struct intel_mipmap_tree
*mt
,
3069 struct intel_miptree_map
*map
,
3073 _mesa_align_free(map
->buffer
);
3080 intel_miptree_map_s8(struct brw_context
*brw
,
3081 struct intel_mipmap_tree
*mt
,
3082 struct intel_miptree_map
*map
,
3083 unsigned int level
, unsigned int slice
)
3085 map
->stride
= map
->w
;
3086 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3090 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3091 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3092 * invalidate is set, since we'll be writing the whole rectangle from our
3093 * temporary buffer back out.
3095 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3096 uint8_t *untiled_s8_map
= map
->ptr
;
3097 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3098 unsigned int image_x
, image_y
;
3100 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3102 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3103 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3104 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3105 x
+ image_x
+ map
->x
,
3106 y
+ image_y
+ map
->y
,
3107 brw
->has_swizzling
);
3108 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3112 intel_miptree_unmap_raw(mt
);
3114 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3115 map
->x
, map
->y
, map
->w
, map
->h
,
3116 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3118 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3119 map
->x
, map
->y
, map
->w
, map
->h
,
3120 mt
, map
->ptr
, map
->stride
);
3125 intel_miptree_unmap_s8(struct brw_context
*brw
,
3126 struct intel_mipmap_tree
*mt
,
3127 struct intel_miptree_map
*map
,
3131 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3132 unsigned int image_x
, image_y
;
3133 uint8_t *untiled_s8_map
= map
->ptr
;
3134 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3136 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3138 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3139 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3140 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3141 image_x
+ x
+ map
->x
,
3142 image_y
+ y
+ map
->y
,
3143 brw
->has_swizzling
);
3144 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3148 intel_miptree_unmap_raw(mt
);
3155 intel_miptree_map_etc(struct brw_context
*brw
,
3156 struct intel_mipmap_tree
*mt
,
3157 struct intel_miptree_map
*map
,
3161 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3162 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3163 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3166 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3167 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3169 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3170 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3171 map
->w
, map
->h
, 1));
3172 map
->ptr
= map
->buffer
;
3176 intel_miptree_unmap_etc(struct brw_context
*brw
,
3177 struct intel_mipmap_tree
*mt
,
3178 struct intel_miptree_map
*map
,
3184 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3189 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3190 + image_y
* mt
->surf
.row_pitch
3191 + image_x
* mt
->cpp
;
3193 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3194 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3195 map
->ptr
, map
->stride
,
3198 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3199 map
->ptr
, map
->stride
,
3200 map
->w
, map
->h
, mt
->etc_format
);
3202 intel_miptree_unmap_raw(mt
);
3207 * Mapping function for packed depth/stencil miptrees backed by real separate
3208 * miptrees for depth and stencil.
3210 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3211 * separate from the depth buffer. Yet at the GL API level, we have to expose
3212 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3213 * be able to map that memory for texture storage and glReadPixels-type
3214 * operations. We give Mesa core that access by mallocing a temporary and
3215 * copying the data between the actual backing store and the temporary.
3218 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3219 struct intel_mipmap_tree
*mt
,
3220 struct intel_miptree_map
*map
,
3221 unsigned int level
, unsigned int slice
)
3223 struct intel_mipmap_tree
*z_mt
= mt
;
3224 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3225 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3226 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3228 map
->stride
= map
->w
* packed_bpp
;
3229 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3233 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3234 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3235 * invalidate is set, since we'll be writing the whole rectangle from our
3236 * temporary buffer back out.
3238 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3239 uint32_t *packed_map
= map
->ptr
;
3240 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3241 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3242 unsigned int s_image_x
, s_image_y
;
3243 unsigned int z_image_x
, z_image_y
;
3245 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3246 &s_image_x
, &s_image_y
);
3247 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3248 &z_image_x
, &z_image_y
);
3250 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3251 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3252 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3253 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3256 brw
->has_swizzling
);
3257 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3258 (z_mt
->surf
.row_pitch
/ 4) +
3259 (map_x
+ z_image_x
));
3260 uint8_t s
= s_map
[s_offset
];
3261 uint32_t z
= z_map
[z_offset
];
3263 if (map_z32f_x24s8
) {
3264 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3265 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3267 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3272 intel_miptree_unmap_raw(s_mt
);
3273 intel_miptree_unmap_raw(z_mt
);
3275 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3277 map
->x
, map
->y
, map
->w
, map
->h
,
3278 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3279 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3280 map
->ptr
, map
->stride
);
3282 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3283 map
->x
, map
->y
, map
->w
, map
->h
,
3284 mt
, map
->ptr
, map
->stride
);
3289 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3290 struct intel_mipmap_tree
*mt
,
3291 struct intel_miptree_map
*map
,
3295 struct intel_mipmap_tree
*z_mt
= mt
;
3296 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3297 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3299 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3300 uint32_t *packed_map
= map
->ptr
;
3301 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3302 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3303 unsigned int s_image_x
, s_image_y
;
3304 unsigned int z_image_x
, z_image_y
;
3306 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3307 &s_image_x
, &s_image_y
);
3308 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3309 &z_image_x
, &z_image_y
);
3311 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3312 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3313 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3314 x
+ s_image_x
+ map
->x
,
3315 y
+ s_image_y
+ map
->y
,
3316 brw
->has_swizzling
);
3317 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3318 (z_mt
->surf
.row_pitch
/ 4) +
3319 (x
+ z_image_x
+ map
->x
));
3321 if (map_z32f_x24s8
) {
3322 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3323 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3325 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3326 s_map
[s_offset
] = packed
>> 24;
3327 z_map
[z_offset
] = packed
;
3332 intel_miptree_unmap_raw(s_mt
);
3333 intel_miptree_unmap_raw(z_mt
);
3335 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3337 map
->x
, map
->y
, map
->w
, map
->h
,
3338 z_mt
, _mesa_get_format_name(z_mt
->format
),
3339 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3340 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3341 map
->ptr
, map
->stride
);
3348 * Create and attach a map to the miptree at (level, slice). Return the
3351 static struct intel_miptree_map
*
3352 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3361 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3366 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3367 mt
->level
[level
].slice
[slice
].map
= map
;
3379 * Release the map at (level, slice).
3382 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3386 struct intel_miptree_map
**map
;
3388 map
= &mt
->level
[level
].slice
[slice
].map
;
3394 can_blit_slice(struct intel_mipmap_tree
*mt
,
3395 unsigned int level
, unsigned int slice
)
3397 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3398 if (mt
->surf
.row_pitch
>= 32768)
3405 use_intel_mipree_map_blit(struct brw_context
*brw
,
3406 struct intel_mipmap_tree
*mt
,
3412 /* It's probably not worth swapping to the blit ring because of
3413 * all the overhead involved.
3415 !(mode
& GL_MAP_WRITE_BIT
) &&
3417 (mt
->surf
.tiling
== ISL_TILING_X
||
3418 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3419 (brw
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3420 /* Fast copy blit on skl+ supports all tiling formats. */
3422 can_blit_slice(mt
, level
, slice
))
3425 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3426 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3427 assert(can_blit_slice(mt
, level
, slice
));
3435 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3436 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3437 * arithmetic overflow.
3439 * If you call this function and use \a out_stride, then you're doing pointer
3440 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3441 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3442 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3443 * which usually have type uint32_t or GLuint.
3446 intel_miptree_map(struct brw_context
*brw
,
3447 struct intel_mipmap_tree
*mt
,
3456 ptrdiff_t *out_stride
)
3458 struct intel_miptree_map
*map
;
3460 assert(mt
->surf
.samples
== 1);
3462 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3469 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3470 map
->mode
& GL_MAP_WRITE_BIT
);
3472 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3473 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3474 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3475 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3476 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3477 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3478 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3479 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3480 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3481 #if defined(USE_SSE41)
3482 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3483 !mt
->compressed
&& cpu_has_sse4_1
&&
3484 (mt
->surf
.row_pitch
% 16 == 0)) {
3485 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3488 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3491 *out_ptr
= map
->ptr
;
3492 *out_stride
= map
->stride
;
3494 if (map
->ptr
== NULL
)
3495 intel_miptree_release_map(mt
, level
, slice
);
3499 intel_miptree_unmap(struct brw_context
*brw
,
3500 struct intel_mipmap_tree
*mt
,
3504 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3506 assert(mt
->surf
.samples
== 1);
3511 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3512 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3514 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3515 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3516 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3517 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3518 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3519 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3520 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3521 } else if (map
->linear_mt
) {
3522 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3523 #if defined(USE_SSE41)
3524 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3525 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3528 intel_miptree_unmap_gtt(mt
);
3531 intel_miptree_release_map(mt
, level
, slice
);
3535 get_isl_surf_dim(GLenum target
)
3539 case GL_TEXTURE_1D_ARRAY
:
3540 return ISL_SURF_DIM_1D
;
3543 case GL_TEXTURE_2D_ARRAY
:
3544 case GL_TEXTURE_RECTANGLE
:
3545 case GL_TEXTURE_CUBE_MAP
:
3546 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3547 case GL_TEXTURE_2D_MULTISAMPLE
:
3548 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3549 case GL_TEXTURE_EXTERNAL_OES
:
3550 return ISL_SURF_DIM_2D
;
3553 return ISL_SURF_DIM_3D
;
3556 unreachable("Invalid texture target");
3560 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3561 enum isl_tiling tiling
, GLenum target
)
3565 case GL_TEXTURE_1D_ARRAY
:
3566 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3567 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3570 case GL_TEXTURE_2D_ARRAY
:
3571 case GL_TEXTURE_RECTANGLE
:
3572 case GL_TEXTURE_2D_MULTISAMPLE
:
3573 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3574 case GL_TEXTURE_EXTERNAL_OES
:
3575 return ISL_DIM_LAYOUT_GEN4_2D
;
3577 case GL_TEXTURE_CUBE_MAP
:
3578 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3579 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3580 ISL_DIM_LAYOUT_GEN4_2D
);
3583 return (devinfo
->gen
>= 9 ?
3584 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3587 unreachable("Invalid texture target");
3591 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3592 const struct intel_mipmap_tree
*mt
)
3595 return ISL_AUX_USAGE_HIZ
;
3598 return ISL_AUX_USAGE_NONE
;
3600 return mt
->aux_usage
;