2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_resolve_map.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
);
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 bool disable_aux_buffers
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (disable_aux_buffers
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
106 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
107 * scaled-down bitfield representation of the color buffer which is capable of
108 * recording when blocks of the color buffer are equal to the clear value.
109 * This function returns the block size that will be used by the MCS buffer
110 * corresponding to a certain color miptree.
112 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
113 * beneath the "Fast Color Clear" bullet (p327):
115 * The following table describes the RT alignment
129 * This alignment has the following uses:
131 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
132 * buffer contains 128 blocks horizontally and 256 blocks vertically.
134 * - For figuring out alignment restrictions for a fast clear operation. Fast
135 * clear operations must always clear aligned multiples of 16 blocks
136 * horizontally and 32 blocks vertically.
138 * - For scaling down the coordinates sent through the render pipeline during
139 * a fast clear. X coordinates must be scaled down by 8 times the block
140 * width, and Y coordinates by 16 times the block height.
142 * - For scaling down the coordinates sent through the render pipeline during
143 * a "Render Target Resolve" operation. X coordinates must be scaled down
144 * by half the block width, and Y coordinates by half the block height.
147 intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree
*mt
,
148 unsigned *width_px
, unsigned *height
)
150 switch (mt
->tiling
) {
152 unreachable("Non-MSRT MCS requires X or Y tiling");
153 /* In release builds, fall through */
155 *width_px
= 32 / mt
->cpp
;
159 *width_px
= 64 / mt
->cpp
;
165 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
168 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
169 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
171 * - Support is limited to tiled render targets.
173 * Gen9 changes the restriction to Y-tile only.
176 return tiling
== I915_TILING_Y
;
177 else if (brw
->gen
>= 7)
178 return tiling
!= I915_TILING_NONE
;
184 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
185 * can be used. This doesn't (and should not) inspect any of the properties of
188 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
189 * beneath the "Fast Color Clear" bullet (p326):
191 * - Support is for non-mip-mapped and non-array surface types only.
193 * And then later, on p327:
195 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
198 * From the Skylake documentation, it is made clear that X-tiling is no longer
201 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
205 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
206 const struct intel_mipmap_tree
*mt
)
208 /* MCS support does not exist prior to Gen7 */
212 if (mt
->disable_aux_buffers
)
215 /* This function applies only to non-multisampled render targets. */
216 if (mt
->num_samples
> 1)
219 /* MCS is only supported for color buffers */
220 switch (_mesa_get_format_base_format(mt
->format
)) {
221 case GL_DEPTH_COMPONENT
:
222 case GL_DEPTH_STENCIL
:
223 case GL_STENCIL_INDEX
:
227 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
229 if (mt
->first_level
!= 0 || mt
->last_level
!= 0) {
231 perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
232 mt
->logical_width0
, mt
->logical_height0
, mt
->last_level
);
238 /* Check for layered surfaces. */
239 if (mt
->physical_depth0
!= 1) {
240 /* Multisample surfaces with the CMS layout are not layered surfaces,
241 * yet still have physical_depth0 > 1. Assert that we don't
242 * accidentally reject a multisampled surface here. We should have
243 * rejected it earlier by explicitly checking the sample count.
245 assert(mt
->num_samples
<= 1);
248 perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
249 mt
->logical_width0
, mt
->logical_height0
,
250 mt
->physical_depth0
);
256 /* There's no point in using an MCS buffer if the surface isn't in a
259 if (!brw
->format_supported_as_render_target
[mt
->format
])
263 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
264 const uint32_t brw_format
= brw_format_for_mesa_format(linear_format
);
265 return isl_format_supports_lossless_compression(brw
->intelScreen
->devinfo
,
271 /* On Gen9 support for color buffer compression was extended to single
272 * sampled surfaces. This is a helper considering both auxiliary buffer
273 * type and number of samples telling if the given miptree represents
274 * the new single sampled case - also called lossless compression.
277 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
278 const struct intel_mipmap_tree
*mt
)
280 /* Only available from Gen9 onwards. */
284 /* Compression always requires auxiliary buffer. */
288 /* Single sample compression is represented re-using msaa compression
289 * layout type: "Compressed Multisampled Surfaces".
291 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
294 /* And finally distinguish between msaa and single sample case. */
295 return mt
->num_samples
<= 1;
299 intel_miptree_supports_lossless_compressed(struct brw_context
*brw
,
300 const struct intel_mipmap_tree
*mt
)
302 /* For now compression is only enabled for integer formats even though
303 * there exist supported floating point formats also. This is a heuristic
304 * decision based on current public benchmarks. In none of the cases these
305 * formats provided any improvement but a few cases were seen to regress.
306 * Hence these are left to to be enabled in the future when they are known
309 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
312 /* Fast clear mechanism and lossless compression go hand in hand. */
313 if (!intel_miptree_supports_non_msrt_fast_clear(brw
, mt
))
316 /* Fast clear can be also used to clear srgb surfaces by using equivalent
317 * linear format. This trick, however, can't be extended to be used with
318 * lossless compression and therefore a check is needed to see if the format
321 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
325 * Determine depth format corresponding to a depth+stencil format,
326 * for separate stencil.
329 intel_depth_format_for_depthstencil_format(mesa_format format
) {
331 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
332 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
333 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
334 return MESA_FORMAT_Z_FLOAT32
;
342 * @param for_bo Indicates that the caller is
343 * intel_miptree_create_for_bo(). If true, then do not create
346 static struct intel_mipmap_tree
*
347 intel_miptree_create_layout(struct brw_context
*brw
,
356 uint32_t layout_flags
)
358 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
362 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
363 _mesa_enum_to_string(target
),
364 _mesa_get_format_name(format
),
365 first_level
, last_level
, depth0
, mt
);
367 if (target
== GL_TEXTURE_1D_ARRAY
) {
368 /* For a 1D Array texture the OpenGL API will treat the height0
369 * parameter as the number of array slices. For Intel hardware, we treat
370 * the 1D array as a 2D Array with a height of 1.
372 * So, when we first come through this path to create a 1D Array
373 * texture, height0 stores the number of slices, and depth0 is 1. In
374 * this case, we want to swap height0 and depth0.
376 * Since some miptrees will be created based on the base miptree, we may
377 * come through this path and see height0 as 1 and depth0 being the
378 * number of slices. In this case we don't need to do the swap.
380 assert(height0
== 1 || depth0
== 1);
389 mt
->first_level
= first_level
;
390 mt
->last_level
= last_level
;
391 mt
->logical_width0
= width0
;
392 mt
->logical_height0
= height0
;
393 mt
->logical_depth0
= depth0
;
394 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
395 mt
->disable_aux_buffers
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0;
396 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
397 exec_list_make_empty(&mt
->hiz_map
);
398 mt
->cpp
= _mesa_get_format_bytes(format
);
399 mt
->num_samples
= num_samples
;
400 mt
->compressed
= _mesa_is_format_compressed(format
);
401 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
404 if (num_samples
> 1) {
405 /* Adjust width/height/depth for MSAA */
406 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
407 mt
->disable_aux_buffers
);
408 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
409 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
410 * "If the surface is multisampled and it is a depth or stencil
411 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
412 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
415 * +----------------------------------------------------------------+
416 * | Num Multisamples | W_l = | H_l = |
417 * +----------------------------------------------------------------+
418 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
419 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
420 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
421 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
422 * +----------------------------------------------------------------+
425 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
426 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
427 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
429 * Another more complicated explanation for these adjustments comes
430 * from the Sandybridge PRM, volume 4, part 1, page 31:
432 * "Any of the other messages (sample*, LOD, load4) used with a
433 * (4x) multisampled surface will in-effect sample a surface with
434 * double the height and width as that indicated in the surface
435 * state. Each pixel position on the original-sized surface is
436 * replaced with a 2x2 of samples with the following arrangement:
441 * Thus, when sampling from a multisampled texture, it behaves as
442 * though the layout in memory for (x,y,sample) is:
444 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
445 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
447 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
448 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
450 * However, the actual layout of multisampled data in memory is:
452 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
453 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
455 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
456 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
458 * This pattern repeats for each 2x2 pixel block.
460 * As a result, when calculating the size of our 4-sample buffer for
461 * an odd width or height, we have to align before scaling up because
462 * sample 3 is in that bottom right 2x2 block.
464 switch (num_samples
) {
466 assert(brw
->gen
>= 8);
467 width0
= ALIGN(width0
, 2) * 2;
468 height0
= ALIGN(height0
, 2);
471 width0
= ALIGN(width0
, 2) * 2;
472 height0
= ALIGN(height0
, 2) * 2;
475 width0
= ALIGN(width0
, 2) * 4;
476 height0
= ALIGN(height0
, 2) * 2;
479 width0
= ALIGN(width0
, 2) * 4;
480 height0
= ALIGN(height0
, 2) * 4;
483 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
486 unreachable("not reached");
489 /* Non-interleaved */
490 depth0
*= num_samples
;
494 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
495 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
496 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
497 * used on Gen8 to make it pick a qpitch value which doesn't include space
498 * for the mipmaps. On Gen9 this is not necessary because it will
499 * automatically pick a packed qpitch value whenever mt->first_level ==
501 * TODO: can we use it elsewhere?
502 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
505 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
507 switch (mt
->msaa_layout
) {
508 case INTEL_MSAA_LAYOUT_NONE
:
509 case INTEL_MSAA_LAYOUT_IMS
:
510 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
512 case INTEL_MSAA_LAYOUT_UMS
:
513 case INTEL_MSAA_LAYOUT_CMS
:
514 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
519 if (target
== GL_TEXTURE_CUBE_MAP
) {
524 mt
->physical_width0
= width0
;
525 mt
->physical_height0
= height0
;
526 mt
->physical_depth0
= depth0
;
528 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
529 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
530 (brw
->must_use_separate_stencil
||
531 (brw
->has_separate_stencil
&&
532 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
533 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
535 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
|
536 MIPTREE_LAYOUT_TILING_ANY
;
539 mt
->stencil_mt
= intel_miptree_create(brw
,
550 if (!mt
->stencil_mt
) {
551 intel_miptree_release(&mt
);
555 /* Fix up the Z miptree format for how we're splitting out separate
556 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
558 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
561 if (format
== mt
->format
) {
562 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
563 _mesa_get_format_name(mt
->format
));
567 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
568 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
571 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
572 * multisampled or have an AUX buffer attached to it.
574 * GEN | MSRT | AUX_CCS_* or AUX_MCS
575 * -------------------------------------------
576 * 9 | HALIGN_16 | HALIGN_16
577 * 8 | HALIGN_ANY | HALIGN_16
581 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
582 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
583 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
584 } else if (brw
->gen
>= 9 && num_samples
> 1) {
585 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
587 const UNUSED
bool is_lossless_compressed_aux
=
588 brw
->gen
>= 9 && num_samples
== 1 &&
589 mt
->format
== MESA_FORMAT_R_UINT32
;
591 /* For now, nothing else has this requirement */
592 assert(is_lossless_compressed_aux
||
593 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
596 brw_miptree_layout(brw
, mt
, layout_flags
);
598 if (mt
->disable_aux_buffers
)
599 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
606 * Choose an appropriate uncompressed format for a requested
607 * compressed format, if unsupported.
610 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
612 /* No need to lower ETC formats on these platforms,
613 * they are supported natively.
615 if (brw
->gen
>= 8 || brw
->is_baytrail
)
619 case MESA_FORMAT_ETC1_RGB8
:
620 return MESA_FORMAT_R8G8B8X8_UNORM
;
621 case MESA_FORMAT_ETC2_RGB8
:
622 return MESA_FORMAT_R8G8B8X8_UNORM
;
623 case MESA_FORMAT_ETC2_SRGB8
:
624 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
625 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
626 return MESA_FORMAT_B8G8R8A8_SRGB
;
627 case MESA_FORMAT_ETC2_RGBA8_EAC
:
628 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
629 return MESA_FORMAT_R8G8B8A8_UNORM
;
630 case MESA_FORMAT_ETC2_R11_EAC
:
631 return MESA_FORMAT_R_UNORM16
;
632 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
633 return MESA_FORMAT_R_SNORM16
;
634 case MESA_FORMAT_ETC2_RG11_EAC
:
635 return MESA_FORMAT_R16G16_UNORM
;
636 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
637 return MESA_FORMAT_R16G16_SNORM
;
639 /* Non ETC1 / ETC2 format */
644 /* This function computes Yf/Ys tiled bo size, alignment and pitch. */
646 intel_get_yf_ys_bo_size(struct intel_mipmap_tree
*mt
, unsigned *alignment
,
647 unsigned long *pitch
)
649 uint32_t tile_width
, tile_height
;
650 unsigned long stride
, size
, aligned_y
;
652 assert(mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
);
653 intel_get_tile_dims(mt
->tiling
, mt
->tr_mode
, mt
->cpp
,
654 &tile_width
, &tile_height
);
656 aligned_y
= ALIGN(mt
->total_height
, tile_height
);
657 stride
= mt
->total_width
* mt
->cpp
;
658 stride
= ALIGN(stride
, tile_width
);
659 size
= stride
* aligned_y
;
661 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
) {
662 assert(size
% 4096 == 0);
665 assert(size
% (64 * 1024) == 0);
666 *alignment
= 64 * 1024;
672 static struct intel_mipmap_tree
*
673 miptree_create(struct brw_context
*brw
,
682 uint32_t layout_flags
)
684 struct intel_mipmap_tree
*mt
;
685 mesa_format tex_format
= format
;
686 mesa_format etc_format
= MESA_FORMAT_NONE
;
687 uint32_t alloc_flags
= 0;
689 format
= intel_lower_compressed_format(brw
, format
);
691 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
693 assert((layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) == 0);
694 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
695 mt
= intel_miptree_create_layout(brw
, target
, format
,
696 first_level
, last_level
, width0
,
697 height0
, depth0
, num_samples
,
700 * pitch == 0 || height == 0 indicates the null texture
702 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
703 intel_miptree_release(&mt
);
707 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
708 mt
->tiling
= I915_TILING_Y
;
710 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
711 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
714 mt
->etc_format
= etc_format
;
716 if (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
717 unsigned alignment
= 0;
719 size
= intel_get_yf_ys_bo_size(mt
, &alignment
, &pitch
);
721 mt
->bo
= drm_intel_bo_alloc_for_render(brw
->bufmgr
, "miptree",
724 if (format
== MESA_FORMAT_S_UINT8
) {
725 /* Align to size of W tile, 64x64. */
726 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
727 ALIGN(mt
->total_width
, 64),
728 ALIGN(mt
->total_height
, 64),
729 mt
->cpp
, &mt
->tiling
, &pitch
,
732 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
733 mt
->total_width
, mt
->total_height
,
734 mt
->cpp
, &mt
->tiling
, &pitch
,
744 struct intel_mipmap_tree
*
745 intel_miptree_create(struct brw_context
*brw
,
754 uint32_t layout_flags
)
756 struct intel_mipmap_tree
*mt
= miptree_create(
758 first_level
, last_level
,
759 width0
, height0
, depth0
, num_samples
,
762 /* If the BO is too large to fit in the aperture, we need to use the
763 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
764 * handle Y-tiling, so we need to fall back to X.
766 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
767 mt
->tiling
== I915_TILING_Y
) {
768 unsigned long pitch
= mt
->pitch
;
769 const uint32_t alloc_flags
=
770 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
771 BO_ALLOC_FOR_RENDER
: 0;
772 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
773 mt
->total_width
, mt
->total_height
);
775 mt
->tiling
= I915_TILING_X
;
776 drm_intel_bo_unreference(mt
->bo
);
777 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
778 mt
->total_width
, mt
->total_height
, mt
->cpp
,
779 &mt
->tiling
, &pitch
, alloc_flags
);
786 intel_miptree_release(&mt
);
791 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
792 assert(mt
->num_samples
> 1);
793 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
794 intel_miptree_release(&mt
);
799 /* If this miptree is capable of supporting fast color clears, set
800 * fast_clear_state appropriately to ensure that fast clears will occur.
801 * Allocation of the MCS miptree will be deferred until the first fast
802 * clear actually occurs or when compressed single sampled buffer is
803 * written by the GPU for the first time.
805 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
806 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
807 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
808 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
814 struct intel_mipmap_tree
*
815 intel_miptree_create_for_bo(struct brw_context
*brw
,
823 uint32_t layout_flags
)
825 struct intel_mipmap_tree
*mt
;
826 uint32_t tiling
, swizzle
;
829 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
831 /* Nothing will be able to use this miptree with the BO if the offset isn't
834 if (tiling
!= I915_TILING_NONE
)
835 assert(offset
% 4096 == 0);
837 /* miptrees can't handle negative pitch. If you need flipping of images,
838 * that's outside of the scope of the mt.
842 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
844 /* The BO already has a tiling format and we shouldn't confuse the lower
845 * layers by making it try to find a tiling format again.
847 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
848 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
850 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
851 mt
= intel_miptree_create_layout(brw
, target
, format
,
853 width
, height
, depth
, 0,
858 drm_intel_bo_reference(bo
);
868 * For a singlesample renderbuffer, this simply wraps the given BO with a
871 * For a multisample renderbuffer, this wraps the window system's
872 * (singlesample) BO with a singlesample miptree attached to the
873 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
874 * that will contain the actual rendering (which is lazily resolved to
875 * irb->singlesample_mt).
878 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
879 struct intel_renderbuffer
*irb
,
881 uint32_t width
, uint32_t height
,
884 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
885 struct intel_mipmap_tree
*multisample_mt
= NULL
;
886 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
887 mesa_format format
= rb
->Format
;
888 int num_samples
= rb
->NumSamples
;
890 /* Only the front and back buffers, which are color buffers, are allocated
891 * through the image loader.
893 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
894 _mesa_get_format_base_format(format
) == GL_RGBA
);
896 singlesample_mt
= intel_miptree_create_for_bo(intel
,
904 MIPTREE_LAYOUT_FOR_SCANOUT
);
905 if (!singlesample_mt
)
908 /* If this miptree is capable of supporting fast color clears, set
909 * mcs_state appropriately to ensure that fast clears will occur.
910 * Allocation of the MCS miptree will be deferred until the first fast
911 * clear actually occurs.
913 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
914 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
915 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
918 if (num_samples
== 0) {
919 intel_miptree_release(&irb
->mt
);
920 irb
->mt
= singlesample_mt
;
922 assert(!irb
->singlesample_mt
);
924 intel_miptree_release(&irb
->singlesample_mt
);
925 irb
->singlesample_mt
= singlesample_mt
;
928 irb
->mt
->logical_width0
!= width
||
929 irb
->mt
->logical_height0
!= height
) {
930 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
938 irb
->need_downsample
= false;
939 intel_miptree_release(&irb
->mt
);
940 irb
->mt
= multisample_mt
;
946 intel_miptree_release(&irb
->singlesample_mt
);
947 intel_miptree_release(&irb
->mt
);
951 struct intel_mipmap_tree
*
952 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
956 uint32_t num_samples
)
958 struct intel_mipmap_tree
*mt
;
961 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
962 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
963 MIPTREE_LAYOUT_TILING_ANY
|
964 MIPTREE_LAYOUT_FOR_SCANOUT
;
966 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
967 width
, height
, depth
, num_samples
,
972 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
973 ok
= intel_miptree_alloc_hiz(brw
, mt
);
981 intel_miptree_release(&mt
);
986 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
987 struct intel_mipmap_tree
*src
)
992 intel_miptree_release(dst
);
996 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1004 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1009 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1010 if (--(*mt
)->refcount
<= 0) {
1013 DBG("%s deleting %p\n", __func__
, *mt
);
1015 drm_intel_bo_unreference((*mt
)->bo
);
1016 intel_miptree_release(&(*mt
)->stencil_mt
);
1017 if ((*mt
)->hiz_buf
) {
1018 if ((*mt
)->hiz_buf
->mt
)
1019 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
1021 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
1022 free((*mt
)->hiz_buf
);
1024 intel_miptree_release(&(*mt
)->mcs_mt
);
1025 intel_resolve_map_clear(&(*mt
)->hiz_map
);
1027 intel_miptree_release(&(*mt
)->plane
[0]);
1028 intel_miptree_release(&(*mt
)->plane
[1]);
1030 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1031 free((*mt
)->level
[i
].slice
);
1041 intel_get_image_dims(struct gl_texture_image
*image
,
1042 int *width
, int *height
, int *depth
)
1044 switch (image
->TexObject
->Target
) {
1045 case GL_TEXTURE_1D_ARRAY
:
1046 /* For a 1D Array texture the OpenGL API will treat the image height as
1047 * the number of array slices. For Intel hardware, we treat the 1D array
1048 * as a 2D Array with a height of 1. So, here we want to swap image
1051 *width
= image
->Width
;
1053 *depth
= image
->Height
;
1056 *width
= image
->Width
;
1057 *height
= image
->Height
;
1058 *depth
= image
->Depth
;
1064 * Can the image be pulled into a unified mipmap tree? This mirrors
1065 * the completeness test in a lot of ways.
1067 * Not sure whether I want to pass gl_texture_image here.
1070 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1071 struct gl_texture_image
*image
)
1073 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1074 GLuint level
= intelImage
->base
.Base
.Level
;
1075 int width
, height
, depth
;
1077 /* glTexImage* choose the texture object based on the target passed in, and
1078 * objects can't change targets over their lifetimes, so this should be
1081 assert(image
->TexObject
->Target
== mt
->target
);
1083 mesa_format mt_format
= mt
->format
;
1084 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1085 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1086 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1087 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1088 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1089 mt_format
= mt
->etc_format
;
1091 if (image
->TexFormat
!= mt_format
)
1094 intel_get_image_dims(image
, &width
, &height
, &depth
);
1096 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1099 int level_depth
= mt
->level
[level
].depth
;
1100 if (mt
->num_samples
> 1) {
1101 switch (mt
->msaa_layout
) {
1102 case INTEL_MSAA_LAYOUT_NONE
:
1103 case INTEL_MSAA_LAYOUT_IMS
:
1105 case INTEL_MSAA_LAYOUT_UMS
:
1106 case INTEL_MSAA_LAYOUT_CMS
:
1107 level_depth
/= mt
->num_samples
;
1112 /* Test image dimensions against the base level image adjusted for
1113 * minification. This will also catch images not present in the
1114 * tree, changed targets, etc.
1116 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1117 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1118 depth
!= level_depth
) {
1122 if (image
->NumSamples
!= mt
->num_samples
)
1130 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1132 GLuint x
, GLuint y
, GLuint d
)
1134 mt
->level
[level
].depth
= d
;
1135 mt
->level
[level
].level_x
= x
;
1136 mt
->level
[level
].level_y
= y
;
1138 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1141 assert(mt
->level
[level
].slice
== NULL
);
1143 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1144 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1145 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1150 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1151 GLuint level
, GLuint img
,
1154 if (img
== 0 && level
== 0)
1155 assert(x
== 0 && y
== 0);
1157 assert(img
< mt
->level
[level
].depth
);
1159 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1160 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1162 DBG("%s level %d img %d pos %d,%d\n",
1163 __func__
, level
, img
,
1164 mt
->level
[level
].slice
[img
].x_offset
,
1165 mt
->level
[level
].slice
[img
].y_offset
);
1169 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1170 GLuint level
, GLuint slice
,
1171 GLuint
*x
, GLuint
*y
)
1173 assert(slice
< mt
->level
[level
].depth
);
1175 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1176 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1181 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1182 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1183 * and tile_h is set to 1.
1186 intel_get_tile_dims(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1187 uint32_t *tile_w
, uint32_t *tile_h
)
1189 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
) {
1199 case I915_TILING_NONE
:
1204 unreachable("not reached");
1207 uint32_t aspect_ratio
= 1;
1208 assert(_mesa_is_pow_two(cpp
));
1223 unreachable("not reached");
1226 if (cpp
== 2 || cpp
== 8)
1229 if (tr_mode
== INTEL_MIPTREE_TRMODE_YS
)
1232 *tile_w
= *tile_h
* aspect_ratio
* cpp
;
1238 * This function computes masks that may be used to select the bits of the X
1239 * and Y coordinates that indicate the offset within a tile. If the BO is
1240 * untiled, the masks are set to 0.
1243 intel_get_tile_masks(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1244 bool map_stencil_as_y_tiled
,
1245 uint32_t *mask_x
, uint32_t *mask_y
)
1247 uint32_t tile_w_bytes
, tile_h
;
1248 if (map_stencil_as_y_tiled
)
1249 tiling
= I915_TILING_Y
;
1251 intel_get_tile_dims(tiling
, tr_mode
, cpp
, &tile_w_bytes
, &tile_h
);
1253 *mask_x
= tile_w_bytes
/ cpp
- 1;
1254 *mask_y
= tile_h
- 1;
1258 * Compute the offset (in bytes) from the start of the BO to the given x
1259 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1260 * multiples of the tile size.
1263 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1264 uint32_t x
, uint32_t y
,
1265 bool map_stencil_as_y_tiled
)
1268 uint32_t pitch
= mt
->pitch
;
1269 uint32_t tiling
= mt
->tiling
;
1271 if (map_stencil_as_y_tiled
) {
1272 tiling
= I915_TILING_Y
;
1274 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1275 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1276 * the resulting surface is twice the pitch of the original miptree,
1277 * since each row in the Y-tiled view corresponds to two rows in the
1278 * actual W-tiled surface. So we need to correct the pitch before
1279 * computing the offsets.
1286 unreachable("not reached");
1287 case I915_TILING_NONE
:
1288 return y
* pitch
+ x
* cpp
;
1290 assert((x
% (512 / cpp
)) == 0);
1291 assert((y
% 8) == 0);
1292 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1294 assert((x
% (128 / cpp
)) == 0);
1295 assert((y
% 32) == 0);
1296 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1301 * Rendering with tiled buffers requires that the base address of the buffer
1302 * be aligned to a page boundary. For renderbuffers, and sometimes with
1303 * textures, we may want the surface to point at a texture image level that
1304 * isn't at a page boundary.
1306 * This function returns an appropriately-aligned base offset
1307 * according to the tiling restrictions, plus any required x/y offset
1311 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1312 GLuint level
, GLuint slice
,
1317 uint32_t mask_x
, mask_y
;
1319 intel_get_tile_masks(mt
->tiling
, mt
->tr_mode
, mt
->cpp
, false, &mask_x
, &mask_y
);
1320 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1322 *tile_x
= x
& mask_x
;
1323 *tile_y
= y
& mask_y
;
1325 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1329 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1330 struct intel_mipmap_tree
*dst_mt
,
1331 struct intel_mipmap_tree
*src_mt
,
1338 ptrdiff_t src_stride
, dst_stride
;
1339 int cpp
= dst_mt
->cpp
;
1341 intel_miptree_map(brw
, src_mt
,
1345 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1348 intel_miptree_map(brw
, dst_mt
,
1352 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1356 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1357 _mesa_get_format_name(src_mt
->format
),
1358 src_mt
, src
, src_stride
,
1359 _mesa_get_format_name(dst_mt
->format
),
1360 dst_mt
, dst
, dst_stride
,
1363 int row_size
= cpp
* width
;
1364 if (src_stride
== row_size
&&
1365 dst_stride
== row_size
) {
1366 memcpy(dst
, src
, row_size
* height
);
1368 for (int i
= 0; i
< height
; i
++) {
1369 memcpy(dst
, src
, row_size
);
1375 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1376 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1378 /* Don't forget to copy the stencil data over, too. We could have skipped
1379 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1380 * shuffling the two data sources in/out of temporary storage instead of
1381 * the direct mapping we get this way.
1383 if (dst_mt
->stencil_mt
) {
1384 assert(src_mt
->stencil_mt
);
1385 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1386 level
, slice
, width
, height
);
1391 intel_miptree_copy_slice(struct brw_context
*brw
,
1392 struct intel_mipmap_tree
*dst_mt
,
1393 struct intel_mipmap_tree
*src_mt
,
1399 mesa_format format
= src_mt
->format
;
1400 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1401 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1409 assert(depth
< src_mt
->level
[level
].depth
);
1410 assert(src_mt
->format
== dst_mt
->format
);
1412 if (dst_mt
->compressed
) {
1414 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1415 height
= ALIGN_NPOT(height
, j
) / j
;
1416 width
= ALIGN_NPOT(width
, i
) / i
;
1419 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1420 * below won't apply since we can't do the depth's Y tiling or the
1421 * stencil's W tiling in the blitter.
1423 if (src_mt
->stencil_mt
) {
1424 intel_miptree_copy_slice_sw(brw
,
1431 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1432 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1433 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1435 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1436 _mesa_get_format_name(src_mt
->format
),
1437 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1438 _mesa_get_format_name(dst_mt
->format
),
1439 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1442 if (!intel_miptree_blit(brw
,
1443 src_mt
, level
, slice
, 0, 0, false,
1444 dst_mt
, level
, slice
, 0, 0, false,
1445 width
, height
, GL_COPY
)) {
1446 perf_debug("miptree validate blit for %s failed\n",
1447 _mesa_get_format_name(format
));
1449 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1455 * Copies the image's current data to the given miptree, and associates that
1456 * miptree with the image.
1458 * If \c invalidate is true, then the actual image data does not need to be
1459 * copied, but the image still needs to be associated to the new miptree (this
1460 * is set to true if we're about to clear the image).
1463 intel_miptree_copy_teximage(struct brw_context
*brw
,
1464 struct intel_texture_image
*intelImage
,
1465 struct intel_mipmap_tree
*dst_mt
,
1468 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1469 struct intel_texture_object
*intel_obj
=
1470 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1471 int level
= intelImage
->base
.Base
.Level
;
1472 int face
= intelImage
->base
.Base
.Face
;
1475 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1476 depth
= intelImage
->base
.Base
.Height
;
1478 depth
= intelImage
->base
.Base
.Depth
;
1481 for (int slice
= 0; slice
< depth
; slice
++) {
1482 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1486 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1487 intel_obj
->needs_validate
= true;
1491 intel_miptree_init_mcs(struct brw_context
*brw
,
1492 struct intel_mipmap_tree
*mt
,
1495 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1497 * When MCS buffer is enabled and bound to MSRT, it is required that it
1498 * is cleared prior to any rendering.
1500 * Since we don't use the MCS buffer for any purpose other than rendering,
1501 * it makes sense to just clear it immediately upon allocation.
1503 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1505 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1506 memset(data
, init_value
, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1507 intel_miptree_unmap_raw(mt
->mcs_mt
);
1508 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1512 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1513 struct intel_mipmap_tree
*mt
,
1516 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1517 assert(mt
->mcs_mt
== NULL
);
1518 assert(!mt
->disable_aux_buffers
);
1520 /* Choose the correct format for the MCS buffer. All that really matters
1521 * is that we allocate the right buffer size, since we'll always be
1522 * accessing this miptree using MCS-specific hardware mechanisms, which
1523 * infer the correct format based on num_samples.
1526 switch (num_samples
) {
1529 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1532 format
= MESA_FORMAT_R_UNORM8
;
1535 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1536 * for each sample, plus 8 padding bits).
1538 format
= MESA_FORMAT_R_UINT32
;
1541 /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
1544 format
= MESA_FORMAT_RG_UINT32
;
1547 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1550 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1552 * "The MCS surface must be stored as Tile Y."
1554 const uint32_t mcs_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1555 MIPTREE_LAYOUT_TILING_Y
;
1556 mt
->mcs_mt
= miptree_create(brw
,
1562 mt
->logical_height0
,
1564 0 /* num_samples */,
1567 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1574 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1575 struct intel_mipmap_tree
*mt
)
1577 assert(mt
->mcs_mt
== NULL
);
1578 assert(!mt
->disable_aux_buffers
);
1580 /* The format of the MCS buffer is opaque to the driver; all that matters
1581 * is that we get its size and pitch right. We'll pretend that the format
1582 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1583 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1584 * the block width and then a further factor of 4. Since an MCS tile
1585 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1586 * we'll need to scale the height down by the block height and then a
1587 * further factor of 8.
1589 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1590 unsigned block_width_px
;
1591 unsigned block_height
;
1592 intel_get_non_msrt_mcs_alignment(mt
, &block_width_px
, &block_height
);
1593 unsigned width_divisor
= block_width_px
* 4;
1594 unsigned height_divisor
= block_height
* 8;
1596 /* The Skylake MCS is twice as tall as the Broadwell MCS.
1598 * In pre-Skylake, each bit in the MCS contained the state of 2 cachelines
1599 * in the main surface. In Skylake, it's two bits. The extra bit
1600 * doubles the MCS height, not width, because in Skylake the MCS is always
1604 height_divisor
/= 2;
1606 unsigned mcs_width
=
1607 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1608 unsigned mcs_height
=
1609 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1610 assert(mt
->logical_depth0
== 1);
1611 uint32_t layout_flags
= MIPTREE_LAYOUT_TILING_Y
;
1613 if (brw
->gen
>= 8) {
1614 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
1617 /* On Gen9+ clients are not currently capable of consuming compressed
1618 * single-sampled buffers. Disabling compression allows us to skip
1621 const bool lossless_compression_disabled
= INTEL_DEBUG
& DEBUG_NO_RBC
;
1622 const bool is_lossless_compressed
=
1623 unlikely(!lossless_compression_disabled
) &&
1624 brw
->gen
>= 9 && !mt
->is_scanout
&&
1625 intel_miptree_supports_lossless_compressed(brw
, mt
);
1627 /* In case of compression mcs buffer needs to be initialised requiring the
1628 * buffer to be immediately mapped to cpu space for writing. Therefore do
1629 * not use the gpu access flag which can cause an unnecessary delay if the
1630 * backing pages happened to be just used by the GPU.
1632 if (!is_lossless_compressed
)
1633 layout_flags
|= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1635 mt
->mcs_mt
= miptree_create(brw
,
1643 0 /* num_samples */,
1646 /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
1647 * used for lossless compression which requires similar initialisation
1648 * as multi-sample compression.
1650 if (is_lossless_compressed
) {
1651 /* Hardware sets the auxiliary buffer to all zeroes when it does full
1652 * resolve. Initialize it accordingly in case the first renderer is
1653 * cpu (or other none compression aware party).
1655 * This is also explicitly stated in the spec (MCS Buffer for Render
1657 * "If Software wants to enable Color Compression without Fast clear,
1658 * Software needs to initialize MCS with zeros."
1660 intel_miptree_init_mcs(brw
, mt
, 0);
1661 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
1662 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_CMS
;
1669 intel_miptree_prepare_mcs(struct brw_context
*brw
,
1670 struct intel_mipmap_tree
*mt
)
1678 /* Single sample compression is represented re-using msaa compression
1679 * layout type: "Compressed Multisampled Surfaces".
1681 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
|| mt
->num_samples
> 1)
1684 /* Clients are not currently capable of consuming compressed
1685 * single-sampled buffers.
1690 assert(intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) ||
1691 intel_miptree_supports_lossless_compressed(brw
, mt
));
1693 /* Consider if lossless compression is supported but the needed
1694 * auxiliary buffer doesn't exist yet.
1696 * Failing to allocate the auxiliary buffer means running out of
1697 * memory. The pointer to the aux miptree is left NULL which should
1698 * signal non-compressed behavior.
1700 if (!intel_miptree_alloc_non_msrt_mcs(brw
, mt
)) {
1702 "Failed to allocated aux buffer for lossless"
1703 " compressed %p %u:%u %s\n",
1704 mt
, mt
->logical_width0
, mt
->logical_height0
,
1705 _mesa_get_format_name(mt
->format
));
1710 * Helper for intel_miptree_alloc_hiz() that sets
1711 * \c mt->level[level].has_hiz. Return true if and only if
1712 * \c has_hiz was set.
1715 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1716 struct intel_mipmap_tree
*mt
,
1719 assert(mt
->hiz_buf
);
1721 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1722 uint32_t width
= minify(mt
->physical_width0
, level
);
1723 uint32_t height
= minify(mt
->physical_height0
, level
);
1725 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1726 * and the height is 4 aligned. This allows our HiZ support
1727 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1728 * we can grow the width & height to allow the HiZ op to
1729 * force the proper size alignments.
1731 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1732 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1737 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1738 mt
->level
[level
].has_hiz
= true;
1744 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1745 * buffer dimensions and allocates a bo for the hiz buffer.
1747 static struct intel_miptree_aux_buffer
*
1748 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1749 struct intel_mipmap_tree
*mt
)
1751 unsigned z_width
= mt
->logical_width0
;
1752 unsigned z_height
= mt
->logical_height0
;
1753 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1754 unsigned hz_width
, hz_height
;
1755 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1760 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1761 * adjustments required for Z_Height and Z_Width based on multisampling.
1763 switch (mt
->num_samples
) {
1777 unreachable("unsupported sample count");
1780 const unsigned vertical_align
= 8; /* 'j' in the docs */
1781 const unsigned H0
= z_height
;
1782 const unsigned h0
= ALIGN(H0
, vertical_align
);
1783 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1784 const unsigned Z0
= z_depth
;
1786 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1787 hz_width
= ALIGN(z_width
, 16);
1789 if (mt
->target
== GL_TEXTURE_3D
) {
1793 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1794 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1795 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1796 hz_height
+= h_i
* Z_i
;
1797 H_i
= minify(H_i
, 1);
1798 Z_i
= minify(Z_i
, 1);
1801 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1803 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1805 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1806 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1807 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1808 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth * 6/2) /8 ) * 8 */
1809 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
* 6, 2 * 8) * 8;
1811 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1812 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1816 unsigned long pitch
;
1817 uint32_t tiling
= I915_TILING_Y
;
1818 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1819 hz_width
, hz_height
, 1,
1821 BO_ALLOC_FOR_RENDER
);
1825 } else if (tiling
!= I915_TILING_Y
) {
1826 drm_intel_bo_unreference(buf
->bo
);
1838 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1839 * buffer dimensions and allocates a bo for the hiz buffer.
1841 static struct intel_miptree_aux_buffer
*
1842 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1843 struct intel_mipmap_tree
*mt
)
1845 unsigned z_width
= mt
->logical_width0
;
1846 unsigned z_height
= mt
->logical_height0
;
1847 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1848 unsigned hz_width
, hz_height
;
1849 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1854 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1855 * adjustments required for Z_Height and Z_Width based on multisampling.
1858 switch (mt
->num_samples
) {
1872 unreachable("unsupported sample count");
1876 const unsigned vertical_align
= 8; /* 'j' in the docs */
1877 const unsigned H0
= z_height
;
1878 const unsigned h0
= ALIGN(H0
, vertical_align
);
1879 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1880 const unsigned Z0
= z_depth
;
1882 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1883 hz_width
= ALIGN(z_width
, 16);
1887 unsigned sum_h_i
= 0;
1888 unsigned hz_height_3d_sum
= 0;
1889 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1890 unsigned i
= level
- mt
->first_level
;
1891 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1892 /* sum(i=2 to m; h_i) */
1896 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1897 hz_height_3d_sum
+= h_i
* Z_i
;
1898 H_i
= minify(H_i
, 1);
1899 Z_i
= minify(Z_i
, 1);
1901 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1902 buf
->qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1904 if (mt
->target
== GL_TEXTURE_3D
) {
1905 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1906 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1908 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1909 hz_height
= DIV_ROUND_UP(buf
->qpitch
, 2 * 8) * 8 * Z0
;
1910 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1911 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1912 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * 6 * Z_Depth
1914 * We can can just take our hz_height calculation from above, and
1915 * multiply by 6 for the cube map and cube map array types.
1921 unsigned long pitch
;
1922 uint32_t tiling
= I915_TILING_Y
;
1923 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1924 hz_width
, hz_height
, 1,
1926 BO_ALLOC_FOR_RENDER
);
1930 } else if (tiling
!= I915_TILING_Y
) {
1931 drm_intel_bo_unreference(buf
->bo
);
1942 static struct intel_miptree_aux_buffer
*
1943 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1944 struct intel_mipmap_tree
*mt
)
1946 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1947 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1950 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1955 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1956 buf
->mt
= intel_miptree_create(brw
,
1962 mt
->logical_height0
,
1971 buf
->bo
= buf
->mt
->bo
;
1972 buf
->pitch
= buf
->mt
->pitch
;
1973 buf
->qpitch
= buf
->mt
->qpitch
;
1979 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1980 struct intel_mipmap_tree
*mt
)
1985 if (mt
->hiz_buf
!= NULL
)
1988 if (mt
->disable_aux_buffers
)
1991 switch (mt
->format
) {
1992 case MESA_FORMAT_Z_FLOAT32
:
1993 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1994 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1995 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1996 case MESA_FORMAT_Z_UNORM16
:
2004 intel_miptree_alloc_hiz(struct brw_context
*brw
,
2005 struct intel_mipmap_tree
*mt
)
2007 assert(mt
->hiz_buf
== NULL
);
2008 assert(!mt
->disable_aux_buffers
);
2010 if (brw
->gen
== 7) {
2011 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
2012 } else if (brw
->gen
>= 8) {
2013 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
2015 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
2021 /* Mark that all slices need a HiZ resolve. */
2022 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
2023 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
2026 for (unsigned layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
2027 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
2028 exec_node_init(&m
->link
);
2031 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
2033 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
2041 * Does the miptree slice have hiz enabled?
2044 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
2046 intel_miptree_check_level_layer(mt
, level
, 0);
2047 return mt
->level
[level
].has_hiz
;
2051 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
2055 if (!intel_miptree_level_has_hiz(mt
, level
))
2058 intel_resolve_map_set(&mt
->hiz_map
,
2059 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
2064 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
2068 if (!intel_miptree_level_has_hiz(mt
, level
))
2071 intel_resolve_map_set(&mt
->hiz_map
,
2072 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
2076 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
2080 uint32_t end_layer
= mt
->level
[level
].depth
;
2082 for (layer
= 0; layer
< end_layer
; layer
++) {
2083 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
2088 intel_miptree_slice_resolve(struct brw_context
*brw
,
2089 struct intel_mipmap_tree
*mt
,
2092 enum gen6_hiz_op need
)
2094 intel_miptree_check_level_layer(mt
, level
, layer
);
2096 struct intel_resolve_map
*item
=
2097 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
2099 if (!item
|| item
->need
!= need
)
2102 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
2103 intel_resolve_map_remove(item
);
2108 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
2109 struct intel_mipmap_tree
*mt
,
2113 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2114 GEN6_HIZ_OP_HIZ_RESOLVE
);
2118 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
2119 struct intel_mipmap_tree
*mt
,
2123 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2124 GEN6_HIZ_OP_DEPTH_RESOLVE
);
2128 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
2129 struct intel_mipmap_tree
*mt
,
2130 enum gen6_hiz_op need
)
2132 bool did_resolve
= false;
2134 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
2135 if (map
->need
!= need
)
2138 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
2139 intel_resolve_map_remove(map
);
2147 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
2148 struct intel_mipmap_tree
*mt
)
2150 return intel_miptree_all_slices_resolve(brw
, mt
,
2151 GEN6_HIZ_OP_HIZ_RESOLVE
);
2155 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
2156 struct intel_mipmap_tree
*mt
)
2158 return intel_miptree_all_slices_resolve(brw
, mt
,
2159 GEN6_HIZ_OP_DEPTH_RESOLVE
);
2164 intel_miptree_resolve_color(struct brw_context
*brw
,
2165 struct intel_mipmap_tree
*mt
,
2168 /* From gen9 onwards there is new compression scheme for single sampled
2169 * surfaces called "lossless compressed". These don't need to be always
2172 if ((flags
& INTEL_MIPTREE_IGNORE_CCS_E
) &&
2173 intel_miptree_is_lossless_compressed(brw
, mt
))
2176 switch (mt
->fast_clear_state
) {
2177 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
2178 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
2179 /* No resolve needed */
2181 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
2182 case INTEL_FAST_CLEAR_STATE_CLEAR
:
2183 /* Fast color clear resolves only make sense for non-MSAA buffers. */
2184 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
||
2185 intel_miptree_is_lossless_compressed(brw
, mt
)) {
2186 brw_blorp_resolve_color(brw
, mt
);
2194 * Make it possible to share the BO backing the given miptree with another
2195 * process or another miptree.
2197 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2198 * then discard the MCS buffer, if present. We also set the fast_clear_state
2199 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
2200 * allocated in the future.
2203 intel_miptree_make_shareable(struct brw_context
*brw
,
2204 struct intel_mipmap_tree
*mt
)
2206 /* MCS buffers are also used for multisample buffers, but we can't resolve
2207 * away a multisample MCS buffer because it's an integral part of how the
2208 * pixel data is stored. Fortunately this code path should never be
2209 * reached for multisample buffers.
2211 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
2214 intel_miptree_resolve_color(brw
, mt
, 0);
2215 intel_miptree_release(&mt
->mcs_mt
);
2216 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
2222 * \brief Get pointer offset into stencil buffer.
2224 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2225 * must decode the tile's layout in software.
2228 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2230 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2232 * Even though the returned offset is always positive, the return type is
2234 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2235 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2238 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2240 uint32_t tile_size
= 4096;
2241 uint32_t tile_width
= 64;
2242 uint32_t tile_height
= 64;
2243 uint32_t row_size
= 64 * stride
;
2245 uint32_t tile_x
= x
/ tile_width
;
2246 uint32_t tile_y
= y
/ tile_height
;
2248 /* The byte's address relative to the tile's base addres. */
2249 uint32_t byte_x
= x
% tile_width
;
2250 uint32_t byte_y
= y
% tile_height
;
2252 uintptr_t u
= tile_y
* row_size
2253 + tile_x
* tile_size
2254 + 512 * (byte_x
/ 8)
2256 + 32 * ((byte_y
/ 4) % 2)
2257 + 16 * ((byte_x
/ 4) % 2)
2258 + 8 * ((byte_y
/ 2) % 2)
2259 + 4 * ((byte_x
/ 2) % 2)
2264 /* adjust for bit6 swizzling */
2265 if (((byte_x
/ 8) % 2) == 1) {
2266 if (((byte_y
/ 8) % 2) == 0) {
2278 intel_miptree_updownsample(struct brw_context
*brw
,
2279 struct intel_mipmap_tree
*src
,
2280 struct intel_mipmap_tree
*dst
)
2282 brw_blorp_blit_miptrees(brw
,
2283 src
, 0 /* level */, 0 /* layer */,
2284 src
->format
, SWIZZLE_XYZW
,
2285 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2287 src
->logical_width0
, src
->logical_height0
,
2289 dst
->logical_width0
, dst
->logical_height0
,
2290 GL_NEAREST
, false, false /*mirror x, y*/,
2293 if (src
->stencil_mt
) {
2294 brw_blorp_blit_miptrees(brw
,
2295 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2296 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2297 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2298 dst
->stencil_mt
->format
,
2300 src
->logical_width0
, src
->logical_height0
,
2302 dst
->logical_width0
, dst
->logical_height0
,
2303 GL_NEAREST
, false, false /*mirror x, y*/,
2304 false, false /* decode/encode srgb */);
2309 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2311 /* CPU accesses to color buffers don't understand fast color clears, so
2312 * resolve any pending fast color clears before we map.
2314 intel_miptree_resolve_color(brw
, mt
, 0);
2316 drm_intel_bo
*bo
= mt
->bo
;
2318 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2319 intel_batchbuffer_flush(brw
);
2321 if (mt
->tiling
!= I915_TILING_NONE
)
2322 brw_bo_map_gtt(brw
, bo
, "miptree");
2324 brw_bo_map(brw
, bo
, true, "miptree");
2330 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2332 drm_intel_bo_unmap(mt
->bo
);
2336 intel_miptree_map_gtt(struct brw_context
*brw
,
2337 struct intel_mipmap_tree
*mt
,
2338 struct intel_miptree_map
*map
,
2339 unsigned int level
, unsigned int slice
)
2341 unsigned int bw
, bh
;
2343 unsigned int image_x
, image_y
;
2344 intptr_t x
= map
->x
;
2345 intptr_t y
= map
->y
;
2347 /* For compressed formats, the stride is the number of bytes per
2348 * row of blocks. intel_miptree_get_image_offset() already does
2351 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2352 assert(y
% bh
== 0);
2353 assert(x
% bw
== 0);
2357 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2362 /* Note that in the case of cube maps, the caller must have passed the
2363 * slice number referencing the face.
2365 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2369 map
->stride
= mt
->pitch
;
2370 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2373 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2374 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2375 map
->x
, map
->y
, map
->w
, map
->h
,
2376 mt
, _mesa_get_format_name(mt
->format
),
2377 x
, y
, map
->ptr
, map
->stride
);
2381 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2383 intel_miptree_unmap_raw(mt
);
2387 intel_miptree_map_blit(struct brw_context
*brw
,
2388 struct intel_mipmap_tree
*mt
,
2389 struct intel_miptree_map
*map
,
2390 unsigned int level
, unsigned int slice
)
2392 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2393 /* first_level */ 0,
2397 MIPTREE_LAYOUT_TILING_NONE
);
2399 if (!map
->linear_mt
) {
2400 fprintf(stderr
, "Failed to allocate blit temporary\n");
2403 map
->stride
= map
->linear_mt
->pitch
;
2405 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2406 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2407 * invalidate is set, since we'll be writing the whole rectangle from our
2408 * temporary buffer back out.
2410 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2411 if (!intel_miptree_blit(brw
,
2413 map
->x
, map
->y
, false,
2414 map
->linear_mt
, 0, 0,
2416 map
->w
, map
->h
, GL_COPY
)) {
2417 fprintf(stderr
, "Failed to blit\n");
2422 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
);
2424 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2425 map
->x
, map
->y
, map
->w
, map
->h
,
2426 mt
, _mesa_get_format_name(mt
->format
),
2427 level
, slice
, map
->ptr
, map
->stride
);
2432 intel_miptree_release(&map
->linear_mt
);
2438 intel_miptree_unmap_blit(struct brw_context
*brw
,
2439 struct intel_mipmap_tree
*mt
,
2440 struct intel_miptree_map
*map
,
2444 struct gl_context
*ctx
= &brw
->ctx
;
2446 intel_miptree_unmap_raw(map
->linear_mt
);
2448 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2449 bool ok
= intel_miptree_blit(brw
,
2450 map
->linear_mt
, 0, 0,
2453 map
->x
, map
->y
, false,
2454 map
->w
, map
->h
, GL_COPY
);
2455 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2458 intel_miptree_release(&map
->linear_mt
);
2462 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2464 #if defined(USE_SSE41)
2466 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2467 struct intel_mipmap_tree
*mt
,
2468 struct intel_miptree_map
*map
,
2469 unsigned int level
, unsigned int slice
)
2471 assert(map
->mode
& GL_MAP_READ_BIT
);
2472 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2474 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2475 map
->x
, map
->y
, map
->w
, map
->h
,
2476 mt
, _mesa_get_format_name(mt
->format
),
2477 level
, slice
, map
->ptr
, map
->stride
);
2479 /* Map the original image */
2482 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2486 void *src
= intel_miptree_map_raw(brw
, mt
);
2489 src
+= image_y
* mt
->pitch
;
2490 src
+= image_x
* mt
->cpp
;
2492 /* Due to the pixel offsets for the particular image being mapped, our
2493 * src pointer may not be 16-byte aligned. However, if the pitch is
2494 * divisible by 16, then the amount by which it's misaligned will remain
2495 * consistent from row to row.
2497 assert((mt
->pitch
% 16) == 0);
2498 const int misalignment
= ((uintptr_t) src
) & 15;
2500 /* Create an untiled temporary buffer for the mapping. */
2501 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2503 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2505 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2506 /* Offset the destination so it has the same misalignment as src. */
2507 map
->ptr
= map
->buffer
+ misalignment
;
2509 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2511 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2512 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2513 void *src_ptr
= src
+ y
* mt
->pitch
;
2515 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2518 intel_miptree_unmap_raw(mt
);
2522 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2523 struct intel_mipmap_tree
*mt
,
2524 struct intel_miptree_map
*map
,
2528 _mesa_align_free(map
->buffer
);
2535 intel_miptree_map_s8(struct brw_context
*brw
,
2536 struct intel_mipmap_tree
*mt
,
2537 struct intel_miptree_map
*map
,
2538 unsigned int level
, unsigned int slice
)
2540 map
->stride
= map
->w
;
2541 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2545 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2546 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2547 * invalidate is set, since we'll be writing the whole rectangle from our
2548 * temporary buffer back out.
2550 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2551 uint8_t *untiled_s8_map
= map
->ptr
;
2552 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2553 unsigned int image_x
, image_y
;
2555 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2557 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2558 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2559 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2560 x
+ image_x
+ map
->x
,
2561 y
+ image_y
+ map
->y
,
2562 brw
->has_swizzling
);
2563 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2567 intel_miptree_unmap_raw(mt
);
2569 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2570 map
->x
, map
->y
, map
->w
, map
->h
,
2571 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2573 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2574 map
->x
, map
->y
, map
->w
, map
->h
,
2575 mt
, map
->ptr
, map
->stride
);
2580 intel_miptree_unmap_s8(struct brw_context
*brw
,
2581 struct intel_mipmap_tree
*mt
,
2582 struct intel_miptree_map
*map
,
2586 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2587 unsigned int image_x
, image_y
;
2588 uint8_t *untiled_s8_map
= map
->ptr
;
2589 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2591 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2593 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2594 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2595 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2596 image_x
+ x
+ map
->x
,
2597 image_y
+ y
+ map
->y
,
2598 brw
->has_swizzling
);
2599 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2603 intel_miptree_unmap_raw(mt
);
2610 intel_miptree_map_etc(struct brw_context
*brw
,
2611 struct intel_mipmap_tree
*mt
,
2612 struct intel_miptree_map
*map
,
2616 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2617 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2618 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2621 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2622 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2624 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2625 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2626 map
->w
, map
->h
, 1));
2627 map
->ptr
= map
->buffer
;
2631 intel_miptree_unmap_etc(struct brw_context
*brw
,
2632 struct intel_mipmap_tree
*mt
,
2633 struct intel_miptree_map
*map
,
2639 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2644 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2645 + image_y
* mt
->pitch
2646 + image_x
* mt
->cpp
;
2648 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2649 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2650 map
->ptr
, map
->stride
,
2653 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2654 map
->ptr
, map
->stride
,
2655 map
->w
, map
->h
, mt
->etc_format
);
2657 intel_miptree_unmap_raw(mt
);
2662 * Mapping function for packed depth/stencil miptrees backed by real separate
2663 * miptrees for depth and stencil.
2665 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2666 * separate from the depth buffer. Yet at the GL API level, we have to expose
2667 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2668 * be able to map that memory for texture storage and glReadPixels-type
2669 * operations. We give Mesa core that access by mallocing a temporary and
2670 * copying the data between the actual backing store and the temporary.
2673 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2674 struct intel_mipmap_tree
*mt
,
2675 struct intel_miptree_map
*map
,
2676 unsigned int level
, unsigned int slice
)
2678 struct intel_mipmap_tree
*z_mt
= mt
;
2679 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2680 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2681 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2683 map
->stride
= map
->w
* packed_bpp
;
2684 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2688 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2689 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2690 * invalidate is set, since we'll be writing the whole rectangle from our
2691 * temporary buffer back out.
2693 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2694 uint32_t *packed_map
= map
->ptr
;
2695 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2696 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2697 unsigned int s_image_x
, s_image_y
;
2698 unsigned int z_image_x
, z_image_y
;
2700 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2701 &s_image_x
, &s_image_y
);
2702 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2703 &z_image_x
, &z_image_y
);
2705 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2706 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2707 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2708 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2711 brw
->has_swizzling
);
2712 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2714 (map_x
+ z_image_x
));
2715 uint8_t s
= s_map
[s_offset
];
2716 uint32_t z
= z_map
[z_offset
];
2718 if (map_z32f_x24s8
) {
2719 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2720 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2722 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2727 intel_miptree_unmap_raw(s_mt
);
2728 intel_miptree_unmap_raw(z_mt
);
2730 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2732 map
->x
, map
->y
, map
->w
, map
->h
,
2733 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2734 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2735 map
->ptr
, map
->stride
);
2737 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2738 map
->x
, map
->y
, map
->w
, map
->h
,
2739 mt
, map
->ptr
, map
->stride
);
2744 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2745 struct intel_mipmap_tree
*mt
,
2746 struct intel_miptree_map
*map
,
2750 struct intel_mipmap_tree
*z_mt
= mt
;
2751 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2752 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2754 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2755 uint32_t *packed_map
= map
->ptr
;
2756 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2757 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2758 unsigned int s_image_x
, s_image_y
;
2759 unsigned int z_image_x
, z_image_y
;
2761 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2762 &s_image_x
, &s_image_y
);
2763 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2764 &z_image_x
, &z_image_y
);
2766 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2767 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2768 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2769 x
+ s_image_x
+ map
->x
,
2770 y
+ s_image_y
+ map
->y
,
2771 brw
->has_swizzling
);
2772 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2774 (x
+ z_image_x
+ map
->x
));
2776 if (map_z32f_x24s8
) {
2777 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2778 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2780 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2781 s_map
[s_offset
] = packed
>> 24;
2782 z_map
[z_offset
] = packed
;
2787 intel_miptree_unmap_raw(s_mt
);
2788 intel_miptree_unmap_raw(z_mt
);
2790 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2792 map
->x
, map
->y
, map
->w
, map
->h
,
2793 z_mt
, _mesa_get_format_name(z_mt
->format
),
2794 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2795 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2796 map
->ptr
, map
->stride
);
2803 * Create and attach a map to the miptree at (level, slice). Return the
2806 static struct intel_miptree_map
*
2807 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2816 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2821 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2822 mt
->level
[level
].slice
[slice
].map
= map
;
2834 * Release the map at (level, slice).
2837 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2841 struct intel_miptree_map
**map
;
2843 map
= &mt
->level
[level
].slice
[slice
].map
;
2849 can_blit_slice(struct intel_mipmap_tree
*mt
,
2850 unsigned int level
, unsigned int slice
)
2854 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2855 if (image_x
>= 32768 || image_y
>= 32768)
2858 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2859 if (mt
->pitch
>= 32768)
2866 use_intel_mipree_map_blit(struct brw_context
*brw
,
2867 struct intel_mipmap_tree
*mt
,
2873 /* It's probably not worth swapping to the blit ring because of
2874 * all the overhead involved. But, we must use blitter for the
2875 * surfaces with INTEL_MIPTREE_TRMODE_{YF,YS}.
2877 (!(mode
& GL_MAP_WRITE_BIT
) ||
2878 mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) &&
2880 (mt
->tiling
== I915_TILING_X
||
2881 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2882 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
2883 /* Fast copy blit on skl+ supports all tiling formats. */
2885 can_blit_slice(mt
, level
, slice
))
2888 if (mt
->tiling
!= I915_TILING_NONE
&&
2889 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2890 assert(can_blit_slice(mt
, level
, slice
));
2898 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2899 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2900 * arithmetic overflow.
2902 * If you call this function and use \a out_stride, then you're doing pointer
2903 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2904 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2905 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2906 * which usually have type uint32_t or GLuint.
2909 intel_miptree_map(struct brw_context
*brw
,
2910 struct intel_mipmap_tree
*mt
,
2919 ptrdiff_t *out_stride
)
2921 struct intel_miptree_map
*map
;
2923 assert(mt
->num_samples
<= 1);
2925 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2932 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2933 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2934 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2937 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2938 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2939 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2940 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2941 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2942 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2943 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2944 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2945 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2946 #if defined(USE_SSE41)
2947 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
2948 !mt
->compressed
&& cpu_has_sse4_1
&&
2949 (mt
->pitch
% 16 == 0)) {
2950 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2953 /* intel_miptree_map_gtt() doesn't support surfaces with Yf/Ys tiling. */
2954 assert(mt
->tr_mode
== INTEL_MIPTREE_TRMODE_NONE
);
2955 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2958 *out_ptr
= map
->ptr
;
2959 *out_stride
= map
->stride
;
2961 if (map
->ptr
== NULL
)
2962 intel_miptree_release_map(mt
, level
, slice
);
2966 intel_miptree_unmap(struct brw_context
*brw
,
2967 struct intel_mipmap_tree
*mt
,
2971 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2973 assert(mt
->num_samples
<= 1);
2978 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
2979 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2981 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2982 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2983 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2984 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2985 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2986 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2987 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2988 } else if (map
->linear_mt
) {
2989 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2990 #if defined(USE_SSE41)
2991 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2992 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2995 intel_miptree_unmap_gtt(mt
);
2998 intel_miptree_release_map(mt
, level
, slice
);
3002 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3003 const struct intel_mipmap_tree
*mt
,
3004 struct isl_surf
*surf
)
3006 switch (mt
->target
) {
3008 case GL_TEXTURE_1D_ARRAY
: {
3009 surf
->dim
= ISL_SURF_DIM_1D
;
3010 if (brw
->gen
>= 9 && mt
->tiling
== I915_TILING_NONE
)
3011 surf
->dim_layout
= ISL_DIM_LAYOUT_GEN9_1D
;
3013 surf
->dim_layout
= ISL_DIM_LAYOUT_GEN4_2D
;
3017 case GL_TEXTURE_2D_ARRAY
:
3018 case GL_TEXTURE_RECTANGLE
:
3019 case GL_TEXTURE_CUBE_MAP
:
3020 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3021 case GL_TEXTURE_2D_MULTISAMPLE
:
3022 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3023 case GL_TEXTURE_EXTERNAL_OES
:
3024 surf
->dim
= ISL_SURF_DIM_2D
;
3025 surf
->dim_layout
= ISL_DIM_LAYOUT_GEN4_2D
;
3028 surf
->dim
= ISL_SURF_DIM_3D
;
3030 surf
->dim_layout
= ISL_DIM_LAYOUT_GEN4_2D
;
3032 surf
->dim_layout
= ISL_DIM_LAYOUT_GEN4_3D
;
3035 unreachable("Invalid texture target");
3038 if (mt
->num_samples
> 1) {
3039 switch (mt
->msaa_layout
) {
3040 case INTEL_MSAA_LAYOUT_IMS
:
3041 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3043 case INTEL_MSAA_LAYOUT_UMS
:
3044 case INTEL_MSAA_LAYOUT_CMS
:
3045 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3048 unreachable("Invalid MSAA layout");
3051 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3054 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3055 surf
->tiling
= ISL_TILING_W
;
3056 /* The ISL definition of row_pitch matches the surface state pitch field
3057 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3058 * the factor of 2 for W-tiling in row_pitch.
3060 surf
->row_pitch
= 2 * mt
->pitch
;
3062 switch (mt
->tiling
) {
3063 case I915_TILING_NONE
:
3064 surf
->tiling
= ISL_TILING_LINEAR
;
3067 surf
->tiling
= ISL_TILING_X
;
3070 switch (mt
->tr_mode
) {
3071 case INTEL_MIPTREE_TRMODE_NONE
:
3072 surf
->tiling
= ISL_TILING_Y0
;
3074 case INTEL_MIPTREE_TRMODE_YF
:
3075 surf
->tiling
= ISL_TILING_Yf
;
3077 case INTEL_MIPTREE_TRMODE_YS
:
3078 surf
->tiling
= ISL_TILING_Ys
;
3083 unreachable("Invalid tiling mode");
3086 surf
->row_pitch
= mt
->pitch
;
3089 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3091 if (brw
->gen
>= 9) {
3092 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3093 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3094 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3096 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3097 * alignment in terms of surface elements like we want.
3099 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3102 /* On earlier gens it's stored in pixels. */
3104 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3105 surf
->image_alignment_el
=
3106 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3109 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3110 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3111 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3112 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3113 surf
->logical_level0_px
.array_len
= 1;
3114 } else if (mt
->target
== GL_TEXTURE_CUBE_MAP
||
3115 mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
) {
3116 /* For cube maps, mt->logical_depth0 is in number of cubes */
3117 surf
->logical_level0_px
.depth
= 1;
3118 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
* 6;
3120 surf
->logical_level0_px
.depth
= 1;
3121 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3124 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3125 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3126 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3127 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3128 surf
->phys_level0_sa
.array_len
= 1;
3130 surf
->phys_level0_sa
.depth
= 1;
3131 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3134 surf
->levels
= mt
->last_level
+ 1;
3135 surf
->samples
= MAX2(mt
->num_samples
, 1);
3137 surf
->size
= 0; /* TODO */
3138 surf
->alignment
= 0; /* TODO */
3140 switch (surf
->dim_layout
) {
3141 case ISL_DIM_LAYOUT_GEN4_2D
:
3142 case ISL_DIM_LAYOUT_GEN4_3D
:
3143 if (brw
->gen
>= 9) {
3144 surf
->array_pitch_el_rows
= mt
->qpitch
;
3147 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3148 assert(mt
->qpitch
% bh
== 0);
3149 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3152 case ISL_DIM_LAYOUT_GEN9_1D
:
3153 surf
->array_pitch_el_rows
= 1;
3157 switch (mt
->array_layout
) {
3158 case ALL_LOD_IN_EACH_SLICE
:
3159 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3161 case ALL_SLICES_AT_EACH_LOD
:
3162 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3165 unreachable("Invalid array layout");
3168 surf
->usage
= 0; /* TODO */
3171 /* WARNING: THE SURFACE CREATED BY THIS FUNCTION IS NOT COMPLETE AND CANNOT BE
3172 * USED FOR ANY REAL CALCULATIONS. THE ONLY VALID USE OF SUCH A SURFACE IS TO
3173 * PASS IT INTO isl_surf_fill_state.
3176 intel_miptree_get_aux_isl_surf(struct brw_context
*brw
,
3177 const struct intel_mipmap_tree
*mt
,
3178 struct isl_surf
*surf
,
3179 enum isl_aux_usage
*usage
)
3181 /* Much is the same as the regular surface */
3182 intel_miptree_get_isl_surf(brw
, mt
->mcs_mt
, surf
);
3184 /* Figure out the layout */
3185 if (_mesa_get_format_base_format(mt
->format
) == GL_DEPTH_COMPONENT
) {
3186 *usage
= ISL_AUX_USAGE_HIZ
;
3187 } else if (mt
->num_samples
> 1) {
3188 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
3189 *usage
= ISL_AUX_USAGE_MCS
;
3190 } else if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
3191 assert(brw
->gen
>= 9);
3192 *usage
= ISL_AUX_USAGE_CCS_E
;
3193 } else if (mt
->fast_clear_state
!= INTEL_FAST_CLEAR_STATE_NO_MCS
) {
3194 *usage
= ISL_AUX_USAGE_CCS_D
;
3196 unreachable("Invalid MCS miptree");
3199 /* Figure out the format and tiling of the auxiliary surface */
3201 case ISL_AUX_USAGE_NONE
:
3202 unreachable("Invalid MCS miptree");
3204 case ISL_AUX_USAGE_HIZ
:
3205 surf
->format
= ISL_FORMAT_HIZ
;
3206 surf
->tiling
= ISL_TILING_HIZ
;
3207 surf
->usage
= ISL_SURF_USAGE_HIZ_BIT
;
3210 case ISL_AUX_USAGE_MCS
:
3213 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3214 * HALIGN 16 must be used."
3217 assert(mt
->halign
== 16);
3219 surf
->usage
= ISL_SURF_USAGE_MCS_BIT
;
3221 switch (mt
->num_samples
) {
3222 case 2: surf
->format
= ISL_FORMAT_MCS_2X
; break;
3223 case 4: surf
->format
= ISL_FORMAT_MCS_4X
; break;
3224 case 8: surf
->format
= ISL_FORMAT_MCS_8X
; break;
3225 case 16: surf
->format
= ISL_FORMAT_MCS_16X
; break;
3227 unreachable("Invalid number of samples");
3231 case ISL_AUX_USAGE_CCS_D
:
3232 case ISL_AUX_USAGE_CCS_E
:
3234 * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
3236 * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
3238 * From the hardware spec for GEN9:
3240 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3241 * HALIGN 16 must be used."
3243 assert(mt
->num_samples
<= 1);
3245 assert(mt
->halign
== 16);
3247 surf
->tiling
= ISL_TILING_CCS
;
3248 surf
->usage
= ISL_SURF_USAGE_CCS_BIT
;
3250 if (brw
->gen
>= 9) {
3251 assert(mt
->tiling
== I915_TILING_Y
);
3252 switch (_mesa_get_format_bytes(mt
->format
)) {
3253 case 4: surf
->format
= ISL_FORMAT_GEN9_CCS_32BPP
; break;
3254 case 8: surf
->format
= ISL_FORMAT_GEN9_CCS_64BPP
; break;
3255 case 16: surf
->format
= ISL_FORMAT_GEN9_CCS_128BPP
; break;
3257 unreachable("Invalid format size for color compression");
3259 } else if (mt
->tiling
== I915_TILING_Y
) {
3260 switch (_mesa_get_format_bytes(mt
->format
)) {
3261 case 4: surf
->format
= ISL_FORMAT_GEN7_CCS_32BPP_Y
; break;
3262 case 8: surf
->format
= ISL_FORMAT_GEN7_CCS_64BPP_Y
; break;
3263 case 16: surf
->format
= ISL_FORMAT_GEN7_CCS_128BPP_Y
; break;
3265 unreachable("Invalid format size for color compression");
3268 assert(mt
->tiling
== I915_TILING_X
);
3269 switch (_mesa_get_format_bytes(mt
->format
)) {
3270 case 4: surf
->format
= ISL_FORMAT_GEN7_CCS_32BPP_X
; break;
3271 case 8: surf
->format
= ISL_FORMAT_GEN7_CCS_64BPP_X
; break;
3272 case 16: surf
->format
= ISL_FORMAT_GEN7_CCS_128BPP_X
; break;
3274 unreachable("Invalid format size for color compression");
3280 /* Auxiliary surfaces in ISL have compressed formats and array_pitch_el_rows
3281 * is in elements. This doesn't match intel_mipmap_tree::qpitch which is
3282 * in elements of the primary color surface so we have to divide by the
3283 * compression block height.
3285 surf
->array_pitch_el_rows
= mt
->qpitch
/ isl_format_get_layout(surf
->format
)->bh
;
3288 union isl_color_value
3289 intel_miptree_get_isl_clear_color(struct brw_context
*brw
,
3290 const struct intel_mipmap_tree
*mt
)
3292 union isl_color_value clear_color
;
3294 if (brw
->gen
>= 9) {
3295 clear_color
.i32
[0] = mt
->gen9_fast_clear_color
.i
[0];
3296 clear_color
.i32
[1] = mt
->gen9_fast_clear_color
.i
[1];
3297 clear_color
.i32
[2] = mt
->gen9_fast_clear_color
.i
[2];
3298 clear_color
.i32
[3] = mt
->gen9_fast_clear_color
.i
[3];
3299 } else if (_mesa_is_format_integer(mt
->format
)) {
3300 clear_color
.i32
[0] = (mt
->fast_clear_color_value
& (1u << 31)) != 0;
3301 clear_color
.i32
[1] = (mt
->fast_clear_color_value
& (1u << 30)) != 0;
3302 clear_color
.i32
[2] = (mt
->fast_clear_color_value
& (1u << 29)) != 0;
3303 clear_color
.i32
[3] = (mt
->fast_clear_color_value
& (1u << 28)) != 0;
3305 clear_color
.f32
[0] = (mt
->fast_clear_color_value
& (1u << 31)) != 0;
3306 clear_color
.f32
[1] = (mt
->fast_clear_color_value
& (1u << 30)) != 0;
3307 clear_color
.f32
[2] = (mt
->fast_clear_color_value
& (1u << 29)) != 0;
3308 clear_color
.f32
[3] = (mt
->fast_clear_color_value
& (1u << 28)) != 0;