2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
28 #include <drm_fourcc.h>
30 #include "intel_batchbuffer.h"
31 #include "intel_image.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_tex.h"
34 #include "intel_blit.h"
35 #include "intel_fbo.h"
37 #include "brw_blorp.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
48 #include "x86/common_x86_asm.h"
50 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
52 static void *intel_miptree_map_raw(struct brw_context
*brw
,
53 struct intel_mipmap_tree
*mt
,
56 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
59 intel_miptree_alloc_aux(struct brw_context
*brw
,
60 struct intel_mipmap_tree
*mt
);
63 intel_miptree_supports_mcs(struct brw_context
*brw
,
64 const struct intel_mipmap_tree
*mt
)
66 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
68 /* MCS compression only applies to multisampled miptrees */
69 if (mt
->surf
.samples
<= 1)
72 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
76 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
77 switch (_mesa_get_format_base_format(mt
->format
)) {
78 case GL_DEPTH_COMPONENT
:
79 case GL_STENCIL_INDEX
:
80 case GL_DEPTH_STENCIL
:
83 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
85 * This field must be set to 0 for all SINT MSRTs when all RT channels
88 * In practice this means that we have to disable MCS for all signed
89 * integer MSAA buffers. The alternative, to disable MCS only when one
90 * of the render target channels is disabled, is impractical because it
91 * would require converting between CMS and UMS MSAA layouts on the fly,
94 if (devinfo
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
103 intel_tiling_supports_ccs(const struct brw_context
*brw
,
104 enum isl_tiling tiling
)
106 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
108 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
109 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
111 * - Support is limited to tiled render targets.
113 * Gen9 changes the restriction to Y-tile only.
115 if (devinfo
->gen
>= 9)
116 return tiling
== ISL_TILING_Y0
;
117 else if (devinfo
->gen
>= 7)
118 return tiling
!= ISL_TILING_LINEAR
;
124 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
125 * can be used. This doesn't (and should not) inspect any of the properties of
128 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
129 * beneath the "Fast Color Clear" bullet (p326):
131 * - Support is for non-mip-mapped and non-array surface types only.
133 * And then later, on p327:
135 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
138 * From the Skylake documentation, it is made clear that X-tiling is no longer
141 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
145 intel_miptree_supports_ccs(struct brw_context
*brw
,
146 const struct intel_mipmap_tree
*mt
)
148 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
150 /* MCS support does not exist prior to Gen7 */
151 if (devinfo
->gen
< 7)
154 /* This function applies only to non-multisampled render targets. */
155 if (mt
->surf
.samples
> 1)
158 /* MCS is only supported for color buffers */
159 switch (_mesa_get_format_base_format(mt
->format
)) {
160 case GL_DEPTH_COMPONENT
:
161 case GL_DEPTH_STENCIL
:
162 case GL_STENCIL_INDEX
:
166 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
169 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
170 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
171 mt
->surf
.logical_level0_px
.depth
> 1;
174 /* Multisample surfaces with the CMS layout are not layered surfaces,
175 * yet still have physical_depth0 > 1. Assert that we don't
176 * accidentally reject a multisampled surface here. We should have
177 * rejected it earlier by explicitly checking the sample count.
179 assert(mt
->surf
.samples
== 1);
182 /* Handle the hardware restrictions...
184 * All GENs have the following restriction: "MCS buffer for non-MSRT is
185 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
187 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
188 * Non-MultiSampler Render Target Restrictions) Support is for
189 * non-mip-mapped and non-array surface types only.
191 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
192 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
193 * surfaces are supported with MCS buffer layout with these alignments in
194 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
196 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
197 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
198 * surfaces are supported with MCS buffer layout with these alignments in
199 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
201 if (devinfo
->gen
< 8 && (mip_mapped
|| arrayed
))
204 /* There's no point in using an MCS buffer if the surface isn't in a
207 if (!brw
->mesa_format_supports_render
[mt
->format
])
214 intel_tiling_supports_hiz(const struct brw_context
*brw
,
215 enum isl_tiling tiling
)
217 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
219 if (devinfo
->gen
< 6)
222 return tiling
== ISL_TILING_Y0
;
226 intel_miptree_supports_hiz(const struct brw_context
*brw
,
227 const struct intel_mipmap_tree
*mt
)
232 switch (mt
->format
) {
233 case MESA_FORMAT_Z_FLOAT32
:
234 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
235 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
236 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
237 case MESA_FORMAT_Z_UNORM16
:
245 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
246 const struct intel_mipmap_tree
*mt
)
248 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
250 if (devinfo
->gen
< 9)
253 /* For now compression is only enabled for integer formats even though
254 * there exist supported floating point formats also. This is a heuristic
255 * decision based on current public benchmarks. In none of the cases these
256 * formats provided any improvement but a few cases were seen to regress.
257 * Hence these are left to to be enabled in the future when they are known
260 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
263 if (!intel_miptree_supports_ccs(brw
, mt
))
266 /* Many window system buffers are sRGB even if they are never rendered as
267 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
268 * surface is used as sRGB, we fall back to CCS_D.
270 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
271 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
272 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
276 * Determine depth format corresponding to a depth+stencil format,
277 * for separate stencil.
280 intel_depth_format_for_depthstencil_format(mesa_format format
) {
282 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
283 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
284 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
285 return MESA_FORMAT_Z_FLOAT32
;
292 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
293 unsigned depth0
, struct intel_mipmap_level
*table
)
295 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
297 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
299 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
300 if (!table
[level
].slice
)
307 for (unsigned level
= first_level
; level
<= last_level
; level
++)
308 free(table
[level
].slice
);
314 needs_separate_stencil(const struct brw_context
*brw
,
315 struct intel_mipmap_tree
*mt
,
318 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
320 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
323 if (devinfo
->must_use_separate_stencil
)
326 return brw
->has_separate_stencil
&&
327 intel_miptree_supports_hiz(brw
, mt
);
331 * Choose the aux usage for this miptree. This function must be called fairly
332 * late in the miptree create process after we have a tiling.
335 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
336 struct intel_mipmap_tree
*mt
)
338 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
340 if (intel_miptree_supports_mcs(brw
, mt
)) {
341 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
342 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
343 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
344 intel_miptree_supports_ccs(brw
, mt
)) {
345 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
346 intel_miptree_supports_ccs_e(brw
, mt
)) {
347 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
349 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
351 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
352 intel_miptree_supports_hiz(brw
, mt
)) {
353 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
356 /* We can do fast-clear on all auxiliary surface types that are
357 * allocated through the normal texture creation paths.
359 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
360 mt
->supports_fast_clear
= true;
365 * Choose an appropriate uncompressed format for a requested
366 * compressed format, if unsupported.
369 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
371 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
373 /* No need to lower ETC formats on these platforms,
374 * they are supported natively.
376 if (devinfo
->gen
>= 8 || devinfo
->is_baytrail
)
380 case MESA_FORMAT_ETC1_RGB8
:
381 return MESA_FORMAT_R8G8B8X8_UNORM
;
382 case MESA_FORMAT_ETC2_RGB8
:
383 return MESA_FORMAT_R8G8B8X8_UNORM
;
384 case MESA_FORMAT_ETC2_SRGB8
:
385 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
386 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
387 return MESA_FORMAT_B8G8R8A8_SRGB
;
388 case MESA_FORMAT_ETC2_RGBA8_EAC
:
389 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
390 return MESA_FORMAT_R8G8B8A8_UNORM
;
391 case MESA_FORMAT_ETC2_R11_EAC
:
392 return MESA_FORMAT_R_UNORM16
;
393 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
394 return MESA_FORMAT_R_SNORM16
;
395 case MESA_FORMAT_ETC2_RG11_EAC
:
396 return MESA_FORMAT_R16G16_UNORM
;
397 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
398 return MESA_FORMAT_R16G16_SNORM
;
400 /* Non ETC1 / ETC2 format */
406 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
408 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
409 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
411 return mt
->surf
.logical_level0_px
.array_len
;
414 UNUSED
static unsigned
415 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
417 /* In case of physical dimensions one needs to consider also the layout.
418 * See isl_calc_phys_level0_extent_sa().
420 if (surf
->dim
!= ISL_SURF_DIM_3D
)
421 return surf
->phys_level0_sa
.array_len
;
423 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
424 return minify(surf
->phys_level0_sa
.array_len
, level
);
426 return minify(surf
->phys_level0_sa
.depth
, level
);
429 /** \brief Assert that the level and layer are valid for the miptree. */
431 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
439 assert(level
>= mt
->first_level
);
440 assert(level
<= mt
->last_level
);
441 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
444 static enum isl_aux_state
**
445 create_aux_state_map(struct intel_mipmap_tree
*mt
,
446 enum isl_aux_state initial
)
448 const uint32_t levels
= mt
->last_level
+ 1;
450 uint32_t total_slices
= 0;
451 for (uint32_t level
= 0; level
< levels
; level
++)
452 total_slices
+= brw_get_num_logical_layers(mt
, level
);
454 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
456 /* We're going to allocate a single chunk of data for both the per-level
457 * reference array and the arrays of aux_state. This makes cleanup
458 * significantly easier.
460 const size_t total_size
= per_level_array_size
+
461 total_slices
* sizeof(enum isl_aux_state
);
462 void *data
= malloc(total_size
);
466 enum isl_aux_state
**per_level_arr
= data
;
467 enum isl_aux_state
*s
= data
+ per_level_array_size
;
468 for (uint32_t level
= 0; level
< levels
; level
++) {
469 per_level_arr
[level
] = s
;
470 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
471 for (uint32_t a
= 0; a
< level_layers
; a
++)
474 assert((void *)s
== data
+ total_size
);
476 return per_level_arr
;
480 free_aux_state_map(enum isl_aux_state
**state
)
486 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
487 enum isl_tiling tiling
, unsigned samples
)
492 if (tiling
== ISL_TILING_LINEAR
)
495 /* If the width is much smaller than a tile, don't bother tiling. */
499 if (ALIGN(row_pitch
, 512) >= 32768) {
500 perf_debug("row pitch %u too large to blit, falling back to untiled",
509 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
510 enum isl_tiling tiling
)
512 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
514 /* If the BO is too large to fit in the aperture, we need to use the
515 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
516 * handle Y-tiling, so we need to fall back to X.
518 if (devinfo
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
519 tiling
== ISL_TILING_Y0
)
525 static struct intel_mipmap_tree
*
526 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
527 unsigned first_level
, unsigned last_level
,
528 unsigned width0
, unsigned height0
, unsigned depth0
,
529 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
530 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
531 unsigned row_pitch
, struct brw_bo
*bo
)
533 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
537 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
545 if (target
== GL_TEXTURE_CUBE_MAP
||
546 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
547 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
549 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
551 _mesa_enum_to_string(target
),
552 _mesa_get_format_name(format
),
553 num_samples
, width0
, height0
, depth0
,
554 first_level
, last_level
, mt
);
556 struct isl_surf_init_info init_info
= {
557 .dim
= get_isl_surf_dim(target
),
558 .format
= translate_tex_format(brw
, format
, false),
561 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
562 .levels
= last_level
- first_level
+ 1,
563 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
564 .samples
= num_samples
,
565 .row_pitch
= row_pitch
,
566 .usage
= isl_usage_flags
,
567 .tiling_flags
= tiling_flags
,
570 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
573 /* Depth surfaces are always Y-tiled and stencil is always W-tiled, although
574 * on gen7 platforms we also need to create Y-tiled copies of stencil for
575 * texturing since the hardware can't sample from W-tiled surfaces. For
576 * everything else, check for corner cases needing special treatment.
578 bool is_depth_stencil
=
579 mt
->surf
.usage
& (ISL_SURF_USAGE_STENCIL_BIT
| ISL_SURF_USAGE_DEPTH_BIT
);
580 if (!is_depth_stencil
) {
581 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
582 mt
->surf
.tiling
, mt
->surf
.samples
)) {
583 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
584 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
586 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
587 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
588 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
593 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
594 * the size may not be multiple of row_pitch.
595 * See isl_apply_surface_padding().
597 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
598 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
601 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
603 isl_tiling_to_i915_tiling(
605 mt
->surf
.row_pitch
, alloc_flags
);
612 mt
->first_level
= first_level
;
613 mt
->last_level
= last_level
;
616 mt
->aux_state
= NULL
;
617 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
618 mt
->compressed
= _mesa_is_format_compressed(format
);
619 mt
->drm_modifier
= DRM_FORMAT_MOD_INVALID
;
624 intel_miptree_release(&mt
);
629 make_separate_stencil_surface(struct brw_context
*brw
,
630 struct intel_mipmap_tree
*mt
)
632 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
633 0, mt
->surf
.levels
- 1,
634 mt
->surf
.logical_level0_px
.width
,
635 mt
->surf
.logical_level0_px
.height
,
636 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
637 mt
->surf
.logical_level0_px
.depth
:
638 mt
->surf
.logical_level0_px
.array_len
,
639 mt
->surf
.samples
, ISL_TILING_W_BIT
,
640 ISL_SURF_USAGE_STENCIL_BIT
|
641 ISL_SURF_USAGE_TEXTURE_BIT
,
642 BO_ALLOC_BUSY
, 0, NULL
);
647 mt
->stencil_mt
->r8stencil_needs_update
= true;
652 static struct intel_mipmap_tree
*
653 miptree_create(struct brw_context
*brw
,
662 enum intel_miptree_create_flags flags
)
664 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
666 if (format
== MESA_FORMAT_S_UINT8
)
667 return make_surface(brw
, target
, format
, first_level
, last_level
,
668 width0
, height0
, depth0
, num_samples
,
670 ISL_SURF_USAGE_STENCIL_BIT
|
671 ISL_SURF_USAGE_TEXTURE_BIT
,
676 const GLenum base_format
= _mesa_get_format_base_format(format
);
677 if ((base_format
== GL_DEPTH_COMPONENT
||
678 base_format
== GL_DEPTH_STENCIL
) &&
679 !(flags
& MIPTREE_CREATE_LINEAR
)) {
680 /* Fix up the Z miptree format for how we're splitting out separate
681 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
683 const mesa_format depth_only_format
=
684 intel_depth_format_for_depthstencil_format(format
);
685 struct intel_mipmap_tree
*mt
= make_surface(
686 brw
, target
, devinfo
->gen
>= 6 ? depth_only_format
: format
,
687 first_level
, last_level
,
688 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
689 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
690 BO_ALLOC_BUSY
, 0, NULL
);
692 if (needs_separate_stencil(brw
, mt
, format
) &&
693 !make_separate_stencil_surface(brw
, mt
)) {
694 intel_miptree_release(&mt
);
698 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
699 intel_miptree_choose_aux_usage(brw
, mt
);
704 mesa_format tex_format
= format
;
705 mesa_format etc_format
= MESA_FORMAT_NONE
;
706 uint32_t alloc_flags
= 0;
708 format
= intel_lower_compressed_format(brw
, format
);
710 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
712 if (flags
& MIPTREE_CREATE_BUSY
)
713 alloc_flags
|= BO_ALLOC_BUSY
;
715 isl_tiling_flags_t tiling_flags
= (flags
& MIPTREE_CREATE_LINEAR
) ?
716 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
718 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
719 if (devinfo
->gen
< 6)
720 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
722 struct intel_mipmap_tree
*mt
= make_surface(
724 first_level
, last_level
,
725 width0
, height0
, depth0
,
726 num_samples
, tiling_flags
,
727 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
728 ISL_SURF_USAGE_TEXTURE_BIT
,
729 alloc_flags
, 0, NULL
);
733 mt
->etc_format
= etc_format
;
735 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
736 intel_miptree_choose_aux_usage(brw
, mt
);
741 struct intel_mipmap_tree
*
742 intel_miptree_create(struct brw_context
*brw
,
751 enum intel_miptree_create_flags flags
)
753 assert(num_samples
> 0);
755 struct intel_mipmap_tree
*mt
= miptree_create(
757 first_level
, last_level
,
758 width0
, height0
, depth0
, num_samples
,
765 if (!intel_miptree_alloc_aux(brw
, mt
)) {
766 intel_miptree_release(&mt
);
773 struct intel_mipmap_tree
*
774 intel_miptree_create_for_bo(struct brw_context
*brw
,
782 enum intel_miptree_create_flags flags
)
784 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
785 struct intel_mipmap_tree
*mt
;
786 uint32_t tiling
, swizzle
;
787 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
788 const GLenum base_format
= _mesa_get_format_base_format(format
);
790 if ((base_format
== GL_DEPTH_COMPONENT
||
791 base_format
== GL_DEPTH_STENCIL
)) {
792 const mesa_format depth_only_format
=
793 intel_depth_format_for_depthstencil_format(format
);
794 mt
= make_surface(brw
, target
,
795 devinfo
->gen
>= 6 ? depth_only_format
: format
,
796 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
797 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
798 BO_ALLOC_BUSY
, pitch
, bo
);
802 brw_bo_reference(bo
);
804 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
805 intel_miptree_choose_aux_usage(brw
, mt
);
808 } else if (format
== MESA_FORMAT_S_UINT8
) {
809 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
810 0, 0, width
, height
, depth
, 1,
812 ISL_SURF_USAGE_STENCIL_BIT
|
813 ISL_SURF_USAGE_TEXTURE_BIT
,
814 BO_ALLOC_BUSY
, pitch
, bo
);
818 assert(bo
->size
>= mt
->surf
.size
);
820 brw_bo_reference(bo
);
824 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
826 /* Nothing will be able to use this miptree with the BO if the offset isn't
829 if (tiling
!= I915_TILING_NONE
)
830 assert(offset
% 4096 == 0);
832 /* miptrees can't handle negative pitch. If you need flipping of images,
833 * that's outside of the scope of the mt.
837 /* The BO already has a tiling format and we shouldn't confuse the lower
838 * layers by making it try to find a tiling format again.
840 assert((flags
& MIPTREE_CREATE_LINEAR
) == 0);
842 mt
= make_surface(brw
, target
, format
,
843 0, 0, width
, height
, depth
, 1,
844 1lu << isl_tiling_from_i915_tiling(tiling
),
845 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
846 ISL_SURF_USAGE_TEXTURE_BIT
,
851 brw_bo_reference(bo
);
855 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
856 intel_miptree_choose_aux_usage(brw
, mt
);
858 if (!intel_miptree_alloc_aux(brw
, mt
)) {
859 intel_miptree_release(&mt
);
867 static struct intel_mipmap_tree
*
868 miptree_create_for_planar_image(struct brw_context
*brw
,
869 __DRIimage
*image
, GLenum target
)
871 const struct intel_image_format
*f
= image
->planar_format
;
872 struct intel_mipmap_tree
*planar_mt
= NULL
;
874 for (int i
= 0; i
< f
->nplanes
; i
++) {
875 const int index
= f
->planes
[i
].buffer_index
;
876 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
877 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
878 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
879 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
881 /* Disable creation of the texture's aux buffers because the driver
882 * exposes no EGL API to manage them. That is, there is no API for
883 * resolving the aux buffer's content to the main buffer nor for
884 * invalidating the aux buffer's content.
886 struct intel_mipmap_tree
*mt
=
887 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
888 image
->offsets
[index
],
890 image
->strides
[index
],
891 MIPTREE_CREATE_NO_AUX
);
900 planar_mt
->plane
[i
- 1] = mt
;
903 planar_mt
->drm_modifier
= image
->modifier
;
909 create_ccs_buf_for_image(struct brw_context
*brw
,
911 struct intel_mipmap_tree
*mt
,
912 enum isl_aux_state initial_state
)
914 struct isl_surf temp_ccs_surf
;
916 /* CCS is only supported for very simple miptrees */
917 assert(image
->aux_offset
!= 0 && image
->aux_pitch
!= 0);
918 assert(image
->tile_x
== 0 && image
->tile_y
== 0);
919 assert(mt
->surf
.samples
== 1);
920 assert(mt
->surf
.levels
== 1);
921 assert(mt
->surf
.logical_level0_px
.depth
== 1);
922 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
923 assert(mt
->first_level
== 0);
924 assert(mt
->last_level
== 0);
926 /* We shouldn't already have a CCS */
927 assert(!mt
->mcs_buf
);
929 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
,
933 assert(image
->aux_offset
< image
->bo
->size
);
934 assert(temp_ccs_surf
.size
<= image
->bo
->size
- image
->aux_offset
);
936 mt
->mcs_buf
= calloc(sizeof(*mt
->mcs_buf
), 1);
937 if (mt
->mcs_buf
== NULL
)
940 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
941 if (!mt
->aux_state
) {
947 mt
->mcs_buf
->bo
= image
->bo
;
948 brw_bo_reference(image
->bo
);
950 mt
->mcs_buf
->offset
= image
->aux_offset
;
951 mt
->mcs_buf
->size
= image
->bo
->size
- image
->aux_offset
;
952 mt
->mcs_buf
->pitch
= image
->aux_pitch
;
953 mt
->mcs_buf
->qpitch
= 0;
954 mt
->mcs_buf
->surf
= temp_ccs_surf
;
959 struct intel_mipmap_tree
*
960 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
961 __DRIimage
*image
, GLenum target
,
962 enum isl_colorspace colorspace
,
963 bool is_winsys_image
)
965 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1) {
966 assert(colorspace
== ISL_COLORSPACE_NONE
||
967 colorspace
== ISL_COLORSPACE_YUV
);
968 return miptree_create_for_planar_image(brw
, image
, target
);
971 if (image
->planar_format
)
972 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
974 mesa_format format
= image
->format
;
975 switch (colorspace
) {
976 case ISL_COLORSPACE_NONE
:
977 /* Keep the image format unmodified */
980 case ISL_COLORSPACE_LINEAR
:
981 format
=_mesa_get_srgb_format_linear(format
);
984 case ISL_COLORSPACE_SRGB
:
985 format
=_mesa_get_linear_format_srgb(format
);
989 unreachable("Inalid colorspace for non-planar image");
992 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
993 /* The texture storage paths in core Mesa detect if the driver does not
994 * support the user-requested format, and then searches for a
995 * fallback format. The DRIimage code bypasses core Mesa, though. So we
996 * do the fallbacks here for important formats.
998 * We must support DRM_FOURCC_XBGR8888 textures because the Android
999 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1000 * the Chrome OS compositor consumes as dma_buf EGLImages.
1002 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1005 if (!brw
->ctx
.TextureFormatSupported
[format
])
1008 const struct isl_drm_modifier_info
*mod_info
=
1009 isl_drm_modifier_get_info(image
->modifier
);
1011 enum intel_miptree_create_flags mt_create_flags
= 0;
1013 /* If this image comes in from a window system, we have different
1014 * requirements than if it comes in via an EGL import operation. Window
1015 * system images can use any form of auxiliary compression we wish because
1016 * they get "flushed" before being handed off to the window system and we
1017 * have the opportunity to do resolves. Non window-system images, on the
1018 * other hand, have no resolve point so we can't have aux without a
1021 if (!is_winsys_image
)
1022 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1024 /* If we have a modifier which specifies aux, don't create one yet */
1025 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
1026 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1028 /* Disable creation of the texture's aux buffers because the driver exposes
1029 * no EGL API to manage them. That is, there is no API for resolving the aux
1030 * buffer's content to the main buffer nor for invalidating the aux buffer's
1033 struct intel_mipmap_tree
*mt
=
1034 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1035 image
->offset
, image
->width
, image
->height
, 1,
1036 image
->pitch
, mt_create_flags
);
1040 mt
->target
= target
;
1041 mt
->level
[0].level_x
= image
->tile_x
;
1042 mt
->level
[0].level_y
= image
->tile_y
;
1043 mt
->drm_modifier
= image
->modifier
;
1045 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1046 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1047 * trouble resolving back to destination image due to alignment issues.
1049 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1050 if (!devinfo
->has_surface_tile_offset
) {
1051 uint32_t draw_x
, draw_y
;
1052 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1054 if (draw_x
!= 0 || draw_y
!= 0) {
1055 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1056 intel_miptree_release(&mt
);
1061 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1062 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1064 mt
->aux_usage
= mod_info
->aux_usage
;
1065 /* If we are a window system buffer, then we can support fast-clears
1066 * even if the modifier doesn't support them by doing a partial resolve
1067 * as part of the flush operation.
1069 mt
->supports_fast_clear
=
1070 is_winsys_image
|| mod_info
->supports_clear_color
;
1072 /* We don't know the actual state of the surface when we get it but we
1073 * can make a pretty good guess based on the modifier. What we do know
1074 * for sure is that it isn't in the AUX_INVALID state, so we just assume
1075 * a worst case of compression.
1077 enum isl_aux_state initial_state
=
1078 isl_drm_modifier_get_default_aux_state(image
->modifier
);
1080 if (!create_ccs_buf_for_image(brw
, image
, mt
, initial_state
)) {
1081 intel_miptree_release(&mt
);
1086 /* Don't assume coherency for imported EGLimages. We don't know what
1087 * external clients are going to do with it. They may scan it out.
1089 image
->bo
->cache_coherent
= false;
1095 * For a singlesample renderbuffer, this simply wraps the given BO with a
1098 * For a multisample renderbuffer, this wraps the window system's
1099 * (singlesample) BO with a singlesample miptree attached to the
1100 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1101 * that will contain the actual rendering (which is lazily resolved to
1102 * irb->singlesample_mt).
1105 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1106 struct intel_renderbuffer
*irb
,
1107 struct intel_mipmap_tree
*singlesample_mt
,
1108 uint32_t width
, uint32_t height
,
1111 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1112 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1113 mesa_format format
= rb
->Format
;
1114 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1116 /* Only the front and back buffers, which are color buffers, are allocated
1117 * through the image loader.
1119 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1120 _mesa_get_format_base_format(format
) == GL_RGBA
);
1122 assert(singlesample_mt
);
1124 if (num_samples
== 1) {
1125 intel_miptree_release(&irb
->mt
);
1126 irb
->mt
= singlesample_mt
;
1128 assert(!irb
->singlesample_mt
);
1130 intel_miptree_release(&irb
->singlesample_mt
);
1131 irb
->singlesample_mt
= singlesample_mt
;
1134 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1135 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1136 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1141 if (!multisample_mt
)
1144 irb
->need_downsample
= false;
1145 intel_miptree_release(&irb
->mt
);
1146 irb
->mt
= multisample_mt
;
1152 intel_miptree_release(&irb
->mt
);
1156 struct intel_mipmap_tree
*
1157 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1161 uint32_t num_samples
)
1163 struct intel_mipmap_tree
*mt
;
1165 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1167 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1168 width
, height
, depth
, num_samples
,
1169 MIPTREE_CREATE_BUSY
);
1176 intel_miptree_release(&mt
);
1181 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1182 struct intel_mipmap_tree
*src
)
1187 intel_miptree_release(dst
);
1191 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1198 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1200 if (aux_buf
== NULL
)
1203 brw_bo_unreference(aux_buf
->bo
);
1209 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1214 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1215 if (--(*mt
)->refcount
<= 0) {
1218 DBG("%s deleting %p\n", __func__
, *mt
);
1220 brw_bo_unreference((*mt
)->bo
);
1221 intel_miptree_release(&(*mt
)->stencil_mt
);
1222 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1223 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1224 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1225 free_aux_state_map((*mt
)->aux_state
);
1227 intel_miptree_release(&(*mt
)->plane
[0]);
1228 intel_miptree_release(&(*mt
)->plane
[1]);
1230 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1231 free((*mt
)->level
[i
].slice
);
1241 intel_get_image_dims(struct gl_texture_image
*image
,
1242 int *width
, int *height
, int *depth
)
1244 switch (image
->TexObject
->Target
) {
1245 case GL_TEXTURE_1D_ARRAY
:
1246 /* For a 1D Array texture the OpenGL API will treat the image height as
1247 * the number of array slices. For Intel hardware, we treat the 1D array
1248 * as a 2D Array with a height of 1. So, here we want to swap image
1251 assert(image
->Depth
== 1);
1252 *width
= image
->Width
;
1254 *depth
= image
->Height
;
1256 case GL_TEXTURE_CUBE_MAP
:
1257 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1258 * though we really have 6 slices.
1260 assert(image
->Depth
== 1);
1261 *width
= image
->Width
;
1262 *height
= image
->Height
;
1266 *width
= image
->Width
;
1267 *height
= image
->Height
;
1268 *depth
= image
->Depth
;
1274 * Can the image be pulled into a unified mipmap tree? This mirrors
1275 * the completeness test in a lot of ways.
1277 * Not sure whether I want to pass gl_texture_image here.
1280 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1281 struct gl_texture_image
*image
)
1283 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1284 GLuint level
= intelImage
->base
.Base
.Level
;
1285 int width
, height
, depth
;
1287 /* glTexImage* choose the texture object based on the target passed in, and
1288 * objects can't change targets over their lifetimes, so this should be
1291 assert(image
->TexObject
->Target
== mt
->target
);
1293 mesa_format mt_format
= mt
->format
;
1294 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1295 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1296 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1297 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1298 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1299 mt_format
= mt
->etc_format
;
1301 if (image
->TexFormat
!= mt_format
)
1304 intel_get_image_dims(image
, &width
, &height
, &depth
);
1306 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1309 if (level
>= mt
->surf
.levels
)
1312 const unsigned level_depth
=
1313 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1314 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1315 mt
->surf
.logical_level0_px
.array_len
;
1317 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1318 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1319 depth
== level_depth
&&
1320 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1324 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1325 GLuint level
, GLuint slice
,
1326 GLuint
*x
, GLuint
*y
)
1328 if (level
== 0 && slice
== 0) {
1329 *x
= mt
->level
[0].level_x
;
1330 *y
= mt
->level
[0].level_y
;
1334 uint32_t x_offset_sa
, y_offset_sa
;
1336 /* Miptree itself can have an offset only if it represents a single
1337 * slice in an imported buffer object.
1338 * See intel_miptree_create_for_dri_image().
1340 assert(mt
->level
[0].level_x
== 0);
1341 assert(mt
->level
[0].level_y
== 0);
1343 /* Given level is relative to level zero while the miptree may be
1344 * represent just a subset of all levels starting from 'first_level'.
1346 assert(level
>= mt
->first_level
);
1347 level
-= mt
->first_level
;
1349 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1350 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1351 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1352 &x_offset_sa
, &y_offset_sa
);
1360 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1361 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1362 * and tile_h is set to 1.
1365 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1366 uint32_t *tile_w
, uint32_t *tile_h
)
1377 case ISL_TILING_LINEAR
:
1382 unreachable("not reached");
1388 * This function computes masks that may be used to select the bits of the X
1389 * and Y coordinates that indicate the offset within a tile. If the BO is
1390 * untiled, the masks are set to 0.
1393 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1394 uint32_t *mask_x
, uint32_t *mask_y
)
1396 uint32_t tile_w_bytes
, tile_h
;
1398 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1400 *mask_x
= tile_w_bytes
/ cpp
- 1;
1401 *mask_y
= tile_h
- 1;
1405 * Compute the offset (in bytes) from the start of the BO to the given x
1406 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1407 * multiples of the tile size.
1410 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1411 uint32_t x
, uint32_t y
)
1414 uint32_t pitch
= mt
->surf
.row_pitch
;
1416 switch (mt
->surf
.tiling
) {
1418 unreachable("not reached");
1419 case ISL_TILING_LINEAR
:
1420 return y
* pitch
+ x
* cpp
;
1422 assert((x
% (512 / cpp
)) == 0);
1423 assert((y
% 8) == 0);
1424 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1426 assert((x
% (128 / cpp
)) == 0);
1427 assert((y
% 32) == 0);
1428 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1433 * Rendering with tiled buffers requires that the base address of the buffer
1434 * be aligned to a page boundary. For renderbuffers, and sometimes with
1435 * textures, we may want the surface to point at a texture image level that
1436 * isn't at a page boundary.
1438 * This function returns an appropriately-aligned base offset
1439 * according to the tiling restrictions, plus any required x/y offset
1443 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1444 GLuint level
, GLuint slice
,
1449 uint32_t mask_x
, mask_y
;
1451 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1452 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1454 *tile_x
= x
& mask_x
;
1455 *tile_y
= y
& mask_y
;
1457 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1461 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1462 struct intel_mipmap_tree
*src_mt
,
1463 unsigned src_level
, unsigned src_layer
,
1464 struct intel_mipmap_tree
*dst_mt
,
1465 unsigned dst_level
, unsigned dst_layer
,
1466 unsigned width
, unsigned height
)
1469 ptrdiff_t src_stride
, dst_stride
;
1470 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1472 intel_miptree_map(brw
, src_mt
,
1473 src_level
, src_layer
,
1476 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1479 intel_miptree_map(brw
, dst_mt
,
1480 dst_level
, dst_layer
,
1483 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1487 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1488 _mesa_get_format_name(src_mt
->format
),
1489 src_mt
, src
, src_stride
,
1490 _mesa_get_format_name(dst_mt
->format
),
1491 dst_mt
, dst
, dst_stride
,
1494 int row_size
= cpp
* width
;
1495 if (src_stride
== row_size
&&
1496 dst_stride
== row_size
) {
1497 memcpy(dst
, src
, row_size
* height
);
1499 for (int i
= 0; i
< height
; i
++) {
1500 memcpy(dst
, src
, row_size
);
1506 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1507 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1509 /* Don't forget to copy the stencil data over, too. We could have skipped
1510 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1511 * shuffling the two data sources in/out of temporary storage instead of
1512 * the direct mapping we get this way.
1514 if (dst_mt
->stencil_mt
) {
1515 assert(src_mt
->stencil_mt
);
1516 intel_miptree_copy_slice_sw(brw
,
1517 src_mt
->stencil_mt
, src_level
, src_layer
,
1518 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1524 intel_miptree_copy_slice(struct brw_context
*brw
,
1525 struct intel_mipmap_tree
*src_mt
,
1526 unsigned src_level
, unsigned src_layer
,
1527 struct intel_mipmap_tree
*dst_mt
,
1528 unsigned dst_level
, unsigned dst_layer
)
1531 mesa_format format
= src_mt
->format
;
1532 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1533 src_level
- src_mt
->first_level
);
1534 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1535 src_level
- src_mt
->first_level
);
1537 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1538 src_level
- src_mt
->first_level
));
1540 assert(src_mt
->format
== dst_mt
->format
);
1542 if (dst_mt
->compressed
) {
1544 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1545 height
= ALIGN_NPOT(height
, j
) / j
;
1546 width
= ALIGN_NPOT(width
, i
) / i
;
1549 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1550 * below won't apply since we can't do the depth's Y tiling or the
1551 * stencil's W tiling in the blitter.
1553 if (src_mt
->stencil_mt
) {
1554 intel_miptree_copy_slice_sw(brw
,
1555 src_mt
, src_level
, src_layer
,
1556 dst_mt
, dst_level
, dst_layer
,
1561 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1562 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1564 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1567 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1568 _mesa_get_format_name(src_mt
->format
),
1569 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1570 _mesa_get_format_name(dst_mt
->format
),
1571 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1574 if (!intel_miptree_blit(brw
,
1575 src_mt
, src_level
, src_layer
, 0, 0, false,
1576 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1577 width
, height
, GL_COPY
)) {
1578 perf_debug("miptree validate blit for %s failed\n",
1579 _mesa_get_format_name(format
));
1581 intel_miptree_copy_slice_sw(brw
,
1582 src_mt
, src_level
, src_layer
,
1583 dst_mt
, dst_level
, dst_layer
,
1589 * Copies the image's current data to the given miptree, and associates that
1590 * miptree with the image.
1592 * If \c invalidate is true, then the actual image data does not need to be
1593 * copied, but the image still needs to be associated to the new miptree (this
1594 * is set to true if we're about to clear the image).
1597 intel_miptree_copy_teximage(struct brw_context
*brw
,
1598 struct intel_texture_image
*intelImage
,
1599 struct intel_mipmap_tree
*dst_mt
,
1602 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1603 struct intel_texture_object
*intel_obj
=
1604 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1605 int level
= intelImage
->base
.Base
.Level
;
1606 const unsigned face
= intelImage
->base
.Base
.Face
;
1607 unsigned start_layer
, end_layer
;
1609 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1611 assert(intelImage
->base
.Base
.Height
);
1613 end_layer
= intelImage
->base
.Base
.Height
- 1;
1614 } else if (face
> 0) {
1618 assert(intelImage
->base
.Base
.Depth
);
1620 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1624 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1625 intel_miptree_copy_slice(brw
,
1631 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1632 intel_obj
->needs_validate
= true;
1636 intel_miptree_init_mcs(struct brw_context
*brw
,
1637 struct intel_mipmap_tree
*mt
,
1640 assert(mt
->mcs_buf
!= NULL
);
1642 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1644 * When MCS buffer is enabled and bound to MSRT, it is required that it
1645 * is cleared prior to any rendering.
1647 * Since we don't use the MCS buffer for any purpose other than rendering,
1648 * it makes sense to just clear it immediately upon allocation.
1650 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1652 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1653 if (unlikely(map
== NULL
)) {
1654 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1655 brw_bo_unreference(mt
->mcs_buf
->bo
);
1660 memset(data
, init_value
, mt
->mcs_buf
->size
);
1661 brw_bo_unmap(mt
->mcs_buf
->bo
);
1664 static struct intel_miptree_aux_buffer
*
1665 intel_alloc_aux_buffer(struct brw_context
*brw
,
1667 const struct isl_surf
*aux_surf
,
1668 uint32_t alloc_flags
,
1669 struct intel_mipmap_tree
*mt
)
1671 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1675 buf
->size
= aux_surf
->size
;
1676 buf
->pitch
= aux_surf
->row_pitch
;
1677 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1679 /* ISL has stricter set of alignment rules then the drm allocator.
1680 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1681 * trying to recalculate based on different format block sizes.
1683 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1684 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1690 buf
->surf
= *aux_surf
;
1696 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1697 struct intel_mipmap_tree
*mt
,
1700 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1702 assert(devinfo
->gen
>= 7); /* MCS only used on Gen7+ */
1703 assert(mt
->mcs_buf
== NULL
);
1704 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1706 /* Multisampled miptrees are only supported for single level. */
1707 assert(mt
->first_level
== 0);
1708 enum isl_aux_state
**aux_state
=
1709 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1713 struct isl_surf temp_mcs_surf
;
1715 MAYBE_UNUSED
bool ok
=
1716 isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_mcs_surf
);
1719 /* Buffer needs to be initialised requiring the buffer to be immediately
1720 * mapped to cpu space for writing. Therefore do not use the gpu access
1721 * flag which can cause an unnecessary delay if the backing pages happened
1722 * to be just used by the GPU.
1724 const uint32_t alloc_flags
= 0;
1725 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1726 &temp_mcs_surf
, alloc_flags
, mt
);
1732 mt
->aux_state
= aux_state
;
1734 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1740 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1741 struct intel_mipmap_tree
*mt
)
1743 assert(mt
->mcs_buf
== NULL
);
1744 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1745 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1747 struct isl_surf temp_ccs_surf
;
1749 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
, 0))
1752 assert(temp_ccs_surf
.size
&&
1753 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1755 enum isl_aux_state
**aux_state
=
1756 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1760 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1761 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1763 * "If Software wants to enable Color Compression without Fast clear,
1764 * Software needs to initialize MCS with zeros."
1766 * A CCS value of 0 indicates that the corresponding block is in the
1767 * pass-through state which is what we want.
1769 * For CCS_D, on the other hand, we don't care as we're about to perform a
1770 * fast-clear operation. In that case, being hot in caches more useful.
1772 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1773 BO_ALLOC_ZEROED
: BO_ALLOC_BUSY
;
1774 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1775 &temp_ccs_surf
, alloc_flags
, mt
);
1781 mt
->aux_state
= aux_state
;
1787 * Helper for intel_miptree_alloc_hiz() that sets
1788 * \c mt->level[level].has_hiz. Return true if and only if
1789 * \c has_hiz was set.
1792 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1793 struct intel_mipmap_tree
*mt
,
1796 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1798 assert(mt
->hiz_buf
);
1799 assert(mt
->surf
.size
> 0);
1801 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
1802 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1803 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1805 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1806 * and the height is 4 aligned. This allows our HiZ support
1807 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1808 * we can grow the width & height to allow the HiZ op to
1809 * force the proper size alignments.
1811 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1812 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1817 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1818 mt
->level
[level
].has_hiz
= true;
1823 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1824 struct intel_mipmap_tree
*mt
)
1826 assert(mt
->hiz_buf
== NULL
);
1827 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1829 enum isl_aux_state
**aux_state
=
1830 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1834 struct isl_surf temp_hiz_surf
;
1836 MAYBE_UNUSED
bool ok
=
1837 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
1840 const uint32_t alloc_flags
= BO_ALLOC_BUSY
;
1841 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1842 &temp_hiz_surf
, alloc_flags
, mt
);
1849 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1850 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1852 mt
->aux_state
= aux_state
;
1859 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1861 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1862 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1863 * compress clear color so we wait until an actual fast-clear to allocate it.
1866 intel_miptree_alloc_aux(struct brw_context
*brw
,
1867 struct intel_mipmap_tree
*mt
)
1869 switch (mt
->aux_usage
) {
1870 case ISL_AUX_USAGE_NONE
:
1873 case ISL_AUX_USAGE_HIZ
:
1874 assert(!_mesa_is_format_color_format(mt
->format
));
1875 if (!intel_miptree_alloc_hiz(brw
, mt
))
1879 case ISL_AUX_USAGE_MCS
:
1880 assert(_mesa_is_format_color_format(mt
->format
));
1881 assert(mt
->surf
.samples
> 1);
1882 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
1886 case ISL_AUX_USAGE_CCS_D
:
1887 /* Since CCS_D can only compress clear color so we wait until an actual
1888 * fast-clear to allocate it.
1892 case ISL_AUX_USAGE_CCS_E
:
1893 assert(_mesa_is_format_color_format(mt
->format
));
1894 assert(mt
->surf
.samples
== 1);
1895 if (!intel_miptree_alloc_ccs(brw
, mt
))
1900 unreachable("Invalid aux usage");
1905 * Can the miptree sample using the hiz buffer?
1908 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1909 struct intel_mipmap_tree
*mt
)
1911 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1913 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1914 * so keep things conservative for now and never enable it unless we're SKL+.
1916 if (devinfo
->gen
< 9) {
1924 /* It seems the hardware won't fallback to the depth buffer if some of the
1925 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1926 * of the texture to be HiZ enabled.
1928 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1929 if (!intel_miptree_level_has_hiz(mt
, level
))
1933 /* If compressed multisampling is enabled, then we use it for the auxiliary
1936 * From the BDW PRM (Volume 2d: Command Reference: Structures
1937 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1939 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1940 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1942 * There is no such blurb for 1D textures, but there is sufficient evidence
1943 * that this is broken on SKL+.
1945 return (mt
->surf
.samples
== 1 &&
1946 mt
->target
!= GL_TEXTURE_3D
&&
1947 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1951 * Does the miptree slice have hiz enabled?
1954 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1956 intel_miptree_check_level_layer(mt
, level
, 0);
1957 return mt
->level
[level
].has_hiz
;
1960 static inline uint32_t
1961 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1962 uint32_t start_level
, uint32_t num_levels
)
1964 assert(start_level
>= mt
->first_level
);
1965 assert(start_level
<= mt
->last_level
);
1967 if (num_levels
== INTEL_REMAINING_LAYERS
)
1968 num_levels
= mt
->last_level
- start_level
+ 1;
1969 /* Check for overflow */
1970 assert(start_level
+ num_levels
>= start_level
);
1971 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
1976 static inline uint32_t
1977 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
1978 uint32_t start_layer
, uint32_t num_layers
)
1980 assert(level
<= mt
->last_level
);
1982 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
1983 assert(start_layer
< total_num_layers
);
1984 if (num_layers
== INTEL_REMAINING_LAYERS
)
1985 num_layers
= total_num_layers
- start_layer
;
1986 /* Check for overflow */
1987 assert(start_layer
+ num_layers
>= start_layer
);
1988 assert(start_layer
+ num_layers
<= total_num_layers
);
1994 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1995 unsigned start_level
, unsigned num_levels
,
1996 unsigned start_layer
, unsigned num_layers
)
1998 assert(_mesa_is_format_color_format(mt
->format
));
2003 /* Clamp the level range to fit the miptree */
2004 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2006 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2007 const uint32_t level
= start_level
+ l
;
2008 const uint32_t level_layers
=
2009 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2010 for (unsigned a
= 0; a
< level_layers
; a
++) {
2011 enum isl_aux_state aux_state
=
2012 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2013 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2014 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2023 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2024 const struct intel_mipmap_tree
*mt
,
2025 unsigned level
, unsigned layer
)
2027 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2032 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2033 assert(devinfo
->gen
>= 8 ||
2034 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2036 /* Compression of arrayed msaa surfaces is supported. */
2037 if (mt
->surf
.samples
> 1)
2040 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2041 assert(devinfo
->gen
>= 8 ||
2043 mt
->surf
.logical_level0_px
.depth
== 1 &&
2044 mt
->surf
.logical_level0_px
.array_len
== 1));
2050 static enum blorp_fast_clear_op
2051 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2052 enum isl_aux_usage aux_usage
,
2053 bool fast_clear_supported
)
2055 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
2057 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
2059 assert(ccs_supported
== fast_clear_supported
);
2061 switch (aux_state
) {
2062 case ISL_AUX_STATE_CLEAR
:
2063 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2065 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2067 return BLORP_FAST_CLEAR_OP_NONE
;
2069 case ISL_AUX_STATE_PASS_THROUGH
:
2070 return BLORP_FAST_CLEAR_OP_NONE
;
2072 case ISL_AUX_STATE_RESOLVED
:
2073 case ISL_AUX_STATE_AUX_INVALID
:
2074 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2075 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2079 unreachable("Invalid aux state for CCS_D");
2082 static enum blorp_fast_clear_op
2083 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2084 enum isl_aux_usage aux_usage
,
2085 bool fast_clear_supported
)
2087 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
2088 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2089 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2090 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2092 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
2093 assert(fast_clear_supported
);
2095 switch (aux_state
) {
2096 case ISL_AUX_STATE_CLEAR
:
2097 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2098 if (fast_clear_supported
)
2099 return BLORP_FAST_CLEAR_OP_NONE
;
2100 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
2101 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2103 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2105 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2106 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2107 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2108 else if (!fast_clear_supported
)
2109 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2111 return BLORP_FAST_CLEAR_OP_NONE
;
2113 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2114 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2115 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2117 return BLORP_FAST_CLEAR_OP_NONE
;
2119 case ISL_AUX_STATE_PASS_THROUGH
:
2120 return BLORP_FAST_CLEAR_OP_NONE
;
2122 case ISL_AUX_STATE_RESOLVED
:
2123 case ISL_AUX_STATE_AUX_INVALID
:
2127 unreachable("Invalid aux state for CCS_E");
2131 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2132 struct intel_mipmap_tree
*mt
,
2133 uint32_t level
, uint32_t layer
,
2134 enum isl_aux_usage aux_usage
,
2135 bool fast_clear_supported
)
2137 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2139 enum blorp_fast_clear_op resolve_op
;
2140 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2141 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2142 fast_clear_supported
);
2144 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2145 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2146 fast_clear_supported
);
2149 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2150 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2151 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2153 switch (resolve_op
) {
2154 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2155 /* The CCS full resolve operation destroys the CCS and sets it to the
2156 * pass-through state. (You can also think of this as being both a
2157 * resolve and an ambiguate in one operation.)
2159 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2160 ISL_AUX_STATE_PASS_THROUGH
);
2163 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2164 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2165 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2169 unreachable("Invalid resolve op");
2175 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2176 struct intel_mipmap_tree
*mt
,
2177 uint32_t level
, uint32_t layer
,
2178 enum isl_aux_usage aux_usage
)
2180 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2181 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2182 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2184 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2186 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2187 switch (aux_state
) {
2188 case ISL_AUX_STATE_CLEAR
:
2189 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2190 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2191 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2193 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2194 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2195 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2196 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2197 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2198 ISL_AUX_STATE_PARTIAL_CLEAR
);
2202 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2203 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2204 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2205 break; /* Nothing to do */
2207 case ISL_AUX_STATE_PASS_THROUGH
:
2208 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2209 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2210 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2216 case ISL_AUX_STATE_RESOLVED
:
2217 case ISL_AUX_STATE_AUX_INVALID
:
2218 unreachable("Invalid aux state for CCS_E");
2221 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2222 /* CCS_D is a bit simpler */
2223 switch (aux_state
) {
2224 case ISL_AUX_STATE_CLEAR
:
2225 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2226 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2227 ISL_AUX_STATE_PARTIAL_CLEAR
);
2230 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2231 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2232 break; /* Nothing to do */
2234 case ISL_AUX_STATE_PASS_THROUGH
:
2238 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2239 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2240 case ISL_AUX_STATE_RESOLVED
:
2241 case ISL_AUX_STATE_AUX_INVALID
:
2242 unreachable("Invalid aux state for CCS_D");
2248 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2249 struct intel_mipmap_tree
*mt
,
2251 enum isl_aux_usage aux_usage
,
2252 bool fast_clear_supported
)
2254 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2256 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2257 case ISL_AUX_STATE_CLEAR
:
2258 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2259 if (!fast_clear_supported
) {
2260 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2261 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2262 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2266 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2267 break; /* Nothing to do */
2269 case ISL_AUX_STATE_RESOLVED
:
2270 case ISL_AUX_STATE_PASS_THROUGH
:
2271 case ISL_AUX_STATE_AUX_INVALID
:
2272 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2273 unreachable("Invalid aux state for MCS");
2278 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2279 struct intel_mipmap_tree
*mt
,
2281 enum isl_aux_usage aux_usage
)
2283 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2285 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2286 case ISL_AUX_STATE_CLEAR
:
2287 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2288 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2291 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2292 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2293 break; /* Nothing to do */
2295 case ISL_AUX_STATE_RESOLVED
:
2296 case ISL_AUX_STATE_PASS_THROUGH
:
2297 case ISL_AUX_STATE_AUX_INVALID
:
2298 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2299 unreachable("Invalid aux state for MCS");
2304 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2305 struct intel_mipmap_tree
*mt
,
2306 uint32_t level
, uint32_t layer
,
2307 enum isl_aux_usage aux_usage
,
2308 bool fast_clear_supported
)
2310 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2312 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2313 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2314 case ISL_AUX_STATE_CLEAR
:
2315 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2316 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2317 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2320 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2321 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2322 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2325 case ISL_AUX_STATE_PASS_THROUGH
:
2326 case ISL_AUX_STATE_RESOLVED
:
2329 case ISL_AUX_STATE_AUX_INVALID
:
2330 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2331 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2334 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2335 unreachable("Invalid HiZ state");
2338 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2339 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2342 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2343 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2344 ISL_AUX_STATE_RESOLVED
);
2347 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2348 /* The HiZ resolve operation is actually an ambiguate */
2349 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2350 ISL_AUX_STATE_PASS_THROUGH
);
2354 unreachable("Invalid HiZ op");
2360 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2361 struct intel_mipmap_tree
*mt
,
2362 uint32_t level
, uint32_t layer
,
2363 enum isl_aux_usage aux_usage
)
2365 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2367 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2368 case ISL_AUX_STATE_CLEAR
:
2369 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2370 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2371 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2374 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2375 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2376 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2377 break; /* Nothing to do */
2379 case ISL_AUX_STATE_RESOLVED
:
2380 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2381 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2382 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2384 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2385 ISL_AUX_STATE_AUX_INVALID
);
2389 case ISL_AUX_STATE_PASS_THROUGH
:
2390 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2391 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2392 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2396 case ISL_AUX_STATE_AUX_INVALID
:
2397 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2400 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2401 unreachable("Invalid HiZ state");
2406 intel_miptree_prepare_access(struct brw_context
*brw
,
2407 struct intel_mipmap_tree
*mt
,
2408 uint32_t start_level
, uint32_t num_levels
,
2409 uint32_t start_layer
, uint32_t num_layers
,
2410 enum isl_aux_usage aux_usage
,
2411 bool fast_clear_supported
)
2413 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2415 switch (mt
->aux_usage
) {
2416 case ISL_AUX_USAGE_NONE
:
2420 case ISL_AUX_USAGE_MCS
:
2421 assert(mt
->mcs_buf
);
2422 assert(start_level
== 0 && num_levels
== 1);
2423 const uint32_t level_layers
=
2424 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2425 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2426 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2427 aux_usage
, fast_clear_supported
);
2431 case ISL_AUX_USAGE_CCS_D
:
2432 case ISL_AUX_USAGE_CCS_E
:
2436 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2437 const uint32_t level
= start_level
+ l
;
2438 const uint32_t level_layers
=
2439 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2440 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2441 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2443 aux_usage
, fast_clear_supported
);
2448 case ISL_AUX_USAGE_HIZ
:
2449 assert(mt
->hiz_buf
);
2450 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2451 const uint32_t level
= start_level
+ l
;
2452 if (!intel_miptree_level_has_hiz(mt
, level
))
2455 const uint32_t level_layers
=
2456 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2457 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2458 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2459 aux_usage
, fast_clear_supported
);
2465 unreachable("Invalid aux usage");
2470 intel_miptree_finish_write(struct brw_context
*brw
,
2471 struct intel_mipmap_tree
*mt
, uint32_t level
,
2472 uint32_t start_layer
, uint32_t num_layers
,
2473 enum isl_aux_usage aux_usage
)
2475 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2477 switch (mt
->aux_usage
) {
2478 case ISL_AUX_USAGE_NONE
:
2482 case ISL_AUX_USAGE_MCS
:
2483 assert(mt
->mcs_buf
);
2484 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2485 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2490 case ISL_AUX_USAGE_CCS_D
:
2491 case ISL_AUX_USAGE_CCS_E
:
2495 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2496 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2501 case ISL_AUX_USAGE_HIZ
:
2502 if (!intel_miptree_level_has_hiz(mt
, level
))
2505 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2506 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2512 unreachable("Invavlid aux usage");
2517 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2518 uint32_t level
, uint32_t layer
)
2520 intel_miptree_check_level_layer(mt
, level
, layer
);
2522 if (_mesa_is_format_color_format(mt
->format
)) {
2523 assert(mt
->mcs_buf
!= NULL
);
2524 assert(mt
->surf
.samples
== 1 ||
2525 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2526 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2527 unreachable("Cannot get aux state for stencil");
2529 assert(intel_miptree_level_has_hiz(mt
, level
));
2532 return mt
->aux_state
[level
][layer
];
2536 intel_miptree_set_aux_state(struct brw_context
*brw
,
2537 struct intel_mipmap_tree
*mt
, uint32_t level
,
2538 uint32_t start_layer
, uint32_t num_layers
,
2539 enum isl_aux_state aux_state
)
2541 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2543 if (_mesa_is_format_color_format(mt
->format
)) {
2544 assert(mt
->mcs_buf
!= NULL
);
2545 assert(mt
->surf
.samples
== 1 ||
2546 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2547 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2548 unreachable("Cannot get aux state for stencil");
2550 assert(intel_miptree_level_has_hiz(mt
, level
));
2553 for (unsigned a
= 0; a
< num_layers
; a
++) {
2554 if (mt
->aux_state
[level
][start_layer
+ a
] != aux_state
) {
2555 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2556 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2561 /* On Gen9 color buffers may be compressed by the hardware (lossless
2562 * compression). There are, however, format restrictions and care needs to be
2563 * taken that the sampler engine is capable for re-interpreting a buffer with
2564 * format different the buffer was originally written with.
2566 * For example, SRGB formats are not compressible and the sampler engine isn't
2567 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2568 * color buffer needs to be resolved so that the sampling surface can be
2569 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2573 can_texture_with_ccs(struct brw_context
*brw
,
2574 struct intel_mipmap_tree
*mt
,
2575 enum isl_format view_format
)
2577 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2580 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2581 mt
->surf
.format
, view_format
)) {
2582 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2583 isl_format_get_layout(view_format
)->name
,
2584 _mesa_get_format_name(mt
->format
));
2592 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2593 struct intel_mipmap_tree
*mt
,
2594 enum isl_format view_format
)
2596 switch (mt
->aux_usage
) {
2597 case ISL_AUX_USAGE_HIZ
:
2598 if (intel_miptree_sample_with_hiz(brw
, mt
))
2599 return ISL_AUX_USAGE_HIZ
;
2602 case ISL_AUX_USAGE_MCS
:
2603 return ISL_AUX_USAGE_MCS
;
2605 case ISL_AUX_USAGE_CCS_D
:
2606 case ISL_AUX_USAGE_CCS_E
:
2608 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2609 return ISL_AUX_USAGE_NONE
;
2612 /* If we don't have any unresolved color, report an aux usage of
2613 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
2614 * aux surface and we can save some bandwidth.
2616 if (!intel_miptree_has_color_unresolved(mt
, 0, INTEL_REMAINING_LEVELS
,
2617 0, INTEL_REMAINING_LAYERS
))
2618 return ISL_AUX_USAGE_NONE
;
2620 if (can_texture_with_ccs(brw
, mt
, view_format
))
2621 return ISL_AUX_USAGE_CCS_E
;
2628 return ISL_AUX_USAGE_NONE
;
2632 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2634 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2635 * values so sRGB curve application was a no-op for all fast-clearable
2638 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2639 * values, the hardware interprets the floats, not as what would be
2640 * returned from the sampler (or written by the shader), but as being
2641 * between format conversion and sRGB curve application. This means that
2642 * we can switch between sRGB and UNORM without having to whack the clear
2645 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2649 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2650 struct intel_mipmap_tree
*mt
,
2651 enum isl_format view_format
,
2652 uint32_t start_level
, uint32_t num_levels
,
2653 uint32_t start_layer
, uint32_t num_layers
,
2654 bool *aux_supported_out
)
2656 enum isl_aux_usage aux_usage
=
2657 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2658 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2660 /* Clear color is specified as ints or floats and the conversion is done by
2661 * the sampler. If we have a texture view, we would have to perform the
2662 * clear color conversion manually. Just disable clear color.
2664 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2665 clear_supported
= false;
2667 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2668 start_layer
, num_layers
,
2669 aux_usage
, clear_supported
);
2670 if (aux_supported_out
)
2671 *aux_supported_out
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2675 intel_miptree_prepare_texture(struct brw_context
*brw
,
2676 struct intel_mipmap_tree
*mt
,
2677 enum isl_format view_format
,
2678 bool *aux_supported_out
)
2680 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2681 0, INTEL_REMAINING_LEVELS
,
2682 0, INTEL_REMAINING_LAYERS
,
2687 intel_miptree_prepare_image(struct brw_context
*brw
,
2688 struct intel_mipmap_tree
*mt
)
2690 /* The data port doesn't understand any compression */
2691 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2692 0, INTEL_REMAINING_LAYERS
,
2693 ISL_AUX_USAGE_NONE
, false);
2697 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2698 struct intel_mipmap_tree
*mt
, uint32_t level
,
2699 uint32_t start_layer
, uint32_t num_layers
)
2701 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->surf
.format
, level
, 1,
2702 start_layer
, num_layers
, NULL
);
2706 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2707 struct intel_mipmap_tree
*mt
,
2708 bool srgb_enabled
, bool blend_enabled
)
2710 switch (mt
->aux_usage
) {
2711 case ISL_AUX_USAGE_MCS
:
2712 assert(mt
->mcs_buf
);
2713 return ISL_AUX_USAGE_MCS
;
2715 case ISL_AUX_USAGE_CCS_D
:
2716 return mt
->mcs_buf
? ISL_AUX_USAGE_CCS_D
: ISL_AUX_USAGE_NONE
;
2718 case ISL_AUX_USAGE_CCS_E
: {
2719 mesa_format mesa_format
=
2720 srgb_enabled
? mt
->format
:_mesa_get_srgb_format_linear(mt
->format
);
2721 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
2723 /* If the format supports CCS_E, then we can just use it */
2724 if (isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
))
2725 return ISL_AUX_USAGE_CCS_E
;
2727 /* Otherwise, we have to fall back to CCS_D */
2729 /* gen9 hardware technically supports non-0/1 clear colors with sRGB
2730 * formats. However, there are issues with blending where it doesn't
2731 * properly apply the sRGB curve to the clear color when blending.
2733 if (blend_enabled
&& isl_format_is_srgb(isl_format
) &&
2734 !isl_color_value_is_zero_one(mt
->fast_clear_color
, isl_format
))
2735 return ISL_AUX_USAGE_NONE
;
2737 return ISL_AUX_USAGE_CCS_D
;
2741 return ISL_AUX_USAGE_NONE
;
2746 intel_miptree_prepare_render(struct brw_context
*brw
,
2747 struct intel_mipmap_tree
*mt
, uint32_t level
,
2748 uint32_t start_layer
, uint32_t layer_count
,
2749 bool srgb_enabled
, bool blend_enabled
)
2751 enum isl_aux_usage aux_usage
=
2752 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
, blend_enabled
);
2753 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2754 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2758 intel_miptree_finish_render(struct brw_context
*brw
,
2759 struct intel_mipmap_tree
*mt
, uint32_t level
,
2760 uint32_t start_layer
, uint32_t layer_count
,
2761 bool srgb_enabled
, bool blend_enabled
)
2763 assert(_mesa_is_format_color_format(mt
->format
));
2765 enum isl_aux_usage aux_usage
=
2766 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
, blend_enabled
);
2767 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2772 intel_miptree_prepare_depth(struct brw_context
*brw
,
2773 struct intel_mipmap_tree
*mt
, uint32_t level
,
2774 uint32_t start_layer
, uint32_t layer_count
)
2776 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2777 mt
->aux_usage
, mt
->hiz_buf
!= NULL
);
2781 intel_miptree_finish_depth(struct brw_context
*brw
,
2782 struct intel_mipmap_tree
*mt
, uint32_t level
,
2783 uint32_t start_layer
, uint32_t layer_count
,
2786 if (depth_written
) {
2787 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2788 mt
->hiz_buf
!= NULL
);
2793 intel_miptree_prepare_external(struct brw_context
*brw
,
2794 struct intel_mipmap_tree
*mt
)
2796 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
2797 bool supports_fast_clear
= false;
2799 const struct isl_drm_modifier_info
*mod_info
=
2800 isl_drm_modifier_get_info(mt
->drm_modifier
);
2802 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
2803 /* CCS_E is the only supported aux for external images and it's only
2804 * supported on very simple images.
2806 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
2807 assert(_mesa_is_format_color_format(mt
->format
));
2808 assert(mt
->first_level
== 0 && mt
->last_level
== 0);
2809 assert(mt
->surf
.logical_level0_px
.depth
== 1);
2810 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
2811 assert(mt
->surf
.samples
== 1);
2812 assert(mt
->mcs_buf
!= NULL
);
2814 aux_usage
= mod_info
->aux_usage
;
2815 supports_fast_clear
= mod_info
->supports_clear_color
;
2818 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2819 0, INTEL_REMAINING_LAYERS
,
2820 aux_usage
, supports_fast_clear
);
2824 intel_miptree_finish_external(struct brw_context
*brw
,
2825 struct intel_mipmap_tree
*mt
)
2830 /* We just got this image in from the window system via glxBindTexImageEXT
2831 * or similar and have no idea what the actual aux state is other than that
2832 * we aren't in AUX_INVALID. Reset the aux state to the default for the
2835 enum isl_aux_state default_aux_state
=
2836 isl_drm_modifier_get_default_aux_state(mt
->drm_modifier
);
2837 assert(mt
->last_level
== mt
->first_level
);
2838 intel_miptree_set_aux_state(brw
, mt
, 0, 0, INTEL_REMAINING_LAYERS
,
2843 * Make it possible to share the BO backing the given miptree with another
2844 * process or another miptree.
2846 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2847 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2848 * ensure that no MCS buffer gets allocated in the future.
2850 * HiZ is similarly unsafe with shared buffers.
2853 intel_miptree_make_shareable(struct brw_context
*brw
,
2854 struct intel_mipmap_tree
*mt
)
2856 /* MCS buffers are also used for multisample buffers, but we can't resolve
2857 * away a multisample MCS buffer because it's an integral part of how the
2858 * pixel data is stored. Fortunately this code path should never be
2859 * reached for multisample buffers.
2861 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2862 mt
->surf
.samples
== 1);
2864 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2865 0, INTEL_REMAINING_LAYERS
,
2866 ISL_AUX_USAGE_NONE
, false);
2869 brw_bo_unreference(mt
->mcs_buf
->bo
);
2873 /* Any pending MCS/CCS operations are no longer needed. Trying to
2874 * execute any will likely crash due to the missing aux buffer. So let's
2875 * delete all pending ops.
2877 free(mt
->aux_state
);
2878 mt
->aux_state
= NULL
;
2879 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2883 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2886 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2887 mt
->level
[l
].has_hiz
= false;
2890 /* Any pending HiZ operations are no longer needed. Trying to execute
2891 * any will likely crash due to the missing aux buffer. So let's delete
2894 free(mt
->aux_state
);
2895 mt
->aux_state
= NULL
;
2896 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2899 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2900 mt
->supports_fast_clear
= false;
2905 * \brief Get pointer offset into stencil buffer.
2907 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2908 * must decode the tile's layout in software.
2911 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2913 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2915 * Even though the returned offset is always positive, the return type is
2917 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2918 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2921 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2923 uint32_t tile_size
= 4096;
2924 uint32_t tile_width
= 64;
2925 uint32_t tile_height
= 64;
2926 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2928 uint32_t tile_x
= x
/ tile_width
;
2929 uint32_t tile_y
= y
/ tile_height
;
2931 /* The byte's address relative to the tile's base addres. */
2932 uint32_t byte_x
= x
% tile_width
;
2933 uint32_t byte_y
= y
% tile_height
;
2935 uintptr_t u
= tile_y
* row_size
2936 + tile_x
* tile_size
2937 + 512 * (byte_x
/ 8)
2939 + 32 * ((byte_y
/ 4) % 2)
2940 + 16 * ((byte_x
/ 4) % 2)
2941 + 8 * ((byte_y
/ 2) % 2)
2942 + 4 * ((byte_x
/ 2) % 2)
2947 /* adjust for bit6 swizzling */
2948 if (((byte_x
/ 8) % 2) == 1) {
2949 if (((byte_y
/ 8) % 2) == 0) {
2961 intel_miptree_updownsample(struct brw_context
*brw
,
2962 struct intel_mipmap_tree
*src
,
2963 struct intel_mipmap_tree
*dst
)
2965 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2966 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2967 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2968 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2970 brw_blorp_blit_miptrees(brw
,
2971 src
, 0 /* level */, 0 /* layer */,
2972 src
->format
, SWIZZLE_XYZW
,
2973 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2976 GL_NEAREST
, false, false /*mirror x, y*/,
2979 if (src
->stencil_mt
) {
2980 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2981 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2982 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2983 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2985 brw_blorp_blit_miptrees(brw
,
2986 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2987 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2988 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2989 dst
->stencil_mt
->format
,
2992 GL_NEAREST
, false, false /*mirror x, y*/,
2993 false, false /* decode/encode srgb */);
2998 intel_update_r8stencil(struct brw_context
*brw
,
2999 struct intel_mipmap_tree
*mt
)
3001 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3003 assert(devinfo
->gen
>= 7);
3004 struct intel_mipmap_tree
*src
=
3005 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
3006 if (!src
|| devinfo
->gen
>= 8 || !src
->r8stencil_needs_update
)
3009 assert(src
->surf
.size
> 0);
3011 if (!mt
->r8stencil_mt
) {
3012 assert(devinfo
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
3013 mt
->r8stencil_mt
= make_surface(
3016 MESA_FORMAT_R_UINT8
,
3017 src
->first_level
, src
->last_level
,
3018 src
->surf
.logical_level0_px
.width
,
3019 src
->surf
.logical_level0_px
.height
,
3020 src
->surf
.dim
== ISL_SURF_DIM_3D
?
3021 src
->surf
.logical_level0_px
.depth
:
3022 src
->surf
.logical_level0_px
.array_len
,
3025 ISL_SURF_USAGE_TEXTURE_BIT
,
3026 BO_ALLOC_BUSY
, 0, NULL
);
3027 assert(mt
->r8stencil_mt
);
3030 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
3032 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
3033 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
3034 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
3035 src
->surf
.phys_level0_sa
.array_len
;
3037 for (unsigned layer
= 0; layer
< depth
; layer
++) {
3038 brw_blorp_copy_miptrees(brw
,
3042 minify(src
->surf
.logical_level0_px
.width
,
3044 minify(src
->surf
.logical_level0_px
.height
,
3049 brw_render_cache_set_check_flush(brw
, dst
->bo
);
3050 src
->r8stencil_needs_update
= false;
3054 intel_miptree_map_raw(struct brw_context
*brw
,
3055 struct intel_mipmap_tree
*mt
,
3058 struct brw_bo
*bo
= mt
->bo
;
3060 if (brw_batch_references(&brw
->batch
, bo
))
3061 intel_batchbuffer_flush(brw
);
3063 return brw_bo_map(brw
, bo
, mode
);
3067 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3069 brw_bo_unmap(mt
->bo
);
3073 intel_miptree_map_gtt(struct brw_context
*brw
,
3074 struct intel_mipmap_tree
*mt
,
3075 struct intel_miptree_map
*map
,
3076 unsigned int level
, unsigned int slice
)
3078 unsigned int bw
, bh
;
3080 unsigned int image_x
, image_y
;
3081 intptr_t x
= map
->x
;
3082 intptr_t y
= map
->y
;
3084 /* For compressed formats, the stride is the number of bytes per
3085 * row of blocks. intel_miptree_get_image_offset() already does
3088 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3089 assert(y
% bh
== 0);
3090 assert(x
% bw
== 0);
3094 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3101 /* Note that in the case of cube maps, the caller must have passed the
3102 * slice number referencing the face.
3104 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3108 map
->stride
= mt
->surf
.row_pitch
;
3109 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3112 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3113 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3114 map
->x
, map
->y
, map
->w
, map
->h
,
3115 mt
, _mesa_get_format_name(mt
->format
),
3116 x
, y
, map
->ptr
, map
->stride
);
3120 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3122 intel_miptree_unmap_raw(mt
);
3126 intel_miptree_map_blit(struct brw_context
*brw
,
3127 struct intel_mipmap_tree
*mt
,
3128 struct intel_miptree_map
*map
,
3129 unsigned int level
, unsigned int slice
)
3131 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3132 /* first_level */ 0,
3136 MIPTREE_CREATE_LINEAR
);
3138 if (!map
->linear_mt
) {
3139 fprintf(stderr
, "Failed to allocate blit temporary\n");
3142 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3144 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3145 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3146 * invalidate is set, since we'll be writing the whole rectangle from our
3147 * temporary buffer back out.
3149 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3150 if (!intel_miptree_copy(brw
,
3151 mt
, level
, slice
, map
->x
, map
->y
,
3152 map
->linear_mt
, 0, 0, 0, 0,
3154 fprintf(stderr
, "Failed to blit\n");
3159 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3161 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3162 map
->x
, map
->y
, map
->w
, map
->h
,
3163 mt
, _mesa_get_format_name(mt
->format
),
3164 level
, slice
, map
->ptr
, map
->stride
);
3169 intel_miptree_release(&map
->linear_mt
);
3175 intel_miptree_unmap_blit(struct brw_context
*brw
,
3176 struct intel_mipmap_tree
*mt
,
3177 struct intel_miptree_map
*map
,
3181 struct gl_context
*ctx
= &brw
->ctx
;
3183 intel_miptree_unmap_raw(map
->linear_mt
);
3185 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3186 bool ok
= intel_miptree_copy(brw
,
3187 map
->linear_mt
, 0, 0, 0, 0,
3188 mt
, level
, slice
, map
->x
, map
->y
,
3190 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3193 intel_miptree_release(&map
->linear_mt
);
3197 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3199 #if defined(USE_SSE41)
3201 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3202 struct intel_mipmap_tree
*mt
,
3203 struct intel_miptree_map
*map
,
3204 unsigned int level
, unsigned int slice
)
3206 assert(map
->mode
& GL_MAP_READ_BIT
);
3207 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3209 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3210 map
->x
, map
->y
, map
->w
, map
->h
,
3211 mt
, _mesa_get_format_name(mt
->format
),
3212 level
, slice
, map
->ptr
, map
->stride
);
3214 /* Map the original image */
3217 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3221 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3227 src
+= image_y
* mt
->surf
.row_pitch
;
3228 src
+= image_x
* mt
->cpp
;
3230 /* Due to the pixel offsets for the particular image being mapped, our
3231 * src pointer may not be 16-byte aligned. However, if the pitch is
3232 * divisible by 16, then the amount by which it's misaligned will remain
3233 * consistent from row to row.
3235 assert((mt
->surf
.row_pitch
% 16) == 0);
3236 const int misalignment
= ((uintptr_t) src
) & 15;
3238 /* Create an untiled temporary buffer for the mapping. */
3239 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3241 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3243 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3244 /* Offset the destination so it has the same misalignment as src. */
3245 map
->ptr
= map
->buffer
+ misalignment
;
3247 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3249 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3250 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3251 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3253 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3256 intel_miptree_unmap_raw(mt
);
3260 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3261 struct intel_mipmap_tree
*mt
,
3262 struct intel_miptree_map
*map
,
3266 _mesa_align_free(map
->buffer
);
3273 intel_miptree_map_s8(struct brw_context
*brw
,
3274 struct intel_mipmap_tree
*mt
,
3275 struct intel_miptree_map
*map
,
3276 unsigned int level
, unsigned int slice
)
3278 map
->stride
= map
->w
;
3279 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3283 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3284 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3285 * invalidate is set, since we'll be writing the whole rectangle from our
3286 * temporary buffer back out.
3288 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3289 uint8_t *untiled_s8_map
= map
->ptr
;
3290 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3291 unsigned int image_x
, image_y
;
3293 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3295 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3296 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3297 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3298 x
+ image_x
+ map
->x
,
3299 y
+ image_y
+ map
->y
,
3300 brw
->has_swizzling
);
3301 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3305 intel_miptree_unmap_raw(mt
);
3307 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3308 map
->x
, map
->y
, map
->w
, map
->h
,
3309 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3311 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3312 map
->x
, map
->y
, map
->w
, map
->h
,
3313 mt
, map
->ptr
, map
->stride
);
3318 intel_miptree_unmap_s8(struct brw_context
*brw
,
3319 struct intel_mipmap_tree
*mt
,
3320 struct intel_miptree_map
*map
,
3324 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3325 unsigned int image_x
, image_y
;
3326 uint8_t *untiled_s8_map
= map
->ptr
;
3327 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3329 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3331 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3332 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3333 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3334 image_x
+ x
+ map
->x
,
3335 image_y
+ y
+ map
->y
,
3336 brw
->has_swizzling
);
3337 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3341 intel_miptree_unmap_raw(mt
);
3348 intel_miptree_map_etc(struct brw_context
*brw
,
3349 struct intel_mipmap_tree
*mt
,
3350 struct intel_miptree_map
*map
,
3354 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3355 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3356 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3359 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3360 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3362 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3363 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3364 map
->w
, map
->h
, 1));
3365 map
->ptr
= map
->buffer
;
3369 intel_miptree_unmap_etc(struct brw_context
*brw
,
3370 struct intel_mipmap_tree
*mt
,
3371 struct intel_miptree_map
*map
,
3377 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3382 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3383 + image_y
* mt
->surf
.row_pitch
3384 + image_x
* mt
->cpp
;
3386 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3387 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3388 map
->ptr
, map
->stride
,
3391 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3392 map
->ptr
, map
->stride
,
3393 map
->w
, map
->h
, mt
->etc_format
);
3395 intel_miptree_unmap_raw(mt
);
3400 * Mapping function for packed depth/stencil miptrees backed by real separate
3401 * miptrees for depth and stencil.
3403 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3404 * separate from the depth buffer. Yet at the GL API level, we have to expose
3405 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3406 * be able to map that memory for texture storage and glReadPixels-type
3407 * operations. We give Mesa core that access by mallocing a temporary and
3408 * copying the data between the actual backing store and the temporary.
3411 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3412 struct intel_mipmap_tree
*mt
,
3413 struct intel_miptree_map
*map
,
3414 unsigned int level
, unsigned int slice
)
3416 struct intel_mipmap_tree
*z_mt
= mt
;
3417 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3418 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3419 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3421 map
->stride
= map
->w
* packed_bpp
;
3422 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3426 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3427 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3428 * invalidate is set, since we'll be writing the whole rectangle from our
3429 * temporary buffer back out.
3431 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3432 uint32_t *packed_map
= map
->ptr
;
3433 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3434 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3435 unsigned int s_image_x
, s_image_y
;
3436 unsigned int z_image_x
, z_image_y
;
3438 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3439 &s_image_x
, &s_image_y
);
3440 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3441 &z_image_x
, &z_image_y
);
3443 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3444 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3445 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3446 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3449 brw
->has_swizzling
);
3450 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3451 (z_mt
->surf
.row_pitch
/ 4) +
3452 (map_x
+ z_image_x
));
3453 uint8_t s
= s_map
[s_offset
];
3454 uint32_t z
= z_map
[z_offset
];
3456 if (map_z32f_x24s8
) {
3457 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3458 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3460 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3465 intel_miptree_unmap_raw(s_mt
);
3466 intel_miptree_unmap_raw(z_mt
);
3468 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3470 map
->x
, map
->y
, map
->w
, map
->h
,
3471 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3472 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3473 map
->ptr
, map
->stride
);
3475 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3476 map
->x
, map
->y
, map
->w
, map
->h
,
3477 mt
, map
->ptr
, map
->stride
);
3482 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3483 struct intel_mipmap_tree
*mt
,
3484 struct intel_miptree_map
*map
,
3488 struct intel_mipmap_tree
*z_mt
= mt
;
3489 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3490 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3492 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3493 uint32_t *packed_map
= map
->ptr
;
3494 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3495 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3496 unsigned int s_image_x
, s_image_y
;
3497 unsigned int z_image_x
, z_image_y
;
3499 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3500 &s_image_x
, &s_image_y
);
3501 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3502 &z_image_x
, &z_image_y
);
3504 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3505 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3506 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3507 x
+ s_image_x
+ map
->x
,
3508 y
+ s_image_y
+ map
->y
,
3509 brw
->has_swizzling
);
3510 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3511 (z_mt
->surf
.row_pitch
/ 4) +
3512 (x
+ z_image_x
+ map
->x
));
3514 if (map_z32f_x24s8
) {
3515 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3516 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3518 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3519 s_map
[s_offset
] = packed
>> 24;
3520 z_map
[z_offset
] = packed
;
3525 intel_miptree_unmap_raw(s_mt
);
3526 intel_miptree_unmap_raw(z_mt
);
3528 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3530 map
->x
, map
->y
, map
->w
, map
->h
,
3531 z_mt
, _mesa_get_format_name(z_mt
->format
),
3532 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3533 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3534 map
->ptr
, map
->stride
);
3541 * Create and attach a map to the miptree at (level, slice). Return the
3544 static struct intel_miptree_map
*
3545 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3554 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3559 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3560 mt
->level
[level
].slice
[slice
].map
= map
;
3572 * Release the map at (level, slice).
3575 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3579 struct intel_miptree_map
**map
;
3581 map
= &mt
->level
[level
].slice
[slice
].map
;
3587 can_blit_slice(struct intel_mipmap_tree
*mt
,
3588 unsigned int level
, unsigned int slice
)
3590 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3591 if (mt
->surf
.row_pitch
>= 32768)
3598 use_intel_mipree_map_blit(struct brw_context
*brw
,
3599 struct intel_mipmap_tree
*mt
,
3604 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3606 if (devinfo
->has_llc
&&
3607 /* It's probably not worth swapping to the blit ring because of
3608 * all the overhead involved.
3610 !(mode
& GL_MAP_WRITE_BIT
) &&
3612 (mt
->surf
.tiling
== ISL_TILING_X
||
3613 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3614 (devinfo
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3615 /* Fast copy blit on skl+ supports all tiling formats. */
3616 devinfo
->gen
>= 9) &&
3617 can_blit_slice(mt
, level
, slice
))
3620 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3621 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3622 assert(can_blit_slice(mt
, level
, slice
));
3630 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3631 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3632 * arithmetic overflow.
3634 * If you call this function and use \a out_stride, then you're doing pointer
3635 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3636 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3637 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3638 * which usually have type uint32_t or GLuint.
3641 intel_miptree_map(struct brw_context
*brw
,
3642 struct intel_mipmap_tree
*mt
,
3651 ptrdiff_t *out_stride
)
3653 struct intel_miptree_map
*map
;
3655 assert(mt
->surf
.samples
== 1);
3657 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3664 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3665 map
->mode
& GL_MAP_WRITE_BIT
);
3667 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3668 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3669 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3670 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3671 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3672 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3673 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3674 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3675 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3676 #if defined(USE_SSE41)
3677 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3678 !mt
->compressed
&& cpu_has_sse4_1
&&
3679 (mt
->surf
.row_pitch
% 16 == 0)) {
3680 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3683 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3686 *out_ptr
= map
->ptr
;
3687 *out_stride
= map
->stride
;
3689 if (map
->ptr
== NULL
)
3690 intel_miptree_release_map(mt
, level
, slice
);
3694 intel_miptree_unmap(struct brw_context
*brw
,
3695 struct intel_mipmap_tree
*mt
,
3699 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3701 assert(mt
->surf
.samples
== 1);
3706 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3707 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3709 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3710 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3711 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3712 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3713 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3714 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3715 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3716 } else if (map
->linear_mt
) {
3717 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3718 #if defined(USE_SSE41)
3719 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3720 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3723 intel_miptree_unmap_gtt(mt
);
3726 intel_miptree_release_map(mt
, level
, slice
);
3730 get_isl_surf_dim(GLenum target
)
3734 case GL_TEXTURE_1D_ARRAY
:
3735 return ISL_SURF_DIM_1D
;
3738 case GL_TEXTURE_2D_ARRAY
:
3739 case GL_TEXTURE_RECTANGLE
:
3740 case GL_TEXTURE_CUBE_MAP
:
3741 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3742 case GL_TEXTURE_2D_MULTISAMPLE
:
3743 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3744 case GL_TEXTURE_EXTERNAL_OES
:
3745 return ISL_SURF_DIM_2D
;
3748 return ISL_SURF_DIM_3D
;
3751 unreachable("Invalid texture target");
3755 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3756 enum isl_tiling tiling
, GLenum target
)
3760 case GL_TEXTURE_1D_ARRAY
:
3761 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3762 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3765 case GL_TEXTURE_2D_ARRAY
:
3766 case GL_TEXTURE_RECTANGLE
:
3767 case GL_TEXTURE_2D_MULTISAMPLE
:
3768 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3769 case GL_TEXTURE_EXTERNAL_OES
:
3770 return ISL_DIM_LAYOUT_GEN4_2D
;
3772 case GL_TEXTURE_CUBE_MAP
:
3773 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3774 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3775 ISL_DIM_LAYOUT_GEN4_2D
);
3778 return (devinfo
->gen
>= 9 ?
3779 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3782 unreachable("Invalid texture target");
3786 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3787 const struct intel_mipmap_tree
*mt
)
3790 return ISL_AUX_USAGE_HIZ
;
3793 return ISL_AUX_USAGE_NONE
;
3795 return mt
->aux_usage
;