2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_image.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
,
55 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
58 intel_miptree_alloc_aux(struct brw_context
*brw
,
59 struct intel_mipmap_tree
*mt
);
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 uint32_t layout_flags
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
105 intel_tiling_supports_ccs(const struct brw_context
*brw
, unsigned tiling
)
107 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
108 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
110 * - Support is limited to tiled render targets.
112 * Gen9 changes the restriction to Y-tile only.
115 return tiling
== I915_TILING_Y
;
116 else if (brw
->gen
>= 7)
117 return tiling
!= I915_TILING_NONE
;
123 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
124 * can be used. This doesn't (and should not) inspect any of the properties of
127 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
128 * beneath the "Fast Color Clear" bullet (p326):
130 * - Support is for non-mip-mapped and non-array surface types only.
132 * And then later, on p327:
134 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
137 * From the Skylake documentation, it is made clear that X-tiling is no longer
140 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
144 intel_miptree_supports_ccs(struct brw_context
*brw
,
145 const struct intel_mipmap_tree
*mt
)
147 /* MCS support does not exist prior to Gen7 */
151 /* This function applies only to non-multisampled render targets. */
152 if (mt
->num_samples
> 1)
155 /* MCS is only supported for color buffers */
156 switch (_mesa_get_format_base_format(mt
->format
)) {
157 case GL_DEPTH_COMPONENT
:
158 case GL_DEPTH_STENCIL
:
159 case GL_STENCIL_INDEX
:
163 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
166 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
167 const bool arrayed
= mt
->physical_depth0
!= 1;
170 /* Multisample surfaces with the CMS layout are not layered surfaces,
171 * yet still have physical_depth0 > 1. Assert that we don't
172 * accidentally reject a multisampled surface here. We should have
173 * rejected it earlier by explicitly checking the sample count.
175 assert(mt
->num_samples
<= 1);
178 /* Handle the hardware restrictions...
180 * All GENs have the following restriction: "MCS buffer for non-MSRT is
181 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
183 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
184 * Non-MultiSampler Render Target Restrictions) Support is for
185 * non-mip-mapped and non-array surface types only.
187 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
188 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
189 * surfaces are supported with MCS buffer layout with these alignments in
190 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
192 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
193 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
194 * surfaces are supported with MCS buffer layout with these alignments in
195 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
197 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
200 /* There's no point in using an MCS buffer if the surface isn't in a
203 if (!brw
->mesa_format_supports_render
[mt
->format
])
207 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
208 const enum isl_format isl_format
=
209 brw_isl_format_for_mesa_format(linear_format
);
210 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
216 intel_tiling_supports_hiz(const struct brw_context
*brw
, unsigned tiling
)
221 return tiling
== I915_TILING_Y
;
225 intel_miptree_supports_hiz(const struct brw_context
*brw
,
226 const struct intel_mipmap_tree
*mt
)
231 switch (mt
->format
) {
232 case MESA_FORMAT_Z_FLOAT32
:
233 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
234 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
235 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
236 case MESA_FORMAT_Z_UNORM16
:
244 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
245 const struct intel_mipmap_tree
*mt
)
247 /* For now compression is only enabled for integer formats even though
248 * there exist supported floating point formats also. This is a heuristic
249 * decision based on current public benchmarks. In none of the cases these
250 * formats provided any improvement but a few cases were seen to regress.
251 * Hence these are left to to be enabled in the future when they are known
254 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
257 if (!intel_miptree_supports_ccs(brw
, mt
))
260 /* Fast clear can be also used to clear srgb surfaces by using equivalent
261 * linear format. This trick, however, can't be extended to be used with
262 * lossless compression and therefore a check is needed to see if the format
265 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
269 * Determine depth format corresponding to a depth+stencil format,
270 * for separate stencil.
273 intel_depth_format_for_depthstencil_format(mesa_format format
) {
275 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
276 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
277 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
278 return MESA_FORMAT_Z_FLOAT32
;
285 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
286 unsigned depth0
, struct intel_mipmap_level
*table
)
288 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
290 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
292 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
293 if (!table
[level
].slice
)
300 for (unsigned level
= first_level
; level
<= last_level
; level
++)
301 free(table
[level
].slice
);
307 * @param for_bo Indicates that the caller is
308 * intel_miptree_create_for_bo(). If true, then do not create
311 static struct intel_mipmap_tree
*
312 intel_miptree_create_layout(struct brw_context
*brw
,
321 uint32_t layout_flags
)
323 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
327 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
328 _mesa_enum_to_string(target
),
329 _mesa_get_format_name(format
),
330 first_level
, last_level
, depth0
, mt
);
332 if (target
== GL_TEXTURE_1D_ARRAY
)
333 assert(height0
== 1);
337 mt
->first_level
= first_level
;
338 mt
->last_level
= last_level
;
339 mt
->logical_width0
= width0
;
340 mt
->logical_height0
= height0
;
341 mt
->logical_depth0
= depth0
;
342 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
343 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
344 mt
->supports_fast_clear
= false;
345 mt
->aux_state
= NULL
;
346 mt
->cpp
= _mesa_get_format_bytes(format
);
347 mt
->num_samples
= num_samples
;
348 mt
->compressed
= _mesa_is_format_compressed(format
);
349 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
352 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
353 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
355 int depth_multiply
= 1;
356 if (num_samples
> 1) {
357 /* Adjust width/height/depth for MSAA */
358 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, layout_flags
);
359 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
360 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
361 * "If the surface is multisampled and it is a depth or stencil
362 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
363 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
366 * +----------------------------------------------------------------+
367 * | Num Multisamples | W_l = | H_l = |
368 * +----------------------------------------------------------------+
369 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
370 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
371 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
372 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
373 * +----------------------------------------------------------------+
376 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
377 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
378 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
380 * Another more complicated explanation for these adjustments comes
381 * from the Sandybridge PRM, volume 4, part 1, page 31:
383 * "Any of the other messages (sample*, LOD, load4) used with a
384 * (4x) multisampled surface will in-effect sample a surface with
385 * double the height and width as that indicated in the surface
386 * state. Each pixel position on the original-sized surface is
387 * replaced with a 2x2 of samples with the following arrangement:
392 * Thus, when sampling from a multisampled texture, it behaves as
393 * though the layout in memory for (x,y,sample) is:
395 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
396 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
398 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
399 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
401 * However, the actual layout of multisampled data in memory is:
403 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
404 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
406 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
407 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
409 * This pattern repeats for each 2x2 pixel block.
411 * As a result, when calculating the size of our 4-sample buffer for
412 * an odd width or height, we have to align before scaling up because
413 * sample 3 is in that bottom right 2x2 block.
415 switch (num_samples
) {
417 assert(brw
->gen
>= 8);
418 width0
= ALIGN(width0
, 2) * 2;
419 height0
= ALIGN(height0
, 2);
422 width0
= ALIGN(width0
, 2) * 2;
423 height0
= ALIGN(height0
, 2) * 2;
426 width0
= ALIGN(width0
, 2) * 4;
427 height0
= ALIGN(height0
, 2) * 2;
430 width0
= ALIGN(width0
, 2) * 4;
431 height0
= ALIGN(height0
, 2) * 4;
434 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
437 unreachable("not reached");
440 /* Non-interleaved */
441 depth_multiply
= num_samples
;
442 depth0
*= depth_multiply
;
446 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
452 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
453 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
454 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
455 * used on Gen8 to make it pick a qpitch value which doesn't include space
456 * for the mipmaps. On Gen9 this is not necessary because it will
457 * automatically pick a packed qpitch value whenever mt->first_level ==
459 * TODO: can we use it elsewhere?
460 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
463 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
465 switch (mt
->msaa_layout
) {
466 case INTEL_MSAA_LAYOUT_NONE
:
467 case INTEL_MSAA_LAYOUT_IMS
:
468 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
470 case INTEL_MSAA_LAYOUT_UMS
:
471 case INTEL_MSAA_LAYOUT_CMS
:
472 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
477 if (target
== GL_TEXTURE_CUBE_MAP
)
478 assert(depth0
== 6 * depth_multiply
);
480 mt
->physical_width0
= width0
;
481 mt
->physical_height0
= height0
;
482 mt
->physical_depth0
= depth0
;
484 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
485 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
486 (brw
->must_use_separate_stencil
||
487 (brw
->has_separate_stencil
&& intel_miptree_supports_hiz(brw
, mt
)))) {
488 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
490 stencil_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
493 mt
->stencil_mt
= intel_miptree_create(brw
,
504 if (!mt
->stencil_mt
) {
505 intel_miptree_release(&mt
);
508 mt
->stencil_mt
->r8stencil_needs_update
= true;
510 /* Fix up the Z miptree format for how we're splitting out separate
511 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
513 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
516 if (format
== mt
->format
) {
517 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
518 _mesa_get_format_name(mt
->format
));
522 if (layout_flags
& MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
)
523 mt
->array_layout
= GEN6_HIZ_STENCIL
;
526 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
527 * multisampled or have an AUX buffer attached to it.
529 * GEN | MSRT | AUX_CCS_* or AUX_MCS
530 * -------------------------------------------
531 * 9 | HALIGN_16 | HALIGN_16
532 * 8 | HALIGN_ANY | HALIGN_16
536 if (intel_miptree_supports_ccs(brw
, mt
)) {
537 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
538 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
539 } else if (brw
->gen
>= 9 && num_samples
> 1) {
540 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
542 const UNUSED
bool is_lossless_compressed_aux
=
543 brw
->gen
>= 9 && num_samples
== 1 &&
544 mt
->format
== MESA_FORMAT_R_UINT32
;
546 /* For now, nothing else has this requirement */
547 assert(is_lossless_compressed_aux
||
548 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
551 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
552 intel_miptree_release(&mt
);
561 * Choose the aux usage for this miptree. This function must be called fairly
562 * late in the miptree create process after we have a tiling.
565 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
566 struct intel_mipmap_tree
*mt
)
568 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
570 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
571 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
572 } else if (intel_tiling_supports_ccs(brw
, mt
->tiling
) &&
573 intel_miptree_supports_ccs(brw
, mt
)) {
574 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
575 brw
->gen
>= 9 && !mt
->is_scanout
&&
576 intel_miptree_supports_ccs_e(brw
, mt
)) {
577 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
579 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
581 } else if (intel_tiling_supports_hiz(brw
, mt
->tiling
) &&
582 intel_miptree_supports_hiz(brw
, mt
)) {
583 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
586 /* We can do fast-clear on all auxiliary surface types that are
587 * allocated through the normal texture creation paths.
589 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
590 mt
->supports_fast_clear
= true;
595 * Choose an appropriate uncompressed format for a requested
596 * compressed format, if unsupported.
599 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
601 /* No need to lower ETC formats on these platforms,
602 * they are supported natively.
604 if (brw
->gen
>= 8 || brw
->is_baytrail
)
608 case MESA_FORMAT_ETC1_RGB8
:
609 return MESA_FORMAT_R8G8B8X8_UNORM
;
610 case MESA_FORMAT_ETC2_RGB8
:
611 return MESA_FORMAT_R8G8B8X8_UNORM
;
612 case MESA_FORMAT_ETC2_SRGB8
:
613 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
614 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
615 return MESA_FORMAT_B8G8R8A8_SRGB
;
616 case MESA_FORMAT_ETC2_RGBA8_EAC
:
617 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
618 return MESA_FORMAT_R8G8B8A8_UNORM
;
619 case MESA_FORMAT_ETC2_R11_EAC
:
620 return MESA_FORMAT_R_UNORM16
;
621 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
622 return MESA_FORMAT_R_SNORM16
;
623 case MESA_FORMAT_ETC2_RG11_EAC
:
624 return MESA_FORMAT_R16G16_UNORM
;
625 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
626 return MESA_FORMAT_R16G16_SNORM
;
628 /* Non ETC1 / ETC2 format */
633 /** \brief Assert that the level and layer are valid for the miptree. */
635 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
643 assert(level
>= mt
->first_level
);
644 assert(level
<= mt
->last_level
);
646 if (mt
->surf
.size
> 0)
647 assert(layer
< (mt
->surf
.dim
== ISL_SURF_DIM_3D
?
648 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
649 mt
->surf
.phys_level0_sa
.array_len
));
651 assert(layer
< mt
->level
[level
].depth
);
654 static enum isl_aux_state
**
655 create_aux_state_map(struct intel_mipmap_tree
*mt
,
656 enum isl_aux_state initial
)
658 const uint32_t levels
= mt
->last_level
+ 1;
660 uint32_t total_slices
= 0;
661 for (uint32_t level
= 0; level
< levels
; level
++)
662 total_slices
+= mt
->level
[level
].depth
;
664 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
666 /* We're going to allocate a single chunk of data for both the per-level
667 * reference array and the arrays of aux_state. This makes cleanup
668 * significantly easier.
670 const size_t total_size
= per_level_array_size
+
671 total_slices
* sizeof(enum isl_aux_state
);
672 void *data
= malloc(total_size
);
676 enum isl_aux_state
**per_level_arr
= data
;
677 enum isl_aux_state
*s
= data
+ per_level_array_size
;
678 for (uint32_t level
= 0; level
< levels
; level
++) {
679 per_level_arr
[level
] = s
;
680 for (uint32_t a
= 0; a
< mt
->level
[level
].depth
; a
++)
683 assert((void *)s
== data
+ total_size
);
685 return per_level_arr
;
689 free_aux_state_map(enum isl_aux_state
**state
)
694 static struct intel_mipmap_tree
*
695 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
696 unsigned first_level
, unsigned last_level
,
697 unsigned width0
, unsigned height0
, unsigned depth0
,
698 unsigned num_samples
, enum isl_tiling isl_tiling
,
699 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
702 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
706 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
714 if (target
== GL_TEXTURE_CUBE_MAP
||
715 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
716 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
718 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
720 _mesa_enum_to_string(target
),
721 _mesa_get_format_name(format
),
722 num_samples
, width0
, height0
, depth0
,
723 first_level
, last_level
, mt
);
725 struct isl_surf_init_info init_info
= {
726 .dim
= get_isl_surf_dim(target
),
727 .format
= translate_tex_format(brw
, format
, false),
730 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
731 .levels
= last_level
- first_level
+ 1,
732 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
733 .samples
= MAX2(num_samples
, 1),
734 .usage
= isl_usage_flags
,
735 .tiling_flags
= 1u << isl_tiling
738 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
741 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
744 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
746 isl_tiling_to_bufmgr_tiling(isl_tiling
),
747 mt
->surf
.row_pitch
, alloc_flags
);
754 mt
->first_level
= first_level
;
755 mt
->last_level
= last_level
;
758 mt
->aux_state
= NULL
;
763 intel_miptree_release(&mt
);
767 static struct intel_mipmap_tree
*
768 miptree_create(struct brw_context
*brw
,
777 uint32_t layout_flags
)
779 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
780 return make_surface(brw
, target
, format
, first_level
, last_level
,
781 width0
, height0
, depth0
, num_samples
, ISL_TILING_W
,
782 ISL_SURF_USAGE_STENCIL_BIT
|
783 ISL_SURF_USAGE_TEXTURE_BIT
,
784 BO_ALLOC_FOR_RENDER
, NULL
);
786 struct intel_mipmap_tree
*mt
;
787 mesa_format tex_format
= format
;
788 mesa_format etc_format
= MESA_FORMAT_NONE
;
789 uint32_t alloc_flags
= 0;
791 format
= intel_lower_compressed_format(brw
, format
);
793 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
795 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
796 mt
= intel_miptree_create_layout(brw
, target
, format
,
797 first_level
, last_level
, width0
,
798 height0
, depth0
, num_samples
,
803 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
804 mt
->tiling
= I915_TILING_Y
;
806 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
807 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
809 mt
->etc_format
= etc_format
;
811 if (format
== MESA_FORMAT_S_UINT8
) {
812 /* Align to size of W tile, 64x64. */
813 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
814 ALIGN(mt
->total_width
, 64),
815 ALIGN(mt
->total_height
, 64),
816 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
819 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
820 mt
->total_width
, mt
->total_height
,
821 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
825 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
826 mt
->bo
->cache_coherent
= false;
828 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
829 intel_miptree_choose_aux_usage(brw
, mt
);
834 struct intel_mipmap_tree
*
835 intel_miptree_create(struct brw_context
*brw
,
844 uint32_t layout_flags
)
846 struct intel_mipmap_tree
*mt
= miptree_create(
848 first_level
, last_level
,
849 width0
, height0
, depth0
, num_samples
,
852 /* If the BO is too large to fit in the aperture, we need to use the
853 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
854 * handle Y-tiling, so we need to fall back to X.
856 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
857 mt
->tiling
== I915_TILING_Y
) {
858 const uint32_t alloc_flags
=
859 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
860 BO_ALLOC_FOR_RENDER
: 0;
861 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
862 mt
->total_width
, mt
->total_height
);
864 mt
->tiling
= I915_TILING_X
;
865 brw_bo_unreference(mt
->bo
);
866 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
867 mt
->total_width
, mt
->total_height
, mt
->cpp
,
868 mt
->tiling
, &mt
->pitch
, alloc_flags
);
874 intel_miptree_release(&mt
);
878 if (!intel_miptree_alloc_aux(brw
, mt
)) {
879 intel_miptree_release(&mt
);
886 struct intel_mipmap_tree
*
887 intel_miptree_create_for_bo(struct brw_context
*brw
,
895 uint32_t layout_flags
)
897 struct intel_mipmap_tree
*mt
;
898 uint32_t tiling
, swizzle
;
899 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
901 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
) {
902 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
903 0, 0, width
, height
, depth
, 1, ISL_TILING_W
,
904 ISL_SURF_USAGE_STENCIL_BIT
|
905 ISL_SURF_USAGE_TEXTURE_BIT
,
906 BO_ALLOC_FOR_RENDER
, bo
);
910 assert(bo
->size
>= mt
->surf
.size
);
912 brw_bo_reference(bo
);
916 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
918 /* Nothing will be able to use this miptree with the BO if the offset isn't
921 if (tiling
!= I915_TILING_NONE
)
922 assert(offset
% 4096 == 0);
924 /* miptrees can't handle negative pitch. If you need flipping of images,
925 * that's outside of the scope of the mt.
929 /* The BO already has a tiling format and we shouldn't confuse the lower
930 * layers by making it try to find a tiling format again.
932 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
933 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
935 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
936 mt
= intel_miptree_create_layout(brw
, target
, format
,
938 width
, height
, depth
, 0,
943 brw_bo_reference(bo
);
949 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
950 intel_miptree_choose_aux_usage(brw
, mt
);
955 static struct intel_mipmap_tree
*
956 miptree_create_for_planar_image(struct brw_context
*brw
,
957 __DRIimage
*image
, GLenum target
)
959 struct intel_image_format
*f
= image
->planar_format
;
960 struct intel_mipmap_tree
*planar_mt
= NULL
;
962 for (int i
= 0; i
< f
->nplanes
; i
++) {
963 const int index
= f
->planes
[i
].buffer_index
;
964 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
965 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
966 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
967 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
969 /* Disable creation of the texture's aux buffers because the driver
970 * exposes no EGL API to manage them. That is, there is no API for
971 * resolving the aux buffer's content to the main buffer nor for
972 * invalidating the aux buffer's content.
974 struct intel_mipmap_tree
*mt
=
975 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
976 image
->offsets
[index
],
978 image
->strides
[index
],
979 MIPTREE_LAYOUT_DISABLE_AUX
);
984 mt
->total_width
= width
;
985 mt
->total_height
= height
;
990 planar_mt
->plane
[i
- 1] = mt
;
996 struct intel_mipmap_tree
*
997 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
998 __DRIimage
*image
, GLenum target
,
999 enum isl_colorspace colorspace
,
1000 bool is_winsys_image
)
1002 if (image
->planar_format
&& image
->planar_format
->nplanes
> 0) {
1003 assert(colorspace
== ISL_COLORSPACE_NONE
||
1004 colorspace
== ISL_COLORSPACE_YUV
);
1005 return miptree_create_for_planar_image(brw
, image
, target
);
1008 mesa_format format
= image
->format
;
1009 switch (colorspace
) {
1010 case ISL_COLORSPACE_NONE
:
1011 /* Keep the image format unmodified */
1014 case ISL_COLORSPACE_LINEAR
:
1015 format
=_mesa_get_srgb_format_linear(format
);
1018 case ISL_COLORSPACE_SRGB
:
1019 format
=_mesa_get_linear_format_srgb(format
);
1023 unreachable("Inalid colorspace for non-planar image");
1026 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1027 /* The texture storage paths in core Mesa detect if the driver does not
1028 * support the user-requested format, and then searches for a
1029 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1030 * do the fallbacks here for important formats.
1032 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1033 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1034 * the Chrome OS compositor consumes as dma_buf EGLImages.
1036 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1039 if (!brw
->ctx
.TextureFormatSupported
[format
])
1042 /* If this image comes in from a window system, we have different
1043 * requirements than if it comes in via an EGL import operation. Window
1044 * system images can use any form of auxiliary compression we wish because
1045 * they get "flushed" before being handed off to the window system and we
1046 * have the opportunity to do resolves. Window system buffers also may be
1047 * used for scanout so we need to flag that appropriately.
1049 const uint32_t mt_layout_flags
=
1050 is_winsys_image
? MIPTREE_LAYOUT_FOR_SCANOUT
: MIPTREE_LAYOUT_DISABLE_AUX
;
1052 /* Disable creation of the texture's aux buffers because the driver exposes
1053 * no EGL API to manage them. That is, there is no API for resolving the aux
1054 * buffer's content to the main buffer nor for invalidating the aux buffer's
1057 struct intel_mipmap_tree
*mt
=
1058 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1059 image
->offset
, image
->width
, image
->height
, 1,
1060 image
->pitch
, mt_layout_flags
);
1064 mt
->target
= target
;
1065 mt
->level
[0].level_x
= image
->tile_x
;
1066 mt
->level
[0].level_y
= image
->tile_y
;
1067 mt
->level
[0].slice
[0].x_offset
= image
->tile_x
;
1068 mt
->level
[0].slice
[0].y_offset
= image
->tile_y
;
1069 mt
->total_width
+= image
->tile_x
;
1070 mt
->total_height
+= image
->tile_y
;
1072 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1073 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1074 * trouble resolving back to destination image due to alignment issues.
1076 if (!brw
->has_surface_tile_offset
) {
1077 uint32_t draw_x
, draw_y
;
1078 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1080 if (draw_x
!= 0 || draw_y
!= 0) {
1081 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1082 intel_miptree_release(&mt
);
1087 if (!intel_miptree_alloc_aux(brw
, mt
)) {
1088 intel_miptree_release(&mt
);
1096 * For a singlesample renderbuffer, this simply wraps the given BO with a
1099 * For a multisample renderbuffer, this wraps the window system's
1100 * (singlesample) BO with a singlesample miptree attached to the
1101 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1102 * that will contain the actual rendering (which is lazily resolved to
1103 * irb->singlesample_mt).
1106 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1107 struct intel_renderbuffer
*irb
,
1108 struct intel_mipmap_tree
*singlesample_mt
,
1109 uint32_t width
, uint32_t height
,
1112 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1113 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1114 mesa_format format
= rb
->Format
;
1115 int num_samples
= rb
->NumSamples
;
1117 /* Only the front and back buffers, which are color buffers, are allocated
1118 * through the image loader.
1120 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1121 _mesa_get_format_base_format(format
) == GL_RGBA
);
1123 assert(singlesample_mt
);
1125 if (num_samples
== 0) {
1126 intel_miptree_release(&irb
->mt
);
1127 irb
->mt
= singlesample_mt
;
1129 assert(!irb
->singlesample_mt
);
1131 intel_miptree_release(&irb
->singlesample_mt
);
1132 irb
->singlesample_mt
= singlesample_mt
;
1135 irb
->mt
->logical_width0
!= width
||
1136 irb
->mt
->logical_height0
!= height
) {
1137 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1142 if (!multisample_mt
)
1145 irb
->need_downsample
= false;
1146 intel_miptree_release(&irb
->mt
);
1147 irb
->mt
= multisample_mt
;
1153 intel_miptree_release(&irb
->mt
);
1157 struct intel_mipmap_tree
*
1158 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1162 uint32_t num_samples
)
1164 struct intel_mipmap_tree
*mt
;
1166 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1167 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1168 MIPTREE_LAYOUT_TILING_ANY
|
1169 MIPTREE_LAYOUT_FOR_SCANOUT
;
1171 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1172 width
, height
, depth
, num_samples
,
1180 intel_miptree_release(&mt
);
1185 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1186 struct intel_mipmap_tree
*src
)
1191 intel_miptree_release(dst
);
1195 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1202 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1204 if (aux_buf
== NULL
)
1207 brw_bo_unreference(aux_buf
->bo
);
1213 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1218 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1219 if (--(*mt
)->refcount
<= 0) {
1222 DBG("%s deleting %p\n", __func__
, *mt
);
1224 brw_bo_unreference((*mt
)->bo
);
1225 intel_miptree_release(&(*mt
)->stencil_mt
);
1226 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1227 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1228 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1229 free_aux_state_map((*mt
)->aux_state
);
1231 intel_miptree_release(&(*mt
)->plane
[0]);
1232 intel_miptree_release(&(*mt
)->plane
[1]);
1234 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1235 free((*mt
)->level
[i
].slice
);
1245 intel_get_image_dims(struct gl_texture_image
*image
,
1246 int *width
, int *height
, int *depth
)
1248 switch (image
->TexObject
->Target
) {
1249 case GL_TEXTURE_1D_ARRAY
:
1250 /* For a 1D Array texture the OpenGL API will treat the image height as
1251 * the number of array slices. For Intel hardware, we treat the 1D array
1252 * as a 2D Array with a height of 1. So, here we want to swap image
1255 assert(image
->Depth
== 1);
1256 *width
= image
->Width
;
1258 *depth
= image
->Height
;
1260 case GL_TEXTURE_CUBE_MAP
:
1261 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1262 * though we really have 6 slices.
1264 assert(image
->Depth
== 1);
1265 *width
= image
->Width
;
1266 *height
= image
->Height
;
1270 *width
= image
->Width
;
1271 *height
= image
->Height
;
1272 *depth
= image
->Depth
;
1278 * Can the image be pulled into a unified mipmap tree? This mirrors
1279 * the completeness test in a lot of ways.
1281 * Not sure whether I want to pass gl_texture_image here.
1284 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1285 struct gl_texture_image
*image
)
1287 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1288 GLuint level
= intelImage
->base
.Base
.Level
;
1289 int width
, height
, depth
;
1291 /* glTexImage* choose the texture object based on the target passed in, and
1292 * objects can't change targets over their lifetimes, so this should be
1295 assert(image
->TexObject
->Target
== mt
->target
);
1297 mesa_format mt_format
= mt
->format
;
1298 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1299 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1300 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1301 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1302 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1303 mt_format
= mt
->etc_format
;
1305 if (image
->TexFormat
!= mt_format
)
1308 intel_get_image_dims(image
, &width
, &height
, &depth
);
1310 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1313 if (mt
->surf
.size
> 0) {
1314 if (level
>= mt
->surf
.levels
)
1317 const unsigned level_depth
=
1318 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1319 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1320 mt
->surf
.logical_level0_px
.array_len
;
1322 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1323 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1324 depth
== level_depth
&&
1325 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1328 int level_depth
= mt
->level
[level
].depth
;
1329 if (mt
->num_samples
> 1) {
1330 switch (mt
->msaa_layout
) {
1331 case INTEL_MSAA_LAYOUT_NONE
:
1332 case INTEL_MSAA_LAYOUT_IMS
:
1334 case INTEL_MSAA_LAYOUT_UMS
:
1335 case INTEL_MSAA_LAYOUT_CMS
:
1336 level_depth
/= mt
->num_samples
;
1341 /* Test image dimensions against the base level image adjusted for
1342 * minification. This will also catch images not present in the
1343 * tree, changed targets, etc.
1345 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1346 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1347 depth
!= level_depth
) {
1351 if (image
->NumSamples
!= mt
->num_samples
)
1359 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1361 GLuint x
, GLuint y
, GLuint d
)
1363 mt
->level
[level
].depth
= d
;
1364 mt
->level
[level
].level_x
= x
;
1365 mt
->level
[level
].level_y
= y
;
1367 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1370 assert(mt
->level
[level
].slice
);
1372 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1373 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1378 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1379 GLuint level
, GLuint img
,
1382 if (img
== 0 && level
== 0)
1383 assert(x
== 0 && y
== 0);
1385 assert(img
< mt
->level
[level
].depth
);
1387 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1388 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1390 DBG("%s level %d img %d pos %d,%d\n",
1391 __func__
, level
, img
,
1392 mt
->level
[level
].slice
[img
].x_offset
,
1393 mt
->level
[level
].slice
[img
].y_offset
);
1397 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1398 GLuint level
, GLuint slice
,
1399 GLuint
*x
, GLuint
*y
)
1401 if (mt
->surf
.size
> 0) {
1402 uint32_t x_offset_sa
, y_offset_sa
;
1404 /* Given level is relative to level zero while the miptree may be
1405 * represent just a subset of all levels starting from 'first_level'.
1407 assert(level
>= mt
->first_level
);
1408 level
-= mt
->first_level
;
1410 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1411 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1412 isl_surf_get_image_offset_sa(&mt
->surf
, level
, slice
, z
,
1413 &x_offset_sa
, &y_offset_sa
);
1420 assert(slice
< mt
->level
[level
].depth
);
1422 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1423 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1428 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1429 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1430 * and tile_h is set to 1.
1433 intel_get_tile_dims(uint32_t tiling
, uint32_t cpp
,
1434 uint32_t *tile_w
, uint32_t *tile_h
)
1445 case I915_TILING_NONE
:
1450 unreachable("not reached");
1456 * This function computes masks that may be used to select the bits of the X
1457 * and Y coordinates that indicate the offset within a tile. If the BO is
1458 * untiled, the masks are set to 0.
1461 intel_get_tile_masks(uint32_t tiling
, uint32_t cpp
,
1462 uint32_t *mask_x
, uint32_t *mask_y
)
1464 uint32_t tile_w_bytes
, tile_h
;
1466 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1468 *mask_x
= tile_w_bytes
/ cpp
- 1;
1469 *mask_y
= tile_h
- 1;
1473 * Compute the offset (in bytes) from the start of the BO to the given x
1474 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1475 * multiples of the tile size.
1478 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1479 uint32_t x
, uint32_t y
)
1482 uint32_t pitch
= mt
->pitch
;
1483 uint32_t tiling
= mt
->tiling
;
1487 unreachable("not reached");
1488 case I915_TILING_NONE
:
1489 return y
* pitch
+ x
* cpp
;
1491 assert((x
% (512 / cpp
)) == 0);
1492 assert((y
% 8) == 0);
1493 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1495 assert((x
% (128 / cpp
)) == 0);
1496 assert((y
% 32) == 0);
1497 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1502 * Rendering with tiled buffers requires that the base address of the buffer
1503 * be aligned to a page boundary. For renderbuffers, and sometimes with
1504 * textures, we may want the surface to point at a texture image level that
1505 * isn't at a page boundary.
1507 * This function returns an appropriately-aligned base offset
1508 * according to the tiling restrictions, plus any required x/y offset
1512 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1513 GLuint level
, GLuint slice
,
1518 uint32_t mask_x
, mask_y
;
1520 intel_get_tile_masks(mt
->tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1521 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1523 *tile_x
= x
& mask_x
;
1524 *tile_y
= y
& mask_y
;
1526 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1530 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1531 struct intel_mipmap_tree
*src_mt
,
1532 unsigned src_level
, unsigned src_layer
,
1533 struct intel_mipmap_tree
*dst_mt
,
1534 unsigned dst_level
, unsigned dst_layer
,
1535 unsigned width
, unsigned height
)
1538 ptrdiff_t src_stride
, dst_stride
;
1539 const unsigned cpp
= dst_mt
->surf
.size
> 0 ?
1540 (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8) : dst_mt
->cpp
;
1542 intel_miptree_map(brw
, src_mt
,
1543 src_level
, src_layer
,
1546 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1549 intel_miptree_map(brw
, dst_mt
,
1550 dst_level
, dst_layer
,
1553 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1557 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1558 _mesa_get_format_name(src_mt
->format
),
1559 src_mt
, src
, src_stride
,
1560 _mesa_get_format_name(dst_mt
->format
),
1561 dst_mt
, dst
, dst_stride
,
1564 int row_size
= cpp
* width
;
1565 if (src_stride
== row_size
&&
1566 dst_stride
== row_size
) {
1567 memcpy(dst
, src
, row_size
* height
);
1569 for (int i
= 0; i
< height
; i
++) {
1570 memcpy(dst
, src
, row_size
);
1576 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1577 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1579 /* Don't forget to copy the stencil data over, too. We could have skipped
1580 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1581 * shuffling the two data sources in/out of temporary storage instead of
1582 * the direct mapping we get this way.
1584 if (dst_mt
->stencil_mt
) {
1585 assert(src_mt
->stencil_mt
);
1586 intel_miptree_copy_slice_sw(brw
,
1587 src_mt
->stencil_mt
, src_level
, src_layer
,
1588 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1594 intel_miptree_copy_slice(struct brw_context
*brw
,
1595 struct intel_mipmap_tree
*src_mt
,
1596 unsigned src_level
, unsigned src_layer
,
1597 struct intel_mipmap_tree
*dst_mt
,
1598 unsigned dst_level
, unsigned dst_layer
)
1601 mesa_format format
= src_mt
->format
;
1602 uint32_t width
, height
;
1604 if (src_mt
->surf
.size
> 0) {
1605 width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1606 src_level
- src_mt
->first_level
);
1607 height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1608 src_level
- src_mt
->first_level
);
1610 if (src_mt
->surf
.dim
== ISL_SURF_DIM_3D
)
1611 assert(src_layer
< minify(src_mt
->surf
.phys_level0_sa
.depth
,
1612 src_level
- src_mt
->first_level
));
1614 assert(src_layer
< src_mt
->surf
.phys_level0_sa
.array_len
);
1616 width
= minify(src_mt
->physical_width0
,
1617 src_level
- src_mt
->first_level
);
1618 height
= minify(src_mt
->physical_height0
,
1619 src_level
- src_mt
->first_level
);
1620 assert(src_layer
< src_mt
->level
[src_level
].depth
);
1623 assert(src_mt
->format
== dst_mt
->format
);
1625 if (dst_mt
->compressed
) {
1627 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1628 height
= ALIGN_NPOT(height
, j
) / j
;
1629 width
= ALIGN_NPOT(width
, i
) / i
;
1632 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1633 * below won't apply since we can't do the depth's Y tiling or the
1634 * stencil's W tiling in the blitter.
1636 if (src_mt
->stencil_mt
) {
1637 intel_miptree_copy_slice_sw(brw
,
1638 src_mt
, src_level
, src_layer
,
1639 dst_mt
, dst_level
, dst_layer
,
1644 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1645 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1647 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1650 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1651 _mesa_get_format_name(src_mt
->format
),
1652 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1653 _mesa_get_format_name(dst_mt
->format
),
1654 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1657 if (!intel_miptree_blit(brw
,
1658 src_mt
, src_level
, src_layer
, 0, 0, false,
1659 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1660 width
, height
, GL_COPY
)) {
1661 perf_debug("miptree validate blit for %s failed\n",
1662 _mesa_get_format_name(format
));
1664 intel_miptree_copy_slice_sw(brw
,
1665 src_mt
, src_level
, src_layer
,
1666 dst_mt
, dst_level
, dst_layer
,
1672 * Copies the image's current data to the given miptree, and associates that
1673 * miptree with the image.
1675 * If \c invalidate is true, then the actual image data does not need to be
1676 * copied, but the image still needs to be associated to the new miptree (this
1677 * is set to true if we're about to clear the image).
1680 intel_miptree_copy_teximage(struct brw_context
*brw
,
1681 struct intel_texture_image
*intelImage
,
1682 struct intel_mipmap_tree
*dst_mt
,
1685 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1686 struct intel_texture_object
*intel_obj
=
1687 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1688 int level
= intelImage
->base
.Base
.Level
;
1689 const unsigned face
= intelImage
->base
.Base
.Face
;
1690 unsigned start_layer
, end_layer
;
1692 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1694 assert(intelImage
->base
.Base
.Height
);
1696 end_layer
= intelImage
->base
.Base
.Height
- 1;
1697 } else if (face
> 0) {
1701 assert(intelImage
->base
.Base
.Depth
);
1703 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1707 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1708 intel_miptree_copy_slice(brw
,
1714 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1715 intel_obj
->needs_validate
= true;
1719 intel_miptree_init_mcs(struct brw_context
*brw
,
1720 struct intel_mipmap_tree
*mt
,
1723 assert(mt
->mcs_buf
!= NULL
);
1725 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1727 * When MCS buffer is enabled and bound to MSRT, it is required that it
1728 * is cleared prior to any rendering.
1730 * Since we don't use the MCS buffer for any purpose other than rendering,
1731 * it makes sense to just clear it immediately upon allocation.
1733 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1735 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1736 if (unlikely(map
== NULL
)) {
1737 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1738 brw_bo_unreference(mt
->mcs_buf
->bo
);
1743 memset(data
, init_value
, mt
->mcs_buf
->size
);
1744 brw_bo_unmap(mt
->mcs_buf
->bo
);
1747 static struct intel_miptree_aux_buffer
*
1748 intel_alloc_aux_buffer(struct brw_context
*brw
,
1750 const struct isl_surf
*aux_surf
,
1751 uint32_t alloc_flags
,
1752 struct intel_mipmap_tree
*mt
)
1754 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1758 buf
->size
= aux_surf
->size
;
1759 buf
->pitch
= aux_surf
->row_pitch
;
1760 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1762 /* ISL has stricter set of alignment rules then the drm allocator.
1763 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1764 * trying to recalculate based on different format block sizes.
1766 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1767 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1773 buf
->surf
= *aux_surf
;
1779 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1780 struct intel_mipmap_tree
*mt
,
1783 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1784 assert(mt
->mcs_buf
== NULL
);
1785 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1787 /* Multisampled miptrees are only supported for single level. */
1788 assert(mt
->first_level
== 0);
1789 enum isl_aux_state
**aux_state
=
1790 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1794 struct isl_surf temp_main_surf
;
1795 struct isl_surf temp_mcs_surf
;
1797 /* Create first an ISL presentation for the main color surface and let ISL
1798 * calculate equivalent MCS surface against it.
1800 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1801 MAYBE_UNUSED
bool ok
=
1802 isl_surf_get_mcs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_mcs_surf
);
1805 /* Buffer needs to be initialised requiring the buffer to be immediately
1806 * mapped to cpu space for writing. Therefore do not use the gpu access
1807 * flag which can cause an unnecessary delay if the backing pages happened
1808 * to be just used by the GPU.
1810 const uint32_t alloc_flags
= 0;
1811 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1812 &temp_mcs_surf
, alloc_flags
, mt
);
1818 mt
->aux_state
= aux_state
;
1820 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1826 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1827 struct intel_mipmap_tree
*mt
)
1829 assert(mt
->mcs_buf
== NULL
);
1830 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1831 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1833 struct isl_surf temp_main_surf
;
1834 struct isl_surf temp_ccs_surf
;
1836 /* Create first an ISL presentation for the main color surface and let ISL
1837 * calculate equivalent CCS surface against it.
1839 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1840 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
,
1844 assert(temp_ccs_surf
.size
&&
1845 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1847 enum isl_aux_state
**aux_state
=
1848 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1852 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1853 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1855 * "If Software wants to enable Color Compression without Fast clear,
1856 * Software needs to initialize MCS with zeros."
1858 * A CCS value of 0 indicates that the corresponding block is in the
1859 * pass-through state which is what we want.
1861 * For CCS_D, on the other hand, we don't care as we're about to perform a
1862 * fast-clear operation. In that case, being hot in caches more useful.
1864 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1865 BO_ALLOC_ZEROED
: BO_ALLOC_FOR_RENDER
;
1866 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1867 &temp_ccs_surf
, alloc_flags
, mt
);
1873 mt
->aux_state
= aux_state
;
1879 * Helper for intel_miptree_alloc_hiz() that sets
1880 * \c mt->level[level].has_hiz. Return true if and only if
1881 * \c has_hiz was set.
1884 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1885 struct intel_mipmap_tree
*mt
,
1888 assert(mt
->hiz_buf
);
1890 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1891 uint32_t width
= minify(mt
->physical_width0
, level
);
1892 uint32_t height
= minify(mt
->physical_height0
, level
);
1894 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1895 * and the height is 4 aligned. This allows our HiZ support
1896 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1897 * we can grow the width & height to allow the HiZ op to
1898 * force the proper size alignments.
1900 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1901 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1906 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1907 mt
->level
[level
].has_hiz
= true;
1912 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1913 struct intel_mipmap_tree
*mt
)
1915 assert(mt
->hiz_buf
== NULL
);
1916 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1918 enum isl_aux_state
**aux_state
=
1919 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1923 struct isl_surf temp_main_surf
;
1924 struct isl_surf temp_hiz_surf
;
1926 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1927 MAYBE_UNUSED
bool ok
=
1928 isl_surf_get_hiz_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_hiz_surf
);
1931 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
1932 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1933 &temp_hiz_surf
, alloc_flags
, mt
);
1940 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1941 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1943 mt
->aux_state
= aux_state
;
1950 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1952 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1953 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1954 * compress clear color so we wait until an actual fast-clear to allocate it.
1957 intel_miptree_alloc_aux(struct brw_context
*brw
,
1958 struct intel_mipmap_tree
*mt
)
1960 switch (mt
->aux_usage
) {
1961 case ISL_AUX_USAGE_NONE
:
1964 case ISL_AUX_USAGE_HIZ
:
1965 assert(!_mesa_is_format_color_format(mt
->format
));
1966 if (!intel_miptree_alloc_hiz(brw
, mt
))
1970 case ISL_AUX_USAGE_MCS
:
1971 assert(_mesa_is_format_color_format(mt
->format
));
1972 assert(mt
->num_samples
> 1);
1973 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->num_samples
))
1977 case ISL_AUX_USAGE_CCS_D
:
1978 /* Since CCS_D can only compress clear color so we wait until an actual
1979 * fast-clear to allocate it.
1983 case ISL_AUX_USAGE_CCS_E
:
1984 assert(_mesa_is_format_color_format(mt
->format
));
1985 assert(mt
->num_samples
<= 1);
1986 if (!intel_miptree_alloc_ccs(brw
, mt
))
1991 unreachable("Invalid aux usage");
1996 * Can the miptree sample using the hiz buffer?
1999 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
2000 struct intel_mipmap_tree
*mt
)
2002 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
2003 * so keep things conservative for now and never enable it unless we're SKL+.
2013 /* It seems the hardware won't fallback to the depth buffer if some of the
2014 * mipmap levels aren't available in the HiZ buffer. So we need all levels
2015 * of the texture to be HiZ enabled.
2017 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
2018 if (!intel_miptree_level_has_hiz(mt
, level
))
2022 /* If compressed multisampling is enabled, then we use it for the auxiliary
2025 * From the BDW PRM (Volume 2d: Command Reference: Structures
2026 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
2028 * "If this field is set to AUX_HIZ, Number of Multisamples must be
2029 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
2031 * There is no such blurb for 1D textures, but there is sufficient evidence
2032 * that this is broken on SKL+.
2034 return (mt
->num_samples
<= 1 &&
2035 mt
->target
!= GL_TEXTURE_3D
&&
2036 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
2040 * Does the miptree slice have hiz enabled?
2043 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
2045 intel_miptree_check_level_layer(mt
, level
, 0);
2046 return mt
->level
[level
].has_hiz
;
2050 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2051 unsigned start_level
, unsigned num_levels
,
2052 unsigned start_layer
, unsigned num_layers
)
2054 assert(_mesa_is_format_color_format(mt
->format
));
2059 /* Clamp the level range to fit the miptree */
2060 assert(start_level
+ num_levels
>= start_level
);
2061 const uint32_t last_level
=
2062 MIN2(mt
->last_level
, start_level
+ num_levels
- 1);
2063 start_level
= MAX2(mt
->first_level
, start_level
);
2064 num_levels
= last_level
- start_level
+ 1;
2066 for (uint32_t level
= start_level
; level
<= last_level
; level
++) {
2067 const uint32_t level_layers
= MIN2(num_layers
, mt
->level
[level
].depth
);
2068 for (unsigned a
= 0; a
< level_layers
; a
++) {
2069 enum isl_aux_state aux_state
=
2070 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2071 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2072 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2081 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2082 const struct intel_mipmap_tree
*mt
,
2083 unsigned level
, unsigned layer
)
2089 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2090 assert(brw
->gen
>= 8 ||
2091 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2093 /* Compression of arrayed msaa surfaces is supported. */
2094 if (mt
->num_samples
> 1)
2097 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2098 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
2104 static enum blorp_fast_clear_op
2105 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2106 bool ccs_supported
, bool fast_clear_supported
)
2108 assert(ccs_supported
== fast_clear_supported
);
2110 switch (aux_state
) {
2111 case ISL_AUX_STATE_CLEAR
:
2112 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2114 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2116 return BLORP_FAST_CLEAR_OP_NONE
;
2118 case ISL_AUX_STATE_PASS_THROUGH
:
2119 return BLORP_FAST_CLEAR_OP_NONE
;
2121 case ISL_AUX_STATE_RESOLVED
:
2122 case ISL_AUX_STATE_AUX_INVALID
:
2123 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2127 unreachable("Invalid aux state for CCS_D");
2130 static enum blorp_fast_clear_op
2131 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2132 bool ccs_supported
, bool fast_clear_supported
)
2134 switch (aux_state
) {
2135 case ISL_AUX_STATE_CLEAR
:
2136 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2138 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2139 else if (!fast_clear_supported
)
2140 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2142 return BLORP_FAST_CLEAR_OP_NONE
;
2144 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2146 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2148 return BLORP_FAST_CLEAR_OP_NONE
;
2150 case ISL_AUX_STATE_PASS_THROUGH
:
2151 return BLORP_FAST_CLEAR_OP_NONE
;
2153 case ISL_AUX_STATE_RESOLVED
:
2154 case ISL_AUX_STATE_AUX_INVALID
:
2158 unreachable("Invalid aux state for CCS_E");
2162 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2163 struct intel_mipmap_tree
*mt
,
2164 uint32_t level
, uint32_t layer
,
2166 bool fast_clear_supported
)
2168 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2170 enum blorp_fast_clear_op resolve_op
;
2171 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2172 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_supported
,
2173 fast_clear_supported
);
2175 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2176 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_supported
,
2177 fast_clear_supported
);
2180 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2181 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2182 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2184 switch (resolve_op
) {
2185 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2186 /* The CCS full resolve operation destroys the CCS and sets it to the
2187 * pass-through state. (You can also think of this as being both a
2188 * resolve and an ambiguate in one operation.)
2190 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2191 ISL_AUX_STATE_PASS_THROUGH
);
2194 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2195 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2196 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2200 unreachable("Invalid resolve op");
2206 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2207 struct intel_mipmap_tree
*mt
,
2208 uint32_t level
, uint32_t layer
,
2209 bool written_with_ccs
)
2211 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2213 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2214 switch (aux_state
) {
2215 case ISL_AUX_STATE_CLEAR
:
2216 assert(written_with_ccs
);
2217 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2218 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2221 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2222 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2223 assert(written_with_ccs
);
2224 break; /* Nothing to do */
2226 case ISL_AUX_STATE_PASS_THROUGH
:
2227 if (written_with_ccs
) {
2228 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2229 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2235 case ISL_AUX_STATE_RESOLVED
:
2236 case ISL_AUX_STATE_AUX_INVALID
:
2237 unreachable("Invalid aux state for CCS_E");
2240 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2241 /* CCS_D is a bit simpler */
2242 switch (aux_state
) {
2243 case ISL_AUX_STATE_CLEAR
:
2244 assert(written_with_ccs
);
2245 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2246 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2249 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2250 assert(written_with_ccs
);
2251 break; /* Nothing to do */
2253 case ISL_AUX_STATE_PASS_THROUGH
:
2257 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2258 case ISL_AUX_STATE_RESOLVED
:
2259 case ISL_AUX_STATE_AUX_INVALID
:
2260 unreachable("Invalid aux state for CCS_D");
2266 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2267 struct intel_mipmap_tree
*mt
,
2268 uint32_t level
, uint32_t layer
,
2269 bool written_with_aux
)
2271 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2272 case ISL_AUX_STATE_CLEAR
:
2273 assert(written_with_aux
);
2274 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2275 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2278 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2279 assert(written_with_aux
);
2280 break; /* Nothing to do */
2282 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2283 case ISL_AUX_STATE_RESOLVED
:
2284 case ISL_AUX_STATE_PASS_THROUGH
:
2285 case ISL_AUX_STATE_AUX_INVALID
:
2286 unreachable("Invalid aux state for MCS");
2291 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2292 struct intel_mipmap_tree
*mt
,
2293 uint32_t level
, uint32_t layer
,
2294 bool hiz_supported
, bool fast_clear_supported
)
2296 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2297 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2298 case ISL_AUX_STATE_CLEAR
:
2299 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2300 if (!hiz_supported
|| !fast_clear_supported
)
2301 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2304 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2306 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2309 case ISL_AUX_STATE_PASS_THROUGH
:
2310 case ISL_AUX_STATE_RESOLVED
:
2313 case ISL_AUX_STATE_AUX_INVALID
:
2315 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2319 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2320 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2323 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2324 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2325 ISL_AUX_STATE_RESOLVED
);
2328 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2329 /* The HiZ resolve operation is actually an ambiguate */
2330 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2331 ISL_AUX_STATE_PASS_THROUGH
);
2335 unreachable("Invalid HiZ op");
2341 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2342 struct intel_mipmap_tree
*mt
,
2343 uint32_t level
, uint32_t layer
,
2344 bool written_with_hiz
)
2346 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2347 case ISL_AUX_STATE_CLEAR
:
2348 assert(written_with_hiz
);
2349 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2350 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2353 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2354 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2355 assert(written_with_hiz
);
2356 break; /* Nothing to do */
2358 case ISL_AUX_STATE_RESOLVED
:
2359 if (written_with_hiz
) {
2360 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2361 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2363 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2364 ISL_AUX_STATE_AUX_INVALID
);
2368 case ISL_AUX_STATE_PASS_THROUGH
:
2369 if (written_with_hiz
) {
2370 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2371 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2375 case ISL_AUX_STATE_AUX_INVALID
:
2376 assert(!written_with_hiz
);
2381 static inline uint32_t
2382 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
2383 uint32_t start_level
, uint32_t num_levels
)
2385 assert(start_level
>= mt
->first_level
);
2386 assert(start_level
<= mt
->last_level
);
2388 if (num_levels
== INTEL_REMAINING_LAYERS
)
2389 num_levels
= mt
->last_level
- start_level
+ 1;
2390 /* Check for overflow */
2391 assert(start_level
+ num_levels
>= start_level
);
2392 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2397 static inline uint32_t
2398 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2399 uint32_t start_layer
, uint32_t num_layers
)
2401 assert(level
<= mt
->last_level
);
2402 uint32_t total_num_layers
;
2404 if (mt
->surf
.size
> 0)
2405 total_num_layers
= mt
->surf
.dim
== ISL_SURF_DIM_3D
?
2406 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
2407 mt
->surf
.phys_level0_sa
.array_len
;
2409 total_num_layers
= mt
->level
[level
].depth
;
2411 assert(start_layer
< total_num_layers
);
2412 if (num_layers
== INTEL_REMAINING_LAYERS
)
2413 num_layers
= total_num_layers
- start_layer
;
2414 /* Check for overflow */
2415 assert(start_layer
+ num_layers
>= start_layer
);
2416 assert(start_layer
+ num_layers
<= total_num_layers
);
2422 intel_miptree_prepare_access(struct brw_context
*brw
,
2423 struct intel_mipmap_tree
*mt
,
2424 uint32_t start_level
, uint32_t num_levels
,
2425 uint32_t start_layer
, uint32_t num_layers
,
2426 bool aux_supported
, bool fast_clear_supported
)
2428 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2430 if (_mesa_is_format_color_format(mt
->format
)) {
2434 if (mt
->num_samples
> 1) {
2435 /* Nothing to do for MSAA */
2436 assert(aux_supported
&& fast_clear_supported
);
2438 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2439 const uint32_t level
= start_level
+ l
;
2440 const uint32_t level_layers
=
2441 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2442 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2443 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2444 start_layer
+ a
, aux_supported
,
2445 fast_clear_supported
);
2449 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2450 /* Nothing to do for stencil */
2455 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2456 const uint32_t level
= start_level
+ l
;
2457 if (!intel_miptree_level_has_hiz(mt
, level
))
2460 const uint32_t level_layers
=
2461 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2462 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2463 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2465 fast_clear_supported
);
2472 intel_miptree_finish_write(struct brw_context
*brw
,
2473 struct intel_mipmap_tree
*mt
, uint32_t level
,
2474 uint32_t start_layer
, uint32_t num_layers
,
2475 bool written_with_aux
)
2477 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2479 if (_mesa_is_format_color_format(mt
->format
)) {
2483 if (mt
->num_samples
> 1) {
2484 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2485 intel_miptree_finish_mcs_write(brw
, mt
, level
, start_layer
+ a
,
2489 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2490 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2494 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2495 /* Nothing to do for stencil */
2497 if (!intel_miptree_level_has_hiz(mt
, level
))
2500 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2501 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2508 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2509 uint32_t level
, uint32_t layer
)
2511 intel_miptree_check_level_layer(mt
, level
, layer
);
2513 if (_mesa_is_format_color_format(mt
->format
)) {
2514 assert(mt
->mcs_buf
!= NULL
);
2515 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2516 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2517 unreachable("Cannot get aux state for stencil");
2519 assert(intel_miptree_level_has_hiz(mt
, level
));
2522 return mt
->aux_state
[level
][layer
];
2526 intel_miptree_set_aux_state(struct brw_context
*brw
,
2527 struct intel_mipmap_tree
*mt
, uint32_t level
,
2528 uint32_t start_layer
, uint32_t num_layers
,
2529 enum isl_aux_state aux_state
)
2531 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2533 if (_mesa_is_format_color_format(mt
->format
)) {
2534 assert(mt
->mcs_buf
!= NULL
);
2535 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2536 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2537 unreachable("Cannot get aux state for stencil");
2539 assert(intel_miptree_level_has_hiz(mt
, level
));
2542 for (unsigned a
= 0; a
< num_layers
; a
++)
2543 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2546 /* On Gen9 color buffers may be compressed by the hardware (lossless
2547 * compression). There are, however, format restrictions and care needs to be
2548 * taken that the sampler engine is capable for re-interpreting a buffer with
2549 * format different the buffer was originally written with.
2551 * For example, SRGB formats are not compressible and the sampler engine isn't
2552 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2553 * color buffer needs to be resolved so that the sampling surface can be
2554 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2558 can_texture_with_ccs(struct brw_context
*brw
,
2559 struct intel_mipmap_tree
*mt
,
2560 mesa_format view_format
)
2562 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2565 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2566 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2568 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2569 isl_mt_format
, isl_view_format
)) {
2570 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2571 _mesa_get_format_name(view_format
),
2572 _mesa_get_format_name(mt
->format
));
2580 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2581 struct intel_mipmap_tree
*mt
,
2582 mesa_format view_format
,
2583 uint32_t start_level
, uint32_t num_levels
,
2584 uint32_t start_layer
, uint32_t num_layers
,
2585 bool *aux_supported_out
)
2587 bool aux_supported
, clear_supported
;
2588 if (_mesa_is_format_color_format(mt
->format
)) {
2589 if (mt
->num_samples
> 1) {
2590 aux_supported
= clear_supported
= true;
2592 aux_supported
= can_texture_with_ccs(brw
, mt
, view_format
);
2594 /* Clear color is specified as ints or floats and the conversion is
2595 * done by the sampler. If we have a texture view, we would have to
2596 * perform the clear color conversion manually. Just disable clear
2599 clear_supported
= aux_supported
&& (mt
->format
== view_format
);
2601 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2602 aux_supported
= clear_supported
= false;
2604 aux_supported
= clear_supported
= intel_miptree_sample_with_hiz(brw
, mt
);
2607 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2608 start_layer
, num_layers
,
2609 aux_supported
, clear_supported
);
2610 if (aux_supported_out
)
2611 *aux_supported_out
= aux_supported
;
2615 intel_miptree_prepare_texture(struct brw_context
*brw
,
2616 struct intel_mipmap_tree
*mt
,
2617 mesa_format view_format
,
2618 bool *aux_supported_out
)
2620 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2621 0, INTEL_REMAINING_LEVELS
,
2622 0, INTEL_REMAINING_LAYERS
,
2627 intel_miptree_prepare_image(struct brw_context
*brw
,
2628 struct intel_mipmap_tree
*mt
)
2630 /* The data port doesn't understand any compression */
2631 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2632 0, INTEL_REMAINING_LAYERS
, false, false);
2636 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2637 struct intel_mipmap_tree
*mt
, uint32_t level
,
2638 uint32_t start_layer
, uint32_t num_layers
)
2640 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2641 start_layer
, num_layers
, NULL
);
2645 intel_miptree_prepare_render(struct brw_context
*brw
,
2646 struct intel_mipmap_tree
*mt
, uint32_t level
,
2647 uint32_t start_layer
, uint32_t layer_count
,
2650 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2651 * the single-sampled color renderbuffers because the CCS buffer isn't
2652 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2653 * enabled because otherwise the surface state will be programmed with
2654 * the linear equivalent format anyway.
2656 if (brw
->gen
== 9 && srgb_enabled
&& mt
->num_samples
<= 1 &&
2657 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2659 /* Lossless compression is not supported for SRGB formats, it
2660 * should be impossible to get here with such surfaces.
2662 assert(mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
);
2663 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2669 intel_miptree_finish_render(struct brw_context
*brw
,
2670 struct intel_mipmap_tree
*mt
, uint32_t level
,
2671 uint32_t start_layer
, uint32_t layer_count
)
2673 assert(_mesa_is_format_color_format(mt
->format
));
2674 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2675 mt
->mcs_buf
!= NULL
);
2679 intel_miptree_prepare_depth(struct brw_context
*brw
,
2680 struct intel_mipmap_tree
*mt
, uint32_t level
,
2681 uint32_t start_layer
, uint32_t layer_count
)
2683 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2684 mt
->hiz_buf
!= NULL
, mt
->hiz_buf
!= NULL
);
2688 intel_miptree_finish_depth(struct brw_context
*brw
,
2689 struct intel_mipmap_tree
*mt
, uint32_t level
,
2690 uint32_t start_layer
, uint32_t layer_count
,
2693 if (depth_written
) {
2694 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2695 mt
->hiz_buf
!= NULL
);
2700 * Make it possible to share the BO backing the given miptree with another
2701 * process or another miptree.
2703 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2704 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2705 * ensure that no MCS buffer gets allocated in the future.
2707 * HiZ is similarly unsafe with shared buffers.
2710 intel_miptree_make_shareable(struct brw_context
*brw
,
2711 struct intel_mipmap_tree
*mt
)
2713 /* MCS buffers are also used for multisample buffers, but we can't resolve
2714 * away a multisample MCS buffer because it's an integral part of how the
2715 * pixel data is stored. Fortunately this code path should never be
2716 * reached for multisample buffers.
2718 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
|| mt
->num_samples
<= 1);
2720 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2721 0, INTEL_REMAINING_LAYERS
, false, false);
2724 brw_bo_unreference(mt
->mcs_buf
->bo
);
2728 /* Any pending MCS/CCS operations are no longer needed. Trying to
2729 * execute any will likely crash due to the missing aux buffer. So let's
2730 * delete all pending ops.
2732 free(mt
->aux_state
);
2733 mt
->aux_state
= NULL
;
2737 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2740 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2741 mt
->level
[l
].has_hiz
= false;
2744 /* Any pending HiZ operations are no longer needed. Trying to execute
2745 * any will likely crash due to the missing aux buffer. So let's delete
2748 free(mt
->aux_state
);
2749 mt
->aux_state
= NULL
;
2752 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2757 * \brief Get pointer offset into stencil buffer.
2759 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2760 * must decode the tile's layout in software.
2763 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2765 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2767 * Even though the returned offset is always positive, the return type is
2769 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2770 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2773 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2775 uint32_t tile_size
= 4096;
2776 uint32_t tile_width
= 64;
2777 uint32_t tile_height
= 64;
2778 uint32_t row_size
= 64 * stride
;
2780 uint32_t tile_x
= x
/ tile_width
;
2781 uint32_t tile_y
= y
/ tile_height
;
2783 /* The byte's address relative to the tile's base addres. */
2784 uint32_t byte_x
= x
% tile_width
;
2785 uint32_t byte_y
= y
% tile_height
;
2787 uintptr_t u
= tile_y
* row_size
2788 + tile_x
* tile_size
2789 + 512 * (byte_x
/ 8)
2791 + 32 * ((byte_y
/ 4) % 2)
2792 + 16 * ((byte_x
/ 4) % 2)
2793 + 8 * ((byte_y
/ 2) % 2)
2794 + 4 * ((byte_x
/ 2) % 2)
2799 /* adjust for bit6 swizzling */
2800 if (((byte_x
/ 8) % 2) == 1) {
2801 if (((byte_y
/ 8) % 2) == 0) {
2813 intel_miptree_updownsample(struct brw_context
*brw
,
2814 struct intel_mipmap_tree
*src
,
2815 struct intel_mipmap_tree
*dst
)
2817 unsigned src_w
, src_h
, dst_w
, dst_h
;
2819 if (src
->surf
.size
> 0) {
2820 src_w
= src
->surf
.logical_level0_px
.width
;
2821 src_h
= src
->surf
.logical_level0_px
.height
;
2823 src_w
= src
->logical_width0
;
2824 src_h
= src
->logical_height0
;
2827 if (dst
->surf
.size
> 0) {
2828 dst_w
= dst
->surf
.logical_level0_px
.width
;
2829 dst_h
= dst
->surf
.logical_level0_px
.height
;
2831 dst_w
= dst
->logical_width0
;
2832 dst_h
= dst
->logical_height0
;
2835 brw_blorp_blit_miptrees(brw
,
2836 src
, 0 /* level */, 0 /* layer */,
2837 src
->format
, SWIZZLE_XYZW
,
2838 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2841 GL_NEAREST
, false, false /*mirror x, y*/,
2844 if (src
->stencil_mt
) {
2845 if (src
->stencil_mt
->surf
.size
> 0) {
2846 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2847 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2849 src_w
= src
->stencil_mt
->logical_width0
;
2850 src_h
= src
->stencil_mt
->logical_height0
;
2853 if (dst
->stencil_mt
->surf
.size
> 0) {
2854 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2855 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2857 dst_w
= dst
->stencil_mt
->logical_width0
;
2858 dst_h
= dst
->stencil_mt
->logical_height0
;
2861 brw_blorp_blit_miptrees(brw
,
2862 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2863 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2864 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2865 dst
->stencil_mt
->format
,
2868 GL_NEAREST
, false, false /*mirror x, y*/,
2869 false, false /* decode/encode srgb */);
2874 intel_update_r8stencil(struct brw_context
*brw
,
2875 struct intel_mipmap_tree
*mt
)
2877 assert(brw
->gen
>= 7);
2878 struct intel_mipmap_tree
*src
=
2879 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2880 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2883 if (!mt
->r8stencil_mt
) {
2884 const uint32_t r8stencil_flags
=
2885 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2886 MIPTREE_LAYOUT_DISABLE_AUX
;
2887 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2888 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2890 MESA_FORMAT_R_UINT8
,
2893 src
->logical_width0
,
2894 src
->logical_height0
,
2895 src
->logical_depth0
,
2898 assert(mt
->r8stencil_mt
);
2901 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2903 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2904 const unsigned depth
= src
->level
[level
].depth
;
2906 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2907 brw_blorp_copy_miptrees(brw
,
2911 minify(src
->logical_width0
, level
),
2912 minify(src
->logical_height0
, level
));
2916 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2917 src
->r8stencil_needs_update
= false;
2921 intel_miptree_map_raw(struct brw_context
*brw
,
2922 struct intel_mipmap_tree
*mt
,
2925 struct brw_bo
*bo
= mt
->bo
;
2927 if (brw_batch_references(&brw
->batch
, bo
))
2928 intel_batchbuffer_flush(brw
);
2930 return brw_bo_map(brw
, bo
, mode
);
2934 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2936 brw_bo_unmap(mt
->bo
);
2940 intel_miptree_map_gtt(struct brw_context
*brw
,
2941 struct intel_mipmap_tree
*mt
,
2942 struct intel_miptree_map
*map
,
2943 unsigned int level
, unsigned int slice
)
2945 unsigned int bw
, bh
;
2947 unsigned int image_x
, image_y
;
2948 intptr_t x
= map
->x
;
2949 intptr_t y
= map
->y
;
2951 /* For compressed formats, the stride is the number of bytes per
2952 * row of blocks. intel_miptree_get_image_offset() already does
2955 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2956 assert(y
% bh
== 0);
2957 assert(x
% bw
== 0);
2961 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
2968 /* Note that in the case of cube maps, the caller must have passed the
2969 * slice number referencing the face.
2971 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2975 map
->stride
= mt
->pitch
;
2976 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2979 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2980 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2981 map
->x
, map
->y
, map
->w
, map
->h
,
2982 mt
, _mesa_get_format_name(mt
->format
),
2983 x
, y
, map
->ptr
, map
->stride
);
2987 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2989 intel_miptree_unmap_raw(mt
);
2993 intel_miptree_map_blit(struct brw_context
*brw
,
2994 struct intel_mipmap_tree
*mt
,
2995 struct intel_miptree_map
*map
,
2996 unsigned int level
, unsigned int slice
)
2998 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2999 /* first_level */ 0,
3003 MIPTREE_LAYOUT_TILING_NONE
);
3005 if (!map
->linear_mt
) {
3006 fprintf(stderr
, "Failed to allocate blit temporary\n");
3009 map
->stride
= map
->linear_mt
->pitch
;
3011 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3012 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3013 * invalidate is set, since we'll be writing the whole rectangle from our
3014 * temporary buffer back out.
3016 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3017 if (!intel_miptree_copy(brw
,
3018 mt
, level
, slice
, map
->x
, map
->y
,
3019 map
->linear_mt
, 0, 0, 0, 0,
3021 fprintf(stderr
, "Failed to blit\n");
3026 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3028 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3029 map
->x
, map
->y
, map
->w
, map
->h
,
3030 mt
, _mesa_get_format_name(mt
->format
),
3031 level
, slice
, map
->ptr
, map
->stride
);
3036 intel_miptree_release(&map
->linear_mt
);
3042 intel_miptree_unmap_blit(struct brw_context
*brw
,
3043 struct intel_mipmap_tree
*mt
,
3044 struct intel_miptree_map
*map
,
3048 struct gl_context
*ctx
= &brw
->ctx
;
3050 intel_miptree_unmap_raw(map
->linear_mt
);
3052 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3053 bool ok
= intel_miptree_copy(brw
,
3054 map
->linear_mt
, 0, 0, 0, 0,
3055 mt
, level
, slice
, map
->x
, map
->y
,
3057 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3060 intel_miptree_release(&map
->linear_mt
);
3064 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3066 #if defined(USE_SSE41)
3068 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3069 struct intel_mipmap_tree
*mt
,
3070 struct intel_miptree_map
*map
,
3071 unsigned int level
, unsigned int slice
)
3073 assert(map
->mode
& GL_MAP_READ_BIT
);
3074 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3076 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3077 map
->x
, map
->y
, map
->w
, map
->h
,
3078 mt
, _mesa_get_format_name(mt
->format
),
3079 level
, slice
, map
->ptr
, map
->stride
);
3081 /* Map the original image */
3084 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3088 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3094 src
+= image_y
* mt
->pitch
;
3095 src
+= image_x
* mt
->cpp
;
3097 /* Due to the pixel offsets for the particular image being mapped, our
3098 * src pointer may not be 16-byte aligned. However, if the pitch is
3099 * divisible by 16, then the amount by which it's misaligned will remain
3100 * consistent from row to row.
3102 assert((mt
->pitch
% 16) == 0);
3103 const int misalignment
= ((uintptr_t) src
) & 15;
3105 /* Create an untiled temporary buffer for the mapping. */
3106 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3108 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3110 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3111 /* Offset the destination so it has the same misalignment as src. */
3112 map
->ptr
= map
->buffer
+ misalignment
;
3114 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3116 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3117 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3118 void *src_ptr
= src
+ y
* mt
->pitch
;
3120 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3123 intel_miptree_unmap_raw(mt
);
3127 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3128 struct intel_mipmap_tree
*mt
,
3129 struct intel_miptree_map
*map
,
3133 _mesa_align_free(map
->buffer
);
3140 intel_miptree_map_s8(struct brw_context
*brw
,
3141 struct intel_mipmap_tree
*mt
,
3142 struct intel_miptree_map
*map
,
3143 unsigned int level
, unsigned int slice
)
3145 map
->stride
= map
->w
;
3146 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3150 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3151 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3152 * invalidate is set, since we'll be writing the whole rectangle from our
3153 * temporary buffer back out.
3155 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3156 /* ISL uses a stencil pitch value that is expected by hardware whereas
3157 * traditional miptree uses half of that. Below the value gets supplied
3158 * to intel_offset_S8() which expects the legacy interpretation.
3160 const unsigned pitch
= mt
->surf
.size
> 0 ?
3161 mt
->surf
.row_pitch
/ 2 : mt
->pitch
;
3162 uint8_t *untiled_s8_map
= map
->ptr
;
3163 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3164 unsigned int image_x
, image_y
;
3166 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3168 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3169 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3170 ptrdiff_t offset
= intel_offset_S8(pitch
,
3171 x
+ image_x
+ map
->x
,
3172 y
+ image_y
+ map
->y
,
3173 brw
->has_swizzling
);
3174 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3178 intel_miptree_unmap_raw(mt
);
3180 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3181 map
->x
, map
->y
, map
->w
, map
->h
,
3182 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3184 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3185 map
->x
, map
->y
, map
->w
, map
->h
,
3186 mt
, map
->ptr
, map
->stride
);
3191 intel_miptree_unmap_s8(struct brw_context
*brw
,
3192 struct intel_mipmap_tree
*mt
,
3193 struct intel_miptree_map
*map
,
3197 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3198 /* ISL uses a stencil pitch value that is expected by hardware whereas
3199 * traditional miptree uses half of that. Below the value gets supplied
3200 * to intel_offset_S8() which expects the legacy interpretation.
3202 const unsigned pitch
= mt
->surf
.size
> 0 ?
3203 mt
->surf
.row_pitch
/ 2: mt
->pitch
;
3204 unsigned int image_x
, image_y
;
3205 uint8_t *untiled_s8_map
= map
->ptr
;
3206 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3208 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3210 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3211 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3212 ptrdiff_t offset
= intel_offset_S8(pitch
,
3213 image_x
+ x
+ map
->x
,
3214 image_y
+ y
+ map
->y
,
3215 brw
->has_swizzling
);
3216 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3220 intel_miptree_unmap_raw(mt
);
3227 intel_miptree_map_etc(struct brw_context
*brw
,
3228 struct intel_mipmap_tree
*mt
,
3229 struct intel_miptree_map
*map
,
3233 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3234 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3235 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3238 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3239 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3241 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3242 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3243 map
->w
, map
->h
, 1));
3244 map
->ptr
= map
->buffer
;
3248 intel_miptree_unmap_etc(struct brw_context
*brw
,
3249 struct intel_mipmap_tree
*mt
,
3250 struct intel_miptree_map
*map
,
3256 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3261 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3262 + image_y
* mt
->pitch
3263 + image_x
* mt
->cpp
;
3265 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3266 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
3267 map
->ptr
, map
->stride
,
3270 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
3271 map
->ptr
, map
->stride
,
3272 map
->w
, map
->h
, mt
->etc_format
);
3274 intel_miptree_unmap_raw(mt
);
3279 * Mapping function for packed depth/stencil miptrees backed by real separate
3280 * miptrees for depth and stencil.
3282 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3283 * separate from the depth buffer. Yet at the GL API level, we have to expose
3284 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3285 * be able to map that memory for texture storage and glReadPixels-type
3286 * operations. We give Mesa core that access by mallocing a temporary and
3287 * copying the data between the actual backing store and the temporary.
3290 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3291 struct intel_mipmap_tree
*mt
,
3292 struct intel_miptree_map
*map
,
3293 unsigned int level
, unsigned int slice
)
3295 struct intel_mipmap_tree
*z_mt
= mt
;
3296 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3297 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3298 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3300 map
->stride
= map
->w
* packed_bpp
;
3301 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3305 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3306 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3307 * invalidate is set, since we'll be writing the whole rectangle from our
3308 * temporary buffer back out.
3310 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3311 /* ISL uses a stencil pitch value that is expected by hardware whereas
3312 * traditional miptree uses half of that. Below the value gets supplied
3313 * to intel_offset_S8() which expects the legacy interpretation.
3315 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3316 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3317 uint32_t *packed_map
= map
->ptr
;
3318 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3319 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3320 unsigned int s_image_x
, s_image_y
;
3321 unsigned int z_image_x
, z_image_y
;
3323 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3324 &s_image_x
, &s_image_y
);
3325 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3326 &z_image_x
, &z_image_y
);
3328 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3329 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3330 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3331 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3334 brw
->has_swizzling
);
3335 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3337 (map_x
+ z_image_x
));
3338 uint8_t s
= s_map
[s_offset
];
3339 uint32_t z
= z_map
[z_offset
];
3341 if (map_z32f_x24s8
) {
3342 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3343 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3345 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3350 intel_miptree_unmap_raw(s_mt
);
3351 intel_miptree_unmap_raw(z_mt
);
3353 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3355 map
->x
, map
->y
, map
->w
, map
->h
,
3356 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3357 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3358 map
->ptr
, map
->stride
);
3360 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3361 map
->x
, map
->y
, map
->w
, map
->h
,
3362 mt
, map
->ptr
, map
->stride
);
3367 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3368 struct intel_mipmap_tree
*mt
,
3369 struct intel_miptree_map
*map
,
3373 struct intel_mipmap_tree
*z_mt
= mt
;
3374 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3375 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3377 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3378 /* ISL uses a stencil pitch value that is expected by hardware whereas
3379 * traditional miptree uses half of that. Below the value gets supplied
3380 * to intel_offset_S8() which expects the legacy interpretation.
3382 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3383 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3384 uint32_t *packed_map
= map
->ptr
;
3385 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3386 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3387 unsigned int s_image_x
, s_image_y
;
3388 unsigned int z_image_x
, z_image_y
;
3390 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3391 &s_image_x
, &s_image_y
);
3392 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3393 &z_image_x
, &z_image_y
);
3395 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3396 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3397 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3398 x
+ s_image_x
+ map
->x
,
3399 y
+ s_image_y
+ map
->y
,
3400 brw
->has_swizzling
);
3401 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3403 (x
+ z_image_x
+ map
->x
));
3405 if (map_z32f_x24s8
) {
3406 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3407 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3409 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3410 s_map
[s_offset
] = packed
>> 24;
3411 z_map
[z_offset
] = packed
;
3416 intel_miptree_unmap_raw(s_mt
);
3417 intel_miptree_unmap_raw(z_mt
);
3419 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3421 map
->x
, map
->y
, map
->w
, map
->h
,
3422 z_mt
, _mesa_get_format_name(z_mt
->format
),
3423 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3424 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3425 map
->ptr
, map
->stride
);
3432 * Create and attach a map to the miptree at (level, slice). Return the
3435 static struct intel_miptree_map
*
3436 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3445 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3450 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3451 mt
->level
[level
].slice
[slice
].map
= map
;
3463 * Release the map at (level, slice).
3466 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3470 struct intel_miptree_map
**map
;
3472 map
= &mt
->level
[level
].slice
[slice
].map
;
3478 can_blit_slice(struct intel_mipmap_tree
*mt
,
3479 unsigned int level
, unsigned int slice
)
3481 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3482 if (mt
->pitch
>= 32768)
3489 use_intel_mipree_map_blit(struct brw_context
*brw
,
3490 struct intel_mipmap_tree
*mt
,
3496 /* It's probably not worth swapping to the blit ring because of
3497 * all the overhead involved.
3499 !(mode
& GL_MAP_WRITE_BIT
) &&
3501 (mt
->tiling
== I915_TILING_X
||
3502 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3503 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
3504 /* Fast copy blit on skl+ supports all tiling formats. */
3506 can_blit_slice(mt
, level
, slice
))
3509 if (mt
->tiling
!= I915_TILING_NONE
&&
3510 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3511 assert(can_blit_slice(mt
, level
, slice
));
3519 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3520 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3521 * arithmetic overflow.
3523 * If you call this function and use \a out_stride, then you're doing pointer
3524 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3525 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3526 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3527 * which usually have type uint32_t or GLuint.
3530 intel_miptree_map(struct brw_context
*brw
,
3531 struct intel_mipmap_tree
*mt
,
3540 ptrdiff_t *out_stride
)
3542 struct intel_miptree_map
*map
;
3544 assert(mt
->num_samples
<= 1);
3546 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3553 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3554 map
->mode
& GL_MAP_WRITE_BIT
);
3556 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3557 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3558 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3559 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3560 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3561 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3562 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3563 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3564 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3565 #if defined(USE_SSE41)
3566 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3567 !mt
->compressed
&& cpu_has_sse4_1
&&
3568 (mt
->pitch
% 16 == 0)) {
3569 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3572 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3575 *out_ptr
= map
->ptr
;
3576 *out_stride
= map
->stride
;
3578 if (map
->ptr
== NULL
)
3579 intel_miptree_release_map(mt
, level
, slice
);
3583 intel_miptree_unmap(struct brw_context
*brw
,
3584 struct intel_mipmap_tree
*mt
,
3588 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3590 assert(mt
->num_samples
<= 1);
3595 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3596 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3598 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3599 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3600 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3601 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3602 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3603 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3604 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3605 } else if (map
->linear_mt
) {
3606 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3607 #if defined(USE_SSE41)
3608 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3609 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3612 intel_miptree_unmap_gtt(mt
);
3615 intel_miptree_release_map(mt
, level
, slice
);
3619 get_isl_surf_dim(GLenum target
)
3623 case GL_TEXTURE_1D_ARRAY
:
3624 return ISL_SURF_DIM_1D
;
3627 case GL_TEXTURE_2D_ARRAY
:
3628 case GL_TEXTURE_RECTANGLE
:
3629 case GL_TEXTURE_CUBE_MAP
:
3630 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3631 case GL_TEXTURE_2D_MULTISAMPLE
:
3632 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3633 case GL_TEXTURE_EXTERNAL_OES
:
3634 return ISL_SURF_DIM_2D
;
3637 return ISL_SURF_DIM_3D
;
3640 unreachable("Invalid texture target");
3644 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3645 GLenum target
, enum miptree_array_layout array_layout
)
3647 if (array_layout
== GEN6_HIZ_STENCIL
)
3648 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
3652 case GL_TEXTURE_1D_ARRAY
:
3653 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3654 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3657 case GL_TEXTURE_2D_ARRAY
:
3658 case GL_TEXTURE_RECTANGLE
:
3659 case GL_TEXTURE_2D_MULTISAMPLE
:
3660 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3661 case GL_TEXTURE_EXTERNAL_OES
:
3662 return ISL_DIM_LAYOUT_GEN4_2D
;
3664 case GL_TEXTURE_CUBE_MAP
:
3665 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3666 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3667 ISL_DIM_LAYOUT_GEN4_2D
);
3670 return (devinfo
->gen
>= 9 ?
3671 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3674 unreachable("Invalid texture target");
3678 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3680 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3681 return ISL_TILING_W
;
3683 switch (mt
->tiling
) {
3684 case I915_TILING_NONE
:
3685 return ISL_TILING_LINEAR
;
3687 return ISL_TILING_X
;
3689 return ISL_TILING_Y0
;
3691 unreachable("Invalid tiling mode");
3697 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3698 const struct intel_mipmap_tree
*mt
,
3699 struct isl_surf
*surf
)
3701 surf
->dim
= get_isl_surf_dim(mt
->target
);
3702 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3703 mt
->tiling
, mt
->target
,
3706 if (mt
->num_samples
> 1) {
3707 switch (mt
->msaa_layout
) {
3708 case INTEL_MSAA_LAYOUT_IMS
:
3709 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3711 case INTEL_MSAA_LAYOUT_UMS
:
3712 case INTEL_MSAA_LAYOUT_CMS
:
3713 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3716 unreachable("Invalid MSAA layout");
3719 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3722 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3724 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3725 /* The ISL definition of row_pitch matches the surface state pitch field
3726 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3727 * the factor of 2 for W-tiling in row_pitch.
3729 surf
->row_pitch
= 2 * mt
->pitch
;
3731 surf
->row_pitch
= mt
->pitch
;
3734 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3736 if (brw
->gen
>= 9) {
3737 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3738 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3739 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3741 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3742 * alignment in terms of surface elements like we want.
3744 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3747 /* On earlier gens it's stored in pixels. */
3749 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3750 surf
->image_alignment_el
=
3751 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3754 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3755 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3756 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3757 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3758 surf
->logical_level0_px
.array_len
= 1;
3760 surf
->logical_level0_px
.depth
= 1;
3761 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3764 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3765 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3766 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3767 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3768 surf
->phys_level0_sa
.array_len
= 1;
3770 surf
->phys_level0_sa
.depth
= 1;
3771 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3774 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3775 surf
->samples
= MAX2(mt
->num_samples
, 1);
3777 surf
->size
= 0; /* TODO */
3778 surf
->alignment
= 0; /* TODO */
3780 switch (surf
->dim_layout
) {
3781 case ISL_DIM_LAYOUT_GEN4_2D
:
3782 case ISL_DIM_LAYOUT_GEN4_3D
:
3783 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
3784 if (brw
->gen
>= 9) {
3785 surf
->array_pitch_el_rows
= mt
->qpitch
;
3788 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3789 assert(mt
->qpitch
% bh
== 0);
3790 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3793 case ISL_DIM_LAYOUT_GEN9_1D
:
3794 surf
->array_pitch_el_rows
= 1;
3798 switch (mt
->array_layout
) {
3799 case ALL_LOD_IN_EACH_SLICE
:
3800 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3802 case ALL_SLICES_AT_EACH_LOD
:
3803 case GEN6_HIZ_STENCIL
:
3804 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3807 unreachable("Invalid array layout");
3810 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3811 switch (base_format
) {
3812 case GL_DEPTH_COMPONENT
:
3813 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3815 case GL_STENCIL_INDEX
:
3816 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3818 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3820 case GL_DEPTH_STENCIL
:
3821 /* In this case we only texture from the depth part */
3822 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3823 ISL_SURF_USAGE_TEXTURE_BIT
;
3826 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3827 if (brw
->mesa_format_supports_render
[mt
->format
])
3828 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3832 if (_mesa_is_cube_map_texture(mt
->target
))
3833 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3837 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3838 const struct intel_mipmap_tree
*mt
)
3841 return ISL_AUX_USAGE_HIZ
;
3844 return ISL_AUX_USAGE_NONE
;
3846 return mt
->aux_usage
;