1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_chipset.h"
33 #include "intel_mipmap_tree.h"
34 #include "intel_regions.h"
35 #include "intel_resolve_map.h"
36 #include "intel_tex.h"
37 #include "intel_blit.h"
38 #include "intel_fbo.h"
40 #include "brw_blorp.h"
41 #include "brw_context.h"
43 #include "main/enums.h"
44 #include "main/formats.h"
45 #include "main/glformats.h"
46 #include "main/texcompress_etc.h"
47 #include "main/teximage.h"
48 #include "main/streaming-load-memcpy.h"
50 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
53 target_to_target(GLenum target
)
56 case GL_TEXTURE_CUBE_MAP_POSITIVE_X_ARB
:
57 case GL_TEXTURE_CUBE_MAP_NEGATIVE_X_ARB
:
58 case GL_TEXTURE_CUBE_MAP_POSITIVE_Y_ARB
:
59 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y_ARB
:
60 case GL_TEXTURE_CUBE_MAP_POSITIVE_Z_ARB
:
61 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z_ARB
:
62 return GL_TEXTURE_CUBE_MAP_ARB
;
70 * Determine which MSAA layout should be used by the MSAA surface being
71 * created, based on the chip generation and the surface type.
73 static enum intel_msaa_layout
74 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
, GLenum target
)
76 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
81 switch (_mesa_get_format_base_format(format
)) {
82 case GL_DEPTH_COMPONENT
:
83 case GL_STENCIL_INDEX
:
84 case GL_DEPTH_STENCIL
:
85 return INTEL_MSAA_LAYOUT_IMS
;
87 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
89 * This field must be set to 0 for all SINT MSRTs when all RT channels
92 * In practice this means that we have to disable MCS for all signed
93 * integer MSAA buffers. The alternative, to disable MCS only when one
94 * of the render target channels is disabled, is impractical because it
95 * would require converting between CMS and UMS MSAA layouts on the fly,
98 if (_mesa_get_format_datatype(format
) == GL_INT
) {
99 /* TODO: is this workaround needed for future chipsets? */
100 assert(brw
->gen
== 7);
101 return INTEL_MSAA_LAYOUT_UMS
;
103 return INTEL_MSAA_LAYOUT_CMS
;
110 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
111 * scaled-down bitfield representation of the color buffer which is capable of
112 * recording when blocks of the color buffer are equal to the clear value.
113 * This function returns the block size that will be used by the MCS buffer
114 * corresponding to a certain color miptree.
116 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
117 * beneath the "Fast Color Clear" bullet (p327):
119 * The following table describes the RT alignment
133 * This alignment has the following uses:
135 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
136 * buffer contains 128 blocks horizontally and 256 blocks vertically.
138 * - For figuring out alignment restrictions for a fast clear operation. Fast
139 * clear operations must always clear aligned multiples of 16 blocks
140 * horizontally and 32 blocks vertically.
142 * - For scaling down the coordinates sent through the render pipeline during
143 * a fast clear. X coordinates must be scaled down by 8 times the block
144 * width, and Y coordinates by 16 times the block height.
146 * - For scaling down the coordinates sent through the render pipeline during
147 * a "Render Target Resolve" operation. X coordinates must be scaled down
148 * by half the block width, and Y coordinates by half the block height.
151 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
152 struct intel_mipmap_tree
*mt
,
153 unsigned *width_px
, unsigned *height
)
155 switch (mt
->region
->tiling
) {
157 assert(!"Non-MSRT MCS requires X or Y tiling");
158 /* In release builds, fall through */
160 *width_px
= 32 / mt
->cpp
;
164 *width_px
= 64 / mt
->cpp
;
171 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
174 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
175 * beneath the "Fast Color Clear" bullet (p326):
177 * - Support is limited to tiled render targets.
178 * - Support is for non-mip-mapped and non-array surface types only.
180 * And then later, on p327:
182 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
186 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
187 struct intel_mipmap_tree
*mt
)
189 /* MCS support does not exist prior to Gen7 */
190 if (brw
->gen
< 7 || brw
->gen
>= 8)
193 /* MCS is only supported for color buffers */
194 switch (_mesa_get_format_base_format(mt
->format
)) {
195 case GL_DEPTH_COMPONENT
:
196 case GL_DEPTH_STENCIL
:
197 case GL_STENCIL_INDEX
:
201 if (mt
->region
->tiling
!= I915_TILING_X
&&
202 mt
->region
->tiling
!= I915_TILING_Y
)
204 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
206 if (mt
->first_level
!= 0 || mt
->last_level
!= 0)
208 if (mt
->physical_depth0
!= 1)
211 /* There's no point in using an MCS buffer if the surface isn't in a
214 if (!brw
->format_supported_as_render_target
[mt
->format
])
222 * @param for_bo Indicates that the caller is
223 * intel_miptree_create_for_bo(). If true, then do not create
226 struct intel_mipmap_tree
*
227 intel_miptree_create_layout(struct brw_context
*brw
,
238 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
242 DBG("%s target %s format %s level %d..%d <-- %p\n", __FUNCTION__
,
243 _mesa_lookup_enum_by_nr(target
),
244 _mesa_get_format_name(format
),
245 first_level
, last_level
, mt
);
247 mt
->target
= target_to_target(target
);
249 mt
->first_level
= first_level
;
250 mt
->last_level
= last_level
;
251 mt
->logical_width0
= width0
;
252 mt
->logical_height0
= height0
;
253 mt
->logical_depth0
= depth0
;
254 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
256 /* The cpp is bytes per (1, blockheight)-sized block for compressed
257 * textures. This is why you'll see divides by blockheight all over
260 _mesa_get_format_block_size(format
, &bw
, &bh
);
261 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
262 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
264 mt
->num_samples
= num_samples
;
265 mt
->compressed
= _mesa_is_format_compressed(format
);
266 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
269 if (num_samples
> 1) {
270 /* Adjust width/height/depth for MSAA */
271 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->target
);
272 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
273 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says:
275 * "Any of the other messages (sample*, LOD, load4) used with a
276 * (4x) multisampled surface will in-effect sample a surface with
277 * double the height and width as that indicated in the surface
278 * state. Each pixel position on the original-sized surface is
279 * replaced with a 2x2 of samples with the following arrangement:
284 * Thus, when sampling from a multisampled texture, it behaves as
285 * though the layout in memory for (x,y,sample) is:
287 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
288 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
290 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
291 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
293 * However, the actual layout of multisampled data in memory is:
295 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
296 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
298 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
299 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
301 * This pattern repeats for each 2x2 pixel block.
303 * As a result, when calculating the size of our 4-sample buffer for
304 * an odd width or height, we have to align before scaling up because
305 * sample 3 is in that bottom right 2x2 block.
307 switch (num_samples
) {
309 width0
= ALIGN(width0
, 2) * 2;
310 height0
= ALIGN(height0
, 2) * 2;
313 width0
= ALIGN(width0
, 2) * 4;
314 height0
= ALIGN(height0
, 2) * 2;
317 /* num_samples should already have been quantized to 0, 1, 4, or
323 /* Non-interleaved */
324 depth0
*= num_samples
;
328 /* array_spacing_lod0 is only used for non-IMS MSAA surfaces. TODO: can we
331 switch (mt
->msaa_layout
) {
332 case INTEL_MSAA_LAYOUT_NONE
:
333 case INTEL_MSAA_LAYOUT_IMS
:
334 mt
->array_spacing_lod0
= false;
336 case INTEL_MSAA_LAYOUT_UMS
:
337 case INTEL_MSAA_LAYOUT_CMS
:
338 mt
->array_spacing_lod0
= true;
342 if (target
== GL_TEXTURE_CUBE_MAP
) {
347 mt
->physical_width0
= width0
;
348 mt
->physical_height0
= height0
;
349 mt
->physical_depth0
= depth0
;
352 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
353 (brw
->must_use_separate_stencil
||
354 (brw
->has_separate_stencil
&& brw_is_hiz_depth_format(brw
, format
)))) {
355 mt
->stencil_mt
= intel_miptree_create(brw
,
365 INTEL_MIPTREE_TILING_ANY
);
366 if (!mt
->stencil_mt
) {
367 intel_miptree_release(&mt
);
371 /* Fix up the Z miptree format for how we're splitting out separate
372 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
374 if (mt
->format
== MESA_FORMAT_Z24_UNORM_S8_UINT
) {
375 mt
->format
= MESA_FORMAT_Z24_UNORM_X8_UINT
;
376 } else if (mt
->format
== MESA_FORMAT_Z32_FLOAT_S8X24_UINT
) {
377 mt
->format
= MESA_FORMAT_Z_FLOAT32
;
380 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
381 _mesa_get_format_name(mt
->format
));
385 brw_miptree_layout(brw
, mt
);
391 * \brief Helper function for intel_miptree_create().
394 intel_miptree_choose_tiling(struct brw_context
*brw
,
397 uint32_t num_samples
,
398 enum intel_miptree_tiling_mode requested
,
399 struct intel_mipmap_tree
*mt
)
401 if (format
== MESA_FORMAT_S_UINT8
) {
402 /* The stencil buffer is W tiled. However, we request from the kernel a
403 * non-tiled buffer because the GTT is incapable of W fencing.
405 return I915_TILING_NONE
;
408 /* Some usages may want only one type of tiling, like depth miptrees (Y
409 * tiled), or temporary BOs for uploading data once (linear).
412 case INTEL_MIPTREE_TILING_ANY
:
414 case INTEL_MIPTREE_TILING_Y
:
415 return I915_TILING_Y
;
416 case INTEL_MIPTREE_TILING_NONE
:
417 return I915_TILING_NONE
;
420 if (num_samples
> 1) {
421 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
424 * [DevSNB+]: For multi-sample render targets, this field must be
425 * 1. MSRTs can only be tiled.
427 * Our usual reason for preferring X tiling (fast blits using the
428 * blitting engine) doesn't apply to MSAA, since we'll generally be
429 * downsampling or upsampling when blitting between the MSAA buffer
430 * and another buffer, and the blitting engine doesn't support that.
431 * So use Y tiling, since it makes better use of the cache.
433 return I915_TILING_Y
;
436 GLenum base_format
= _mesa_get_format_base_format(format
);
437 if (base_format
== GL_DEPTH_COMPONENT
||
438 base_format
== GL_DEPTH_STENCIL_EXT
)
439 return I915_TILING_Y
;
441 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
443 /* If the width is much smaller than a tile, don't bother tiling. */
444 if (minimum_pitch
< 64)
445 return I915_TILING_NONE
;
447 if (ALIGN(minimum_pitch
, 512) >= 32768 ||
448 mt
->total_width
>= 32768 || mt
->total_height
>= 32768) {
449 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
450 mt
->total_width
, mt
->total_height
);
451 return I915_TILING_NONE
;
454 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
456 return I915_TILING_X
;
458 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
459 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
461 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
462 * all the way back to 965, but is explicitly permitted on Gen7.
464 if (brw
->gen
!= 7 && mt
->cpp
>= 16)
465 return I915_TILING_X
;
467 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
468 * messages), on p64, under the heading "Surface Vertical Alignment":
470 * This field must be set to VALIGN_4 for all tiled Y Render Target
473 * So if the surface is renderable and uses a vertical alignment of 2,
474 * force it to be X tiled. This is somewhat conservative (it's possible
475 * that the client won't ever render to this surface), but it's difficult
476 * to know that ahead of time. And besides, since we use a vertical
477 * alignment of 4 as often as we can, this shouldn't happen very often.
479 if (brw
->gen
== 7 && mt
->align_h
== 2 &&
480 brw
->format_supported_as_render_target
[format
]) {
481 return I915_TILING_X
;
484 return I915_TILING_Y
| I915_TILING_X
;
487 struct intel_mipmap_tree
*
488 intel_miptree_create(struct brw_context
*brw
,
496 bool expect_accelerated_upload
,
498 enum intel_miptree_tiling_mode requested_tiling
)
500 struct intel_mipmap_tree
*mt
;
501 mesa_format tex_format
= format
;
502 mesa_format etc_format
= MESA_FORMAT_NONE
;
503 GLuint total_width
, total_height
;
505 if (brw
->gen
< 8 && !brw
->is_baytrail
) {
507 case MESA_FORMAT_ETC1_RGB8
:
508 format
= MESA_FORMAT_R8G8B8X8_UNORM
;
510 case MESA_FORMAT_ETC2_RGB8
:
511 format
= MESA_FORMAT_R8G8B8X8_UNORM
;
513 case MESA_FORMAT_ETC2_SRGB8
:
514 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
515 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
516 format
= MESA_FORMAT_B8G8R8A8_SRGB
;
518 case MESA_FORMAT_ETC2_RGBA8_EAC
:
519 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
520 format
= MESA_FORMAT_R8G8B8A8_UNORM
;
522 case MESA_FORMAT_ETC2_R11_EAC
:
523 format
= MESA_FORMAT_R_UNORM16
;
525 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
526 format
= MESA_FORMAT_R_SNORM16
;
528 case MESA_FORMAT_ETC2_RG11_EAC
:
529 format
= MESA_FORMAT_R16G16_UNORM
;
531 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
532 format
= MESA_FORMAT_R16G16_SNORM
;
535 /* Non ETC1 / ETC2 format */
540 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
542 mt
= intel_miptree_create_layout(brw
, target
, format
,
543 first_level
, last_level
, width0
,
547 * pitch == 0 || height == 0 indicates the null texture
549 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
550 intel_miptree_release(&mt
);
554 total_width
= mt
->total_width
;
555 total_height
= mt
->total_height
;
557 if (format
== MESA_FORMAT_S_UINT8
) {
558 /* Align to size of W tile, 64x64. */
559 total_width
= ALIGN(total_width
, 64);
560 total_height
= ALIGN(total_height
, 64);
563 uint32_t tiling
= intel_miptree_choose_tiling(brw
, format
, width0
,
564 num_samples
, requested_tiling
,
566 bool y_or_x
= tiling
== (I915_TILING_Y
| I915_TILING_X
);
568 mt
->etc_format
= etc_format
;
569 mt
->region
= intel_region_alloc(brw
->intelScreen
,
570 y_or_x
? I915_TILING_Y
: tiling
,
574 expect_accelerated_upload
);
576 /* If the region is too large to fit in the aperture, we need to use the
577 * BLT engine to support it. The BLT paths can't currently handle Y-tiling,
578 * so we need to fall back to X.
580 if (y_or_x
&& mt
->region
->bo
->size
>= brw
->max_gtt_map_object_size
) {
581 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
582 mt
->total_width
, mt
->total_height
);
583 intel_region_release(&mt
->region
);
585 mt
->region
= intel_region_alloc(brw
->intelScreen
,
590 expect_accelerated_upload
);
596 intel_miptree_release(&mt
);
601 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
602 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
603 intel_miptree_release(&mt
);
608 /* If this miptree is capable of supporting fast color clears, set
609 * fast_clear_state appropriately to ensure that fast clears will occur.
610 * Allocation of the MCS miptree will be deferred until the first fast
611 * clear actually occurs.
613 if (intel_is_non_msrt_mcs_buffer_supported(brw
, mt
))
614 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
619 struct intel_mipmap_tree
*
620 intel_miptree_create_for_bo(struct brw_context
*brw
,
629 struct intel_mipmap_tree
*mt
;
631 struct intel_region
*region
= calloc(1, sizeof(*region
));
635 /* Nothing will be able to use this miptree with the BO if the offset isn't
638 if (tiling
!= I915_TILING_NONE
)
639 assert(offset
% 4096 == 0);
641 /* miptrees can't handle negative pitch. If you need flipping of images,
642 * that's outside of the scope of the mt.
646 mt
= intel_miptree_create_layout(brw
, GL_TEXTURE_2D
, format
,
649 true, 0 /* num_samples */);
655 region
->cpp
= mt
->cpp
;
656 region
->width
= width
;
657 region
->height
= height
;
658 region
->pitch
= pitch
;
659 region
->refcount
= 1;
660 drm_intel_bo_reference(bo
);
662 region
->tiling
= tiling
;
671 * For a singlesample image buffer, this simply wraps the given region with a miptree.
673 * For a multisample image buffer, this wraps the given region with
674 * a singlesample miptree, then creates a multisample miptree into which the
675 * singlesample miptree is embedded as a child.
678 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
679 struct intel_renderbuffer
*irb
,
680 struct intel_region
*region
)
682 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
683 struct intel_mipmap_tree
*multisample_mt
= NULL
;
684 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
685 mesa_format format
= rb
->Format
;
686 int num_samples
= rb
->NumSamples
;
688 intel_miptree_release(&irb
->mt
);
690 /* Only the front and back buffers, which are color buffers, are allocated
691 * through the image loader.
693 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
694 _mesa_get_format_base_format(format
) == GL_RGBA
);
696 singlesample_mt
= intel_miptree_create_for_bo(intel
,
704 if (!singlesample_mt
)
706 singlesample_mt
->region
->name
= region
->name
;
708 /* If this miptree is capable of supporting fast color clears, set
709 * mcs_state appropriately to ensure that fast clears will occur.
710 * Allocation of the MCS miptree will be deferred until the first fast
711 * clear actually occurs.
713 if (intel_is_non_msrt_mcs_buffer_supported(intel
, singlesample_mt
))
714 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
716 if (num_samples
== 0) {
717 irb
->mt
= singlesample_mt
;
721 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
726 if (!multisample_mt
) {
727 intel_miptree_release(&singlesample_mt
);
731 irb
->need_downsample
= false;
732 irb
->mt
= multisample_mt
;
733 irb
->singlesample_mt
= singlesample_mt
;
736 struct intel_mipmap_tree
*
737 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
741 uint32_t num_samples
)
743 struct intel_mipmap_tree
*mt
;
746 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
748 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
749 width
, height
, depth
, true, num_samples
,
750 INTEL_MIPTREE_TILING_ANY
);
754 if (brw_is_hiz_depth_format(brw
, format
)) {
755 ok
= intel_miptree_alloc_hiz(brw
, mt
);
763 intel_miptree_release(&mt
);
768 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
769 struct intel_mipmap_tree
*src
)
774 intel_miptree_release(dst
);
778 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
786 intel_miptree_release(struct intel_mipmap_tree
**mt
)
791 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
792 if (--(*mt
)->refcount
<= 0) {
795 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
797 intel_region_release(&((*mt
)->region
));
798 intel_miptree_release(&(*mt
)->stencil_mt
);
799 intel_miptree_release(&(*mt
)->hiz_mt
);
800 intel_miptree_release(&(*mt
)->mcs_mt
);
801 intel_resolve_map_clear(&(*mt
)->hiz_map
);
803 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
804 free((*mt
)->level
[i
].slice
);
813 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
814 int *width
, int *height
, int *depth
)
816 switch (image
->TexObject
->Target
) {
817 case GL_TEXTURE_1D_ARRAY
:
818 *width
= image
->Width
;
820 *depth
= image
->Height
;
823 *width
= image
->Width
;
824 *height
= image
->Height
;
825 *depth
= image
->Depth
;
831 * Can the image be pulled into a unified mipmap tree? This mirrors
832 * the completeness test in a lot of ways.
834 * Not sure whether I want to pass gl_texture_image here.
837 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
838 struct gl_texture_image
*image
)
840 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
841 GLuint level
= intelImage
->base
.Base
.Level
;
842 int width
, height
, depth
;
844 /* glTexImage* choose the texture object based on the target passed in, and
845 * objects can't change targets over their lifetimes, so this should be
848 assert(target_to_target(image
->TexObject
->Target
) == mt
->target
);
850 mesa_format mt_format
= mt
->format
;
851 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
852 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
853 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
854 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
855 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
856 mt_format
= mt
->etc_format
;
858 if (image
->TexFormat
!= mt_format
)
861 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
863 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
866 /* Test image dimensions against the base level image adjusted for
867 * minification. This will also catch images not present in the
868 * tree, changed targets, etc.
870 if (width
!= minify(mt
->logical_width0
, level
) ||
871 height
!= minify(mt
->logical_height0
, level
) ||
872 depth
!= mt
->level
[level
].depth
) {
876 if (image
->NumSamples
!= mt
->num_samples
)
884 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
886 GLuint x
, GLuint y
, GLuint d
)
888 mt
->level
[level
].depth
= d
;
889 mt
->level
[level
].level_x
= x
;
890 mt
->level
[level
].level_y
= y
;
892 DBG("%s level %d, depth %d, offset %d,%d\n", __FUNCTION__
,
895 assert(mt
->level
[level
].slice
== NULL
);
897 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
898 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
899 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
904 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
905 GLuint level
, GLuint img
,
908 if (img
== 0 && level
== 0)
909 assert(x
== 0 && y
== 0);
911 assert(img
< mt
->level
[level
].depth
);
913 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
914 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
916 DBG("%s level %d img %d pos %d,%d\n",
917 __FUNCTION__
, level
, img
,
918 mt
->level
[level
].slice
[img
].x_offset
,
919 mt
->level
[level
].slice
[img
].y_offset
);
923 intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt
,
924 GLuint level
, GLuint slice
,
925 GLuint
*x
, GLuint
*y
)
927 assert(slice
< mt
->level
[level
].depth
);
929 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
930 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
934 * Rendering with tiled buffers requires that the base address of the buffer
935 * be aligned to a page boundary. For renderbuffers, and sometimes with
936 * textures, we may want the surface to point at a texture image level that
937 * isn't at a page boundary.
939 * This function returns an appropriately-aligned base offset
940 * according to the tiling restrictions, plus any required x/y offset
944 intel_miptree_get_tile_offsets(struct intel_mipmap_tree
*mt
,
945 GLuint level
, GLuint slice
,
949 struct intel_region
*region
= mt
->region
;
951 uint32_t mask_x
, mask_y
;
953 intel_region_get_tile_masks(region
, &mask_x
, &mask_y
, false);
954 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
956 *tile_x
= x
& mask_x
;
957 *tile_y
= y
& mask_y
;
959 return intel_region_get_aligned_offset(region
, x
& ~mask_x
, y
& ~mask_y
,
964 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
965 struct intel_mipmap_tree
*dst_mt
,
966 struct intel_mipmap_tree
*src_mt
,
973 int src_stride
, dst_stride
;
974 int cpp
= dst_mt
->cpp
;
976 intel_miptree_map(brw
, src_mt
,
980 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
983 intel_miptree_map(brw
, dst_mt
,
987 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
991 DBG("sw blit %s mt %p %p/%d -> %s mt %p %p/%d (%dx%d)\n",
992 _mesa_get_format_name(src_mt
->format
),
993 src_mt
, src
, src_stride
,
994 _mesa_get_format_name(dst_mt
->format
),
995 dst_mt
, dst
, dst_stride
,
998 int row_size
= cpp
* width
;
999 if (src_stride
== row_size
&&
1000 dst_stride
== row_size
) {
1001 memcpy(dst
, src
, row_size
* height
);
1003 for (int i
= 0; i
< height
; i
++) {
1004 memcpy(dst
, src
, row_size
);
1010 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1011 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1013 /* Don't forget to copy the stencil data over, too. We could have skipped
1014 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1015 * shuffling the two data sources in/out of temporary storage instead of
1016 * the direct mapping we get this way.
1018 if (dst_mt
->stencil_mt
) {
1019 assert(src_mt
->stencil_mt
);
1020 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1021 level
, slice
, width
, height
);
1026 intel_miptree_copy_slice(struct brw_context
*brw
,
1027 struct intel_mipmap_tree
*dst_mt
,
1028 struct intel_mipmap_tree
*src_mt
,
1034 mesa_format format
= src_mt
->format
;
1035 uint32_t width
= minify(src_mt
->physical_width0
, level
);
1036 uint32_t height
= minify(src_mt
->physical_height0
, level
);
1044 assert(depth
< src_mt
->level
[level
].depth
);
1045 assert(src_mt
->format
== dst_mt
->format
);
1047 if (dst_mt
->compressed
) {
1048 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1049 width
= ALIGN(width
, dst_mt
->align_w
);
1052 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1053 * below won't apply since we can't do the depth's Y tiling or the
1054 * stencil's W tiling in the blitter.
1056 if (src_mt
->stencil_mt
) {
1057 intel_miptree_copy_slice_sw(brw
,
1064 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1065 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1066 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1068 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1069 _mesa_get_format_name(src_mt
->format
),
1070 src_mt
, src_x
, src_y
, src_mt
->region
->pitch
,
1071 _mesa_get_format_name(dst_mt
->format
),
1072 dst_mt
, dst_x
, dst_y
, dst_mt
->region
->pitch
,
1075 if (!intel_miptree_blit(brw
,
1076 src_mt
, level
, slice
, 0, 0, false,
1077 dst_mt
, level
, slice
, 0, 0, false,
1078 width
, height
, GL_COPY
)) {
1079 perf_debug("miptree validate blit for %s failed\n",
1080 _mesa_get_format_name(format
));
1082 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1088 * Copies the image's current data to the given miptree, and associates that
1089 * miptree with the image.
1091 * If \c invalidate is true, then the actual image data does not need to be
1092 * copied, but the image still needs to be associated to the new miptree (this
1093 * is set to true if we're about to clear the image).
1096 intel_miptree_copy_teximage(struct brw_context
*brw
,
1097 struct intel_texture_image
*intelImage
,
1098 struct intel_mipmap_tree
*dst_mt
,
1101 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1102 struct intel_texture_object
*intel_obj
=
1103 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1104 int level
= intelImage
->base
.Base
.Level
;
1105 int face
= intelImage
->base
.Base
.Face
;
1106 GLuint depth
= intelImage
->base
.Base
.Depth
;
1109 for (int slice
= 0; slice
< depth
; slice
++) {
1110 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1114 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1115 intel_obj
->needs_validate
= true;
1119 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1120 struct intel_mipmap_tree
*mt
,
1123 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1124 assert(mt
->mcs_mt
== NULL
);
1126 /* Choose the correct format for the MCS buffer. All that really matters
1127 * is that we allocate the right buffer size, since we'll always be
1128 * accessing this miptree using MCS-specific hardware mechanisms, which
1129 * infer the correct format based on num_samples.
1132 switch (num_samples
) {
1134 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1137 format
= MESA_FORMAT_R_UNORM8
;
1140 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1141 * for each sample, plus 8 padding bits).
1143 format
= MESA_FORMAT_R_UINT32
;
1146 assert(!"Unrecognized sample count in intel_miptree_alloc_mcs");
1150 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1152 * "The MCS surface must be stored as Tile Y."
1154 mt
->mcs_mt
= intel_miptree_create(brw
,
1160 mt
->logical_height0
,
1163 0 /* num_samples */,
1164 INTEL_MIPTREE_TILING_Y
);
1166 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1168 * When MCS buffer is enabled and bound to MSRT, it is required that it
1169 * is cleared prior to any rendering.
1171 * Since we don't use the MCS buffer for any purpose other than rendering,
1172 * it makes sense to just clear it immediately upon allocation.
1174 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1176 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1177 memset(data
, 0xff, mt
->mcs_mt
->region
->bo
->size
);
1178 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1179 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1186 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1187 struct intel_mipmap_tree
*mt
)
1189 assert(mt
->mcs_mt
== NULL
);
1191 /* The format of the MCS buffer is opaque to the driver; all that matters
1192 * is that we get its size and pitch right. We'll pretend that the format
1193 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1194 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1195 * the block width and then a further factor of 4. Since an MCS tile
1196 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1197 * we'll need to scale the height down by the block height and then a
1198 * further factor of 8.
1200 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1201 unsigned block_width_px
;
1202 unsigned block_height
;
1203 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1204 unsigned width_divisor
= block_width_px
* 4;
1205 unsigned height_divisor
= block_height
* 8;
1206 unsigned mcs_width
=
1207 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1208 unsigned mcs_height
=
1209 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1210 assert(mt
->logical_depth0
== 1);
1211 mt
->mcs_mt
= intel_miptree_create(brw
,
1220 0 /* num_samples */,
1221 INTEL_MIPTREE_TILING_Y
);
1228 * Helper for intel_miptree_alloc_hiz() that sets
1229 * \c mt->level[level].slice[layer].has_hiz. Return true if and only if
1230 * \c has_hiz was set.
1233 intel_miptree_slice_enable_hiz(struct brw_context
*brw
,
1234 struct intel_mipmap_tree
*mt
,
1240 if (brw
->is_haswell
) {
1241 uint32_t width
= minify(mt
->physical_width0
, level
);
1242 uint32_t height
= minify(mt
->physical_height0
, level
);
1244 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1245 * and the height is 4 aligned. This allows our HiZ support
1246 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1247 * we can grow the width & height to allow the HiZ op to
1248 * force the proper size alignments.
1250 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1255 mt
->level
[level
].slice
[layer
].has_hiz
= true;
1262 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1263 struct intel_mipmap_tree
*mt
)
1265 assert(mt
->hiz_mt
== NULL
);
1266 mt
->hiz_mt
= intel_miptree_create(brw
,
1272 mt
->logical_height0
,
1276 INTEL_MIPTREE_TILING_ANY
);
1281 /* Mark that all slices need a HiZ resolve. */
1282 struct intel_resolve_map
*head
= &mt
->hiz_map
;
1283 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1284 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1285 if (!intel_miptree_slice_enable_hiz(brw
, mt
, level
, layer
))
1288 head
->next
= malloc(sizeof(*head
->next
));
1289 head
->next
->prev
= head
;
1290 head
->next
->next
= NULL
;
1293 head
->level
= level
;
1294 head
->layer
= layer
;
1295 head
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1303 * Does the miptree slice have hiz enabled?
1306 intel_miptree_slice_has_hiz(struct intel_mipmap_tree
*mt
,
1310 intel_miptree_check_level_layer(mt
, level
, layer
);
1311 return mt
->level
[level
].slice
[layer
].has_hiz
;
1315 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1319 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1322 intel_resolve_map_set(&mt
->hiz_map
,
1323 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1328 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1332 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1335 intel_resolve_map_set(&mt
->hiz_map
,
1336 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1340 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1344 uint32_t end_layer
= mt
->level
[level
].depth
;
1346 for (layer
= 0; layer
< end_layer
; layer
++) {
1347 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1352 intel_miptree_slice_resolve(struct brw_context
*brw
,
1353 struct intel_mipmap_tree
*mt
,
1356 enum gen6_hiz_op need
)
1358 intel_miptree_check_level_layer(mt
, level
, layer
);
1360 struct intel_resolve_map
*item
=
1361 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1363 if (!item
|| item
->need
!= need
)
1366 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1367 intel_resolve_map_remove(item
);
1372 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1373 struct intel_mipmap_tree
*mt
,
1377 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1378 GEN6_HIZ_OP_HIZ_RESOLVE
);
1382 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1383 struct intel_mipmap_tree
*mt
,
1387 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1388 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1392 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1393 struct intel_mipmap_tree
*mt
,
1394 enum gen6_hiz_op need
)
1396 bool did_resolve
= false;
1397 struct intel_resolve_map
*i
, *next
;
1399 for (i
= mt
->hiz_map
.next
; i
; i
= next
) {
1401 if (i
->need
!= need
)
1404 intel_hiz_exec(brw
, mt
, i
->level
, i
->layer
, need
);
1405 intel_resolve_map_remove(i
);
1413 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1414 struct intel_mipmap_tree
*mt
)
1416 return intel_miptree_all_slices_resolve(brw
, mt
,
1417 GEN6_HIZ_OP_HIZ_RESOLVE
);
1421 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1422 struct intel_mipmap_tree
*mt
)
1424 return intel_miptree_all_slices_resolve(brw
, mt
,
1425 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1430 intel_miptree_resolve_color(struct brw_context
*brw
,
1431 struct intel_mipmap_tree
*mt
)
1433 switch (mt
->fast_clear_state
) {
1434 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1435 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1436 /* No resolve needed */
1438 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1439 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1440 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1441 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1442 brw_blorp_resolve_color(brw
, mt
);
1449 * Make it possible to share the region backing the given miptree with another
1450 * process or another miptree.
1452 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1453 * then discard the MCS buffer, if present. We also set the fast_clear_state
1454 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1455 * allocated in the future.
1458 intel_miptree_make_shareable(struct brw_context
*brw
,
1459 struct intel_mipmap_tree
*mt
)
1461 /* MCS buffers are also used for multisample buffers, but we can't resolve
1462 * away a multisample MCS buffer because it's an integral part of how the
1463 * pixel data is stored. Fortunately this code path should never be
1464 * reached for multisample buffers.
1466 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1469 intel_miptree_resolve_color(brw
, mt
);
1470 intel_miptree_release(&mt
->mcs_mt
);
1471 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
1477 * \brief Get pointer offset into stencil buffer.
1479 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1480 * must decode the tile's layout in software.
1483 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1485 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1487 * Even though the returned offset is always positive, the return type is
1489 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1490 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1493 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1495 uint32_t tile_size
= 4096;
1496 uint32_t tile_width
= 64;
1497 uint32_t tile_height
= 64;
1498 uint32_t row_size
= 64 * stride
;
1500 uint32_t tile_x
= x
/ tile_width
;
1501 uint32_t tile_y
= y
/ tile_height
;
1503 /* The byte's address relative to the tile's base addres. */
1504 uint32_t byte_x
= x
% tile_width
;
1505 uint32_t byte_y
= y
% tile_height
;
1507 uintptr_t u
= tile_y
* row_size
1508 + tile_x
* tile_size
1509 + 512 * (byte_x
/ 8)
1511 + 32 * ((byte_y
/ 4) % 2)
1512 + 16 * ((byte_x
/ 4) % 2)
1513 + 8 * ((byte_y
/ 2) % 2)
1514 + 4 * ((byte_x
/ 2) % 2)
1519 /* adjust for bit6 swizzling */
1520 if (((byte_x
/ 8) % 2) == 1) {
1521 if (((byte_y
/ 8) % 2) == 0) {
1533 intel_miptree_updownsample(struct brw_context
*brw
,
1534 struct intel_mipmap_tree
*src
,
1535 struct intel_mipmap_tree
*dst
)
1537 brw_blorp_blit_miptrees(brw
,
1538 src
, 0 /* level */, 0 /* layer */,
1539 dst
, 0 /* level */, 0 /* layer */,
1541 src
->logical_width0
, src
->logical_height0
,
1543 dst
->logical_width0
, dst
->logical_height0
,
1544 GL_NEAREST
, false, false /*mirror x, y*/);
1546 if (src
->stencil_mt
) {
1547 brw_blorp_blit_miptrees(brw
,
1548 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1549 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1551 src
->logical_width0
, src
->logical_height0
,
1553 dst
->logical_width0
, dst
->logical_height0
,
1554 GL_NEAREST
, false, false /*mirror x, y*/);
1559 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
1561 /* CPU accesses to color buffers don't understand fast color clears, so
1562 * resolve any pending fast color clears before we map.
1564 intel_miptree_resolve_color(brw
, mt
);
1566 drm_intel_bo
*bo
= mt
->region
->bo
;
1568 intel_batchbuffer_flush(brw
);
1570 if (mt
->region
->tiling
!= I915_TILING_NONE
)
1571 brw_bo_map_gtt(brw
, bo
, "miptree");
1573 brw_bo_map(brw
, bo
, true, "miptree");
1579 intel_miptree_unmap_raw(struct brw_context
*brw
,
1580 struct intel_mipmap_tree
*mt
)
1582 drm_intel_bo_unmap(mt
->region
->bo
);
1586 intel_miptree_map_gtt(struct brw_context
*brw
,
1587 struct intel_mipmap_tree
*mt
,
1588 struct intel_miptree_map
*map
,
1589 unsigned int level
, unsigned int slice
)
1591 unsigned int bw
, bh
;
1593 unsigned int image_x
, image_y
;
1597 /* For compressed formats, the stride is the number of bytes per
1598 * row of blocks. intel_miptree_get_image_offset() already does
1601 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1602 assert(y
% bh
== 0);
1605 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
1610 /* Note that in the case of cube maps, the caller must have passed the
1611 * slice number referencing the face.
1613 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1617 map
->stride
= mt
->region
->pitch
;
1618 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1621 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1622 map
->x
, map
->y
, map
->w
, map
->h
,
1623 mt
, _mesa_get_format_name(mt
->format
),
1624 x
, y
, map
->ptr
, map
->stride
);
1628 intel_miptree_unmap_gtt(struct brw_context
*brw
,
1629 struct intel_mipmap_tree
*mt
,
1630 struct intel_miptree_map
*map
,
1634 intel_miptree_unmap_raw(brw
, mt
);
1638 intel_miptree_map_blit(struct brw_context
*brw
,
1639 struct intel_mipmap_tree
*mt
,
1640 struct intel_miptree_map
*map
,
1641 unsigned int level
, unsigned int slice
)
1643 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
1647 INTEL_MIPTREE_TILING_NONE
);
1649 fprintf(stderr
, "Failed to allocate blit temporary\n");
1652 map
->stride
= map
->mt
->region
->pitch
;
1654 if (!intel_miptree_blit(brw
,
1656 map
->x
, map
->y
, false,
1659 map
->w
, map
->h
, GL_COPY
)) {
1660 fprintf(stderr
, "Failed to blit\n");
1664 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
1666 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1667 map
->x
, map
->y
, map
->w
, map
->h
,
1668 mt
, _mesa_get_format_name(mt
->format
),
1669 level
, slice
, map
->ptr
, map
->stride
);
1674 intel_miptree_release(&map
->mt
);
1680 intel_miptree_unmap_blit(struct brw_context
*brw
,
1681 struct intel_mipmap_tree
*mt
,
1682 struct intel_miptree_map
*map
,
1686 struct gl_context
*ctx
= &brw
->ctx
;
1688 intel_miptree_unmap_raw(brw
, map
->mt
);
1690 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1691 bool ok
= intel_miptree_blit(brw
,
1695 map
->x
, map
->y
, false,
1696 map
->w
, map
->h
, GL_COPY
);
1697 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
1700 intel_miptree_release(&map
->mt
);
1705 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
1708 intel_miptree_map_movntdqa(struct brw_context
*brw
,
1709 struct intel_mipmap_tree
*mt
,
1710 struct intel_miptree_map
*map
,
1711 unsigned int level
, unsigned int slice
)
1713 assert(map
->mode
& GL_MAP_READ_BIT
);
1714 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
1716 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1717 map
->x
, map
->y
, map
->w
, map
->h
,
1718 mt
, _mesa_get_format_name(mt
->format
),
1719 level
, slice
, map
->ptr
, map
->stride
);
1721 /* Map the original image */
1724 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1728 void *src
= intel_miptree_map_raw(brw
, mt
);
1731 src
+= image_y
* mt
->region
->pitch
;
1732 src
+= image_x
* mt
->region
->cpp
;
1734 /* Due to the pixel offsets for the particular image being mapped, our
1735 * src pointer may not be 16-byte aligned. However, if the pitch is
1736 * divisible by 16, then the amount by which it's misaligned will remain
1737 * consistent from row to row.
1739 assert((mt
->region
->pitch
% 16) == 0);
1740 const int misalignment
= ((uintptr_t) src
) & 15;
1742 /* Create an untiled temporary buffer for the mapping. */
1743 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
1745 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
1747 map
->buffer
= malloc(map
->stride
* map
->h
);
1748 /* Offset the destination so it has the same misalignment as src. */
1749 map
->ptr
= map
->buffer
+ misalignment
;
1751 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
1753 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1754 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
1755 void *src_ptr
= src
+ y
* mt
->region
->pitch
;
1757 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
1760 intel_miptree_unmap_raw(brw
, mt
);
1764 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
1765 struct intel_mipmap_tree
*mt
,
1766 struct intel_miptree_map
*map
,
1777 intel_miptree_map_s8(struct brw_context
*brw
,
1778 struct intel_mipmap_tree
*mt
,
1779 struct intel_miptree_map
*map
,
1780 unsigned int level
, unsigned int slice
)
1782 map
->stride
= map
->w
;
1783 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1787 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1788 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1789 * invalidate is set, since we'll be writing the whole rectangle from our
1790 * temporary buffer back out.
1792 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1793 uint8_t *untiled_s8_map
= map
->ptr
;
1794 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1795 unsigned int image_x
, image_y
;
1797 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1799 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1800 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1801 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1802 x
+ image_x
+ map
->x
,
1803 y
+ image_y
+ map
->y
,
1804 brw
->has_swizzling
);
1805 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
1809 intel_miptree_unmap_raw(brw
, mt
);
1811 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
1812 map
->x
, map
->y
, map
->w
, map
->h
,
1813 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
1815 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1816 map
->x
, map
->y
, map
->w
, map
->h
,
1817 mt
, map
->ptr
, map
->stride
);
1822 intel_miptree_unmap_s8(struct brw_context
*brw
,
1823 struct intel_mipmap_tree
*mt
,
1824 struct intel_miptree_map
*map
,
1828 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1829 unsigned int image_x
, image_y
;
1830 uint8_t *untiled_s8_map
= map
->ptr
;
1831 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1833 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1835 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1836 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1837 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1840 brw
->has_swizzling
);
1841 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
1845 intel_miptree_unmap_raw(brw
, mt
);
1852 intel_miptree_map_etc(struct brw_context
*brw
,
1853 struct intel_mipmap_tree
*mt
,
1854 struct intel_miptree_map
*map
,
1858 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
1859 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
1860 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
1863 assert(map
->mode
& GL_MAP_WRITE_BIT
);
1864 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
1866 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
1867 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
1868 map
->w
, map
->h
, 1));
1869 map
->ptr
= map
->buffer
;
1873 intel_miptree_unmap_etc(struct brw_context
*brw
,
1874 struct intel_mipmap_tree
*mt
,
1875 struct intel_miptree_map
*map
,
1881 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1886 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
1887 + image_y
* mt
->region
->pitch
1888 + image_x
* mt
->region
->cpp
;
1890 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
1891 _mesa_etc1_unpack_rgba8888(dst
, mt
->region
->pitch
,
1892 map
->ptr
, map
->stride
,
1895 _mesa_unpack_etc2_format(dst
, mt
->region
->pitch
,
1896 map
->ptr
, map
->stride
,
1897 map
->w
, map
->h
, mt
->etc_format
);
1899 intel_miptree_unmap_raw(brw
, mt
);
1904 * Mapping function for packed depth/stencil miptrees backed by real separate
1905 * miptrees for depth and stencil.
1907 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
1908 * separate from the depth buffer. Yet at the GL API level, we have to expose
1909 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
1910 * be able to map that memory for texture storage and glReadPixels-type
1911 * operations. We give Mesa core that access by mallocing a temporary and
1912 * copying the data between the actual backing store and the temporary.
1915 intel_miptree_map_depthstencil(struct brw_context
*brw
,
1916 struct intel_mipmap_tree
*mt
,
1917 struct intel_miptree_map
*map
,
1918 unsigned int level
, unsigned int slice
)
1920 struct intel_mipmap_tree
*z_mt
= mt
;
1921 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
1922 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
1923 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
1925 map
->stride
= map
->w
* packed_bpp
;
1926 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1930 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1931 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1932 * invalidate is set, since we'll be writing the whole rectangle from our
1933 * temporary buffer back out.
1935 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1936 uint32_t *packed_map
= map
->ptr
;
1937 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
1938 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
1939 unsigned int s_image_x
, s_image_y
;
1940 unsigned int z_image_x
, z_image_y
;
1942 intel_miptree_get_image_offset(s_mt
, level
, slice
,
1943 &s_image_x
, &s_image_y
);
1944 intel_miptree_get_image_offset(z_mt
, level
, slice
,
1945 &z_image_x
, &z_image_y
);
1947 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1948 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1949 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
1950 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
1953 brw
->has_swizzling
);
1954 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
1955 (z_mt
->region
->pitch
/ 4) +
1956 (map_x
+ z_image_x
));
1957 uint8_t s
= s_map
[s_offset
];
1958 uint32_t z
= z_map
[z_offset
];
1960 if (map_z32f_x24s8
) {
1961 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
1962 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
1964 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
1969 intel_miptree_unmap_raw(brw
, s_mt
);
1970 intel_miptree_unmap_raw(brw
, z_mt
);
1972 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
1974 map
->x
, map
->y
, map
->w
, map
->h
,
1975 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
1976 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
1977 map
->ptr
, map
->stride
);
1979 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1980 map
->x
, map
->y
, map
->w
, map
->h
,
1981 mt
, map
->ptr
, map
->stride
);
1986 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
1987 struct intel_mipmap_tree
*mt
,
1988 struct intel_miptree_map
*map
,
1992 struct intel_mipmap_tree
*z_mt
= mt
;
1993 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
1994 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
1996 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1997 uint32_t *packed_map
= map
->ptr
;
1998 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
1999 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2000 unsigned int s_image_x
, s_image_y
;
2001 unsigned int z_image_x
, z_image_y
;
2003 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2004 &s_image_x
, &s_image_y
);
2005 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2006 &z_image_x
, &z_image_y
);
2008 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2009 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2010 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
2011 x
+ s_image_x
+ map
->x
,
2012 y
+ s_image_y
+ map
->y
,
2013 brw
->has_swizzling
);
2014 ptrdiff_t z_offset
= ((y
+ z_image_y
) *
2015 (z_mt
->region
->pitch
/ 4) +
2018 if (map_z32f_x24s8
) {
2019 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2020 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2022 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2023 s_map
[s_offset
] = packed
>> 24;
2024 z_map
[z_offset
] = packed
;
2029 intel_miptree_unmap_raw(brw
, s_mt
);
2030 intel_miptree_unmap_raw(brw
, z_mt
);
2032 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2034 map
->x
, map
->y
, map
->w
, map
->h
,
2035 z_mt
, _mesa_get_format_name(z_mt
->format
),
2036 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2037 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2038 map
->ptr
, map
->stride
);
2045 * Create and attach a map to the miptree at (level, slice). Return the
2048 static struct intel_miptree_map
*
2049 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2058 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2063 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2064 mt
->level
[level
].slice
[slice
].map
= map
;
2076 * Release the map at (level, slice).
2079 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2083 struct intel_miptree_map
**map
;
2085 map
= &mt
->level
[level
].slice
[slice
].map
;
2091 can_blit_slice(struct intel_mipmap_tree
*mt
,
2092 unsigned int level
, unsigned int slice
)
2096 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2097 if (image_x
>= 32768 || image_y
>= 32768)
2100 if (mt
->region
->pitch
>= 32768)
2107 intel_miptree_map(struct brw_context
*brw
,
2108 struct intel_mipmap_tree
*mt
,
2119 struct intel_miptree_map
*map
;
2121 assert(mt
->num_samples
<= 1);
2123 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2130 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2131 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2132 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2135 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2136 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2137 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2138 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2139 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2140 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2141 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2143 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2144 else if (brw
->has_llc
&&
2145 !(mode
& GL_MAP_WRITE_BIT
) &&
2147 (mt
->region
->tiling
== I915_TILING_X
||
2148 (brw
->gen
>= 6 && mt
->region
->tiling
== I915_TILING_Y
)) &&
2149 can_blit_slice(mt
, level
, slice
)) {
2150 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2151 } else if (mt
->region
->tiling
!= I915_TILING_NONE
&&
2152 mt
->region
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2153 assert(can_blit_slice(mt
, level
, slice
));
2154 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2156 } else if (!(mode
& GL_MAP_WRITE_BIT
) && !mt
->compressed
) {
2157 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2160 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2163 *out_ptr
= map
->ptr
;
2164 *out_stride
= map
->stride
;
2166 if (map
->ptr
== NULL
)
2167 intel_miptree_release_map(mt
, level
, slice
);
2171 intel_miptree_unmap(struct brw_context
*brw
,
2172 struct intel_mipmap_tree
*mt
,
2176 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2178 assert(mt
->num_samples
<= 1);
2183 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
2184 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2186 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2187 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2188 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2189 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2190 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2191 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2192 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2193 } else if (map
->mt
) {
2194 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2196 } else if (map
->buffer
) {
2197 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2200 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2203 intel_miptree_release_map(mt
, level
, slice
);