2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_tex.h"
32 #include "intel_blit.h"
33 #include "intel_fbo.h"
35 #include "brw_blorp.h"
36 #include "brw_context.h"
37 #include "brw_state.h"
39 #include "main/enums.h"
40 #include "main/fbobject.h"
41 #include "main/formats.h"
42 #include "main/glformats.h"
43 #include "main/texcompress_etc.h"
44 #include "main/teximage.h"
45 #include "main/streaming-load-memcpy.h"
46 #include "x86/common_x86_asm.h"
48 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
50 static void *intel_miptree_map_raw(struct brw_context
*brw
,
51 struct intel_mipmap_tree
*mt
,
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 enum intel_aux_disable aux_disable
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (aux_disable
& INTEL_AUX_DISABLE_MCS
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
105 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
108 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
109 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
111 * - Support is limited to tiled render targets.
113 * Gen9 changes the restriction to Y-tile only.
116 return tiling
== I915_TILING_Y
;
117 else if (brw
->gen
>= 7)
118 return tiling
!= I915_TILING_NONE
;
124 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
125 * can be used. This doesn't (and should not) inspect any of the properties of
128 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
129 * beneath the "Fast Color Clear" bullet (p326):
131 * - Support is for non-mip-mapped and non-array surface types only.
133 * And then later, on p327:
135 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
138 * From the Skylake documentation, it is made clear that X-tiling is no longer
141 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
145 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
146 const struct intel_mipmap_tree
*mt
)
148 /* MCS support does not exist prior to Gen7 */
152 if (mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
)
155 /* This function applies only to non-multisampled render targets. */
156 if (mt
->num_samples
> 1)
159 /* MCS is only supported for color buffers */
160 switch (_mesa_get_format_base_format(mt
->format
)) {
161 case GL_DEPTH_COMPONENT
:
162 case GL_DEPTH_STENCIL
:
163 case GL_STENCIL_INDEX
:
167 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
170 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
171 const bool arrayed
= mt
->physical_depth0
!= 1;
174 /* Multisample surfaces with the CMS layout are not layered surfaces,
175 * yet still have physical_depth0 > 1. Assert that we don't
176 * accidentally reject a multisampled surface here. We should have
177 * rejected it earlier by explicitly checking the sample count.
179 assert(mt
->num_samples
<= 1);
182 /* Handle the hardware restrictions...
184 * All GENs have the following restriction: "MCS buffer for non-MSRT is
185 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
187 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
188 * Non-MultiSampler Render Target Restrictions) Support is for
189 * non-mip-mapped and non-array surface types only.
191 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
192 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
193 * surfaces are supported with MCS buffer layout with these alignments in
194 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
196 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
197 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
198 * surfaces are supported with MCS buffer layout with these alignments in
199 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
201 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
204 /* There's no point in using an MCS buffer if the surface isn't in a
207 if (!brw
->format_supported_as_render_target
[mt
->format
])
211 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
212 const enum isl_format isl_format
=
213 brw_isl_format_for_mesa_format(linear_format
);
214 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
219 /* On Gen9 support for color buffer compression was extended to single
220 * sampled surfaces. This is a helper considering both auxiliary buffer
221 * type and number of samples telling if the given miptree represents
222 * the new single sampled case - also called lossless compression.
225 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
226 const struct intel_mipmap_tree
*mt
)
228 /* Only available from Gen9 onwards. */
232 /* Compression always requires auxiliary buffer. */
236 /* Single sample compression is represented re-using msaa compression
237 * layout type: "Compressed Multisampled Surfaces".
239 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
242 /* And finally distinguish between msaa and single sample case. */
243 return mt
->num_samples
<= 1;
247 intel_miptree_supports_lossless_compressed(struct brw_context
*brw
,
248 const struct intel_mipmap_tree
*mt
)
250 /* For now compression is only enabled for integer formats even though
251 * there exist supported floating point formats also. This is a heuristic
252 * decision based on current public benchmarks. In none of the cases these
253 * formats provided any improvement but a few cases were seen to regress.
254 * Hence these are left to to be enabled in the future when they are known
257 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
260 /* Fast clear mechanism and lossless compression go hand in hand. */
261 if (!intel_miptree_supports_non_msrt_fast_clear(brw
, mt
))
264 /* Fast clear can be also used to clear srgb surfaces by using equivalent
265 * linear format. This trick, however, can't be extended to be used with
266 * lossless compression and therefore a check is needed to see if the format
269 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
273 * Determine depth format corresponding to a depth+stencil format,
274 * for separate stencil.
277 intel_depth_format_for_depthstencil_format(mesa_format format
) {
279 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
280 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
281 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
282 return MESA_FORMAT_Z_FLOAT32
;
290 * @param for_bo Indicates that the caller is
291 * intel_miptree_create_for_bo(). If true, then do not create
294 static struct intel_mipmap_tree
*
295 intel_miptree_create_layout(struct brw_context
*brw
,
304 uint32_t layout_flags
)
306 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
310 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
311 _mesa_enum_to_string(target
),
312 _mesa_get_format_name(format
),
313 first_level
, last_level
, depth0
, mt
);
315 if (target
== GL_TEXTURE_1D_ARRAY
)
316 assert(height0
== 1);
320 mt
->first_level
= first_level
;
321 mt
->last_level
= last_level
;
322 mt
->logical_width0
= width0
;
323 mt
->logical_height0
= height0
;
324 mt
->logical_depth0
= depth0
;
325 mt
->aux_disable
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0 ?
326 INTEL_AUX_DISABLE_ALL
: INTEL_AUX_DISABLE_NONE
;
327 mt
->aux_disable
|= INTEL_AUX_DISABLE_CCS
;
328 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
329 mt
->aux_state
= NULL
;
330 mt
->cpp
= _mesa_get_format_bytes(format
);
331 mt
->num_samples
= num_samples
;
332 mt
->compressed
= _mesa_is_format_compressed(format
);
333 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
336 int depth_multiply
= 1;
337 if (num_samples
> 1) {
338 /* Adjust width/height/depth for MSAA */
339 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->aux_disable
);
340 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
341 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
342 * "If the surface is multisampled and it is a depth or stencil
343 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
344 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
347 * +----------------------------------------------------------------+
348 * | Num Multisamples | W_l = | H_l = |
349 * +----------------------------------------------------------------+
350 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
351 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
352 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
353 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
354 * +----------------------------------------------------------------+
357 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
358 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
359 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
361 * Another more complicated explanation for these adjustments comes
362 * from the Sandybridge PRM, volume 4, part 1, page 31:
364 * "Any of the other messages (sample*, LOD, load4) used with a
365 * (4x) multisampled surface will in-effect sample a surface with
366 * double the height and width as that indicated in the surface
367 * state. Each pixel position on the original-sized surface is
368 * replaced with a 2x2 of samples with the following arrangement:
373 * Thus, when sampling from a multisampled texture, it behaves as
374 * though the layout in memory for (x,y,sample) is:
376 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
377 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
379 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
380 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
382 * However, the actual layout of multisampled data in memory is:
384 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
385 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
387 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
388 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
390 * This pattern repeats for each 2x2 pixel block.
392 * As a result, when calculating the size of our 4-sample buffer for
393 * an odd width or height, we have to align before scaling up because
394 * sample 3 is in that bottom right 2x2 block.
396 switch (num_samples
) {
398 assert(brw
->gen
>= 8);
399 width0
= ALIGN(width0
, 2) * 2;
400 height0
= ALIGN(height0
, 2);
403 width0
= ALIGN(width0
, 2) * 2;
404 height0
= ALIGN(height0
, 2) * 2;
407 width0
= ALIGN(width0
, 2) * 4;
408 height0
= ALIGN(height0
, 2) * 2;
411 width0
= ALIGN(width0
, 2) * 4;
412 height0
= ALIGN(height0
, 2) * 4;
415 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
418 unreachable("not reached");
421 /* Non-interleaved */
422 depth_multiply
= num_samples
;
423 depth0
*= depth_multiply
;
427 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
428 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
429 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
430 * used on Gen8 to make it pick a qpitch value which doesn't include space
431 * for the mipmaps. On Gen9 this is not necessary because it will
432 * automatically pick a packed qpitch value whenever mt->first_level ==
434 * TODO: can we use it elsewhere?
435 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
438 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
440 switch (mt
->msaa_layout
) {
441 case INTEL_MSAA_LAYOUT_NONE
:
442 case INTEL_MSAA_LAYOUT_IMS
:
443 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
445 case INTEL_MSAA_LAYOUT_UMS
:
446 case INTEL_MSAA_LAYOUT_CMS
:
447 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
452 if (target
== GL_TEXTURE_CUBE_MAP
)
453 assert(depth0
== 6 * depth_multiply
);
455 mt
->physical_width0
= width0
;
456 mt
->physical_height0
= height0
;
457 mt
->physical_depth0
= depth0
;
459 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
460 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
461 (brw
->must_use_separate_stencil
||
462 (brw
->has_separate_stencil
&&
463 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
464 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
466 stencil_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
|
467 MIPTREE_LAYOUT_TILING_ANY
;
470 mt
->stencil_mt
= intel_miptree_create(brw
,
481 if (!mt
->stencil_mt
) {
482 intel_miptree_release(&mt
);
485 mt
->stencil_mt
->r8stencil_needs_update
= true;
487 /* Fix up the Z miptree format for how we're splitting out separate
488 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
490 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
493 if (format
== mt
->format
) {
494 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
495 _mesa_get_format_name(mt
->format
));
499 if (layout_flags
& MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
)
500 mt
->array_layout
= GEN6_HIZ_STENCIL
;
503 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
504 * multisampled or have an AUX buffer attached to it.
506 * GEN | MSRT | AUX_CCS_* or AUX_MCS
507 * -------------------------------------------
508 * 9 | HALIGN_16 | HALIGN_16
509 * 8 | HALIGN_ANY | HALIGN_16
513 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
514 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
515 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
516 } else if (brw
->gen
>= 9 && num_samples
> 1) {
517 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
519 const UNUSED
bool is_lossless_compressed_aux
=
520 brw
->gen
>= 9 && num_samples
== 1 &&
521 mt
->format
== MESA_FORMAT_R_UINT32
;
523 /* For now, nothing else has this requirement */
524 assert(is_lossless_compressed_aux
||
525 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
528 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
529 intel_miptree_release(&mt
);
533 if (mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
)
534 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
541 * Choose an appropriate uncompressed format for a requested
542 * compressed format, if unsupported.
545 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
547 /* No need to lower ETC formats on these platforms,
548 * they are supported natively.
550 if (brw
->gen
>= 8 || brw
->is_baytrail
)
554 case MESA_FORMAT_ETC1_RGB8
:
555 return MESA_FORMAT_R8G8B8X8_UNORM
;
556 case MESA_FORMAT_ETC2_RGB8
:
557 return MESA_FORMAT_R8G8B8X8_UNORM
;
558 case MESA_FORMAT_ETC2_SRGB8
:
559 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
560 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
561 return MESA_FORMAT_B8G8R8A8_SRGB
;
562 case MESA_FORMAT_ETC2_RGBA8_EAC
:
563 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
564 return MESA_FORMAT_R8G8B8A8_UNORM
;
565 case MESA_FORMAT_ETC2_R11_EAC
:
566 return MESA_FORMAT_R_UNORM16
;
567 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
568 return MESA_FORMAT_R_SNORM16
;
569 case MESA_FORMAT_ETC2_RG11_EAC
:
570 return MESA_FORMAT_R16G16_UNORM
;
571 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
572 return MESA_FORMAT_R16G16_SNORM
;
574 /* Non ETC1 / ETC2 format */
579 static enum isl_aux_state
**
580 create_aux_state_map(struct intel_mipmap_tree
*mt
,
581 enum isl_aux_state initial
)
583 const uint32_t levels
= mt
->last_level
+ 1;
585 uint32_t total_slices
= 0;
586 for (uint32_t level
= 0; level
< levels
; level
++)
587 total_slices
+= mt
->level
[level
].depth
;
589 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
591 /* We're going to allocate a single chunk of data for both the per-level
592 * reference array and the arrays of aux_state. This makes cleanup
593 * significantly easier.
595 const size_t total_size
= per_level_array_size
+
596 total_slices
* sizeof(enum isl_aux_state
);
597 void *data
= malloc(total_size
);
601 enum isl_aux_state
**per_level_arr
= data
;
602 enum isl_aux_state
*s
= data
+ per_level_array_size
;
603 for (uint32_t level
= 0; level
< levels
; level
++) {
604 per_level_arr
[level
] = s
;
605 for (uint32_t a
= 0; a
< mt
->level
[level
].depth
; a
++)
608 assert((void *)s
== data
+ total_size
);
610 return per_level_arr
;
614 free_aux_state_map(enum isl_aux_state
**state
)
619 static struct intel_mipmap_tree
*
620 miptree_create(struct brw_context
*brw
,
629 uint32_t layout_flags
)
631 struct intel_mipmap_tree
*mt
;
632 mesa_format tex_format
= format
;
633 mesa_format etc_format
= MESA_FORMAT_NONE
;
634 uint32_t alloc_flags
= 0;
636 format
= intel_lower_compressed_format(brw
, format
);
638 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
640 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
641 mt
= intel_miptree_create_layout(brw
, target
, format
,
642 first_level
, last_level
, width0
,
643 height0
, depth0
, num_samples
,
648 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
649 mt
->tiling
= I915_TILING_Y
;
651 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
652 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
654 mt
->etc_format
= etc_format
;
656 if (format
== MESA_FORMAT_S_UINT8
) {
657 /* Align to size of W tile, 64x64. */
658 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "miptree",
659 ALIGN(mt
->total_width
, 64),
660 ALIGN(mt
->total_height
, 64),
661 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
664 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "miptree",
665 mt
->total_width
, mt
->total_height
,
666 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
670 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
671 mt
->bo
->cache_coherent
= false;
676 struct intel_mipmap_tree
*
677 intel_miptree_create(struct brw_context
*brw
,
686 uint32_t layout_flags
)
688 struct intel_mipmap_tree
*mt
= miptree_create(
690 first_level
, last_level
,
691 width0
, height0
, depth0
, num_samples
,
694 /* If the BO is too large to fit in the aperture, we need to use the
695 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
696 * handle Y-tiling, so we need to fall back to X.
698 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
699 mt
->tiling
== I915_TILING_Y
) {
700 const uint32_t alloc_flags
=
701 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
702 BO_ALLOC_FOR_RENDER
: 0;
703 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
704 mt
->total_width
, mt
->total_height
);
706 mt
->tiling
= I915_TILING_X
;
707 brw_bo_unreference(mt
->bo
);
708 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "miptree",
709 mt
->total_width
, mt
->total_height
, mt
->cpp
,
710 mt
->tiling
, &mt
->pitch
, alloc_flags
);
716 intel_miptree_release(&mt
);
721 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
722 assert(mt
->num_samples
> 1);
723 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
724 intel_miptree_release(&mt
);
729 /* If this miptree is capable of supporting fast color clears, set
730 * fast_clear_state appropriately to ensure that fast clears will occur.
731 * Allocation of the MCS miptree will be deferred until the first fast
732 * clear actually occurs or when compressed single sampled buffer is
733 * written by the GPU for the first time.
735 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
736 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
737 mt
->aux_disable
&= ~INTEL_AUX_DISABLE_CCS
;
738 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
740 /* On Gen9+ clients are not currently capable of consuming compressed
741 * single-sampled buffers. Disabling compression allows us to skip
744 const bool lossless_compression_disabled
= INTEL_DEBUG
& DEBUG_NO_RBC
;
745 const bool is_lossless_compressed
=
746 unlikely(!lossless_compression_disabled
) &&
747 brw
->gen
>= 9 && !mt
->is_scanout
&&
748 intel_miptree_supports_lossless_compressed(brw
, mt
);
750 if (is_lossless_compressed
) {
751 intel_miptree_alloc_non_msrt_mcs(brw
, mt
, is_lossless_compressed
);
758 struct intel_mipmap_tree
*
759 intel_miptree_create_for_bo(struct brw_context
*brw
,
767 uint32_t layout_flags
)
769 struct intel_mipmap_tree
*mt
;
770 uint32_t tiling
, swizzle
;
773 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
775 /* Nothing will be able to use this miptree with the BO if the offset isn't
778 if (tiling
!= I915_TILING_NONE
)
779 assert(offset
% 4096 == 0);
781 /* miptrees can't handle negative pitch. If you need flipping of images,
782 * that's outside of the scope of the mt.
786 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
788 /* The BO already has a tiling format and we shouldn't confuse the lower
789 * layers by making it try to find a tiling format again.
791 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
792 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
794 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
795 mt
= intel_miptree_create_layout(brw
, target
, format
,
797 width
, height
, depth
, 0,
802 brw_bo_reference(bo
);
812 * For a singlesample renderbuffer, this simply wraps the given BO with a
815 * For a multisample renderbuffer, this wraps the window system's
816 * (singlesample) BO with a singlesample miptree attached to the
817 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
818 * that will contain the actual rendering (which is lazily resolved to
819 * irb->singlesample_mt).
822 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
823 struct intel_renderbuffer
*irb
,
825 uint32_t width
, uint32_t height
,
828 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
829 struct intel_mipmap_tree
*multisample_mt
= NULL
;
830 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
831 mesa_format format
= rb
->Format
;
832 int num_samples
= rb
->NumSamples
;
834 /* Only the front and back buffers, which are color buffers, are allocated
835 * through the image loader.
837 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
838 _mesa_get_format_base_format(format
) == GL_RGBA
);
840 singlesample_mt
= intel_miptree_create_for_bo(intel
,
848 MIPTREE_LAYOUT_FOR_SCANOUT
);
849 if (!singlesample_mt
)
852 /* If this miptree is capable of supporting fast color clears, set
853 * mcs_state appropriately to ensure that fast clears will occur.
854 * Allocation of the MCS miptree will be deferred until the first fast
855 * clear actually occurs.
857 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
858 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
859 singlesample_mt
->aux_disable
&= ~INTEL_AUX_DISABLE_CCS
;
862 if (num_samples
== 0) {
863 intel_miptree_release(&irb
->mt
);
864 irb
->mt
= singlesample_mt
;
866 assert(!irb
->singlesample_mt
);
868 intel_miptree_release(&irb
->singlesample_mt
);
869 irb
->singlesample_mt
= singlesample_mt
;
872 irb
->mt
->logical_width0
!= width
||
873 irb
->mt
->logical_height0
!= height
) {
874 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
882 irb
->need_downsample
= false;
883 intel_miptree_release(&irb
->mt
);
884 irb
->mt
= multisample_mt
;
890 intel_miptree_release(&irb
->singlesample_mt
);
891 intel_miptree_release(&irb
->mt
);
895 struct intel_mipmap_tree
*
896 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
900 uint32_t num_samples
)
902 struct intel_mipmap_tree
*mt
;
905 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
906 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
907 MIPTREE_LAYOUT_TILING_ANY
|
908 MIPTREE_LAYOUT_FOR_SCANOUT
;
910 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
911 width
, height
, depth
, num_samples
,
916 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
917 ok
= intel_miptree_alloc_hiz(brw
, mt
);
925 intel_miptree_release(&mt
);
930 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
931 struct intel_mipmap_tree
*src
)
936 intel_miptree_release(dst
);
940 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
947 intel_miptree_hiz_buffer_free(struct intel_miptree_hiz_buffer
*hiz_buf
)
953 intel_miptree_release(&hiz_buf
->mt
);
955 brw_bo_unreference(hiz_buf
->aux_base
.bo
);
961 intel_miptree_release(struct intel_mipmap_tree
**mt
)
966 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
967 if (--(*mt
)->refcount
<= 0) {
970 DBG("%s deleting %p\n", __func__
, *mt
);
972 brw_bo_unreference((*mt
)->bo
);
973 intel_miptree_release(&(*mt
)->stencil_mt
);
974 intel_miptree_release(&(*mt
)->r8stencil_mt
);
975 intel_miptree_hiz_buffer_free((*mt
)->hiz_buf
);
976 if ((*mt
)->mcs_buf
) {
977 brw_bo_unreference((*mt
)->mcs_buf
->bo
);
978 free((*mt
)->mcs_buf
);
980 free_aux_state_map((*mt
)->aux_state
);
982 intel_miptree_release(&(*mt
)->plane
[0]);
983 intel_miptree_release(&(*mt
)->plane
[1]);
985 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
986 free((*mt
)->level
[i
].slice
);
996 intel_get_image_dims(struct gl_texture_image
*image
,
997 int *width
, int *height
, int *depth
)
999 switch (image
->TexObject
->Target
) {
1000 case GL_TEXTURE_1D_ARRAY
:
1001 /* For a 1D Array texture the OpenGL API will treat the image height as
1002 * the number of array slices. For Intel hardware, we treat the 1D array
1003 * as a 2D Array with a height of 1. So, here we want to swap image
1006 assert(image
->Depth
== 1);
1007 *width
= image
->Width
;
1009 *depth
= image
->Height
;
1011 case GL_TEXTURE_CUBE_MAP
:
1012 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1013 * though we really have 6 slices.
1015 assert(image
->Depth
== 1);
1016 *width
= image
->Width
;
1017 *height
= image
->Height
;
1021 *width
= image
->Width
;
1022 *height
= image
->Height
;
1023 *depth
= image
->Depth
;
1029 * Can the image be pulled into a unified mipmap tree? This mirrors
1030 * the completeness test in a lot of ways.
1032 * Not sure whether I want to pass gl_texture_image here.
1035 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1036 struct gl_texture_image
*image
)
1038 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1039 GLuint level
= intelImage
->base
.Base
.Level
;
1040 int width
, height
, depth
;
1042 /* glTexImage* choose the texture object based on the target passed in, and
1043 * objects can't change targets over their lifetimes, so this should be
1046 assert(image
->TexObject
->Target
== mt
->target
);
1048 mesa_format mt_format
= mt
->format
;
1049 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1050 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1051 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1052 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1053 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1054 mt_format
= mt
->etc_format
;
1056 if (image
->TexFormat
!= mt_format
)
1059 intel_get_image_dims(image
, &width
, &height
, &depth
);
1061 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1064 int level_depth
= mt
->level
[level
].depth
;
1065 if (mt
->num_samples
> 1) {
1066 switch (mt
->msaa_layout
) {
1067 case INTEL_MSAA_LAYOUT_NONE
:
1068 case INTEL_MSAA_LAYOUT_IMS
:
1070 case INTEL_MSAA_LAYOUT_UMS
:
1071 case INTEL_MSAA_LAYOUT_CMS
:
1072 level_depth
/= mt
->num_samples
;
1077 /* Test image dimensions against the base level image adjusted for
1078 * minification. This will also catch images not present in the
1079 * tree, changed targets, etc.
1081 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1082 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1083 depth
!= level_depth
) {
1087 if (image
->NumSamples
!= mt
->num_samples
)
1095 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1097 GLuint x
, GLuint y
, GLuint d
)
1099 mt
->level
[level
].depth
= d
;
1100 mt
->level
[level
].level_x
= x
;
1101 mt
->level
[level
].level_y
= y
;
1103 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1106 assert(mt
->level
[level
].slice
== NULL
);
1108 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1109 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1110 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1115 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1116 GLuint level
, GLuint img
,
1119 if (img
== 0 && level
== 0)
1120 assert(x
== 0 && y
== 0);
1122 assert(img
< mt
->level
[level
].depth
);
1124 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1125 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1127 DBG("%s level %d img %d pos %d,%d\n",
1128 __func__
, level
, img
,
1129 mt
->level
[level
].slice
[img
].x_offset
,
1130 mt
->level
[level
].slice
[img
].y_offset
);
1134 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1135 GLuint level
, GLuint slice
,
1136 GLuint
*x
, GLuint
*y
)
1138 assert(slice
< mt
->level
[level
].depth
);
1140 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1141 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1146 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1147 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1148 * and tile_h is set to 1.
1151 intel_get_tile_dims(uint32_t tiling
, uint32_t cpp
,
1152 uint32_t *tile_w
, uint32_t *tile_h
)
1163 case I915_TILING_NONE
:
1168 unreachable("not reached");
1174 * This function computes masks that may be used to select the bits of the X
1175 * and Y coordinates that indicate the offset within a tile. If the BO is
1176 * untiled, the masks are set to 0.
1179 intel_get_tile_masks(uint32_t tiling
, uint32_t cpp
,
1180 uint32_t *mask_x
, uint32_t *mask_y
)
1182 uint32_t tile_w_bytes
, tile_h
;
1184 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1186 *mask_x
= tile_w_bytes
/ cpp
- 1;
1187 *mask_y
= tile_h
- 1;
1191 * Compute the offset (in bytes) from the start of the BO to the given x
1192 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1193 * multiples of the tile size.
1196 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1197 uint32_t x
, uint32_t y
)
1200 uint32_t pitch
= mt
->pitch
;
1201 uint32_t tiling
= mt
->tiling
;
1205 unreachable("not reached");
1206 case I915_TILING_NONE
:
1207 return y
* pitch
+ x
* cpp
;
1209 assert((x
% (512 / cpp
)) == 0);
1210 assert((y
% 8) == 0);
1211 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1213 assert((x
% (128 / cpp
)) == 0);
1214 assert((y
% 32) == 0);
1215 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1220 * Rendering with tiled buffers requires that the base address of the buffer
1221 * be aligned to a page boundary. For renderbuffers, and sometimes with
1222 * textures, we may want the surface to point at a texture image level that
1223 * isn't at a page boundary.
1225 * This function returns an appropriately-aligned base offset
1226 * according to the tiling restrictions, plus any required x/y offset
1230 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1231 GLuint level
, GLuint slice
,
1236 uint32_t mask_x
, mask_y
;
1238 intel_get_tile_masks(mt
->tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1239 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1241 *tile_x
= x
& mask_x
;
1242 *tile_y
= y
& mask_y
;
1244 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1248 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1249 struct intel_mipmap_tree
*dst_mt
,
1250 struct intel_mipmap_tree
*src_mt
,
1257 ptrdiff_t src_stride
, dst_stride
;
1258 int cpp
= dst_mt
->cpp
;
1260 intel_miptree_map(brw
, src_mt
,
1264 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1267 intel_miptree_map(brw
, dst_mt
,
1271 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1275 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1276 _mesa_get_format_name(src_mt
->format
),
1277 src_mt
, src
, src_stride
,
1278 _mesa_get_format_name(dst_mt
->format
),
1279 dst_mt
, dst
, dst_stride
,
1282 int row_size
= cpp
* width
;
1283 if (src_stride
== row_size
&&
1284 dst_stride
== row_size
) {
1285 memcpy(dst
, src
, row_size
* height
);
1287 for (int i
= 0; i
< height
; i
++) {
1288 memcpy(dst
, src
, row_size
);
1294 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1295 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1297 /* Don't forget to copy the stencil data over, too. We could have skipped
1298 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1299 * shuffling the two data sources in/out of temporary storage instead of
1300 * the direct mapping we get this way.
1302 if (dst_mt
->stencil_mt
) {
1303 assert(src_mt
->stencil_mt
);
1304 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1305 level
, slice
, width
, height
);
1310 intel_miptree_copy_slice(struct brw_context
*brw
,
1311 struct intel_mipmap_tree
*dst_mt
,
1312 struct intel_mipmap_tree
*src_mt
,
1318 mesa_format format
= src_mt
->format
;
1319 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1320 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1328 assert(depth
< src_mt
->level
[level
].depth
);
1329 assert(src_mt
->format
== dst_mt
->format
);
1331 if (dst_mt
->compressed
) {
1333 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1334 height
= ALIGN_NPOT(height
, j
) / j
;
1335 width
= ALIGN_NPOT(width
, i
) / i
;
1338 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1339 * below won't apply since we can't do the depth's Y tiling or the
1340 * stencil's W tiling in the blitter.
1342 if (src_mt
->stencil_mt
) {
1343 intel_miptree_copy_slice_sw(brw
,
1350 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1351 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1352 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1354 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1355 _mesa_get_format_name(src_mt
->format
),
1356 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1357 _mesa_get_format_name(dst_mt
->format
),
1358 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1361 if (!intel_miptree_blit(brw
,
1362 src_mt
, level
, slice
, 0, 0, false,
1363 dst_mt
, level
, slice
, 0, 0, false,
1364 width
, height
, GL_COPY
)) {
1365 perf_debug("miptree validate blit for %s failed\n",
1366 _mesa_get_format_name(format
));
1368 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1374 * Copies the image's current data to the given miptree, and associates that
1375 * miptree with the image.
1377 * If \c invalidate is true, then the actual image data does not need to be
1378 * copied, but the image still needs to be associated to the new miptree (this
1379 * is set to true if we're about to clear the image).
1382 intel_miptree_copy_teximage(struct brw_context
*brw
,
1383 struct intel_texture_image
*intelImage
,
1384 struct intel_mipmap_tree
*dst_mt
,
1387 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1388 struct intel_texture_object
*intel_obj
=
1389 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1390 int level
= intelImage
->base
.Base
.Level
;
1391 int face
= intelImage
->base
.Base
.Face
;
1394 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1395 depth
= intelImage
->base
.Base
.Height
;
1397 depth
= intelImage
->base
.Base
.Depth
;
1400 for (int slice
= 0; slice
< depth
; slice
++) {
1401 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1405 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1406 intel_obj
->needs_validate
= true;
1410 intel_miptree_init_mcs(struct brw_context
*brw
,
1411 struct intel_mipmap_tree
*mt
,
1414 assert(mt
->mcs_buf
!= NULL
);
1416 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1418 * When MCS buffer is enabled and bound to MSRT, it is required that it
1419 * is cleared prior to any rendering.
1421 * Since we don't use the MCS buffer for any purpose other than rendering,
1422 * it makes sense to just clear it immediately upon allocation.
1424 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1426 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1427 if (unlikely(map
== NULL
)) {
1428 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1429 brw_bo_unreference(mt
->mcs_buf
->bo
);
1434 memset(data
, init_value
, mt
->mcs_buf
->size
);
1435 brw_bo_unmap(mt
->mcs_buf
->bo
);
1438 static struct intel_miptree_aux_buffer
*
1439 intel_mcs_miptree_buf_create(struct brw_context
*brw
,
1440 struct intel_mipmap_tree
*mt
,
1443 unsigned mcs_height
,
1444 uint32_t layout_flags
)
1446 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1447 struct intel_mipmap_tree
*temp_mt
;
1452 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1454 * "The MCS surface must be stored as Tile Y."
1456 layout_flags
|= MIPTREE_LAYOUT_TILING_Y
;
1457 temp_mt
= miptree_create(brw
,
1465 0 /* num_samples */,
1472 buf
->bo
= temp_mt
->bo
;
1473 buf
->offset
= temp_mt
->offset
;
1474 buf
->size
= temp_mt
->total_height
* temp_mt
->pitch
;
1475 buf
->pitch
= temp_mt
->pitch
;
1476 buf
->qpitch
= temp_mt
->qpitch
;
1478 /* Just hang on to the BO which backs the AUX buffer; the rest of the miptree
1479 * structure should go away. We use miptree create simply as a means to make
1480 * sure all the constraints for the buffer are satisfied.
1482 brw_bo_reference(temp_mt
->bo
);
1483 intel_miptree_release(&temp_mt
);
1489 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1490 struct intel_mipmap_tree
*mt
,
1493 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1494 assert(mt
->mcs_buf
== NULL
);
1495 assert((mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
) == 0);
1497 /* Choose the correct format for the MCS buffer. All that really matters
1498 * is that we allocate the right buffer size, since we'll always be
1499 * accessing this miptree using MCS-specific hardware mechanisms, which
1500 * infer the correct format based on num_samples.
1503 switch (num_samples
) {
1506 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1509 format
= MESA_FORMAT_R_UNORM8
;
1512 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1513 * for each sample, plus 8 padding bits).
1515 format
= MESA_FORMAT_R_UINT32
;
1518 /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
1521 format
= MESA_FORMAT_RG_UINT32
;
1524 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1527 /* Multisampled miptrees are only supported for single level. */
1528 assert(mt
->first_level
== 0);
1529 enum isl_aux_state
**aux_state
=
1530 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1535 intel_mcs_miptree_buf_create(brw
, mt
,
1538 mt
->logical_height0
,
1539 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
);
1545 mt
->aux_state
= aux_state
;
1547 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1553 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1554 struct intel_mipmap_tree
*mt
,
1555 bool is_lossless_compressed
)
1557 assert(mt
->mcs_buf
== NULL
);
1558 assert(!(mt
->aux_disable
& (INTEL_AUX_DISABLE_MCS
| INTEL_AUX_DISABLE_CCS
)));
1560 struct isl_surf temp_main_surf
;
1561 struct isl_surf temp_ccs_surf
;
1563 /* Create first an ISL presentation for the main color surface and let ISL
1564 * calculate equivalent CCS surface against it.
1566 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1567 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_ccs_surf
))
1570 assert(temp_ccs_surf
.size
&&
1571 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1573 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1577 enum isl_aux_state
**aux_state
=
1578 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1584 buf
->size
= temp_ccs_surf
.size
;
1585 buf
->pitch
= temp_ccs_surf
.row_pitch
;
1586 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(&temp_ccs_surf
);
1588 /* In case of compression mcs buffer needs to be initialised requiring the
1589 * buffer to be immediately mapped to cpu space for writing. Therefore do
1590 * not use the gpu access flag which can cause an unnecessary delay if the
1591 * backing pages happened to be just used by the GPU.
1593 const uint32_t alloc_flags
=
1594 is_lossless_compressed
? 0 : BO_ALLOC_FOR_RENDER
;
1596 /* ISL has stricter set of alignment rules then the drm allocator.
1597 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1598 * trying to recalculate based on different format block sizes.
1600 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "ccs-miptree",
1601 buf
->pitch
, buf
->size
/ buf
->pitch
,
1602 1, I915_TILING_Y
, &buf
->pitch
, alloc_flags
);
1610 mt
->aux_state
= aux_state
;
1612 /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
1613 * used for lossless compression which requires similar initialisation
1614 * as multi-sample compression.
1616 if (is_lossless_compressed
) {
1617 /* Hardware sets the auxiliary buffer to all zeroes when it does full
1618 * resolve. Initialize it accordingly in case the first renderer is
1619 * cpu (or other none compression aware party).
1621 * This is also explicitly stated in the spec (MCS Buffer for Render
1623 * "If Software wants to enable Color Compression without Fast clear,
1624 * Software needs to initialize MCS with zeros."
1626 intel_miptree_init_mcs(brw
, mt
, 0);
1627 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_CMS
;
1634 * Helper for intel_miptree_alloc_hiz() that sets
1635 * \c mt->level[level].has_hiz. Return true if and only if
1636 * \c has_hiz was set.
1639 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1640 struct intel_mipmap_tree
*mt
,
1643 assert(mt
->hiz_buf
);
1645 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1646 uint32_t width
= minify(mt
->physical_width0
, level
);
1647 uint32_t height
= minify(mt
->physical_height0
, level
);
1649 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1650 * and the height is 4 aligned. This allows our HiZ support
1651 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1652 * we can grow the width & height to allow the HiZ op to
1653 * force the proper size alignments.
1655 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1656 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1661 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1662 mt
->level
[level
].has_hiz
= true;
1668 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1669 * buffer dimensions and allocates a bo for the hiz buffer.
1671 static struct intel_miptree_hiz_buffer
*
1672 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1673 struct intel_mipmap_tree
*mt
)
1675 unsigned z_width
= mt
->logical_width0
;
1676 unsigned z_height
= mt
->logical_height0
;
1677 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1678 unsigned hz_width
, hz_height
;
1679 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1684 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1685 * adjustments required for Z_Height and Z_Width based on multisampling.
1687 switch (mt
->num_samples
) {
1701 unreachable("unsupported sample count");
1704 const unsigned vertical_align
= 8; /* 'j' in the docs */
1705 const unsigned H0
= z_height
;
1706 const unsigned h0
= ALIGN(H0
, vertical_align
);
1707 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1708 const unsigned Z0
= z_depth
;
1710 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1711 hz_width
= ALIGN(z_width
, 16);
1713 if (mt
->target
== GL_TEXTURE_3D
) {
1717 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1718 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1719 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1720 hz_height
+= h_i
* Z_i
;
1721 H_i
= minify(H_i
, 1);
1722 Z_i
= minify(Z_i
, 1);
1725 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1727 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1729 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1730 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1731 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1734 buf
->aux_base
.bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1735 hz_width
, hz_height
, 1,
1736 I915_TILING_Y
, &buf
->aux_base
.pitch
,
1737 BO_ALLOC_FOR_RENDER
);
1738 if (!buf
->aux_base
.bo
) {
1743 buf
->aux_base
.size
= hz_width
* hz_height
;
1750 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1751 * buffer dimensions and allocates a bo for the hiz buffer.
1753 static struct intel_miptree_hiz_buffer
*
1754 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1755 struct intel_mipmap_tree
*mt
)
1757 unsigned z_width
= mt
->logical_width0
;
1758 unsigned z_height
= mt
->logical_height0
;
1759 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1760 unsigned hz_width
, hz_height
;
1761 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1766 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1767 * adjustments required for Z_Height and Z_Width based on multisampling.
1770 switch (mt
->num_samples
) {
1784 unreachable("unsupported sample count");
1788 const unsigned vertical_align
= 8; /* 'j' in the docs */
1789 const unsigned H0
= z_height
;
1790 const unsigned h0
= ALIGN(H0
, vertical_align
);
1791 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1792 const unsigned Z0
= z_depth
;
1794 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1795 hz_width
= ALIGN(z_width
, 16);
1799 unsigned sum_h_i
= 0;
1800 unsigned hz_height_3d_sum
= 0;
1801 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1802 unsigned i
= level
- mt
->first_level
;
1803 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1804 /* sum(i=2 to m; h_i) */
1808 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1809 hz_height_3d_sum
+= h_i
* Z_i
;
1810 H_i
= minify(H_i
, 1);
1811 Z_i
= minify(Z_i
, 1);
1813 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1814 buf
->aux_base
.qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1816 if (mt
->target
== GL_TEXTURE_3D
) {
1817 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1818 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1820 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1821 hz_height
= DIV_ROUND_UP(buf
->aux_base
.qpitch
, 2 * 8) * 8 * Z0
;
1824 buf
->aux_base
.bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1825 hz_width
, hz_height
, 1,
1826 I915_TILING_Y
, &buf
->aux_base
.pitch
,
1827 BO_ALLOC_FOR_RENDER
);
1828 if (!buf
->aux_base
.bo
) {
1833 buf
->aux_base
.size
= hz_width
* hz_height
;
1839 static struct intel_miptree_hiz_buffer
*
1840 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1841 struct intel_mipmap_tree
*mt
)
1843 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1844 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1847 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
1852 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1853 buf
->mt
= intel_miptree_create(brw
,
1859 mt
->logical_height0
,
1868 buf
->aux_base
.bo
= buf
->mt
->bo
;
1869 buf
->aux_base
.size
= buf
->mt
->total_height
* buf
->mt
->pitch
;
1870 buf
->aux_base
.pitch
= buf
->mt
->pitch
;
1871 buf
->aux_base
.qpitch
= buf
->mt
->qpitch
* 2;
1877 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1878 struct intel_mipmap_tree
*mt
)
1883 if (mt
->hiz_buf
!= NULL
)
1886 if (mt
->aux_disable
& INTEL_AUX_DISABLE_HIZ
)
1889 switch (mt
->format
) {
1890 case MESA_FORMAT_Z_FLOAT32
:
1891 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1892 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1893 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1894 case MESA_FORMAT_Z_UNORM16
:
1902 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1903 struct intel_mipmap_tree
*mt
)
1905 assert(mt
->hiz_buf
== NULL
);
1906 assert((mt
->aux_disable
& INTEL_AUX_DISABLE_HIZ
) == 0);
1908 enum isl_aux_state
**aux_state
=
1909 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1913 if (brw
->gen
== 7) {
1914 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1915 } else if (brw
->gen
>= 8) {
1916 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1918 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1926 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1927 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1929 mt
->aux_state
= aux_state
;
1935 * Can the miptree sample using the hiz buffer?
1938 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1939 struct intel_mipmap_tree
*mt
)
1941 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1942 * so keep things conservative for now and never enable it unless we're SKL+.
1952 /* It seems the hardware won't fallback to the depth buffer if some of the
1953 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1954 * of the texture to be HiZ enabled.
1956 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1957 if (!intel_miptree_level_has_hiz(mt
, level
))
1961 /* If compressed multisampling is enabled, then we use it for the auxiliary
1964 * From the BDW PRM (Volume 2d: Command Reference: Structures
1965 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1967 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1968 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1970 * There is no such blurb for 1D textures, but there is sufficient evidence
1971 * that this is broken on SKL+.
1973 return (mt
->num_samples
<= 1 &&
1974 mt
->target
!= GL_TEXTURE_3D
&&
1975 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1979 * Does the miptree slice have hiz enabled?
1982 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1984 intel_miptree_check_level_layer(mt
, level
, 0);
1985 return mt
->level
[level
].has_hiz
;
1989 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1990 unsigned start_level
, unsigned num_levels
,
1991 unsigned start_layer
, unsigned num_layers
)
1993 assert(_mesa_is_format_color_format(mt
->format
));
1998 /* Clamp the level range to fit the miptree */
1999 assert(start_level
+ num_levels
>= start_level
);
2000 const uint32_t last_level
=
2001 MIN2(mt
->last_level
, start_level
+ num_levels
- 1);
2002 start_level
= MAX2(mt
->first_level
, start_level
);
2003 num_levels
= last_level
- start_level
+ 1;
2005 for (uint32_t level
= start_level
; level
<= last_level
; level
++) {
2006 const uint32_t level_layers
= MIN2(num_layers
, mt
->level
[level
].depth
);
2007 for (unsigned a
= 0; a
< level_layers
; a
++) {
2008 enum isl_aux_state aux_state
=
2009 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2010 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2011 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2020 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2021 const struct intel_mipmap_tree
*mt
,
2022 unsigned level
, unsigned layer
)
2025 if ((mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) || !mt
->mcs_buf
)
2028 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2029 assert(brw
->gen
>= 8 ||
2030 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2032 /* Compression of arrayed msaa surfaces is supported. */
2033 if (mt
->num_samples
> 1)
2036 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2037 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
2043 static enum blorp_fast_clear_op
2044 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2045 bool ccs_supported
, bool fast_clear_supported
)
2047 assert(ccs_supported
== fast_clear_supported
);
2049 switch (aux_state
) {
2050 case ISL_AUX_STATE_CLEAR
:
2051 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2053 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2055 return BLORP_FAST_CLEAR_OP_NONE
;
2057 case ISL_AUX_STATE_PASS_THROUGH
:
2058 return BLORP_FAST_CLEAR_OP_NONE
;
2060 case ISL_AUX_STATE_RESOLVED
:
2061 case ISL_AUX_STATE_AUX_INVALID
:
2062 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2066 unreachable("Invalid aux state for CCS_D");
2069 static enum blorp_fast_clear_op
2070 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2071 bool ccs_supported
, bool fast_clear_supported
)
2073 switch (aux_state
) {
2074 case ISL_AUX_STATE_CLEAR
:
2075 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2077 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2078 else if (!fast_clear_supported
)
2079 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2081 return BLORP_FAST_CLEAR_OP_NONE
;
2083 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2085 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2087 return BLORP_FAST_CLEAR_OP_NONE
;
2089 case ISL_AUX_STATE_PASS_THROUGH
:
2090 return BLORP_FAST_CLEAR_OP_NONE
;
2092 case ISL_AUX_STATE_RESOLVED
:
2093 case ISL_AUX_STATE_AUX_INVALID
:
2097 unreachable("Invalid aux state for CCS_E");
2101 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2102 struct intel_mipmap_tree
*mt
,
2103 uint32_t level
, uint32_t layer
,
2105 bool fast_clear_supported
)
2107 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2109 enum blorp_fast_clear_op resolve_op
;
2110 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
2111 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_supported
,
2112 fast_clear_supported
);
2114 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_supported
,
2115 fast_clear_supported
);
2118 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2119 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2120 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2122 switch (resolve_op
) {
2123 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2124 /* The CCS full resolve operation destroys the CCS and sets it to the
2125 * pass-through state. (You can also think of this as being both a
2126 * resolve and an ambiguate in one operation.)
2128 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2129 ISL_AUX_STATE_PASS_THROUGH
);
2132 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2133 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2134 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2138 unreachable("Invalid resolve op");
2144 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2145 struct intel_mipmap_tree
*mt
,
2146 uint32_t level
, uint32_t layer
,
2147 bool written_with_ccs
)
2149 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2151 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
2152 switch (aux_state
) {
2153 case ISL_AUX_STATE_CLEAR
:
2154 assert(written_with_ccs
);
2155 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2156 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2159 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2160 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2161 assert(written_with_ccs
);
2162 break; /* Nothing to do */
2164 case ISL_AUX_STATE_PASS_THROUGH
:
2165 if (written_with_ccs
) {
2166 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2167 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2173 case ISL_AUX_STATE_RESOLVED
:
2174 case ISL_AUX_STATE_AUX_INVALID
:
2175 unreachable("Invalid aux state for CCS_E");
2178 /* CCS_D is a bit simpler */
2179 switch (aux_state
) {
2180 case ISL_AUX_STATE_CLEAR
:
2181 assert(written_with_ccs
);
2182 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2183 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2186 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2187 assert(written_with_ccs
);
2188 break; /* Nothing to do */
2190 case ISL_AUX_STATE_PASS_THROUGH
:
2194 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2195 case ISL_AUX_STATE_RESOLVED
:
2196 case ISL_AUX_STATE_AUX_INVALID
:
2197 unreachable("Invalid aux state for CCS_D");
2203 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2204 struct intel_mipmap_tree
*mt
,
2205 uint32_t level
, uint32_t layer
,
2206 bool written_with_aux
)
2208 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2209 case ISL_AUX_STATE_CLEAR
:
2210 assert(written_with_aux
);
2211 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2212 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2215 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2216 assert(written_with_aux
);
2217 break; /* Nothing to do */
2219 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2220 case ISL_AUX_STATE_RESOLVED
:
2221 case ISL_AUX_STATE_PASS_THROUGH
:
2222 case ISL_AUX_STATE_AUX_INVALID
:
2223 unreachable("Invalid aux state for MCS");
2228 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2229 struct intel_mipmap_tree
*mt
,
2230 uint32_t level
, uint32_t layer
,
2231 bool hiz_supported
, bool fast_clear_supported
)
2233 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2234 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2235 case ISL_AUX_STATE_CLEAR
:
2236 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2237 if (!hiz_supported
|| !fast_clear_supported
)
2238 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2241 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2243 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2246 case ISL_AUX_STATE_PASS_THROUGH
:
2247 case ISL_AUX_STATE_RESOLVED
:
2250 case ISL_AUX_STATE_AUX_INVALID
:
2252 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2256 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2257 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2260 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2261 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2262 ISL_AUX_STATE_RESOLVED
);
2265 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2266 /* The HiZ resolve operation is actually an ambiguate */
2267 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2268 ISL_AUX_STATE_PASS_THROUGH
);
2272 unreachable("Invalid HiZ op");
2278 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2279 struct intel_mipmap_tree
*mt
,
2280 uint32_t level
, uint32_t layer
,
2281 bool written_with_hiz
)
2283 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2284 case ISL_AUX_STATE_CLEAR
:
2285 assert(written_with_hiz
);
2286 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2287 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2290 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2291 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2292 assert(written_with_hiz
);
2293 break; /* Nothing to do */
2295 case ISL_AUX_STATE_RESOLVED
:
2296 if (written_with_hiz
) {
2297 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2298 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2300 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2301 ISL_AUX_STATE_AUX_INVALID
);
2304 case ISL_AUX_STATE_PASS_THROUGH
:
2305 if (written_with_hiz
) {
2306 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2307 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2311 case ISL_AUX_STATE_AUX_INVALID
:
2312 assert(!written_with_hiz
);
2317 static inline uint32_t
2318 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
2319 uint32_t start_level
, uint32_t num_levels
)
2321 assert(start_level
>= mt
->first_level
);
2322 assert(start_level
<= mt
->last_level
);
2324 if (num_levels
== INTEL_REMAINING_LAYERS
)
2325 num_levels
= mt
->last_level
- start_level
+ 1;
2326 /* Check for overflow */
2327 assert(start_level
+ num_levels
>= start_level
);
2328 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2333 static inline uint32_t
2334 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2335 uint32_t start_layer
, uint32_t num_layers
)
2337 assert(level
<= mt
->last_level
);
2338 uint32_t total_num_layers
= mt
->level
[level
].depth
;
2340 assert(start_layer
< total_num_layers
);
2341 if (num_layers
== INTEL_REMAINING_LAYERS
)
2342 num_layers
= total_num_layers
- start_layer
;
2343 /* Check for overflow */
2344 assert(start_layer
+ num_layers
>= start_layer
);
2345 assert(start_layer
+ num_layers
<= total_num_layers
);
2351 intel_miptree_prepare_access(struct brw_context
*brw
,
2352 struct intel_mipmap_tree
*mt
,
2353 uint32_t start_level
, uint32_t num_levels
,
2354 uint32_t start_layer
, uint32_t num_layers
,
2355 bool aux_supported
, bool fast_clear_supported
)
2357 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2359 if (_mesa_is_format_color_format(mt
->format
)) {
2363 if (mt
->num_samples
> 1) {
2364 /* Nothing to do for MSAA */
2365 assert(aux_supported
&& fast_clear_supported
);
2367 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2368 const uint32_t level
= start_level
+ l
;
2369 const uint32_t level_layers
=
2370 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2371 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2372 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2373 start_layer
+ a
, aux_supported
,
2374 fast_clear_supported
);
2378 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2379 /* Nothing to do for stencil */
2384 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2385 const uint32_t level
= start_level
+ l
;
2386 if (!intel_miptree_level_has_hiz(mt
, level
))
2389 const uint32_t level_layers
=
2390 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2391 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2392 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2394 fast_clear_supported
);
2401 intel_miptree_finish_write(struct brw_context
*brw
,
2402 struct intel_mipmap_tree
*mt
, uint32_t level
,
2403 uint32_t start_layer
, uint32_t num_layers
,
2404 bool written_with_aux
)
2406 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2408 if (_mesa_is_format_color_format(mt
->format
)) {
2412 if (mt
->num_samples
> 1) {
2413 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2414 intel_miptree_finish_mcs_write(brw
, mt
, level
, start_layer
+ a
,
2418 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2419 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2423 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2424 /* Nothing to do for stencil */
2426 if (!intel_miptree_level_has_hiz(mt
, level
))
2429 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2430 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2437 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2438 uint32_t level
, uint32_t layer
)
2440 intel_miptree_check_level_layer(mt
, level
, layer
);
2442 if (_mesa_is_format_color_format(mt
->format
)) {
2443 assert(mt
->mcs_buf
!= NULL
);
2444 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2445 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2446 unreachable("Cannot get aux state for stencil");
2448 assert(intel_miptree_level_has_hiz(mt
, level
));
2451 return mt
->aux_state
[level
][layer
];
2455 intel_miptree_set_aux_state(struct brw_context
*brw
,
2456 struct intel_mipmap_tree
*mt
, uint32_t level
,
2457 uint32_t start_layer
, uint32_t num_layers
,
2458 enum isl_aux_state aux_state
)
2460 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2462 if (_mesa_is_format_color_format(mt
->format
)) {
2463 assert(mt
->mcs_buf
!= NULL
);
2464 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2465 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2466 unreachable("Cannot get aux state for stencil");
2468 assert(intel_miptree_level_has_hiz(mt
, level
));
2471 for (unsigned a
= 0; a
< num_layers
; a
++)
2472 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2475 /* On Gen9 color buffers may be compressed by the hardware (lossless
2476 * compression). There are, however, format restrictions and care needs to be
2477 * taken that the sampler engine is capable for re-interpreting a buffer with
2478 * format different the buffer was originally written with.
2480 * For example, SRGB formats are not compressible and the sampler engine isn't
2481 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2482 * color buffer needs to be resolved so that the sampling surface can be
2483 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2487 can_texture_with_ccs(struct brw_context
*brw
,
2488 struct intel_mipmap_tree
*mt
,
2489 mesa_format view_format
)
2491 if (!intel_miptree_is_lossless_compressed(brw
, mt
))
2494 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2495 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2497 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2498 isl_mt_format
, isl_view_format
)) {
2499 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2500 _mesa_get_format_name(view_format
),
2501 _mesa_get_format_name(mt
->format
));
2509 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2510 struct intel_mipmap_tree
*mt
,
2511 mesa_format view_format
,
2512 uint32_t start_level
, uint32_t num_levels
,
2513 uint32_t start_layer
, uint32_t num_layers
,
2514 bool *aux_supported_out
)
2516 bool aux_supported
, clear_supported
;
2517 if (_mesa_is_format_color_format(mt
->format
)) {
2518 if (mt
->num_samples
> 1) {
2519 aux_supported
= clear_supported
= true;
2521 aux_supported
= can_texture_with_ccs(brw
, mt
, view_format
);
2523 /* Clear color is specified as ints or floats and the conversion is
2524 * done by the sampler. If we have a texture view, we would have to
2525 * perform the clear color conversion manually. Just disable clear
2528 clear_supported
= aux_supported
&& (mt
->format
== view_format
);
2530 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2531 aux_supported
= clear_supported
= false;
2533 aux_supported
= clear_supported
= intel_miptree_sample_with_hiz(brw
, mt
);
2536 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2537 start_layer
, num_layers
,
2538 aux_supported
, clear_supported
);
2539 if (aux_supported_out
)
2540 *aux_supported_out
= aux_supported
;
2544 intel_miptree_prepare_texture(struct brw_context
*brw
,
2545 struct intel_mipmap_tree
*mt
,
2546 mesa_format view_format
,
2547 bool *aux_supported_out
)
2549 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2550 0, INTEL_REMAINING_LEVELS
,
2551 0, INTEL_REMAINING_LAYERS
,
2556 intel_miptree_prepare_image(struct brw_context
*brw
,
2557 struct intel_mipmap_tree
*mt
)
2559 /* The data port doesn't understand any compression */
2560 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2561 0, INTEL_REMAINING_LAYERS
, false, false);
2565 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2566 struct intel_mipmap_tree
*mt
, uint32_t level
,
2567 uint32_t start_layer
, uint32_t num_layers
)
2569 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2570 start_layer
, num_layers
, NULL
);
2574 intel_miptree_prepare_render(struct brw_context
*brw
,
2575 struct intel_mipmap_tree
*mt
, uint32_t level
,
2576 uint32_t start_layer
, uint32_t layer_count
,
2579 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2580 * the single-sampled color renderbuffers because the CCS buffer isn't
2581 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2582 * enabled because otherwise the surface state will be programmed with
2583 * the linear equivalent format anyway.
2585 if (brw
->gen
>= 9 && srgb_enabled
&& mt
->num_samples
<= 1 &&
2586 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2588 /* Lossless compression is not supported for SRGB formats, it
2589 * should be impossible to get here with such surfaces.
2591 assert(!intel_miptree_is_lossless_compressed(brw
, mt
));
2592 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2596 /* For layered rendering non-compressed fast cleared buffers need to be
2597 * resolved. Surface state can carry only one fast color clear value
2598 * while each layer may have its own fast clear color value. For
2599 * compressed buffers color value is available in the color buffer.
2601 if (layer_count
> 1 &&
2602 !(mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) &&
2603 !intel_miptree_is_lossless_compressed(brw
, mt
)) {
2604 assert(brw
->gen
>= 8);
2606 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2612 intel_miptree_finish_render(struct brw_context
*brw
,
2613 struct intel_mipmap_tree
*mt
, uint32_t level
,
2614 uint32_t start_layer
, uint32_t layer_count
)
2616 assert(_mesa_is_format_color_format(mt
->format
));
2617 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2618 mt
->mcs_buf
!= NULL
);
2622 intel_miptree_prepare_depth(struct brw_context
*brw
,
2623 struct intel_mipmap_tree
*mt
, uint32_t level
,
2624 uint32_t start_layer
, uint32_t layer_count
)
2626 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2627 mt
->hiz_buf
!= NULL
, mt
->hiz_buf
!= NULL
);
2631 intel_miptree_finish_depth(struct brw_context
*brw
,
2632 struct intel_mipmap_tree
*mt
, uint32_t level
,
2633 uint32_t start_layer
, uint32_t layer_count
,
2636 if (depth_written
) {
2637 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2638 mt
->hiz_buf
!= NULL
);
2643 * Make it possible to share the BO backing the given miptree with another
2644 * process or another miptree.
2646 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2647 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2648 * ensure that no MCS buffer gets allocated in the future.
2650 * HiZ is similarly unsafe with shared buffers.
2653 intel_miptree_make_shareable(struct brw_context
*brw
,
2654 struct intel_mipmap_tree
*mt
)
2656 /* MCS buffers are also used for multisample buffers, but we can't resolve
2657 * away a multisample MCS buffer because it's an integral part of how the
2658 * pixel data is stored. Fortunately this code path should never be
2659 * reached for multisample buffers.
2661 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
|| mt
->num_samples
<= 1);
2663 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2664 0, INTEL_REMAINING_LAYERS
, false, false);
2667 mt
->aux_disable
|= (INTEL_AUX_DISABLE_CCS
| INTEL_AUX_DISABLE_MCS
);
2668 brw_bo_unreference(mt
->mcs_buf
->bo
);
2672 /* Any pending MCS/CCS operations are no longer needed. Trying to
2673 * execute any will likely crash due to the missing aux buffer. So let's
2674 * delete all pending ops.
2676 free(mt
->aux_state
);
2677 mt
->aux_state
= NULL
;
2681 mt
->aux_disable
|= INTEL_AUX_DISABLE_HIZ
;
2682 intel_miptree_hiz_buffer_free(mt
->hiz_buf
);
2685 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2686 mt
->level
[l
].has_hiz
= false;
2689 /* Any pending HiZ operations are no longer needed. Trying to execute
2690 * any will likely crash due to the missing aux buffer. So let's delete
2693 free(mt
->aux_state
);
2694 mt
->aux_state
= NULL
;
2700 * \brief Get pointer offset into stencil buffer.
2702 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2703 * must decode the tile's layout in software.
2706 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2708 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2710 * Even though the returned offset is always positive, the return type is
2712 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2713 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2716 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2718 uint32_t tile_size
= 4096;
2719 uint32_t tile_width
= 64;
2720 uint32_t tile_height
= 64;
2721 uint32_t row_size
= 64 * stride
;
2723 uint32_t tile_x
= x
/ tile_width
;
2724 uint32_t tile_y
= y
/ tile_height
;
2726 /* The byte's address relative to the tile's base addres. */
2727 uint32_t byte_x
= x
% tile_width
;
2728 uint32_t byte_y
= y
% tile_height
;
2730 uintptr_t u
= tile_y
* row_size
2731 + tile_x
* tile_size
2732 + 512 * (byte_x
/ 8)
2734 + 32 * ((byte_y
/ 4) % 2)
2735 + 16 * ((byte_x
/ 4) % 2)
2736 + 8 * ((byte_y
/ 2) % 2)
2737 + 4 * ((byte_x
/ 2) % 2)
2742 /* adjust for bit6 swizzling */
2743 if (((byte_x
/ 8) % 2) == 1) {
2744 if (((byte_y
/ 8) % 2) == 0) {
2756 intel_miptree_updownsample(struct brw_context
*brw
,
2757 struct intel_mipmap_tree
*src
,
2758 struct intel_mipmap_tree
*dst
)
2760 brw_blorp_blit_miptrees(brw
,
2761 src
, 0 /* level */, 0 /* layer */,
2762 src
->format
, SWIZZLE_XYZW
,
2763 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2765 src
->logical_width0
, src
->logical_height0
,
2767 dst
->logical_width0
, dst
->logical_height0
,
2768 GL_NEAREST
, false, false /*mirror x, y*/,
2771 if (src
->stencil_mt
) {
2772 brw_blorp_blit_miptrees(brw
,
2773 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2774 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2775 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2776 dst
->stencil_mt
->format
,
2778 src
->logical_width0
, src
->logical_height0
,
2780 dst
->logical_width0
, dst
->logical_height0
,
2781 GL_NEAREST
, false, false /*mirror x, y*/,
2782 false, false /* decode/encode srgb */);
2787 intel_update_r8stencil(struct brw_context
*brw
,
2788 struct intel_mipmap_tree
*mt
)
2790 assert(brw
->gen
>= 7);
2791 struct intel_mipmap_tree
*src
=
2792 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2793 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2796 if (!mt
->r8stencil_mt
) {
2797 const uint32_t r8stencil_flags
=
2798 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2799 MIPTREE_LAYOUT_DISABLE_AUX
;
2800 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2801 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2803 MESA_FORMAT_R_UINT8
,
2806 src
->logical_width0
,
2807 src
->logical_height0
,
2808 src
->logical_depth0
,
2811 assert(mt
->r8stencil_mt
);
2814 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2816 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2817 const unsigned depth
= src
->level
[level
].depth
;
2819 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2820 brw_blorp_copy_miptrees(brw
,
2824 minify(src
->logical_width0
, level
),
2825 minify(src
->logical_height0
, level
));
2829 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2830 src
->r8stencil_needs_update
= false;
2834 intel_miptree_map_raw(struct brw_context
*brw
,
2835 struct intel_mipmap_tree
*mt
,
2838 struct brw_bo
*bo
= mt
->bo
;
2840 if (brw_batch_references(&brw
->batch
, bo
))
2841 intel_batchbuffer_flush(brw
);
2843 return brw_bo_map(brw
, bo
, mode
);
2847 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2849 brw_bo_unmap(mt
->bo
);
2853 intel_miptree_map_gtt(struct brw_context
*brw
,
2854 struct intel_mipmap_tree
*mt
,
2855 struct intel_miptree_map
*map
,
2856 unsigned int level
, unsigned int slice
)
2858 unsigned int bw
, bh
;
2860 unsigned int image_x
, image_y
;
2861 intptr_t x
= map
->x
;
2862 intptr_t y
= map
->y
;
2864 /* For compressed formats, the stride is the number of bytes per
2865 * row of blocks. intel_miptree_get_image_offset() already does
2868 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2869 assert(y
% bh
== 0);
2870 assert(x
% bw
== 0);
2874 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
) + mt
->offset
;
2879 /* Note that in the case of cube maps, the caller must have passed the
2880 * slice number referencing the face.
2882 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2886 map
->stride
= mt
->pitch
;
2887 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2890 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2891 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2892 map
->x
, map
->y
, map
->w
, map
->h
,
2893 mt
, _mesa_get_format_name(mt
->format
),
2894 x
, y
, map
->ptr
, map
->stride
);
2898 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2900 intel_miptree_unmap_raw(mt
);
2904 intel_miptree_map_blit(struct brw_context
*brw
,
2905 struct intel_mipmap_tree
*mt
,
2906 struct intel_miptree_map
*map
,
2907 unsigned int level
, unsigned int slice
)
2909 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2910 /* first_level */ 0,
2914 MIPTREE_LAYOUT_TILING_NONE
);
2916 if (!map
->linear_mt
) {
2917 fprintf(stderr
, "Failed to allocate blit temporary\n");
2920 map
->stride
= map
->linear_mt
->pitch
;
2922 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2923 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2924 * invalidate is set, since we'll be writing the whole rectangle from our
2925 * temporary buffer back out.
2927 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2928 if (!intel_miptree_copy(brw
,
2929 mt
, level
, slice
, map
->x
, map
->y
,
2930 map
->linear_mt
, 0, 0, 0, 0,
2932 fprintf(stderr
, "Failed to blit\n");
2937 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
2939 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2940 map
->x
, map
->y
, map
->w
, map
->h
,
2941 mt
, _mesa_get_format_name(mt
->format
),
2942 level
, slice
, map
->ptr
, map
->stride
);
2947 intel_miptree_release(&map
->linear_mt
);
2953 intel_miptree_unmap_blit(struct brw_context
*brw
,
2954 struct intel_mipmap_tree
*mt
,
2955 struct intel_miptree_map
*map
,
2959 struct gl_context
*ctx
= &brw
->ctx
;
2961 intel_miptree_unmap_raw(map
->linear_mt
);
2963 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2964 bool ok
= intel_miptree_copy(brw
,
2965 map
->linear_mt
, 0, 0, 0, 0,
2966 mt
, level
, slice
, map
->x
, map
->y
,
2968 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2971 intel_miptree_release(&map
->linear_mt
);
2975 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2977 #if defined(USE_SSE41)
2979 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2980 struct intel_mipmap_tree
*mt
,
2981 struct intel_miptree_map
*map
,
2982 unsigned int level
, unsigned int slice
)
2984 assert(map
->mode
& GL_MAP_READ_BIT
);
2985 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2987 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2988 map
->x
, map
->y
, map
->w
, map
->h
,
2989 mt
, _mesa_get_format_name(mt
->format
),
2990 level
, slice
, map
->ptr
, map
->stride
);
2992 /* Map the original image */
2995 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2999 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3005 src
+= image_y
* mt
->pitch
;
3006 src
+= image_x
* mt
->cpp
;
3008 /* Due to the pixel offsets for the particular image being mapped, our
3009 * src pointer may not be 16-byte aligned. However, if the pitch is
3010 * divisible by 16, then the amount by which it's misaligned will remain
3011 * consistent from row to row.
3013 assert((mt
->pitch
% 16) == 0);
3014 const int misalignment
= ((uintptr_t) src
) & 15;
3016 /* Create an untiled temporary buffer for the mapping. */
3017 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3019 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3021 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3022 /* Offset the destination so it has the same misalignment as src. */
3023 map
->ptr
= map
->buffer
+ misalignment
;
3025 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3027 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3028 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3029 void *src_ptr
= src
+ y
* mt
->pitch
;
3031 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3034 intel_miptree_unmap_raw(mt
);
3038 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3039 struct intel_mipmap_tree
*mt
,
3040 struct intel_miptree_map
*map
,
3044 _mesa_align_free(map
->buffer
);
3051 intel_miptree_map_s8(struct brw_context
*brw
,
3052 struct intel_mipmap_tree
*mt
,
3053 struct intel_miptree_map
*map
,
3054 unsigned int level
, unsigned int slice
)
3056 map
->stride
= map
->w
;
3057 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3061 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3062 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3063 * invalidate is set, since we'll be writing the whole rectangle from our
3064 * temporary buffer back out.
3066 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3067 uint8_t *untiled_s8_map
= map
->ptr
;
3068 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3069 unsigned int image_x
, image_y
;
3071 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3073 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3074 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3075 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
3076 x
+ image_x
+ map
->x
,
3077 y
+ image_y
+ map
->y
,
3078 brw
->has_swizzling
);
3079 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3083 intel_miptree_unmap_raw(mt
);
3085 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3086 map
->x
, map
->y
, map
->w
, map
->h
,
3087 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3089 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3090 map
->x
, map
->y
, map
->w
, map
->h
,
3091 mt
, map
->ptr
, map
->stride
);
3096 intel_miptree_unmap_s8(struct brw_context
*brw
,
3097 struct intel_mipmap_tree
*mt
,
3098 struct intel_miptree_map
*map
,
3102 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3103 unsigned int image_x
, image_y
;
3104 uint8_t *untiled_s8_map
= map
->ptr
;
3105 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3107 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3109 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3110 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3111 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
3112 image_x
+ x
+ map
->x
,
3113 image_y
+ y
+ map
->y
,
3114 brw
->has_swizzling
);
3115 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3119 intel_miptree_unmap_raw(mt
);
3126 intel_miptree_map_etc(struct brw_context
*brw
,
3127 struct intel_mipmap_tree
*mt
,
3128 struct intel_miptree_map
*map
,
3132 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3133 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3134 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3137 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3138 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3140 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3141 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3142 map
->w
, map
->h
, 1));
3143 map
->ptr
= map
->buffer
;
3147 intel_miptree_unmap_etc(struct brw_context
*brw
,
3148 struct intel_mipmap_tree
*mt
,
3149 struct intel_miptree_map
*map
,
3155 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3160 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3161 + image_y
* mt
->pitch
3162 + image_x
* mt
->cpp
;
3164 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3165 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
3166 map
->ptr
, map
->stride
,
3169 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
3170 map
->ptr
, map
->stride
,
3171 map
->w
, map
->h
, mt
->etc_format
);
3173 intel_miptree_unmap_raw(mt
);
3178 * Mapping function for packed depth/stencil miptrees backed by real separate
3179 * miptrees for depth and stencil.
3181 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3182 * separate from the depth buffer. Yet at the GL API level, we have to expose
3183 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3184 * be able to map that memory for texture storage and glReadPixels-type
3185 * operations. We give Mesa core that access by mallocing a temporary and
3186 * copying the data between the actual backing store and the temporary.
3189 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3190 struct intel_mipmap_tree
*mt
,
3191 struct intel_miptree_map
*map
,
3192 unsigned int level
, unsigned int slice
)
3194 struct intel_mipmap_tree
*z_mt
= mt
;
3195 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3196 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3197 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3199 map
->stride
= map
->w
* packed_bpp
;
3200 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3204 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3205 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3206 * invalidate is set, since we'll be writing the whole rectangle from our
3207 * temporary buffer back out.
3209 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3210 uint32_t *packed_map
= map
->ptr
;
3211 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3212 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3213 unsigned int s_image_x
, s_image_y
;
3214 unsigned int z_image_x
, z_image_y
;
3216 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3217 &s_image_x
, &s_image_y
);
3218 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3219 &z_image_x
, &z_image_y
);
3221 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3222 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3223 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3224 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
3227 brw
->has_swizzling
);
3228 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3230 (map_x
+ z_image_x
));
3231 uint8_t s
= s_map
[s_offset
];
3232 uint32_t z
= z_map
[z_offset
];
3234 if (map_z32f_x24s8
) {
3235 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3236 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3238 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3243 intel_miptree_unmap_raw(s_mt
);
3244 intel_miptree_unmap_raw(z_mt
);
3246 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3248 map
->x
, map
->y
, map
->w
, map
->h
,
3249 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3250 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3251 map
->ptr
, map
->stride
);
3253 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3254 map
->x
, map
->y
, map
->w
, map
->h
,
3255 mt
, map
->ptr
, map
->stride
);
3260 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3261 struct intel_mipmap_tree
*mt
,
3262 struct intel_miptree_map
*map
,
3266 struct intel_mipmap_tree
*z_mt
= mt
;
3267 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3268 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3270 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3271 uint32_t *packed_map
= map
->ptr
;
3272 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3273 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3274 unsigned int s_image_x
, s_image_y
;
3275 unsigned int z_image_x
, z_image_y
;
3277 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3278 &s_image_x
, &s_image_y
);
3279 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3280 &z_image_x
, &z_image_y
);
3282 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3283 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3284 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
3285 x
+ s_image_x
+ map
->x
,
3286 y
+ s_image_y
+ map
->y
,
3287 brw
->has_swizzling
);
3288 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3290 (x
+ z_image_x
+ map
->x
));
3292 if (map_z32f_x24s8
) {
3293 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3294 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3296 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3297 s_map
[s_offset
] = packed
>> 24;
3298 z_map
[z_offset
] = packed
;
3303 intel_miptree_unmap_raw(s_mt
);
3304 intel_miptree_unmap_raw(z_mt
);
3306 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3308 map
->x
, map
->y
, map
->w
, map
->h
,
3309 z_mt
, _mesa_get_format_name(z_mt
->format
),
3310 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3311 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3312 map
->ptr
, map
->stride
);
3319 * Create and attach a map to the miptree at (level, slice). Return the
3322 static struct intel_miptree_map
*
3323 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3332 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3337 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3338 mt
->level
[level
].slice
[slice
].map
= map
;
3350 * Release the map at (level, slice).
3353 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3357 struct intel_miptree_map
**map
;
3359 map
= &mt
->level
[level
].slice
[slice
].map
;
3365 can_blit_slice(struct intel_mipmap_tree
*mt
,
3366 unsigned int level
, unsigned int slice
)
3368 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3369 if (mt
->pitch
>= 32768)
3376 use_intel_mipree_map_blit(struct brw_context
*brw
,
3377 struct intel_mipmap_tree
*mt
,
3383 /* It's probably not worth swapping to the blit ring because of
3384 * all the overhead involved.
3386 !(mode
& GL_MAP_WRITE_BIT
) &&
3388 (mt
->tiling
== I915_TILING_X
||
3389 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3390 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
3391 /* Fast copy blit on skl+ supports all tiling formats. */
3393 can_blit_slice(mt
, level
, slice
))
3396 if (mt
->tiling
!= I915_TILING_NONE
&&
3397 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3398 assert(can_blit_slice(mt
, level
, slice
));
3406 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3407 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3408 * arithmetic overflow.
3410 * If you call this function and use \a out_stride, then you're doing pointer
3411 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3412 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3413 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3414 * which usually have type uint32_t or GLuint.
3417 intel_miptree_map(struct brw_context
*brw
,
3418 struct intel_mipmap_tree
*mt
,
3427 ptrdiff_t *out_stride
)
3429 struct intel_miptree_map
*map
;
3431 assert(mt
->num_samples
<= 1);
3433 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3440 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3441 map
->mode
& GL_MAP_WRITE_BIT
);
3443 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3444 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3445 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3446 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3447 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3448 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3449 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3450 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3451 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3452 #if defined(USE_SSE41)
3453 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3454 !mt
->compressed
&& cpu_has_sse4_1
&&
3455 (mt
->pitch
% 16 == 0)) {
3456 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3459 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3462 *out_ptr
= map
->ptr
;
3463 *out_stride
= map
->stride
;
3465 if (map
->ptr
== NULL
)
3466 intel_miptree_release_map(mt
, level
, slice
);
3470 intel_miptree_unmap(struct brw_context
*brw
,
3471 struct intel_mipmap_tree
*mt
,
3475 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3477 assert(mt
->num_samples
<= 1);
3482 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3483 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3485 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3486 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3487 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3488 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3489 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3490 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3491 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3492 } else if (map
->linear_mt
) {
3493 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3494 #if defined(USE_SSE41)
3495 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3496 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3499 intel_miptree_unmap_gtt(mt
);
3502 intel_miptree_release_map(mt
, level
, slice
);
3506 get_isl_surf_dim(GLenum target
)
3510 case GL_TEXTURE_1D_ARRAY
:
3511 return ISL_SURF_DIM_1D
;
3514 case GL_TEXTURE_2D_ARRAY
:
3515 case GL_TEXTURE_RECTANGLE
:
3516 case GL_TEXTURE_CUBE_MAP
:
3517 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3518 case GL_TEXTURE_2D_MULTISAMPLE
:
3519 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3520 case GL_TEXTURE_EXTERNAL_OES
:
3521 return ISL_SURF_DIM_2D
;
3524 return ISL_SURF_DIM_3D
;
3527 unreachable("Invalid texture target");
3531 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3532 GLenum target
, enum miptree_array_layout array_layout
)
3534 if (array_layout
== GEN6_HIZ_STENCIL
)
3535 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
3539 case GL_TEXTURE_1D_ARRAY
:
3540 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3541 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3544 case GL_TEXTURE_2D_ARRAY
:
3545 case GL_TEXTURE_RECTANGLE
:
3546 case GL_TEXTURE_2D_MULTISAMPLE
:
3547 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3548 case GL_TEXTURE_EXTERNAL_OES
:
3549 return ISL_DIM_LAYOUT_GEN4_2D
;
3551 case GL_TEXTURE_CUBE_MAP
:
3552 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3553 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3554 ISL_DIM_LAYOUT_GEN4_2D
);
3557 return (devinfo
->gen
>= 9 ?
3558 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3561 unreachable("Invalid texture target");
3565 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3567 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3568 return ISL_TILING_W
;
3570 switch (mt
->tiling
) {
3571 case I915_TILING_NONE
:
3572 return ISL_TILING_LINEAR
;
3574 return ISL_TILING_X
;
3576 return ISL_TILING_Y0
;
3578 unreachable("Invalid tiling mode");
3584 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3585 const struct intel_mipmap_tree
*mt
,
3586 struct isl_surf
*surf
)
3588 surf
->dim
= get_isl_surf_dim(mt
->target
);
3589 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3590 mt
->tiling
, mt
->target
,
3593 if (mt
->num_samples
> 1) {
3594 switch (mt
->msaa_layout
) {
3595 case INTEL_MSAA_LAYOUT_IMS
:
3596 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3598 case INTEL_MSAA_LAYOUT_UMS
:
3599 case INTEL_MSAA_LAYOUT_CMS
:
3600 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3603 unreachable("Invalid MSAA layout");
3606 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3609 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3611 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3612 /* The ISL definition of row_pitch matches the surface state pitch field
3613 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3614 * the factor of 2 for W-tiling in row_pitch.
3616 surf
->row_pitch
= 2 * mt
->pitch
;
3618 surf
->row_pitch
= mt
->pitch
;
3621 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3623 if (brw
->gen
>= 9) {
3624 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3625 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3626 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3628 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3629 * alignment in terms of surface elements like we want.
3631 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3634 /* On earlier gens it's stored in pixels. */
3636 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3637 surf
->image_alignment_el
=
3638 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3641 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3642 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3643 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3644 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3645 surf
->logical_level0_px
.array_len
= 1;
3647 surf
->logical_level0_px
.depth
= 1;
3648 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3651 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3652 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3653 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3654 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3655 surf
->phys_level0_sa
.array_len
= 1;
3657 surf
->phys_level0_sa
.depth
= 1;
3658 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3661 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3662 surf
->samples
= MAX2(mt
->num_samples
, 1);
3664 surf
->size
= 0; /* TODO */
3665 surf
->alignment
= 0; /* TODO */
3667 switch (surf
->dim_layout
) {
3668 case ISL_DIM_LAYOUT_GEN4_2D
:
3669 case ISL_DIM_LAYOUT_GEN4_3D
:
3670 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
3671 if (brw
->gen
>= 9) {
3672 surf
->array_pitch_el_rows
= mt
->qpitch
;
3675 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3676 assert(mt
->qpitch
% bh
== 0);
3677 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3680 case ISL_DIM_LAYOUT_GEN9_1D
:
3681 surf
->array_pitch_el_rows
= 1;
3685 switch (mt
->array_layout
) {
3686 case ALL_LOD_IN_EACH_SLICE
:
3687 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3689 case ALL_SLICES_AT_EACH_LOD
:
3690 case GEN6_HIZ_STENCIL
:
3691 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3694 unreachable("Invalid array layout");
3697 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3698 switch (base_format
) {
3699 case GL_DEPTH_COMPONENT
:
3700 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3702 case GL_STENCIL_INDEX
:
3703 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3705 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3707 case GL_DEPTH_STENCIL
:
3708 /* In this case we only texture from the depth part */
3709 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3710 ISL_SURF_USAGE_TEXTURE_BIT
;
3713 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3714 if (brw
->format_supported_as_render_target
[mt
->format
])
3715 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3719 if (_mesa_is_cube_map_texture(mt
->target
))
3720 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3723 /* WARNING: THE SURFACE CREATED BY THIS FUNCTION IS NOT COMPLETE AND CANNOT BE
3724 * USED FOR ANY REAL CALCULATIONS. THE ONLY VALID USE OF SUCH A SURFACE IS TO
3725 * PASS IT INTO isl_surf_fill_state.
3728 intel_miptree_get_aux_isl_surf(struct brw_context
*brw
,
3729 const struct intel_mipmap_tree
*mt
,
3730 struct isl_surf
*surf
,
3731 enum isl_aux_usage
*usage
)
3733 uint32_t aux_pitch
, aux_qpitch
;
3735 aux_pitch
= mt
->mcs_buf
->pitch
;
3736 aux_qpitch
= mt
->mcs_buf
->qpitch
;
3738 if (mt
->num_samples
> 1) {
3739 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
3740 *usage
= ISL_AUX_USAGE_MCS
;
3741 } else if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
3742 assert(brw
->gen
>= 9);
3743 *usage
= ISL_AUX_USAGE_CCS_E
;
3744 } else if ((mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) == 0) {
3745 *usage
= ISL_AUX_USAGE_CCS_D
;
3747 unreachable("Invalid MCS miptree");
3749 } else if (mt
->hiz_buf
) {
3750 aux_pitch
= mt
->hiz_buf
->aux_base
.pitch
;
3751 aux_qpitch
= mt
->hiz_buf
->aux_base
.qpitch
;
3753 *usage
= ISL_AUX_USAGE_HIZ
;
3755 *usage
= ISL_AUX_USAGE_NONE
;
3759 /* Start with a copy of the original surface. */
3760 intel_miptree_get_isl_surf(brw
, mt
, surf
);
3762 /* Figure out the format and tiling of the auxiliary surface */
3764 case ISL_AUX_USAGE_NONE
:
3765 unreachable("Invalid auxiliary usage");
3767 case ISL_AUX_USAGE_HIZ
:
3768 isl_surf_get_hiz_surf(&brw
->isl_dev
, surf
, surf
);
3771 case ISL_AUX_USAGE_MCS
:
3774 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3775 * HALIGN 16 must be used."
3778 assert(mt
->halign
== 16);
3780 isl_surf_get_mcs_surf(&brw
->isl_dev
, surf
, surf
);
3783 case ISL_AUX_USAGE_CCS_D
:
3784 case ISL_AUX_USAGE_CCS_E
:
3786 * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
3788 * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
3790 * From the hardware spec for GEN9:
3792 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3793 * HALIGN 16 must be used."
3795 assert(mt
->num_samples
<= 1);
3797 assert(mt
->halign
== 16);
3799 isl_surf_get_ccs_surf(&brw
->isl_dev
, surf
, surf
);
3803 /* We want the pitch of the actual aux buffer. */
3804 surf
->row_pitch
= aux_pitch
;
3806 /* Auxiliary surfaces in ISL have compressed formats and array_pitch_el_rows
3807 * is in elements. This doesn't match intel_mipmap_tree::qpitch which is
3808 * in elements of the primary color surface so we have to divide by the
3809 * compression block height.
3811 surf
->array_pitch_el_rows
=
3812 aux_qpitch
/ isl_format_get_layout(surf
->format
)->bh
;