2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_image.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
,
55 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
58 intel_miptree_alloc_aux(struct brw_context
*brw
,
59 struct intel_mipmap_tree
*mt
);
62 is_mcs_supported(const struct brw_context
*brw
, mesa_format format
,
63 uint32_t layout_flags
)
65 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
69 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
70 switch (_mesa_get_format_base_format(format
)) {
71 case GL_DEPTH_COMPONENT
:
72 case GL_STENCIL_INDEX
:
73 case GL_DEPTH_STENCIL
:
76 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
78 * This field must be set to 0 for all SINT MSRTs when all RT channels
81 * In practice this means that we have to disable MCS for all signed
82 * integer MSAA buffers. The alternative, to disable MCS only when one
83 * of the render target channels is disabled, is impractical because it
84 * would require converting between CMS and UMS MSAA layouts on the fly,
87 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
89 } else if (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) {
90 /* We can't use the CMS layout because it uses an aux buffer, the MCS
91 * buffer. So fallback to UMS, which is identical to CMS without the
101 intel_tiling_supports_ccs(const struct brw_context
*brw
,
102 enum isl_tiling tiling
)
104 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
105 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
107 * - Support is limited to tiled render targets.
109 * Gen9 changes the restriction to Y-tile only.
112 return tiling
== ISL_TILING_Y0
;
113 else if (brw
->gen
>= 7)
114 return tiling
!= ISL_TILING_LINEAR
;
120 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
121 * can be used. This doesn't (and should not) inspect any of the properties of
124 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
125 * beneath the "Fast Color Clear" bullet (p326):
127 * - Support is for non-mip-mapped and non-array surface types only.
129 * And then later, on p327:
131 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
134 * From the Skylake documentation, it is made clear that X-tiling is no longer
137 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
141 intel_miptree_supports_ccs(struct brw_context
*brw
,
142 const struct intel_mipmap_tree
*mt
)
144 /* MCS support does not exist prior to Gen7 */
148 /* This function applies only to non-multisampled render targets. */
149 if (mt
->surf
.samples
> 1)
152 /* MCS is only supported for color buffers */
153 switch (_mesa_get_format_base_format(mt
->format
)) {
154 case GL_DEPTH_COMPONENT
:
155 case GL_DEPTH_STENCIL
:
156 case GL_STENCIL_INDEX
:
160 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
163 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
164 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
165 mt
->surf
.logical_level0_px
.depth
> 1;
168 /* Multisample surfaces with the CMS layout are not layered surfaces,
169 * yet still have physical_depth0 > 1. Assert that we don't
170 * accidentally reject a multisampled surface here. We should have
171 * rejected it earlier by explicitly checking the sample count.
173 assert(mt
->surf
.samples
== 1);
176 /* Handle the hardware restrictions...
178 * All GENs have the following restriction: "MCS buffer for non-MSRT is
179 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
181 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
182 * Non-MultiSampler Render Target Restrictions) Support is for
183 * non-mip-mapped and non-array surface types only.
185 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
186 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
187 * surfaces are supported with MCS buffer layout with these alignments in
188 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
190 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
191 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
192 * surfaces are supported with MCS buffer layout with these alignments in
193 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
195 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
198 /* There's no point in using an MCS buffer if the surface isn't in a
201 if (!brw
->mesa_format_supports_render
[mt
->format
])
208 intel_tiling_supports_hiz(const struct brw_context
*brw
,
209 enum isl_tiling tiling
)
214 return tiling
== ISL_TILING_Y0
;
218 intel_miptree_supports_hiz(const struct brw_context
*brw
,
219 const struct intel_mipmap_tree
*mt
)
224 switch (mt
->format
) {
225 case MESA_FORMAT_Z_FLOAT32
:
226 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
227 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
228 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
229 case MESA_FORMAT_Z_UNORM16
:
237 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
238 const struct intel_mipmap_tree
*mt
)
243 /* For now compression is only enabled for integer formats even though
244 * there exist supported floating point formats also. This is a heuristic
245 * decision based on current public benchmarks. In none of the cases these
246 * formats provided any improvement but a few cases were seen to regress.
247 * Hence these are left to to be enabled in the future when they are known
250 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
253 if (!intel_miptree_supports_ccs(brw
, mt
))
256 /* Many window system buffers are sRGB even if they are never rendered as
257 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
258 * surface is used as sRGB, we fall back to CCS_D.
260 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
261 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
262 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
266 * Determine depth format corresponding to a depth+stencil format,
267 * for separate stencil.
270 intel_depth_format_for_depthstencil_format(mesa_format format
) {
272 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
273 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
274 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
275 return MESA_FORMAT_Z_FLOAT32
;
282 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
283 unsigned depth0
, struct intel_mipmap_level
*table
)
285 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
287 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
289 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
290 if (!table
[level
].slice
)
297 for (unsigned level
= first_level
; level
<= last_level
; level
++)
298 free(table
[level
].slice
);
304 needs_separate_stencil(const struct brw_context
*brw
,
305 struct intel_mipmap_tree
*mt
,
306 mesa_format format
, uint32_t layout_flags
)
309 if (layout_flags
& MIPTREE_LAYOUT_FOR_BO
)
312 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
315 if (brw
->must_use_separate_stencil
)
318 return brw
->has_separate_stencil
&&
319 intel_miptree_supports_hiz(brw
, mt
);
323 * Choose the aux usage for this miptree. This function must be called fairly
324 * late in the miptree create process after we have a tiling.
327 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
328 struct intel_mipmap_tree
*mt
)
330 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
332 const unsigned no_flags
= 0;
333 if (mt
->surf
.samples
> 1 && is_mcs_supported(brw
, mt
->format
, no_flags
)) {
334 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
335 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
336 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
337 intel_miptree_supports_ccs(brw
, mt
)) {
338 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
339 intel_miptree_supports_ccs_e(brw
, mt
)) {
340 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
342 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
344 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
345 intel_miptree_supports_hiz(brw
, mt
)) {
346 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
349 /* We can do fast-clear on all auxiliary surface types that are
350 * allocated through the normal texture creation paths.
352 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
353 mt
->supports_fast_clear
= true;
358 * Choose an appropriate uncompressed format for a requested
359 * compressed format, if unsupported.
362 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
364 /* No need to lower ETC formats on these platforms,
365 * they are supported natively.
367 if (brw
->gen
>= 8 || brw
->is_baytrail
)
371 case MESA_FORMAT_ETC1_RGB8
:
372 return MESA_FORMAT_R8G8B8X8_UNORM
;
373 case MESA_FORMAT_ETC2_RGB8
:
374 return MESA_FORMAT_R8G8B8X8_UNORM
;
375 case MESA_FORMAT_ETC2_SRGB8
:
376 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
377 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
378 return MESA_FORMAT_B8G8R8A8_SRGB
;
379 case MESA_FORMAT_ETC2_RGBA8_EAC
:
380 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
381 return MESA_FORMAT_R8G8B8A8_UNORM
;
382 case MESA_FORMAT_ETC2_R11_EAC
:
383 return MESA_FORMAT_R_UNORM16
;
384 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
385 return MESA_FORMAT_R_SNORM16
;
386 case MESA_FORMAT_ETC2_RG11_EAC
:
387 return MESA_FORMAT_R16G16_UNORM
;
388 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
389 return MESA_FORMAT_R16G16_SNORM
;
391 /* Non ETC1 / ETC2 format */
397 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
399 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
400 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
402 return mt
->surf
.logical_level0_px
.array_len
;
406 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
408 /* In case of physical dimensions one needs to consider also the layout.
409 * See isl_calc_phys_level0_extent_sa().
411 if (surf
->dim
!= ISL_SURF_DIM_3D
)
412 return surf
->phys_level0_sa
.array_len
;
414 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
415 return minify(surf
->phys_level0_sa
.array_len
, level
);
417 return minify(surf
->phys_level0_sa
.depth
, level
);
420 /** \brief Assert that the level and layer are valid for the miptree. */
422 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
430 assert(level
>= mt
->first_level
);
431 assert(level
<= mt
->last_level
);
432 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
435 static enum isl_aux_state
**
436 create_aux_state_map(struct intel_mipmap_tree
*mt
,
437 enum isl_aux_state initial
)
439 const uint32_t levels
= mt
->last_level
+ 1;
441 uint32_t total_slices
= 0;
442 for (uint32_t level
= 0; level
< levels
; level
++)
443 total_slices
+= brw_get_num_logical_layers(mt
, level
);
445 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
447 /* We're going to allocate a single chunk of data for both the per-level
448 * reference array and the arrays of aux_state. This makes cleanup
449 * significantly easier.
451 const size_t total_size
= per_level_array_size
+
452 total_slices
* sizeof(enum isl_aux_state
);
453 void *data
= malloc(total_size
);
457 enum isl_aux_state
**per_level_arr
= data
;
458 enum isl_aux_state
*s
= data
+ per_level_array_size
;
459 for (uint32_t level
= 0; level
< levels
; level
++) {
460 per_level_arr
[level
] = s
;
461 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
462 for (uint32_t a
= 0; a
< level_layers
; a
++)
465 assert((void *)s
== data
+ total_size
);
467 return per_level_arr
;
471 free_aux_state_map(enum isl_aux_state
**state
)
477 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
478 enum isl_tiling tiling
, unsigned samples
)
483 if (tiling
== ISL_TILING_LINEAR
)
486 /* If the width is much smaller than a tile, don't bother tiling. */
490 if (ALIGN(row_pitch
, 512) >= 32768) {
491 perf_debug("row pitch %u too large to blit, falling back to untiled",
500 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
501 enum isl_tiling tiling
)
503 /* If the BO is too large to fit in the aperture, we need to use the
504 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
505 * handle Y-tiling, so we need to fall back to X.
507 if (brw
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
508 tiling
== ISL_TILING_Y0
)
514 static struct intel_mipmap_tree
*
515 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
516 unsigned first_level
, unsigned last_level
,
517 unsigned width0
, unsigned height0
, unsigned depth0
,
518 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
519 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
520 unsigned row_pitch
, struct brw_bo
*bo
)
522 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
526 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
534 if (target
== GL_TEXTURE_CUBE_MAP
||
535 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
536 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
538 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
540 _mesa_enum_to_string(target
),
541 _mesa_get_format_name(format
),
542 num_samples
, width0
, height0
, depth0
,
543 first_level
, last_level
, mt
);
545 struct isl_surf_init_info init_info
= {
546 .dim
= get_isl_surf_dim(target
),
547 .format
= translate_tex_format(brw
, format
, false),
550 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
551 .levels
= last_level
- first_level
+ 1,
552 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
553 .samples
= num_samples
,
554 .row_pitch
= row_pitch
,
555 .usage
= isl_usage_flags
,
556 .tiling_flags
= tiling_flags
,
559 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
562 /* In case caller doesn't specifically request Y-tiling (needed
563 * unconditionally for depth), check for corner cases needing special
566 if (tiling_flags
& ~ISL_TILING_Y0_BIT
) {
567 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
568 mt
->surf
.tiling
, mt
->surf
.samples
)) {
569 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
570 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
572 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
573 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
574 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
579 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
580 * the size may not be multiple of row_pitch.
581 * See isl_apply_surface_padding().
583 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
584 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
587 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
589 isl_tiling_to_i915_tiling(
591 mt
->surf
.row_pitch
, alloc_flags
);
598 mt
->first_level
= first_level
;
599 mt
->last_level
= last_level
;
602 mt
->aux_state
= NULL
;
603 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
604 mt
->compressed
= _mesa_is_format_compressed(format
);
609 intel_miptree_release(&mt
);
614 make_separate_stencil_surface(struct brw_context
*brw
,
615 struct intel_mipmap_tree
*mt
)
617 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
618 0, mt
->surf
.levels
- 1,
619 mt
->surf
.logical_level0_px
.width
,
620 mt
->surf
.logical_level0_px
.height
,
621 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
622 mt
->surf
.logical_level0_px
.depth
:
623 mt
->surf
.logical_level0_px
.array_len
,
624 mt
->surf
.samples
, ISL_TILING_W_BIT
,
625 ISL_SURF_USAGE_STENCIL_BIT
|
626 ISL_SURF_USAGE_TEXTURE_BIT
,
627 BO_ALLOC_FOR_RENDER
, 0, NULL
);
632 mt
->stencil_mt
->r8stencil_needs_update
= true;
638 force_linear_tiling(uint32_t layout_flags
)
640 /* ANY includes NONE and Y bit. */
641 if (layout_flags
& MIPTREE_LAYOUT_TILING_Y
)
644 return layout_flags
& MIPTREE_LAYOUT_TILING_NONE
;
647 static struct intel_mipmap_tree
*
648 miptree_create(struct brw_context
*brw
,
657 uint32_t layout_flags
)
659 if (format
== MESA_FORMAT_S_UINT8
)
660 return make_surface(brw
, target
, format
, first_level
, last_level
,
661 width0
, height0
, depth0
, num_samples
,
663 ISL_SURF_USAGE_STENCIL_BIT
|
664 ISL_SURF_USAGE_TEXTURE_BIT
,
669 const GLenum base_format
= _mesa_get_format_base_format(format
);
670 if ((base_format
== GL_DEPTH_COMPONENT
||
671 base_format
== GL_DEPTH_STENCIL
) &&
672 !force_linear_tiling(layout_flags
)) {
673 /* Fix up the Z miptree format for how we're splitting out separate
674 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
676 const mesa_format depth_only_format
=
677 intel_depth_format_for_depthstencil_format(format
);
678 struct intel_mipmap_tree
*mt
= make_surface(
679 brw
, target
, brw
->gen
>= 6 ? depth_only_format
: format
,
680 first_level
, last_level
,
681 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
682 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
683 BO_ALLOC_FOR_RENDER
, 0, NULL
);
685 if (needs_separate_stencil(brw
, mt
, format
, layout_flags
) &&
686 !make_separate_stencil_surface(brw
, mt
)) {
687 intel_miptree_release(&mt
);
691 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
692 intel_miptree_choose_aux_usage(brw
, mt
);
697 mesa_format tex_format
= format
;
698 mesa_format etc_format
= MESA_FORMAT_NONE
;
699 uint32_t alloc_flags
= 0;
701 format
= intel_lower_compressed_format(brw
, format
);
703 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
705 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
706 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
707 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
709 isl_tiling_flags_t tiling_flags
= force_linear_tiling(layout_flags
) ?
710 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
712 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
714 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
716 struct intel_mipmap_tree
*mt
= make_surface(
718 first_level
, last_level
,
719 width0
, height0
, depth0
,
720 num_samples
, tiling_flags
,
721 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
722 ISL_SURF_USAGE_TEXTURE_BIT
,
723 alloc_flags
, 0, NULL
);
727 mt
->etc_format
= etc_format
;
729 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
730 mt
->bo
->cache_coherent
= false;
732 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
733 intel_miptree_choose_aux_usage(brw
, mt
);
738 struct intel_mipmap_tree
*
739 intel_miptree_create(struct brw_context
*brw
,
748 uint32_t layout_flags
)
750 assert(num_samples
> 0);
752 struct intel_mipmap_tree
*mt
= miptree_create(
754 first_level
, last_level
,
755 width0
, height0
, depth0
, num_samples
,
762 if (!intel_miptree_alloc_aux(brw
, mt
)) {
763 intel_miptree_release(&mt
);
770 struct intel_mipmap_tree
*
771 intel_miptree_create_for_bo(struct brw_context
*brw
,
779 uint32_t layout_flags
)
781 struct intel_mipmap_tree
*mt
;
782 uint32_t tiling
, swizzle
;
783 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
784 const GLenum base_format
= _mesa_get_format_base_format(format
);
786 if ((base_format
== GL_DEPTH_COMPONENT
||
787 base_format
== GL_DEPTH_STENCIL
)) {
788 const mesa_format depth_only_format
=
789 intel_depth_format_for_depthstencil_format(format
);
790 mt
= make_surface(brw
, target
,
791 brw
->gen
>= 6 ? depth_only_format
: format
,
792 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
793 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
794 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
798 brw_bo_reference(bo
);
800 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
801 intel_miptree_choose_aux_usage(brw
, mt
);
804 } else if (format
== MESA_FORMAT_S_UINT8
) {
805 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
806 0, 0, width
, height
, depth
, 1,
808 ISL_SURF_USAGE_STENCIL_BIT
|
809 ISL_SURF_USAGE_TEXTURE_BIT
,
810 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
814 assert(bo
->size
>= mt
->surf
.size
);
816 brw_bo_reference(bo
);
820 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
822 /* Nothing will be able to use this miptree with the BO if the offset isn't
825 if (tiling
!= I915_TILING_NONE
)
826 assert(offset
% 4096 == 0);
828 /* miptrees can't handle negative pitch. If you need flipping of images,
829 * that's outside of the scope of the mt.
833 /* The BO already has a tiling format and we shouldn't confuse the lower
834 * layers by making it try to find a tiling format again.
836 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
837 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
839 mt
= make_surface(brw
, target
, format
,
840 0, 0, width
, height
, depth
, 1,
841 1lu << isl_tiling_from_i915_tiling(tiling
),
842 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
843 ISL_SURF_USAGE_TEXTURE_BIT
,
848 brw_bo_reference(bo
);
852 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
853 intel_miptree_choose_aux_usage(brw
, mt
);
858 static struct intel_mipmap_tree
*
859 miptree_create_for_planar_image(struct brw_context
*brw
,
860 __DRIimage
*image
, GLenum target
)
862 struct intel_image_format
*f
= image
->planar_format
;
863 struct intel_mipmap_tree
*planar_mt
= NULL
;
865 for (int i
= 0; i
< f
->nplanes
; i
++) {
866 const int index
= f
->planes
[i
].buffer_index
;
867 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
868 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
869 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
870 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
872 /* Disable creation of the texture's aux buffers because the driver
873 * exposes no EGL API to manage them. That is, there is no API for
874 * resolving the aux buffer's content to the main buffer nor for
875 * invalidating the aux buffer's content.
877 struct intel_mipmap_tree
*mt
=
878 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
879 image
->offsets
[index
],
881 image
->strides
[index
],
882 MIPTREE_LAYOUT_DISABLE_AUX
);
891 planar_mt
->plane
[i
- 1] = mt
;
897 struct intel_mipmap_tree
*
898 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
899 __DRIimage
*image
, GLenum target
,
900 enum isl_colorspace colorspace
,
901 bool is_winsys_image
)
903 if (image
->planar_format
&& image
->planar_format
->nplanes
> 0) {
904 assert(colorspace
== ISL_COLORSPACE_NONE
||
905 colorspace
== ISL_COLORSPACE_YUV
);
906 return miptree_create_for_planar_image(brw
, image
, target
);
909 mesa_format format
= image
->format
;
910 switch (colorspace
) {
911 case ISL_COLORSPACE_NONE
:
912 /* Keep the image format unmodified */
915 case ISL_COLORSPACE_LINEAR
:
916 format
=_mesa_get_srgb_format_linear(format
);
919 case ISL_COLORSPACE_SRGB
:
920 format
=_mesa_get_linear_format_srgb(format
);
924 unreachable("Inalid colorspace for non-planar image");
927 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
928 /* The texture storage paths in core Mesa detect if the driver does not
929 * support the user-requested format, and then searches for a
930 * fallback format. The DRIimage code bypasses core Mesa, though. So we
931 * do the fallbacks here for important formats.
933 * We must support DRM_FOURCC_XBGR8888 textures because the Android
934 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
935 * the Chrome OS compositor consumes as dma_buf EGLImages.
937 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
940 if (!brw
->ctx
.TextureFormatSupported
[format
])
943 /* If this image comes in from a window system, we have different
944 * requirements than if it comes in via an EGL import operation. Window
945 * system images can use any form of auxiliary compression we wish because
946 * they get "flushed" before being handed off to the window system and we
947 * have the opportunity to do resolves. Window system buffers also may be
948 * used for scanout so we need to flag that appropriately.
950 const uint32_t mt_layout_flags
=
951 is_winsys_image
? MIPTREE_LAYOUT_FOR_SCANOUT
: MIPTREE_LAYOUT_DISABLE_AUX
;
953 /* Disable creation of the texture's aux buffers because the driver exposes
954 * no EGL API to manage them. That is, there is no API for resolving the aux
955 * buffer's content to the main buffer nor for invalidating the aux buffer's
958 struct intel_mipmap_tree
*mt
=
959 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
960 image
->offset
, image
->width
, image
->height
, 1,
961 image
->pitch
, mt_layout_flags
);
966 mt
->level
[0].level_x
= image
->tile_x
;
967 mt
->level
[0].level_y
= image
->tile_y
;
969 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
970 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
971 * trouble resolving back to destination image due to alignment issues.
973 if (!brw
->has_surface_tile_offset
) {
974 uint32_t draw_x
, draw_y
;
975 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
977 if (draw_x
!= 0 || draw_y
!= 0) {
978 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
979 intel_miptree_release(&mt
);
984 if (!intel_miptree_alloc_aux(brw
, mt
)) {
985 intel_miptree_release(&mt
);
993 * For a singlesample renderbuffer, this simply wraps the given BO with a
996 * For a multisample renderbuffer, this wraps the window system's
997 * (singlesample) BO with a singlesample miptree attached to the
998 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
999 * that will contain the actual rendering (which is lazily resolved to
1000 * irb->singlesample_mt).
1003 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1004 struct intel_renderbuffer
*irb
,
1005 struct intel_mipmap_tree
*singlesample_mt
,
1006 uint32_t width
, uint32_t height
,
1009 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1010 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1011 mesa_format format
= rb
->Format
;
1012 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1014 /* Only the front and back buffers, which are color buffers, are allocated
1015 * through the image loader.
1017 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1018 _mesa_get_format_base_format(format
) == GL_RGBA
);
1020 assert(singlesample_mt
);
1022 if (num_samples
== 1) {
1023 intel_miptree_release(&irb
->mt
);
1024 irb
->mt
= singlesample_mt
;
1026 assert(!irb
->singlesample_mt
);
1028 intel_miptree_release(&irb
->singlesample_mt
);
1029 irb
->singlesample_mt
= singlesample_mt
;
1032 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1033 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1034 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1039 if (!multisample_mt
)
1042 irb
->need_downsample
= false;
1043 intel_miptree_release(&irb
->mt
);
1044 irb
->mt
= multisample_mt
;
1050 intel_miptree_release(&irb
->mt
);
1054 struct intel_mipmap_tree
*
1055 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1059 uint32_t num_samples
)
1061 struct intel_mipmap_tree
*mt
;
1063 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1064 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1065 MIPTREE_LAYOUT_TILING_ANY
;
1067 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1068 width
, height
, depth
, num_samples
,
1076 intel_miptree_release(&mt
);
1081 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1082 struct intel_mipmap_tree
*src
)
1087 intel_miptree_release(dst
);
1091 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1098 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1100 if (aux_buf
== NULL
)
1103 brw_bo_unreference(aux_buf
->bo
);
1109 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1114 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1115 if (--(*mt
)->refcount
<= 0) {
1118 DBG("%s deleting %p\n", __func__
, *mt
);
1120 brw_bo_unreference((*mt
)->bo
);
1121 intel_miptree_release(&(*mt
)->stencil_mt
);
1122 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1123 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1124 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1125 free_aux_state_map((*mt
)->aux_state
);
1127 intel_miptree_release(&(*mt
)->plane
[0]);
1128 intel_miptree_release(&(*mt
)->plane
[1]);
1130 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1131 free((*mt
)->level
[i
].slice
);
1141 intel_get_image_dims(struct gl_texture_image
*image
,
1142 int *width
, int *height
, int *depth
)
1144 switch (image
->TexObject
->Target
) {
1145 case GL_TEXTURE_1D_ARRAY
:
1146 /* For a 1D Array texture the OpenGL API will treat the image height as
1147 * the number of array slices. For Intel hardware, we treat the 1D array
1148 * as a 2D Array with a height of 1. So, here we want to swap image
1151 assert(image
->Depth
== 1);
1152 *width
= image
->Width
;
1154 *depth
= image
->Height
;
1156 case GL_TEXTURE_CUBE_MAP
:
1157 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1158 * though we really have 6 slices.
1160 assert(image
->Depth
== 1);
1161 *width
= image
->Width
;
1162 *height
= image
->Height
;
1166 *width
= image
->Width
;
1167 *height
= image
->Height
;
1168 *depth
= image
->Depth
;
1174 * Can the image be pulled into a unified mipmap tree? This mirrors
1175 * the completeness test in a lot of ways.
1177 * Not sure whether I want to pass gl_texture_image here.
1180 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1181 struct gl_texture_image
*image
)
1183 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1184 GLuint level
= intelImage
->base
.Base
.Level
;
1185 int width
, height
, depth
;
1187 /* glTexImage* choose the texture object based on the target passed in, and
1188 * objects can't change targets over their lifetimes, so this should be
1191 assert(image
->TexObject
->Target
== mt
->target
);
1193 mesa_format mt_format
= mt
->format
;
1194 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1195 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1196 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1197 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1198 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1199 mt_format
= mt
->etc_format
;
1201 if (image
->TexFormat
!= mt_format
)
1204 intel_get_image_dims(image
, &width
, &height
, &depth
);
1206 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1209 if (level
>= mt
->surf
.levels
)
1212 const unsigned level_depth
=
1213 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1214 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1215 mt
->surf
.logical_level0_px
.array_len
;
1217 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1218 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1219 depth
== level_depth
&&
1220 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1224 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1225 GLuint level
, GLuint slice
,
1226 GLuint
*x
, GLuint
*y
)
1228 if (level
== 0 && slice
== 0) {
1229 *x
= mt
->level
[0].level_x
;
1230 *y
= mt
->level
[0].level_y
;
1234 uint32_t x_offset_sa
, y_offset_sa
;
1236 /* Miptree itself can have an offset only if it represents a single
1237 * slice in an imported buffer object.
1238 * See intel_miptree_create_for_dri_image().
1240 assert(mt
->level
[0].level_x
== 0);
1241 assert(mt
->level
[0].level_y
== 0);
1243 /* Given level is relative to level zero while the miptree may be
1244 * represent just a subset of all levels starting from 'first_level'.
1246 assert(level
>= mt
->first_level
);
1247 level
-= mt
->first_level
;
1249 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1250 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1251 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1252 &x_offset_sa
, &y_offset_sa
);
1260 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1261 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1262 * and tile_h is set to 1.
1265 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1266 uint32_t *tile_w
, uint32_t *tile_h
)
1277 case ISL_TILING_LINEAR
:
1282 unreachable("not reached");
1288 * This function computes masks that may be used to select the bits of the X
1289 * and Y coordinates that indicate the offset within a tile. If the BO is
1290 * untiled, the masks are set to 0.
1293 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1294 uint32_t *mask_x
, uint32_t *mask_y
)
1296 uint32_t tile_w_bytes
, tile_h
;
1298 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1300 *mask_x
= tile_w_bytes
/ cpp
- 1;
1301 *mask_y
= tile_h
- 1;
1305 * Compute the offset (in bytes) from the start of the BO to the given x
1306 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1307 * multiples of the tile size.
1310 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1311 uint32_t x
, uint32_t y
)
1314 uint32_t pitch
= mt
->surf
.row_pitch
;
1316 switch (mt
->surf
.tiling
) {
1318 unreachable("not reached");
1319 case ISL_TILING_LINEAR
:
1320 return y
* pitch
+ x
* cpp
;
1322 assert((x
% (512 / cpp
)) == 0);
1323 assert((y
% 8) == 0);
1324 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1326 assert((x
% (128 / cpp
)) == 0);
1327 assert((y
% 32) == 0);
1328 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1333 * Rendering with tiled buffers requires that the base address of the buffer
1334 * be aligned to a page boundary. For renderbuffers, and sometimes with
1335 * textures, we may want the surface to point at a texture image level that
1336 * isn't at a page boundary.
1338 * This function returns an appropriately-aligned base offset
1339 * according to the tiling restrictions, plus any required x/y offset
1343 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1344 GLuint level
, GLuint slice
,
1349 uint32_t mask_x
, mask_y
;
1351 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1352 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1354 *tile_x
= x
& mask_x
;
1355 *tile_y
= y
& mask_y
;
1357 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1361 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1362 struct intel_mipmap_tree
*src_mt
,
1363 unsigned src_level
, unsigned src_layer
,
1364 struct intel_mipmap_tree
*dst_mt
,
1365 unsigned dst_level
, unsigned dst_layer
,
1366 unsigned width
, unsigned height
)
1369 ptrdiff_t src_stride
, dst_stride
;
1370 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1372 intel_miptree_map(brw
, src_mt
,
1373 src_level
, src_layer
,
1376 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1379 intel_miptree_map(brw
, dst_mt
,
1380 dst_level
, dst_layer
,
1383 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1387 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1388 _mesa_get_format_name(src_mt
->format
),
1389 src_mt
, src
, src_stride
,
1390 _mesa_get_format_name(dst_mt
->format
),
1391 dst_mt
, dst
, dst_stride
,
1394 int row_size
= cpp
* width
;
1395 if (src_stride
== row_size
&&
1396 dst_stride
== row_size
) {
1397 memcpy(dst
, src
, row_size
* height
);
1399 for (int i
= 0; i
< height
; i
++) {
1400 memcpy(dst
, src
, row_size
);
1406 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1407 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1409 /* Don't forget to copy the stencil data over, too. We could have skipped
1410 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1411 * shuffling the two data sources in/out of temporary storage instead of
1412 * the direct mapping we get this way.
1414 if (dst_mt
->stencil_mt
) {
1415 assert(src_mt
->stencil_mt
);
1416 intel_miptree_copy_slice_sw(brw
,
1417 src_mt
->stencil_mt
, src_level
, src_layer
,
1418 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1424 intel_miptree_copy_slice(struct brw_context
*brw
,
1425 struct intel_mipmap_tree
*src_mt
,
1426 unsigned src_level
, unsigned src_layer
,
1427 struct intel_mipmap_tree
*dst_mt
,
1428 unsigned dst_level
, unsigned dst_layer
)
1431 mesa_format format
= src_mt
->format
;
1432 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1433 src_level
- src_mt
->first_level
);
1434 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1435 src_level
- src_mt
->first_level
);
1437 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1438 src_level
- src_mt
->first_level
));
1440 assert(src_mt
->format
== dst_mt
->format
);
1442 if (dst_mt
->compressed
) {
1444 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1445 height
= ALIGN_NPOT(height
, j
) / j
;
1446 width
= ALIGN_NPOT(width
, i
) / i
;
1449 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1450 * below won't apply since we can't do the depth's Y tiling or the
1451 * stencil's W tiling in the blitter.
1453 if (src_mt
->stencil_mt
) {
1454 intel_miptree_copy_slice_sw(brw
,
1455 src_mt
, src_level
, src_layer
,
1456 dst_mt
, dst_level
, dst_layer
,
1461 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1462 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1464 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1467 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1468 _mesa_get_format_name(src_mt
->format
),
1469 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1470 _mesa_get_format_name(dst_mt
->format
),
1471 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1474 if (!intel_miptree_blit(brw
,
1475 src_mt
, src_level
, src_layer
, 0, 0, false,
1476 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1477 width
, height
, GL_COPY
)) {
1478 perf_debug("miptree validate blit for %s failed\n",
1479 _mesa_get_format_name(format
));
1481 intel_miptree_copy_slice_sw(brw
,
1482 src_mt
, src_level
, src_layer
,
1483 dst_mt
, dst_level
, dst_layer
,
1489 * Copies the image's current data to the given miptree, and associates that
1490 * miptree with the image.
1492 * If \c invalidate is true, then the actual image data does not need to be
1493 * copied, but the image still needs to be associated to the new miptree (this
1494 * is set to true if we're about to clear the image).
1497 intel_miptree_copy_teximage(struct brw_context
*brw
,
1498 struct intel_texture_image
*intelImage
,
1499 struct intel_mipmap_tree
*dst_mt
,
1502 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1503 struct intel_texture_object
*intel_obj
=
1504 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1505 int level
= intelImage
->base
.Base
.Level
;
1506 const unsigned face
= intelImage
->base
.Base
.Face
;
1507 unsigned start_layer
, end_layer
;
1509 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1511 assert(intelImage
->base
.Base
.Height
);
1513 end_layer
= intelImage
->base
.Base
.Height
- 1;
1514 } else if (face
> 0) {
1518 assert(intelImage
->base
.Base
.Depth
);
1520 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1524 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1525 intel_miptree_copy_slice(brw
,
1531 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1532 intel_obj
->needs_validate
= true;
1536 intel_miptree_init_mcs(struct brw_context
*brw
,
1537 struct intel_mipmap_tree
*mt
,
1540 assert(mt
->mcs_buf
!= NULL
);
1542 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1544 * When MCS buffer is enabled and bound to MSRT, it is required that it
1545 * is cleared prior to any rendering.
1547 * Since we don't use the MCS buffer for any purpose other than rendering,
1548 * it makes sense to just clear it immediately upon allocation.
1550 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1552 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1553 if (unlikely(map
== NULL
)) {
1554 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1555 brw_bo_unreference(mt
->mcs_buf
->bo
);
1560 memset(data
, init_value
, mt
->mcs_buf
->size
);
1561 brw_bo_unmap(mt
->mcs_buf
->bo
);
1564 static struct intel_miptree_aux_buffer
*
1565 intel_alloc_aux_buffer(struct brw_context
*brw
,
1567 const struct isl_surf
*aux_surf
,
1568 uint32_t alloc_flags
,
1569 struct intel_mipmap_tree
*mt
)
1571 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1575 buf
->size
= aux_surf
->size
;
1576 buf
->pitch
= aux_surf
->row_pitch
;
1577 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1579 /* ISL has stricter set of alignment rules then the drm allocator.
1580 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1581 * trying to recalculate based on different format block sizes.
1583 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1584 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1590 buf
->surf
= *aux_surf
;
1596 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1597 struct intel_mipmap_tree
*mt
,
1600 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1601 assert(mt
->mcs_buf
== NULL
);
1602 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1604 /* Multisampled miptrees are only supported for single level. */
1605 assert(mt
->first_level
== 0);
1606 enum isl_aux_state
**aux_state
=
1607 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1611 struct isl_surf temp_mcs_surf
;
1613 MAYBE_UNUSED
bool ok
=
1614 isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_mcs_surf
);
1617 /* Buffer needs to be initialised requiring the buffer to be immediately
1618 * mapped to cpu space for writing. Therefore do not use the gpu access
1619 * flag which can cause an unnecessary delay if the backing pages happened
1620 * to be just used by the GPU.
1622 const uint32_t alloc_flags
= 0;
1623 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1624 &temp_mcs_surf
, alloc_flags
, mt
);
1630 mt
->aux_state
= aux_state
;
1632 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1638 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1639 struct intel_mipmap_tree
*mt
)
1641 assert(mt
->mcs_buf
== NULL
);
1642 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1643 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1645 struct isl_surf temp_ccs_surf
;
1647 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
, 0))
1650 assert(temp_ccs_surf
.size
&&
1651 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1653 enum isl_aux_state
**aux_state
=
1654 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1658 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1659 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1661 * "If Software wants to enable Color Compression without Fast clear,
1662 * Software needs to initialize MCS with zeros."
1664 * A CCS value of 0 indicates that the corresponding block is in the
1665 * pass-through state which is what we want.
1667 * For CCS_D, on the other hand, we don't care as we're about to perform a
1668 * fast-clear operation. In that case, being hot in caches more useful.
1670 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1671 BO_ALLOC_ZEROED
: BO_ALLOC_FOR_RENDER
;
1672 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1673 &temp_ccs_surf
, alloc_flags
, mt
);
1679 mt
->aux_state
= aux_state
;
1685 * Helper for intel_miptree_alloc_hiz() that sets
1686 * \c mt->level[level].has_hiz. Return true if and only if
1687 * \c has_hiz was set.
1690 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1691 struct intel_mipmap_tree
*mt
,
1694 assert(mt
->hiz_buf
);
1695 assert(mt
->surf
.size
> 0);
1697 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1698 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1699 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1701 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1702 * and the height is 4 aligned. This allows our HiZ support
1703 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1704 * we can grow the width & height to allow the HiZ op to
1705 * force the proper size alignments.
1707 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1708 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1713 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1714 mt
->level
[level
].has_hiz
= true;
1719 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1720 struct intel_mipmap_tree
*mt
)
1722 assert(mt
->hiz_buf
== NULL
);
1723 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1725 enum isl_aux_state
**aux_state
=
1726 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1730 struct isl_surf temp_hiz_surf
;
1732 MAYBE_UNUSED
bool ok
=
1733 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
1736 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
1737 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1738 &temp_hiz_surf
, alloc_flags
, mt
);
1745 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1746 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1748 mt
->aux_state
= aux_state
;
1755 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1757 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1758 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1759 * compress clear color so we wait until an actual fast-clear to allocate it.
1762 intel_miptree_alloc_aux(struct brw_context
*brw
,
1763 struct intel_mipmap_tree
*mt
)
1765 switch (mt
->aux_usage
) {
1766 case ISL_AUX_USAGE_NONE
:
1769 case ISL_AUX_USAGE_HIZ
:
1770 assert(!_mesa_is_format_color_format(mt
->format
));
1771 if (!intel_miptree_alloc_hiz(brw
, mt
))
1775 case ISL_AUX_USAGE_MCS
:
1776 assert(_mesa_is_format_color_format(mt
->format
));
1777 assert(mt
->surf
.samples
> 1);
1778 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
1782 case ISL_AUX_USAGE_CCS_D
:
1783 /* Since CCS_D can only compress clear color so we wait until an actual
1784 * fast-clear to allocate it.
1788 case ISL_AUX_USAGE_CCS_E
:
1789 assert(_mesa_is_format_color_format(mt
->format
));
1790 assert(mt
->surf
.samples
== 1);
1791 if (!intel_miptree_alloc_ccs(brw
, mt
))
1796 unreachable("Invalid aux usage");
1801 * Can the miptree sample using the hiz buffer?
1804 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1805 struct intel_mipmap_tree
*mt
)
1807 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1808 * so keep things conservative for now and never enable it unless we're SKL+.
1818 /* It seems the hardware won't fallback to the depth buffer if some of the
1819 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1820 * of the texture to be HiZ enabled.
1822 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1823 if (!intel_miptree_level_has_hiz(mt
, level
))
1827 /* If compressed multisampling is enabled, then we use it for the auxiliary
1830 * From the BDW PRM (Volume 2d: Command Reference: Structures
1831 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1833 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1834 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1836 * There is no such blurb for 1D textures, but there is sufficient evidence
1837 * that this is broken on SKL+.
1839 return (mt
->surf
.samples
== 1 &&
1840 mt
->target
!= GL_TEXTURE_3D
&&
1841 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1845 * Does the miptree slice have hiz enabled?
1848 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1850 intel_miptree_check_level_layer(mt
, level
, 0);
1851 return mt
->level
[level
].has_hiz
;
1854 static inline uint32_t
1855 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1856 uint32_t start_level
, uint32_t num_levels
)
1858 assert(start_level
>= mt
->first_level
);
1859 assert(start_level
<= mt
->last_level
);
1861 if (num_levels
== INTEL_REMAINING_LAYERS
)
1862 num_levels
= mt
->last_level
- start_level
+ 1;
1863 /* Check for overflow */
1864 assert(start_level
+ num_levels
>= start_level
);
1865 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
1870 static inline uint32_t
1871 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
1872 uint32_t start_layer
, uint32_t num_layers
)
1874 assert(level
<= mt
->last_level
);
1876 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
1877 assert(start_layer
< total_num_layers
);
1878 if (num_layers
== INTEL_REMAINING_LAYERS
)
1879 num_layers
= total_num_layers
- start_layer
;
1880 /* Check for overflow */
1881 assert(start_layer
+ num_layers
>= start_layer
);
1882 assert(start_layer
+ num_layers
<= total_num_layers
);
1888 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1889 unsigned start_level
, unsigned num_levels
,
1890 unsigned start_layer
, unsigned num_layers
)
1892 assert(_mesa_is_format_color_format(mt
->format
));
1897 /* Clamp the level range to fit the miptree */
1898 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
1900 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1901 const uint32_t level
= start_level
+ l
;
1902 const uint32_t level_layers
=
1903 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
1904 for (unsigned a
= 0; a
< level_layers
; a
++) {
1905 enum isl_aux_state aux_state
=
1906 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
1907 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
1908 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
1917 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
1918 const struct intel_mipmap_tree
*mt
,
1919 unsigned level
, unsigned layer
)
1925 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
1926 assert(brw
->gen
>= 8 ||
1927 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
1929 /* Compression of arrayed msaa surfaces is supported. */
1930 if (mt
->surf
.samples
> 1)
1933 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
1934 assert(brw
->gen
>= 8 ||
1936 mt
->surf
.logical_level0_px
.depth
== 1 &&
1937 mt
->surf
.logical_level0_px
.array_len
== 1));
1943 static enum blorp_fast_clear_op
1944 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
1945 enum isl_aux_usage aux_usage
,
1946 bool fast_clear_supported
)
1948 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
1950 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
1952 assert(ccs_supported
== fast_clear_supported
);
1954 switch (aux_state
) {
1955 case ISL_AUX_STATE_CLEAR
:
1956 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1958 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1960 return BLORP_FAST_CLEAR_OP_NONE
;
1962 case ISL_AUX_STATE_PASS_THROUGH
:
1963 return BLORP_FAST_CLEAR_OP_NONE
;
1965 case ISL_AUX_STATE_RESOLVED
:
1966 case ISL_AUX_STATE_AUX_INVALID
:
1967 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1968 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1972 unreachable("Invalid aux state for CCS_D");
1975 static enum blorp_fast_clear_op
1976 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
1977 enum isl_aux_usage aux_usage
,
1978 bool fast_clear_supported
)
1980 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
1981 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
1982 aux_usage
== ISL_AUX_USAGE_CCS_D
||
1983 aux_usage
== ISL_AUX_USAGE_CCS_E
);
1985 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
1986 assert(fast_clear_supported
);
1988 switch (aux_state
) {
1989 case ISL_AUX_STATE_CLEAR
:
1990 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1991 if (fast_clear_supported
)
1992 return BLORP_FAST_CLEAR_OP_NONE
;
1993 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
1994 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
1996 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1998 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1999 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2000 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2001 else if (!fast_clear_supported
)
2002 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2004 return BLORP_FAST_CLEAR_OP_NONE
;
2006 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2007 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2008 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2010 return BLORP_FAST_CLEAR_OP_NONE
;
2012 case ISL_AUX_STATE_PASS_THROUGH
:
2013 return BLORP_FAST_CLEAR_OP_NONE
;
2015 case ISL_AUX_STATE_RESOLVED
:
2016 case ISL_AUX_STATE_AUX_INVALID
:
2020 unreachable("Invalid aux state for CCS_E");
2024 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2025 struct intel_mipmap_tree
*mt
,
2026 uint32_t level
, uint32_t layer
,
2027 enum isl_aux_usage aux_usage
,
2028 bool fast_clear_supported
)
2030 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2032 enum blorp_fast_clear_op resolve_op
;
2033 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2034 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2035 fast_clear_supported
);
2037 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2038 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2039 fast_clear_supported
);
2042 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2043 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2044 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2046 switch (resolve_op
) {
2047 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2048 /* The CCS full resolve operation destroys the CCS and sets it to the
2049 * pass-through state. (You can also think of this as being both a
2050 * resolve and an ambiguate in one operation.)
2052 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2053 ISL_AUX_STATE_PASS_THROUGH
);
2056 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2057 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2058 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2062 unreachable("Invalid resolve op");
2068 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2069 struct intel_mipmap_tree
*mt
,
2070 uint32_t level
, uint32_t layer
,
2071 enum isl_aux_usage aux_usage
)
2073 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2074 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2075 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2077 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2079 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2080 switch (aux_state
) {
2081 case ISL_AUX_STATE_CLEAR
:
2082 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2083 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2084 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2086 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2087 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2088 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2089 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2090 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2091 ISL_AUX_STATE_PARTIAL_CLEAR
);
2095 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2096 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2097 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2098 break; /* Nothing to do */
2100 case ISL_AUX_STATE_PASS_THROUGH
:
2101 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2102 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2103 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2109 case ISL_AUX_STATE_RESOLVED
:
2110 case ISL_AUX_STATE_AUX_INVALID
:
2111 unreachable("Invalid aux state for CCS_E");
2114 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2115 /* CCS_D is a bit simpler */
2116 switch (aux_state
) {
2117 case ISL_AUX_STATE_CLEAR
:
2118 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2119 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2120 ISL_AUX_STATE_PARTIAL_CLEAR
);
2123 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2124 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2125 break; /* Nothing to do */
2127 case ISL_AUX_STATE_PASS_THROUGH
:
2131 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2132 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2133 case ISL_AUX_STATE_RESOLVED
:
2134 case ISL_AUX_STATE_AUX_INVALID
:
2135 unreachable("Invalid aux state for CCS_D");
2141 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2142 struct intel_mipmap_tree
*mt
,
2144 enum isl_aux_usage aux_usage
,
2145 bool fast_clear_supported
)
2147 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2149 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2150 case ISL_AUX_STATE_CLEAR
:
2151 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2152 if (!fast_clear_supported
) {
2153 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2154 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2155 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2159 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2160 break; /* Nothing to do */
2162 case ISL_AUX_STATE_RESOLVED
:
2163 case ISL_AUX_STATE_PASS_THROUGH
:
2164 case ISL_AUX_STATE_AUX_INVALID
:
2165 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2166 unreachable("Invalid aux state for MCS");
2171 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2172 struct intel_mipmap_tree
*mt
,
2174 enum isl_aux_usage aux_usage
)
2176 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2178 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2179 case ISL_AUX_STATE_CLEAR
:
2180 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2181 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2184 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2185 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2186 break; /* Nothing to do */
2188 case ISL_AUX_STATE_RESOLVED
:
2189 case ISL_AUX_STATE_PASS_THROUGH
:
2190 case ISL_AUX_STATE_AUX_INVALID
:
2191 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2192 unreachable("Invalid aux state for MCS");
2197 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2198 struct intel_mipmap_tree
*mt
,
2199 uint32_t level
, uint32_t layer
,
2200 enum isl_aux_usage aux_usage
,
2201 bool fast_clear_supported
)
2203 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2205 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2206 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2207 case ISL_AUX_STATE_CLEAR
:
2208 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2209 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2210 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2213 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2214 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2215 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2218 case ISL_AUX_STATE_PASS_THROUGH
:
2219 case ISL_AUX_STATE_RESOLVED
:
2222 case ISL_AUX_STATE_AUX_INVALID
:
2223 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2224 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2227 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2228 unreachable("Invalid HiZ state");
2231 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2232 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2235 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2236 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2237 ISL_AUX_STATE_RESOLVED
);
2240 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2241 /* The HiZ resolve operation is actually an ambiguate */
2242 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2243 ISL_AUX_STATE_PASS_THROUGH
);
2247 unreachable("Invalid HiZ op");
2253 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2254 struct intel_mipmap_tree
*mt
,
2255 uint32_t level
, uint32_t layer
,
2256 enum isl_aux_usage aux_usage
)
2258 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2260 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2261 case ISL_AUX_STATE_CLEAR
:
2262 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2263 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2264 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2267 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2268 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2269 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2270 break; /* Nothing to do */
2272 case ISL_AUX_STATE_RESOLVED
:
2273 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2274 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2275 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2277 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2278 ISL_AUX_STATE_AUX_INVALID
);
2282 case ISL_AUX_STATE_PASS_THROUGH
:
2283 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2284 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2285 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2289 case ISL_AUX_STATE_AUX_INVALID
:
2290 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2293 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2294 unreachable("Invalid HiZ state");
2299 intel_miptree_prepare_access(struct brw_context
*brw
,
2300 struct intel_mipmap_tree
*mt
,
2301 uint32_t start_level
, uint32_t num_levels
,
2302 uint32_t start_layer
, uint32_t num_layers
,
2303 enum isl_aux_usage aux_usage
,
2304 bool fast_clear_supported
)
2306 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2308 switch (mt
->aux_usage
) {
2309 case ISL_AUX_USAGE_NONE
:
2313 case ISL_AUX_USAGE_MCS
:
2314 assert(mt
->mcs_buf
);
2315 assert(start_level
== 0 && num_levels
== 1);
2316 const uint32_t level_layers
=
2317 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2318 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2319 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2320 aux_usage
, fast_clear_supported
);
2324 case ISL_AUX_USAGE_CCS_D
:
2325 case ISL_AUX_USAGE_CCS_E
:
2329 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2330 const uint32_t level
= start_level
+ l
;
2331 const uint32_t level_layers
=
2332 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2333 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2334 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2336 aux_usage
, fast_clear_supported
);
2341 case ISL_AUX_USAGE_HIZ
:
2342 assert(mt
->hiz_buf
);
2343 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2344 const uint32_t level
= start_level
+ l
;
2345 if (!intel_miptree_level_has_hiz(mt
, level
))
2348 const uint32_t level_layers
=
2349 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2350 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2351 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2352 aux_usage
, fast_clear_supported
);
2358 unreachable("Invalid aux usage");
2363 intel_miptree_finish_write(struct brw_context
*brw
,
2364 struct intel_mipmap_tree
*mt
, uint32_t level
,
2365 uint32_t start_layer
, uint32_t num_layers
,
2366 enum isl_aux_usage aux_usage
)
2368 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2370 switch (mt
->aux_usage
) {
2371 case ISL_AUX_USAGE_NONE
:
2375 case ISL_AUX_USAGE_MCS
:
2376 assert(mt
->mcs_buf
);
2377 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2378 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2383 case ISL_AUX_USAGE_CCS_D
:
2384 case ISL_AUX_USAGE_CCS_E
:
2388 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2389 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2394 case ISL_AUX_USAGE_HIZ
:
2395 if (!intel_miptree_level_has_hiz(mt
, level
))
2398 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2399 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2405 unreachable("Invavlid aux usage");
2410 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2411 uint32_t level
, uint32_t layer
)
2413 intel_miptree_check_level_layer(mt
, level
, layer
);
2415 if (_mesa_is_format_color_format(mt
->format
)) {
2416 assert(mt
->mcs_buf
!= NULL
);
2417 assert(mt
->surf
.samples
== 1 ||
2418 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2419 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2420 unreachable("Cannot get aux state for stencil");
2422 assert(intel_miptree_level_has_hiz(mt
, level
));
2425 return mt
->aux_state
[level
][layer
];
2429 intel_miptree_set_aux_state(struct brw_context
*brw
,
2430 struct intel_mipmap_tree
*mt
, uint32_t level
,
2431 uint32_t start_layer
, uint32_t num_layers
,
2432 enum isl_aux_state aux_state
)
2434 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2436 if (_mesa_is_format_color_format(mt
->format
)) {
2437 assert(mt
->mcs_buf
!= NULL
);
2438 assert(mt
->surf
.samples
== 1 ||
2439 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2440 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2441 unreachable("Cannot get aux state for stencil");
2443 assert(intel_miptree_level_has_hiz(mt
, level
));
2446 for (unsigned a
= 0; a
< num_layers
; a
++)
2447 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2450 /* On Gen9 color buffers may be compressed by the hardware (lossless
2451 * compression). There are, however, format restrictions and care needs to be
2452 * taken that the sampler engine is capable for re-interpreting a buffer with
2453 * format different the buffer was originally written with.
2455 * For example, SRGB formats are not compressible and the sampler engine isn't
2456 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2457 * color buffer needs to be resolved so that the sampling surface can be
2458 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2462 can_texture_with_ccs(struct brw_context
*brw
,
2463 struct intel_mipmap_tree
*mt
,
2464 enum isl_format view_format
)
2466 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2469 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2470 mt
->surf
.format
, view_format
)) {
2471 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2472 isl_format_get_layout(view_format
)->name
,
2473 _mesa_get_format_name(mt
->format
));
2481 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2482 struct intel_mipmap_tree
*mt
,
2483 enum isl_format view_format
)
2485 switch (mt
->aux_usage
) {
2486 case ISL_AUX_USAGE_HIZ
:
2487 if (intel_miptree_sample_with_hiz(brw
, mt
))
2488 return ISL_AUX_USAGE_HIZ
;
2491 case ISL_AUX_USAGE_MCS
:
2492 return ISL_AUX_USAGE_MCS
;
2494 case ISL_AUX_USAGE_CCS_D
:
2495 case ISL_AUX_USAGE_CCS_E
:
2496 if (mt
->mcs_buf
&& can_texture_with_ccs(brw
, mt
, view_format
))
2497 return ISL_AUX_USAGE_CCS_E
;
2504 return ISL_AUX_USAGE_NONE
;
2508 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2510 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2511 * values so sRGB curve application was a no-op for all fast-clearable
2514 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2515 * values, the hardware interprets the floats, not as what would be
2516 * returned from the sampler (or written by the shader), but as being
2517 * between format conversion and sRGB curve application. This means that
2518 * we can switch between sRGB and UNORM without having to whack the clear
2521 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2525 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2526 struct intel_mipmap_tree
*mt
,
2527 enum isl_format view_format
,
2528 uint32_t start_level
, uint32_t num_levels
,
2529 uint32_t start_layer
, uint32_t num_layers
,
2530 bool *aux_supported_out
)
2532 enum isl_aux_usage aux_usage
=
2533 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2534 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2536 /* Clear color is specified as ints or floats and the conversion is done by
2537 * the sampler. If we have a texture view, we would have to perform the
2538 * clear color conversion manually. Just disable clear color.
2540 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2541 clear_supported
= false;
2543 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2544 start_layer
, num_layers
,
2545 aux_usage
, clear_supported
);
2546 if (aux_supported_out
)
2547 *aux_supported_out
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2551 intel_miptree_prepare_texture(struct brw_context
*brw
,
2552 struct intel_mipmap_tree
*mt
,
2553 enum isl_format view_format
,
2554 bool *aux_supported_out
)
2556 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2557 0, INTEL_REMAINING_LEVELS
,
2558 0, INTEL_REMAINING_LAYERS
,
2563 intel_miptree_prepare_image(struct brw_context
*brw
,
2564 struct intel_mipmap_tree
*mt
)
2566 /* The data port doesn't understand any compression */
2567 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2568 0, INTEL_REMAINING_LAYERS
,
2569 ISL_AUX_USAGE_NONE
, false);
2573 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2574 struct intel_mipmap_tree
*mt
, uint32_t level
,
2575 uint32_t start_layer
, uint32_t num_layers
)
2577 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->surf
.format
, level
, 1,
2578 start_layer
, num_layers
, NULL
);
2582 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2583 struct intel_mipmap_tree
*mt
,
2584 bool srgb_enabled
, bool blend_enabled
)
2586 switch (mt
->aux_usage
) {
2587 case ISL_AUX_USAGE_MCS
:
2588 assert(mt
->mcs_buf
);
2589 return ISL_AUX_USAGE_MCS
;
2591 case ISL_AUX_USAGE_CCS_D
:
2592 return mt
->mcs_buf
? ISL_AUX_USAGE_CCS_D
: ISL_AUX_USAGE_NONE
;
2594 case ISL_AUX_USAGE_CCS_E
: {
2595 mesa_format mesa_format
=
2596 srgb_enabled
? mt
->format
:_mesa_get_srgb_format_linear(mt
->format
);
2597 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
2599 /* If the format supports CCS_E, then we can just use it */
2600 if (isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
))
2601 return ISL_AUX_USAGE_CCS_E
;
2603 /* Otherwise, we have to fall back to CCS_D */
2605 /* gen9 hardware technically supports non-0/1 clear colors with sRGB
2606 * formats. However, there are issues with blending where it doesn't
2607 * properly apply the sRGB curve to the clear color when blending.
2609 if (blend_enabled
&& isl_format_is_srgb(isl_format
) &&
2610 !isl_color_value_is_zero_one(mt
->fast_clear_color
, isl_format
))
2611 return ISL_AUX_USAGE_NONE
;
2613 return ISL_AUX_USAGE_CCS_D
;
2617 return ISL_AUX_USAGE_NONE
;
2622 intel_miptree_prepare_render(struct brw_context
*brw
,
2623 struct intel_mipmap_tree
*mt
, uint32_t level
,
2624 uint32_t start_layer
, uint32_t layer_count
,
2625 bool srgb_enabled
, bool blend_enabled
)
2627 enum isl_aux_usage aux_usage
=
2628 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
, blend_enabled
);
2629 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2630 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2634 intel_miptree_finish_render(struct brw_context
*brw
,
2635 struct intel_mipmap_tree
*mt
, uint32_t level
,
2636 uint32_t start_layer
, uint32_t layer_count
,
2637 bool srgb_enabled
, bool blend_enabled
)
2639 assert(_mesa_is_format_color_format(mt
->format
));
2641 enum isl_aux_usage aux_usage
=
2642 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
, blend_enabled
);
2643 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2648 intel_miptree_prepare_depth(struct brw_context
*brw
,
2649 struct intel_mipmap_tree
*mt
, uint32_t level
,
2650 uint32_t start_layer
, uint32_t layer_count
)
2652 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2653 mt
->aux_usage
, mt
->hiz_buf
!= NULL
);
2657 intel_miptree_finish_depth(struct brw_context
*brw
,
2658 struct intel_mipmap_tree
*mt
, uint32_t level
,
2659 uint32_t start_layer
, uint32_t layer_count
,
2662 if (depth_written
) {
2663 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2664 mt
->hiz_buf
!= NULL
);
2669 * Make it possible to share the BO backing the given miptree with another
2670 * process or another miptree.
2672 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2673 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2674 * ensure that no MCS buffer gets allocated in the future.
2676 * HiZ is similarly unsafe with shared buffers.
2679 intel_miptree_make_shareable(struct brw_context
*brw
,
2680 struct intel_mipmap_tree
*mt
)
2682 /* MCS buffers are also used for multisample buffers, but we can't resolve
2683 * away a multisample MCS buffer because it's an integral part of how the
2684 * pixel data is stored. Fortunately this code path should never be
2685 * reached for multisample buffers.
2687 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2688 mt
->surf
.samples
== 1);
2690 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2691 0, INTEL_REMAINING_LAYERS
,
2692 ISL_AUX_USAGE_NONE
, false);
2695 brw_bo_unreference(mt
->mcs_buf
->bo
);
2699 /* Any pending MCS/CCS operations are no longer needed. Trying to
2700 * execute any will likely crash due to the missing aux buffer. So let's
2701 * delete all pending ops.
2703 free(mt
->aux_state
);
2704 mt
->aux_state
= NULL
;
2708 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2711 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2712 mt
->level
[l
].has_hiz
= false;
2715 /* Any pending HiZ operations are no longer needed. Trying to execute
2716 * any will likely crash due to the missing aux buffer. So let's delete
2719 free(mt
->aux_state
);
2720 mt
->aux_state
= NULL
;
2723 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2728 * \brief Get pointer offset into stencil buffer.
2730 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2731 * must decode the tile's layout in software.
2734 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2736 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2738 * Even though the returned offset is always positive, the return type is
2740 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2741 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2744 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2746 uint32_t tile_size
= 4096;
2747 uint32_t tile_width
= 64;
2748 uint32_t tile_height
= 64;
2749 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2751 uint32_t tile_x
= x
/ tile_width
;
2752 uint32_t tile_y
= y
/ tile_height
;
2754 /* The byte's address relative to the tile's base addres. */
2755 uint32_t byte_x
= x
% tile_width
;
2756 uint32_t byte_y
= y
% tile_height
;
2758 uintptr_t u
= tile_y
* row_size
2759 + tile_x
* tile_size
2760 + 512 * (byte_x
/ 8)
2762 + 32 * ((byte_y
/ 4) % 2)
2763 + 16 * ((byte_x
/ 4) % 2)
2764 + 8 * ((byte_y
/ 2) % 2)
2765 + 4 * ((byte_x
/ 2) % 2)
2770 /* adjust for bit6 swizzling */
2771 if (((byte_x
/ 8) % 2) == 1) {
2772 if (((byte_y
/ 8) % 2) == 0) {
2784 intel_miptree_updownsample(struct brw_context
*brw
,
2785 struct intel_mipmap_tree
*src
,
2786 struct intel_mipmap_tree
*dst
)
2788 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2789 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2790 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2791 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2793 brw_blorp_blit_miptrees(brw
,
2794 src
, 0 /* level */, 0 /* layer */,
2795 src
->format
, SWIZZLE_XYZW
,
2796 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2799 GL_NEAREST
, false, false /*mirror x, y*/,
2802 if (src
->stencil_mt
) {
2803 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2804 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2805 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2806 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2808 brw_blorp_blit_miptrees(brw
,
2809 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2810 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2811 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2812 dst
->stencil_mt
->format
,
2815 GL_NEAREST
, false, false /*mirror x, y*/,
2816 false, false /* decode/encode srgb */);
2821 intel_update_r8stencil(struct brw_context
*brw
,
2822 struct intel_mipmap_tree
*mt
)
2824 assert(brw
->gen
>= 7);
2825 struct intel_mipmap_tree
*src
=
2826 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2827 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2830 assert(src
->surf
.size
> 0);
2832 if (!mt
->r8stencil_mt
) {
2833 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2834 mt
->r8stencil_mt
= make_surface(
2837 MESA_FORMAT_R_UINT8
,
2838 src
->first_level
, src
->last_level
,
2839 src
->surf
.logical_level0_px
.width
,
2840 src
->surf
.logical_level0_px
.height
,
2841 src
->surf
.dim
== ISL_SURF_DIM_3D
?
2842 src
->surf
.logical_level0_px
.depth
:
2843 src
->surf
.logical_level0_px
.array_len
,
2846 ISL_SURF_USAGE_TEXTURE_BIT
,
2847 BO_ALLOC_FOR_RENDER
, 0, NULL
);
2848 assert(mt
->r8stencil_mt
);
2851 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2853 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2854 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
2855 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
2856 src
->surf
.phys_level0_sa
.array_len
;
2858 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2859 brw_blorp_copy_miptrees(brw
,
2863 minify(src
->surf
.logical_level0_px
.width
,
2865 minify(src
->surf
.logical_level0_px
.height
,
2870 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2871 src
->r8stencil_needs_update
= false;
2875 intel_miptree_map_raw(struct brw_context
*brw
,
2876 struct intel_mipmap_tree
*mt
,
2879 struct brw_bo
*bo
= mt
->bo
;
2881 if (brw_batch_references(&brw
->batch
, bo
))
2882 intel_batchbuffer_flush(brw
);
2884 return brw_bo_map(brw
, bo
, mode
);
2888 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2890 brw_bo_unmap(mt
->bo
);
2894 intel_miptree_map_gtt(struct brw_context
*brw
,
2895 struct intel_mipmap_tree
*mt
,
2896 struct intel_miptree_map
*map
,
2897 unsigned int level
, unsigned int slice
)
2899 unsigned int bw
, bh
;
2901 unsigned int image_x
, image_y
;
2902 intptr_t x
= map
->x
;
2903 intptr_t y
= map
->y
;
2905 /* For compressed formats, the stride is the number of bytes per
2906 * row of blocks. intel_miptree_get_image_offset() already does
2909 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2910 assert(y
% bh
== 0);
2911 assert(x
% bw
== 0);
2915 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
2922 /* Note that in the case of cube maps, the caller must have passed the
2923 * slice number referencing the face.
2925 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2929 map
->stride
= mt
->surf
.row_pitch
;
2930 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2933 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2934 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2935 map
->x
, map
->y
, map
->w
, map
->h
,
2936 mt
, _mesa_get_format_name(mt
->format
),
2937 x
, y
, map
->ptr
, map
->stride
);
2941 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2943 intel_miptree_unmap_raw(mt
);
2947 intel_miptree_map_blit(struct brw_context
*brw
,
2948 struct intel_mipmap_tree
*mt
,
2949 struct intel_miptree_map
*map
,
2950 unsigned int level
, unsigned int slice
)
2952 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2953 /* first_level */ 0,
2957 MIPTREE_LAYOUT_TILING_NONE
);
2959 if (!map
->linear_mt
) {
2960 fprintf(stderr
, "Failed to allocate blit temporary\n");
2963 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
2965 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2966 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2967 * invalidate is set, since we'll be writing the whole rectangle from our
2968 * temporary buffer back out.
2970 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2971 if (!intel_miptree_copy(brw
,
2972 mt
, level
, slice
, map
->x
, map
->y
,
2973 map
->linear_mt
, 0, 0, 0, 0,
2975 fprintf(stderr
, "Failed to blit\n");
2980 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
2982 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2983 map
->x
, map
->y
, map
->w
, map
->h
,
2984 mt
, _mesa_get_format_name(mt
->format
),
2985 level
, slice
, map
->ptr
, map
->stride
);
2990 intel_miptree_release(&map
->linear_mt
);
2996 intel_miptree_unmap_blit(struct brw_context
*brw
,
2997 struct intel_mipmap_tree
*mt
,
2998 struct intel_miptree_map
*map
,
3002 struct gl_context
*ctx
= &brw
->ctx
;
3004 intel_miptree_unmap_raw(map
->linear_mt
);
3006 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3007 bool ok
= intel_miptree_copy(brw
,
3008 map
->linear_mt
, 0, 0, 0, 0,
3009 mt
, level
, slice
, map
->x
, map
->y
,
3011 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3014 intel_miptree_release(&map
->linear_mt
);
3018 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3020 #if defined(USE_SSE41)
3022 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3023 struct intel_mipmap_tree
*mt
,
3024 struct intel_miptree_map
*map
,
3025 unsigned int level
, unsigned int slice
)
3027 assert(map
->mode
& GL_MAP_READ_BIT
);
3028 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3030 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3031 map
->x
, map
->y
, map
->w
, map
->h
,
3032 mt
, _mesa_get_format_name(mt
->format
),
3033 level
, slice
, map
->ptr
, map
->stride
);
3035 /* Map the original image */
3038 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3042 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3048 src
+= image_y
* mt
->surf
.row_pitch
;
3049 src
+= image_x
* mt
->cpp
;
3051 /* Due to the pixel offsets for the particular image being mapped, our
3052 * src pointer may not be 16-byte aligned. However, if the pitch is
3053 * divisible by 16, then the amount by which it's misaligned will remain
3054 * consistent from row to row.
3056 assert((mt
->surf
.row_pitch
% 16) == 0);
3057 const int misalignment
= ((uintptr_t) src
) & 15;
3059 /* Create an untiled temporary buffer for the mapping. */
3060 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3062 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3064 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3065 /* Offset the destination so it has the same misalignment as src. */
3066 map
->ptr
= map
->buffer
+ misalignment
;
3068 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3070 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3071 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3072 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3074 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3077 intel_miptree_unmap_raw(mt
);
3081 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3082 struct intel_mipmap_tree
*mt
,
3083 struct intel_miptree_map
*map
,
3087 _mesa_align_free(map
->buffer
);
3094 intel_miptree_map_s8(struct brw_context
*brw
,
3095 struct intel_mipmap_tree
*mt
,
3096 struct intel_miptree_map
*map
,
3097 unsigned int level
, unsigned int slice
)
3099 map
->stride
= map
->w
;
3100 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3104 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3105 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3106 * invalidate is set, since we'll be writing the whole rectangle from our
3107 * temporary buffer back out.
3109 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3110 uint8_t *untiled_s8_map
= map
->ptr
;
3111 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3112 unsigned int image_x
, image_y
;
3114 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3116 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3117 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3118 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3119 x
+ image_x
+ map
->x
,
3120 y
+ image_y
+ map
->y
,
3121 brw
->has_swizzling
);
3122 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3126 intel_miptree_unmap_raw(mt
);
3128 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3129 map
->x
, map
->y
, map
->w
, map
->h
,
3130 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3132 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3133 map
->x
, map
->y
, map
->w
, map
->h
,
3134 mt
, map
->ptr
, map
->stride
);
3139 intel_miptree_unmap_s8(struct brw_context
*brw
,
3140 struct intel_mipmap_tree
*mt
,
3141 struct intel_miptree_map
*map
,
3145 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3146 unsigned int image_x
, image_y
;
3147 uint8_t *untiled_s8_map
= map
->ptr
;
3148 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3150 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3152 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3153 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3154 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3155 image_x
+ x
+ map
->x
,
3156 image_y
+ y
+ map
->y
,
3157 brw
->has_swizzling
);
3158 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3162 intel_miptree_unmap_raw(mt
);
3169 intel_miptree_map_etc(struct brw_context
*brw
,
3170 struct intel_mipmap_tree
*mt
,
3171 struct intel_miptree_map
*map
,
3175 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3176 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3177 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3180 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3181 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3183 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3184 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3185 map
->w
, map
->h
, 1));
3186 map
->ptr
= map
->buffer
;
3190 intel_miptree_unmap_etc(struct brw_context
*brw
,
3191 struct intel_mipmap_tree
*mt
,
3192 struct intel_miptree_map
*map
,
3198 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3203 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3204 + image_y
* mt
->surf
.row_pitch
3205 + image_x
* mt
->cpp
;
3207 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3208 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3209 map
->ptr
, map
->stride
,
3212 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3213 map
->ptr
, map
->stride
,
3214 map
->w
, map
->h
, mt
->etc_format
);
3216 intel_miptree_unmap_raw(mt
);
3221 * Mapping function for packed depth/stencil miptrees backed by real separate
3222 * miptrees for depth and stencil.
3224 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3225 * separate from the depth buffer. Yet at the GL API level, we have to expose
3226 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3227 * be able to map that memory for texture storage and glReadPixels-type
3228 * operations. We give Mesa core that access by mallocing a temporary and
3229 * copying the data between the actual backing store and the temporary.
3232 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3233 struct intel_mipmap_tree
*mt
,
3234 struct intel_miptree_map
*map
,
3235 unsigned int level
, unsigned int slice
)
3237 struct intel_mipmap_tree
*z_mt
= mt
;
3238 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3239 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3240 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3242 map
->stride
= map
->w
* packed_bpp
;
3243 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3247 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3248 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3249 * invalidate is set, since we'll be writing the whole rectangle from our
3250 * temporary buffer back out.
3252 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3253 uint32_t *packed_map
= map
->ptr
;
3254 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3255 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3256 unsigned int s_image_x
, s_image_y
;
3257 unsigned int z_image_x
, z_image_y
;
3259 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3260 &s_image_x
, &s_image_y
);
3261 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3262 &z_image_x
, &z_image_y
);
3264 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3265 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3266 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3267 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3270 brw
->has_swizzling
);
3271 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3272 (z_mt
->surf
.row_pitch
/ 4) +
3273 (map_x
+ z_image_x
));
3274 uint8_t s
= s_map
[s_offset
];
3275 uint32_t z
= z_map
[z_offset
];
3277 if (map_z32f_x24s8
) {
3278 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3279 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3281 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3286 intel_miptree_unmap_raw(s_mt
);
3287 intel_miptree_unmap_raw(z_mt
);
3289 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3291 map
->x
, map
->y
, map
->w
, map
->h
,
3292 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3293 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3294 map
->ptr
, map
->stride
);
3296 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3297 map
->x
, map
->y
, map
->w
, map
->h
,
3298 mt
, map
->ptr
, map
->stride
);
3303 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3304 struct intel_mipmap_tree
*mt
,
3305 struct intel_miptree_map
*map
,
3309 struct intel_mipmap_tree
*z_mt
= mt
;
3310 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3311 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3313 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3314 uint32_t *packed_map
= map
->ptr
;
3315 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3316 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3317 unsigned int s_image_x
, s_image_y
;
3318 unsigned int z_image_x
, z_image_y
;
3320 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3321 &s_image_x
, &s_image_y
);
3322 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3323 &z_image_x
, &z_image_y
);
3325 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3326 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3327 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3328 x
+ s_image_x
+ map
->x
,
3329 y
+ s_image_y
+ map
->y
,
3330 brw
->has_swizzling
);
3331 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3332 (z_mt
->surf
.row_pitch
/ 4) +
3333 (x
+ z_image_x
+ map
->x
));
3335 if (map_z32f_x24s8
) {
3336 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3337 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3339 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3340 s_map
[s_offset
] = packed
>> 24;
3341 z_map
[z_offset
] = packed
;
3346 intel_miptree_unmap_raw(s_mt
);
3347 intel_miptree_unmap_raw(z_mt
);
3349 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3351 map
->x
, map
->y
, map
->w
, map
->h
,
3352 z_mt
, _mesa_get_format_name(z_mt
->format
),
3353 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3354 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3355 map
->ptr
, map
->stride
);
3362 * Create and attach a map to the miptree at (level, slice). Return the
3365 static struct intel_miptree_map
*
3366 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3375 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3380 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3381 mt
->level
[level
].slice
[slice
].map
= map
;
3393 * Release the map at (level, slice).
3396 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3400 struct intel_miptree_map
**map
;
3402 map
= &mt
->level
[level
].slice
[slice
].map
;
3408 can_blit_slice(struct intel_mipmap_tree
*mt
,
3409 unsigned int level
, unsigned int slice
)
3411 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3412 if (mt
->surf
.row_pitch
>= 32768)
3419 use_intel_mipree_map_blit(struct brw_context
*brw
,
3420 struct intel_mipmap_tree
*mt
,
3426 /* It's probably not worth swapping to the blit ring because of
3427 * all the overhead involved.
3429 !(mode
& GL_MAP_WRITE_BIT
) &&
3431 (mt
->surf
.tiling
== ISL_TILING_X
||
3432 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3433 (brw
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3434 /* Fast copy blit on skl+ supports all tiling formats. */
3436 can_blit_slice(mt
, level
, slice
))
3439 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3440 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3441 assert(can_blit_slice(mt
, level
, slice
));
3449 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3450 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3451 * arithmetic overflow.
3453 * If you call this function and use \a out_stride, then you're doing pointer
3454 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3455 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3456 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3457 * which usually have type uint32_t or GLuint.
3460 intel_miptree_map(struct brw_context
*brw
,
3461 struct intel_mipmap_tree
*mt
,
3470 ptrdiff_t *out_stride
)
3472 struct intel_miptree_map
*map
;
3474 assert(mt
->surf
.samples
== 1);
3476 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3483 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3484 map
->mode
& GL_MAP_WRITE_BIT
);
3486 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3487 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3488 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3489 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3490 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3491 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3492 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3493 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3494 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3495 #if defined(USE_SSE41)
3496 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3497 !mt
->compressed
&& cpu_has_sse4_1
&&
3498 (mt
->surf
.row_pitch
% 16 == 0)) {
3499 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3502 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3505 *out_ptr
= map
->ptr
;
3506 *out_stride
= map
->stride
;
3508 if (map
->ptr
== NULL
)
3509 intel_miptree_release_map(mt
, level
, slice
);
3513 intel_miptree_unmap(struct brw_context
*brw
,
3514 struct intel_mipmap_tree
*mt
,
3518 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3520 assert(mt
->surf
.samples
== 1);
3525 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3526 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3528 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3529 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3530 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3531 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3532 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3533 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3534 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3535 } else if (map
->linear_mt
) {
3536 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3537 #if defined(USE_SSE41)
3538 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3539 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3542 intel_miptree_unmap_gtt(mt
);
3545 intel_miptree_release_map(mt
, level
, slice
);
3549 get_isl_surf_dim(GLenum target
)
3553 case GL_TEXTURE_1D_ARRAY
:
3554 return ISL_SURF_DIM_1D
;
3557 case GL_TEXTURE_2D_ARRAY
:
3558 case GL_TEXTURE_RECTANGLE
:
3559 case GL_TEXTURE_CUBE_MAP
:
3560 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3561 case GL_TEXTURE_2D_MULTISAMPLE
:
3562 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3563 case GL_TEXTURE_EXTERNAL_OES
:
3564 return ISL_SURF_DIM_2D
;
3567 return ISL_SURF_DIM_3D
;
3570 unreachable("Invalid texture target");
3574 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3575 enum isl_tiling tiling
, GLenum target
)
3579 case GL_TEXTURE_1D_ARRAY
:
3580 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3581 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3584 case GL_TEXTURE_2D_ARRAY
:
3585 case GL_TEXTURE_RECTANGLE
:
3586 case GL_TEXTURE_2D_MULTISAMPLE
:
3587 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3588 case GL_TEXTURE_EXTERNAL_OES
:
3589 return ISL_DIM_LAYOUT_GEN4_2D
;
3591 case GL_TEXTURE_CUBE_MAP
:
3592 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3593 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3594 ISL_DIM_LAYOUT_GEN4_2D
);
3597 return (devinfo
->gen
>= 9 ?
3598 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3601 unreachable("Invalid texture target");
3605 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3606 const struct intel_mipmap_tree
*mt
)
3609 return ISL_AUX_USAGE_HIZ
;
3612 return ISL_AUX_USAGE_NONE
;
3614 return mt
->aux_usage
;