1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_resolve_map.h"
34 #include "intel_tex.h"
35 #include "intel_blit.h"
36 #include "intel_fbo.h"
38 #include "brw_blorp.h"
39 #include "brw_context.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
48 #include "x86/common_x86_asm.h"
50 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
53 intel_miptree_alloc_mcs(struct brw_context
*brw
,
54 struct intel_mipmap_tree
*mt
,
58 * Determine which MSAA layout should be used by the MSAA surface being
59 * created, based on the chip generation and the surface type.
61 static enum intel_msaa_layout
62 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
, GLenum target
,
63 bool disable_aux_buffers
)
65 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
67 return INTEL_MSAA_LAYOUT_IMS
;
69 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
70 switch (_mesa_get_format_base_format(format
)) {
71 case GL_DEPTH_COMPONENT
:
72 case GL_STENCIL_INDEX
:
73 case GL_DEPTH_STENCIL
:
74 return INTEL_MSAA_LAYOUT_IMS
;
76 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
78 * This field must be set to 0 for all SINT MSRTs when all RT channels
81 * In practice this means that we have to disable MCS for all signed
82 * integer MSAA buffers. The alternative, to disable MCS only when one
83 * of the render target channels is disabled, is impractical because it
84 * would require converting between CMS and UMS MSAA layouts on the fly,
87 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
88 return INTEL_MSAA_LAYOUT_UMS
;
89 } else if (disable_aux_buffers
) {
90 /* We can't use the CMS layout because it uses an aux buffer, the MCS
91 * buffer. So fallback to UMS, which is identical to CMS without the
93 return INTEL_MSAA_LAYOUT_UMS
;
95 return INTEL_MSAA_LAYOUT_CMS
;
102 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
103 * scaled-down bitfield representation of the color buffer which is capable of
104 * recording when blocks of the color buffer are equal to the clear value.
105 * This function returns the block size that will be used by the MCS buffer
106 * corresponding to a certain color miptree.
108 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
109 * beneath the "Fast Color Clear" bullet (p327):
111 * The following table describes the RT alignment
125 * This alignment has the following uses:
127 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
128 * buffer contains 128 blocks horizontally and 256 blocks vertically.
130 * - For figuring out alignment restrictions for a fast clear operation. Fast
131 * clear operations must always clear aligned multiples of 16 blocks
132 * horizontally and 32 blocks vertically.
134 * - For scaling down the coordinates sent through the render pipeline during
135 * a fast clear. X coordinates must be scaled down by 8 times the block
136 * width, and Y coordinates by 16 times the block height.
138 * - For scaling down the coordinates sent through the render pipeline during
139 * a "Render Target Resolve" operation. X coordinates must be scaled down
140 * by half the block width, and Y coordinates by half the block height.
143 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
144 struct intel_mipmap_tree
*mt
,
145 unsigned *width_px
, unsigned *height
)
147 switch (mt
->tiling
) {
149 unreachable("Non-MSRT MCS requires X or Y tiling");
150 /* In release builds, fall through */
152 *width_px
= 32 / mt
->cpp
;
156 *width_px
= 64 / mt
->cpp
;
162 intel_tiling_supports_non_msrt_mcs(struct brw_context
*brw
, unsigned tiling
)
164 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
165 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
167 * - Support is limited to tiled render targets.
169 * Gen9 changes the restriction to Y-tile only.
172 return tiling
== I915_TILING_Y
;
173 else if (brw
->gen
>= 7)
174 return tiling
!= I915_TILING_NONE
;
180 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
181 * can be used. This doesn't (and should not) inspect any of the properties of
184 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
185 * beneath the "Fast Color Clear" bullet (p326):
187 * - Support is for non-mip-mapped and non-array surface types only.
189 * And then later, on p327:
191 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
195 intel_miptree_is_fast_clear_capable(struct brw_context
*brw
,
196 struct intel_mipmap_tree
*mt
)
198 /* MCS support does not exist prior to Gen7 */
202 if (mt
->disable_aux_buffers
)
205 /* MCS is only supported for color buffers */
206 switch (_mesa_get_format_base_format(mt
->format
)) {
207 case GL_DEPTH_COMPONENT
:
208 case GL_DEPTH_STENCIL
:
209 case GL_STENCIL_INDEX
:
213 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
215 if (mt
->first_level
!= 0 || mt
->last_level
!= 0) {
217 perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
218 mt
->logical_width0
, mt
->logical_height0
, mt
->last_level
);
223 if (mt
->physical_depth0
!= 1) {
225 perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
226 mt
->logical_width0
, mt
->logical_height0
,
227 mt
->physical_depth0
);
233 /* There's no point in using an MCS buffer if the surface isn't in a
236 if (!brw
->format_supported_as_render_target
[mt
->format
])
244 * Determine depth format corresponding to a depth+stencil format,
245 * for separate stencil.
248 intel_depth_format_for_depthstencil_format(mesa_format format
) {
250 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
251 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
252 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
253 return MESA_FORMAT_Z_FLOAT32
;
261 * @param for_bo Indicates that the caller is
262 * intel_miptree_create_for_bo(). If true, then do not create
265 static struct intel_mipmap_tree
*
266 intel_miptree_create_layout(struct brw_context
*brw
,
275 uint32_t layout_flags
)
277 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
281 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
282 _mesa_enum_to_string(target
),
283 _mesa_get_format_name(format
),
284 first_level
, last_level
, depth0
, mt
);
286 if (target
== GL_TEXTURE_1D_ARRAY
) {
287 /* For a 1D Array texture the OpenGL API will treat the height0
288 * parameter as the number of array slices. For Intel hardware, we treat
289 * the 1D array as a 2D Array with a height of 1.
291 * So, when we first come through this path to create a 1D Array
292 * texture, height0 stores the number of slices, and depth0 is 1. In
293 * this case, we want to swap height0 and depth0.
295 * Since some miptrees will be created based on the base miptree, we may
296 * come through this path and see height0 as 1 and depth0 being the
297 * number of slices. In this case we don't need to do the swap.
299 assert(height0
== 1 || depth0
== 1);
308 mt
->first_level
= first_level
;
309 mt
->last_level
= last_level
;
310 mt
->logical_width0
= width0
;
311 mt
->logical_height0
= height0
;
312 mt
->logical_depth0
= depth0
;
313 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
314 mt
->disable_aux_buffers
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0;
315 exec_list_make_empty(&mt
->hiz_map
);
316 mt
->cpp
= _mesa_get_format_bytes(format
);
317 mt
->num_samples
= num_samples
;
318 mt
->compressed
= _mesa_is_format_compressed(format
);
319 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
322 if (num_samples
> 1) {
323 /* Adjust width/height/depth for MSAA */
324 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
325 mt
->target
, mt
->disable_aux_buffers
);
326 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
327 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
328 * "If the surface is multisampled and it is a depth or stencil
329 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
330 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
333 * +----------------------------------------------------------------+
334 * | Num Multisamples | W_l = | H_l = |
335 * +----------------------------------------------------------------+
336 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
337 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
338 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
339 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
340 * +----------------------------------------------------------------+
343 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
344 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
345 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
347 * Another more complicated explanation for these adjustments comes
348 * from the Sandybridge PRM, volume 4, part 1, page 31:
350 * "Any of the other messages (sample*, LOD, load4) used with a
351 * (4x) multisampled surface will in-effect sample a surface with
352 * double the height and width as that indicated in the surface
353 * state. Each pixel position on the original-sized surface is
354 * replaced with a 2x2 of samples with the following arrangement:
359 * Thus, when sampling from a multisampled texture, it behaves as
360 * though the layout in memory for (x,y,sample) is:
362 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
363 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
365 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
366 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
368 * However, the actual layout of multisampled data in memory is:
370 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
371 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
373 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
374 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
376 * This pattern repeats for each 2x2 pixel block.
378 * As a result, when calculating the size of our 4-sample buffer for
379 * an odd width or height, we have to align before scaling up because
380 * sample 3 is in that bottom right 2x2 block.
382 switch (num_samples
) {
384 assert(brw
->gen
>= 8);
385 width0
= ALIGN(width0
, 2) * 2;
386 height0
= ALIGN(height0
, 2);
389 width0
= ALIGN(width0
, 2) * 2;
390 height0
= ALIGN(height0
, 2) * 2;
393 width0
= ALIGN(width0
, 2) * 4;
394 height0
= ALIGN(height0
, 2) * 2;
397 /* num_samples should already have been quantized to 0, 1, 2, 4, or
400 unreachable("not reached");
403 /* Non-interleaved */
404 depth0
*= num_samples
;
408 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
409 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
410 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
411 * used on Gen8 to make it pick a qpitch value which doesn't include space
412 * for the mipmaps. On Gen9 this is not necessary because it will
413 * automatically pick a packed qpitch value whenever mt->first_level ==
415 * TODO: can we use it elsewhere?
416 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
419 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
421 switch (mt
->msaa_layout
) {
422 case INTEL_MSAA_LAYOUT_NONE
:
423 case INTEL_MSAA_LAYOUT_IMS
:
424 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
426 case INTEL_MSAA_LAYOUT_UMS
:
427 case INTEL_MSAA_LAYOUT_CMS
:
428 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
433 if (target
== GL_TEXTURE_CUBE_MAP
) {
438 mt
->physical_width0
= width0
;
439 mt
->physical_height0
= height0
;
440 mt
->physical_depth0
= depth0
;
442 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
443 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
444 (brw
->must_use_separate_stencil
||
445 (brw
->has_separate_stencil
&&
446 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
447 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
449 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
|
450 MIPTREE_LAYOUT_TILING_ANY
;
453 mt
->stencil_mt
= intel_miptree_create(brw
,
464 if (!mt
->stencil_mt
) {
465 intel_miptree_release(&mt
);
469 /* Fix up the Z miptree format for how we're splitting out separate
470 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
472 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
475 if (format
== mt
->format
) {
476 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
477 _mesa_get_format_name(mt
->format
));
481 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
482 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
485 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
486 * multisampled or have an AUX buffer attached to it.
488 * GEN | MSRT | AUX_CCS_* or AUX_MCS
489 * -------------------------------------------
490 * 9 | HALIGN_16 | HALIGN_16
491 * 8 | HALIGN_ANY | HALIGN_16
495 if (intel_miptree_is_fast_clear_capable(brw
, mt
)) {
496 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
497 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
498 } else if (brw
->gen
>= 9 && num_samples
> 1) {
499 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
501 /* For now, nothing else has this requirement */
502 assert((layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
505 brw_miptree_layout(brw
, mt
, layout_flags
);
507 if (mt
->disable_aux_buffers
)
508 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
515 * Choose an appropriate uncompressed format for a requested
516 * compressed format, if unsupported.
519 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
521 /* No need to lower ETC formats on these platforms,
522 * they are supported natively.
524 if (brw
->gen
>= 8 || brw
->is_baytrail
)
528 case MESA_FORMAT_ETC1_RGB8
:
529 return MESA_FORMAT_R8G8B8X8_UNORM
;
530 case MESA_FORMAT_ETC2_RGB8
:
531 return MESA_FORMAT_R8G8B8X8_UNORM
;
532 case MESA_FORMAT_ETC2_SRGB8
:
533 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
534 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
535 return MESA_FORMAT_B8G8R8A8_SRGB
;
536 case MESA_FORMAT_ETC2_RGBA8_EAC
:
537 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
538 return MESA_FORMAT_R8G8B8A8_UNORM
;
539 case MESA_FORMAT_ETC2_R11_EAC
:
540 return MESA_FORMAT_R_UNORM16
;
541 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
542 return MESA_FORMAT_R_SNORM16
;
543 case MESA_FORMAT_ETC2_RG11_EAC
:
544 return MESA_FORMAT_R16G16_UNORM
;
545 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
546 return MESA_FORMAT_R16G16_SNORM
;
548 /* Non ETC1 / ETC2 format */
553 /* This function computes Yf/Ys tiled bo size, alignment and pitch. */
555 intel_get_yf_ys_bo_size(struct intel_mipmap_tree
*mt
, unsigned *alignment
,
556 unsigned long *pitch
)
558 const uint32_t bpp
= mt
->cpp
* 8;
559 const uint32_t aspect_ratio
= (bpp
== 16 || bpp
== 64) ? 2 : 1;
560 uint32_t tile_width
, tile_height
;
561 unsigned long stride
, size
, aligned_y
;
563 assert(mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
);
578 unreachable("not reached");
581 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YS
)
584 aligned_y
= ALIGN(mt
->total_height
, tile_height
);
585 stride
= mt
->total_width
* mt
->cpp
;
586 tile_width
= tile_height
* mt
->cpp
* aspect_ratio
;
587 stride
= ALIGN(stride
, tile_width
);
588 size
= stride
* aligned_y
;
590 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
) {
591 assert(size
% 4096 == 0);
594 assert(size
% (64 * 1024) == 0);
595 *alignment
= 64 * 1024;
601 struct intel_mipmap_tree
*
602 intel_miptree_create(struct brw_context
*brw
,
611 uint32_t layout_flags
)
613 struct intel_mipmap_tree
*mt
;
614 mesa_format tex_format
= format
;
615 mesa_format etc_format
= MESA_FORMAT_NONE
;
616 GLuint total_width
, total_height
;
617 uint32_t alloc_flags
= 0;
619 format
= intel_lower_compressed_format(brw
, format
);
621 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
623 assert((layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) == 0);
624 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
625 mt
= intel_miptree_create_layout(brw
, target
, format
,
626 first_level
, last_level
, width0
,
627 height0
, depth0
, num_samples
,
630 * pitch == 0 || height == 0 indicates the null texture
632 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
633 intel_miptree_release(&mt
);
637 total_width
= mt
->total_width
;
638 total_height
= mt
->total_height
;
640 if (format
== MESA_FORMAT_S_UINT8
) {
641 /* Align to size of W tile, 64x64. */
642 total_width
= ALIGN(total_width
, 64);
643 total_height
= ALIGN(total_height
, 64);
648 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
)) {
650 mt
->tiling
= I915_TILING_Y
;
653 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
654 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
657 mt
->etc_format
= etc_format
;
659 if (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
660 unsigned alignment
= 0;
662 size
= intel_get_yf_ys_bo_size(mt
, &alignment
, &pitch
);
664 mt
->bo
= drm_intel_bo_alloc_for_render(brw
->bufmgr
, "miptree",
667 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
668 total_width
, total_height
, mt
->cpp
,
675 /* If the BO is too large to fit in the aperture, we need to use the
676 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
677 * handle Y-tiling, so we need to fall back to X.
679 if (brw
->gen
< 6 && y_or_x
&& mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
680 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
681 mt
->total_width
, mt
->total_height
);
683 mt
->tiling
= I915_TILING_X
;
684 drm_intel_bo_unreference(mt
->bo
);
685 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
686 total_width
, total_height
, mt
->cpp
,
687 &mt
->tiling
, &pitch
, alloc_flags
);
694 intel_miptree_release(&mt
);
699 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
700 assert(mt
->num_samples
> 1);
701 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
702 intel_miptree_release(&mt
);
707 /* If this miptree is capable of supporting fast color clears, set
708 * fast_clear_state appropriately to ensure that fast clears will occur.
709 * Allocation of the MCS miptree will be deferred until the first fast
710 * clear actually occurs.
712 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
713 intel_miptree_is_fast_clear_capable(brw
, mt
)) {
714 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
715 assert(brw
->gen
< 8 || mt
->align_w
== 16 || num_samples
<= 1);
721 struct intel_mipmap_tree
*
722 intel_miptree_create_for_bo(struct brw_context
*brw
,
730 uint32_t layout_flags
)
732 struct intel_mipmap_tree
*mt
;
733 uint32_t tiling
, swizzle
;
736 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
738 /* Nothing will be able to use this miptree with the BO if the offset isn't
741 if (tiling
!= I915_TILING_NONE
)
742 assert(offset
% 4096 == 0);
744 /* miptrees can't handle negative pitch. If you need flipping of images,
745 * that's outside of the scope of the mt.
749 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
751 /* The BO already has a tiling format and we shouldn't confuse the lower
752 * layers by making it try to find a tiling format again.
754 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
755 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
757 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
758 mt
= intel_miptree_create_layout(brw
, target
, format
,
760 width
, height
, depth
, 0,
765 drm_intel_bo_reference(bo
);
775 * For a singlesample renderbuffer, this simply wraps the given BO with a
778 * For a multisample renderbuffer, this wraps the window system's
779 * (singlesample) BO with a singlesample miptree attached to the
780 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
781 * that will contain the actual rendering (which is lazily resolved to
782 * irb->singlesample_mt).
785 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
786 struct intel_renderbuffer
*irb
,
788 uint32_t width
, uint32_t height
,
791 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
792 struct intel_mipmap_tree
*multisample_mt
= NULL
;
793 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
794 mesa_format format
= rb
->Format
;
795 int num_samples
= rb
->NumSamples
;
797 /* Only the front and back buffers, which are color buffers, are allocated
798 * through the image loader.
800 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
801 _mesa_get_format_base_format(format
) == GL_RGBA
);
803 singlesample_mt
= intel_miptree_create_for_bo(intel
,
812 if (!singlesample_mt
)
815 /* If this miptree is capable of supporting fast color clears, set
816 * mcs_state appropriately to ensure that fast clears will occur.
817 * Allocation of the MCS miptree will be deferred until the first fast
818 * clear actually occurs.
820 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
821 intel_miptree_is_fast_clear_capable(intel
, singlesample_mt
))
822 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
824 if (num_samples
== 0) {
825 intel_miptree_release(&irb
->mt
);
826 irb
->mt
= singlesample_mt
;
828 assert(!irb
->singlesample_mt
);
830 intel_miptree_release(&irb
->singlesample_mt
);
831 irb
->singlesample_mt
= singlesample_mt
;
834 irb
->mt
->logical_width0
!= width
||
835 irb
->mt
->logical_height0
!= height
) {
836 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
844 irb
->need_downsample
= false;
845 intel_miptree_release(&irb
->mt
);
846 irb
->mt
= multisample_mt
;
852 intel_miptree_release(&irb
->singlesample_mt
);
853 intel_miptree_release(&irb
->mt
);
857 struct intel_mipmap_tree
*
858 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
862 uint32_t num_samples
)
864 struct intel_mipmap_tree
*mt
;
867 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
868 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
869 MIPTREE_LAYOUT_TILING_ANY
;
872 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
873 width
, height
, depth
, num_samples
,
878 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
879 ok
= intel_miptree_alloc_hiz(brw
, mt
);
887 intel_miptree_release(&mt
);
892 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
893 struct intel_mipmap_tree
*src
)
898 intel_miptree_release(dst
);
902 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
910 intel_miptree_release(struct intel_mipmap_tree
**mt
)
915 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
916 if (--(*mt
)->refcount
<= 0) {
919 DBG("%s deleting %p\n", __func__
, *mt
);
921 drm_intel_bo_unreference((*mt
)->bo
);
922 intel_miptree_release(&(*mt
)->stencil_mt
);
923 if ((*mt
)->hiz_buf
) {
924 if ((*mt
)->hiz_buf
->mt
)
925 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
927 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
928 free((*mt
)->hiz_buf
);
930 intel_miptree_release(&(*mt
)->mcs_mt
);
931 intel_resolve_map_clear(&(*mt
)->hiz_map
);
933 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
934 free((*mt
)->level
[i
].slice
);
943 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
944 int *width
, int *height
, int *depth
)
946 switch (image
->TexObject
->Target
) {
947 case GL_TEXTURE_1D_ARRAY
:
948 *width
= image
->Width
;
950 *depth
= image
->Height
;
953 *width
= image
->Width
;
954 *height
= image
->Height
;
955 *depth
= image
->Depth
;
961 * Can the image be pulled into a unified mipmap tree? This mirrors
962 * the completeness test in a lot of ways.
964 * Not sure whether I want to pass gl_texture_image here.
967 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
968 struct gl_texture_image
*image
)
970 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
971 GLuint level
= intelImage
->base
.Base
.Level
;
972 int width
, height
, depth
;
974 /* glTexImage* choose the texture object based on the target passed in, and
975 * objects can't change targets over their lifetimes, so this should be
978 assert(image
->TexObject
->Target
== mt
->target
);
980 mesa_format mt_format
= mt
->format
;
981 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
982 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
983 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
984 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
985 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
986 mt_format
= mt
->etc_format
;
988 if (image
->TexFormat
!= mt_format
)
991 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
993 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
996 int level_depth
= mt
->level
[level
].depth
;
997 if (mt
->num_samples
> 1) {
998 switch (mt
->msaa_layout
) {
999 case INTEL_MSAA_LAYOUT_NONE
:
1000 case INTEL_MSAA_LAYOUT_IMS
:
1002 case INTEL_MSAA_LAYOUT_UMS
:
1003 case INTEL_MSAA_LAYOUT_CMS
:
1004 level_depth
/= mt
->num_samples
;
1009 /* Test image dimensions against the base level image adjusted for
1010 * minification. This will also catch images not present in the
1011 * tree, changed targets, etc.
1013 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1014 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1015 depth
!= level_depth
) {
1019 if (image
->NumSamples
!= mt
->num_samples
)
1027 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1029 GLuint x
, GLuint y
, GLuint d
)
1031 mt
->level
[level
].depth
= d
;
1032 mt
->level
[level
].level_x
= x
;
1033 mt
->level
[level
].level_y
= y
;
1035 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1038 assert(mt
->level
[level
].slice
== NULL
);
1040 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1041 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1042 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1047 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1048 GLuint level
, GLuint img
,
1051 if (img
== 0 && level
== 0)
1052 assert(x
== 0 && y
== 0);
1054 assert(img
< mt
->level
[level
].depth
);
1056 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1057 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1059 DBG("%s level %d img %d pos %d,%d\n",
1060 __func__
, level
, img
,
1061 mt
->level
[level
].slice
[img
].x_offset
,
1062 mt
->level
[level
].slice
[img
].y_offset
);
1066 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1067 GLuint level
, GLuint slice
,
1068 GLuint
*x
, GLuint
*y
)
1070 assert(slice
< mt
->level
[level
].depth
);
1072 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1073 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1077 * This function computes masks that may be used to select the bits of the X
1078 * and Y coordinates that indicate the offset within a tile. If the BO is
1079 * untiled, the masks are set to 0.
1082 intel_miptree_get_tile_masks(const struct intel_mipmap_tree
*mt
,
1083 uint32_t *mask_x
, uint32_t *mask_y
,
1084 bool map_stencil_as_y_tiled
)
1087 uint32_t tiling
= mt
->tiling
;
1089 if (map_stencil_as_y_tiled
)
1090 tiling
= I915_TILING_Y
;
1094 unreachable("not reached");
1095 case I915_TILING_NONE
:
1096 *mask_x
= *mask_y
= 0;
1099 *mask_x
= 512 / cpp
- 1;
1103 *mask_x
= 128 / cpp
- 1;
1110 * Compute the offset (in bytes) from the start of the BO to the given x
1111 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1112 * multiples of the tile size.
1115 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1116 uint32_t x
, uint32_t y
,
1117 bool map_stencil_as_y_tiled
)
1120 uint32_t pitch
= mt
->pitch
;
1121 uint32_t tiling
= mt
->tiling
;
1123 if (map_stencil_as_y_tiled
) {
1124 tiling
= I915_TILING_Y
;
1126 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1127 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1128 * the resulting surface is twice the pitch of the original miptree,
1129 * since each row in the Y-tiled view corresponds to two rows in the
1130 * actual W-tiled surface. So we need to correct the pitch before
1131 * computing the offsets.
1138 unreachable("not reached");
1139 case I915_TILING_NONE
:
1140 return y
* pitch
+ x
* cpp
;
1142 assert((x
% (512 / cpp
)) == 0);
1143 assert((y
% 8) == 0);
1144 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1146 assert((x
% (128 / cpp
)) == 0);
1147 assert((y
% 32) == 0);
1148 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1153 * Rendering with tiled buffers requires that the base address of the buffer
1154 * be aligned to a page boundary. For renderbuffers, and sometimes with
1155 * textures, we may want the surface to point at a texture image level that
1156 * isn't at a page boundary.
1158 * This function returns an appropriately-aligned base offset
1159 * according to the tiling restrictions, plus any required x/y offset
1163 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1164 GLuint level
, GLuint slice
,
1169 uint32_t mask_x
, mask_y
;
1171 intel_miptree_get_tile_masks(mt
, &mask_x
, &mask_y
, false);
1172 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1174 *tile_x
= x
& mask_x
;
1175 *tile_y
= y
& mask_y
;
1177 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1181 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1182 struct intel_mipmap_tree
*dst_mt
,
1183 struct intel_mipmap_tree
*src_mt
,
1190 ptrdiff_t src_stride
, dst_stride
;
1191 int cpp
= dst_mt
->cpp
;
1193 intel_miptree_map(brw
, src_mt
,
1197 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1200 intel_miptree_map(brw
, dst_mt
,
1204 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1208 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1209 _mesa_get_format_name(src_mt
->format
),
1210 src_mt
, src
, src_stride
,
1211 _mesa_get_format_name(dst_mt
->format
),
1212 dst_mt
, dst
, dst_stride
,
1215 int row_size
= cpp
* width
;
1216 if (src_stride
== row_size
&&
1217 dst_stride
== row_size
) {
1218 memcpy(dst
, src
, row_size
* height
);
1220 for (int i
= 0; i
< height
; i
++) {
1221 memcpy(dst
, src
, row_size
);
1227 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1228 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1230 /* Don't forget to copy the stencil data over, too. We could have skipped
1231 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1232 * shuffling the two data sources in/out of temporary storage instead of
1233 * the direct mapping we get this way.
1235 if (dst_mt
->stencil_mt
) {
1236 assert(src_mt
->stencil_mt
);
1237 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1238 level
, slice
, width
, height
);
1243 intel_miptree_copy_slice(struct brw_context
*brw
,
1244 struct intel_mipmap_tree
*dst_mt
,
1245 struct intel_mipmap_tree
*src_mt
,
1251 mesa_format format
= src_mt
->format
;
1252 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1253 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1261 assert(depth
< src_mt
->level
[level
].depth
);
1262 assert(src_mt
->format
== dst_mt
->format
);
1264 if (dst_mt
->compressed
) {
1266 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1267 height
= ALIGN_NPOT(height
, j
) / j
;
1268 width
= ALIGN_NPOT(width
, i
) / i
;
1271 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1272 * below won't apply since we can't do the depth's Y tiling or the
1273 * stencil's W tiling in the blitter.
1275 if (src_mt
->stencil_mt
) {
1276 intel_miptree_copy_slice_sw(brw
,
1283 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1284 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1285 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1287 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1288 _mesa_get_format_name(src_mt
->format
),
1289 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1290 _mesa_get_format_name(dst_mt
->format
),
1291 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1294 if (!intel_miptree_blit(brw
,
1295 src_mt
, level
, slice
, 0, 0, false,
1296 dst_mt
, level
, slice
, 0, 0, false,
1297 width
, height
, GL_COPY
)) {
1298 perf_debug("miptree validate blit for %s failed\n",
1299 _mesa_get_format_name(format
));
1301 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1307 * Copies the image's current data to the given miptree, and associates that
1308 * miptree with the image.
1310 * If \c invalidate is true, then the actual image data does not need to be
1311 * copied, but the image still needs to be associated to the new miptree (this
1312 * is set to true if we're about to clear the image).
1315 intel_miptree_copy_teximage(struct brw_context
*brw
,
1316 struct intel_texture_image
*intelImage
,
1317 struct intel_mipmap_tree
*dst_mt
,
1320 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1321 struct intel_texture_object
*intel_obj
=
1322 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1323 int level
= intelImage
->base
.Base
.Level
;
1324 int face
= intelImage
->base
.Base
.Face
;
1327 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1328 depth
= intelImage
->base
.Base
.Height
;
1330 depth
= intelImage
->base
.Base
.Depth
;
1333 for (int slice
= 0; slice
< depth
; slice
++) {
1334 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1338 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1339 intel_obj
->needs_validate
= true;
1343 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1344 struct intel_mipmap_tree
*mt
,
1347 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1348 assert(mt
->mcs_mt
== NULL
);
1349 assert(!mt
->disable_aux_buffers
);
1351 /* Choose the correct format for the MCS buffer. All that really matters
1352 * is that we allocate the right buffer size, since we'll always be
1353 * accessing this miptree using MCS-specific hardware mechanisms, which
1354 * infer the correct format based on num_samples.
1357 switch (num_samples
) {
1360 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1363 format
= MESA_FORMAT_R_UNORM8
;
1366 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1367 * for each sample, plus 8 padding bits).
1369 format
= MESA_FORMAT_R_UINT32
;
1372 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1375 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1377 * "The MCS surface must be stored as Tile Y."
1379 const uint32_t mcs_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1380 MIPTREE_LAYOUT_TILING_Y
;
1381 mt
->mcs_mt
= intel_miptree_create(brw
,
1387 mt
->logical_height0
,
1389 0 /* num_samples */,
1392 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1394 * When MCS buffer is enabled and bound to MSRT, it is required that it
1395 * is cleared prior to any rendering.
1397 * Since we don't use the MCS buffer for any purpose other than rendering,
1398 * it makes sense to just clear it immediately upon allocation.
1400 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1402 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1403 memset(data
, 0xff, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1404 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1405 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1412 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1413 struct intel_mipmap_tree
*mt
)
1415 assert(mt
->mcs_mt
== NULL
);
1416 assert(!mt
->disable_aux_buffers
);
1418 /* The format of the MCS buffer is opaque to the driver; all that matters
1419 * is that we get its size and pitch right. We'll pretend that the format
1420 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1421 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1422 * the block width and then a further factor of 4. Since an MCS tile
1423 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1424 * we'll need to scale the height down by the block height and then a
1425 * further factor of 8.
1427 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1428 unsigned block_width_px
;
1429 unsigned block_height
;
1430 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1431 unsigned width_divisor
= block_width_px
* 4;
1432 unsigned height_divisor
= block_height
* 8;
1433 unsigned mcs_width
=
1434 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1435 unsigned mcs_height
=
1436 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1437 assert(mt
->logical_depth0
== 1);
1438 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1439 MIPTREE_LAYOUT_TILING_Y
;
1440 if (brw
->gen
>= 8) {
1441 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
1443 mt
->mcs_mt
= intel_miptree_create(brw
,
1451 0 /* num_samples */,
1459 * Helper for intel_miptree_alloc_hiz() that sets
1460 * \c mt->level[level].has_hiz. Return true if and only if
1461 * \c has_hiz was set.
1464 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1465 struct intel_mipmap_tree
*mt
,
1468 assert(mt
->hiz_buf
);
1470 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1471 uint32_t width
= minify(mt
->physical_width0
, level
);
1472 uint32_t height
= minify(mt
->physical_height0
, level
);
1474 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1475 * and the height is 4 aligned. This allows our HiZ support
1476 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1477 * we can grow the width & height to allow the HiZ op to
1478 * force the proper size alignments.
1480 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1481 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1486 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1487 mt
->level
[level
].has_hiz
= true;
1493 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1494 * buffer dimensions and allocates a bo for the hiz buffer.
1496 static struct intel_miptree_aux_buffer
*
1497 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1498 struct intel_mipmap_tree
*mt
)
1500 unsigned z_width
= mt
->logical_width0
;
1501 unsigned z_height
= mt
->logical_height0
;
1502 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1503 unsigned hz_width
, hz_height
;
1504 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1509 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1510 * adjustments required for Z_Height and Z_Width based on multisampling.
1512 switch (mt
->num_samples
) {
1526 unreachable("unsupported sample count");
1529 const unsigned vertical_align
= 8; /* 'j' in the docs */
1530 const unsigned H0
= z_height
;
1531 const unsigned h0
= ALIGN(H0
, vertical_align
);
1532 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1533 const unsigned Z0
= z_depth
;
1535 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1536 hz_width
= ALIGN(z_width
, 16);
1538 if (mt
->target
== GL_TEXTURE_3D
) {
1542 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1543 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1544 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1545 hz_height
+= h_i
* Z_i
;
1546 H_i
= minify(H_i
, 1);
1547 Z_i
= minify(Z_i
, 1);
1550 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1552 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1554 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1555 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1556 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1557 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth * 6/2) /8 ) * 8 */
1558 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
* 6, 2 * 8) * 8;
1560 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1561 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1565 unsigned long pitch
;
1566 uint32_t tiling
= I915_TILING_Y
;
1567 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1568 hz_width
, hz_height
, 1,
1570 BO_ALLOC_FOR_RENDER
);
1574 } else if (tiling
!= I915_TILING_Y
) {
1575 drm_intel_bo_unreference(buf
->bo
);
1587 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1588 * buffer dimensions and allocates a bo for the hiz buffer.
1590 static struct intel_miptree_aux_buffer
*
1591 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1592 struct intel_mipmap_tree
*mt
)
1594 unsigned z_width
= mt
->logical_width0
;
1595 unsigned z_height
= mt
->logical_height0
;
1596 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1597 unsigned hz_width
, hz_height
;
1598 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1603 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1604 * adjustments required for Z_Height and Z_Width based on multisampling.
1607 switch (mt
->num_samples
) {
1621 unreachable("unsupported sample count");
1625 const unsigned vertical_align
= 8; /* 'j' in the docs */
1626 const unsigned H0
= z_height
;
1627 const unsigned h0
= ALIGN(H0
, vertical_align
);
1628 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1629 const unsigned Z0
= z_depth
;
1631 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1632 hz_width
= ALIGN(z_width
, 16);
1636 unsigned sum_h_i
= 0;
1637 unsigned hz_height_3d_sum
= 0;
1638 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1639 unsigned i
= level
- mt
->first_level
;
1640 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1641 /* sum(i=2 to m; h_i) */
1645 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1646 hz_height_3d_sum
+= h_i
* Z_i
;
1647 H_i
= minify(H_i
, 1);
1648 Z_i
= minify(Z_i
, 1);
1650 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1651 buf
->qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1653 if (mt
->target
== GL_TEXTURE_3D
) {
1654 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1655 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1657 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1658 hz_height
= DIV_ROUND_UP(buf
->qpitch
, 2 * 8) * 8 * Z0
;
1659 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1660 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1661 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * 6 * Z_Depth
1663 * We can can just take our hz_height calculation from above, and
1664 * multiply by 6 for the cube map and cube map array types.
1670 unsigned long pitch
;
1671 uint32_t tiling
= I915_TILING_Y
;
1672 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1673 hz_width
, hz_height
, 1,
1675 BO_ALLOC_FOR_RENDER
);
1679 } else if (tiling
!= I915_TILING_Y
) {
1680 drm_intel_bo_unreference(buf
->bo
);
1691 static struct intel_miptree_aux_buffer
*
1692 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1693 struct intel_mipmap_tree
*mt
)
1695 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1696 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1699 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1704 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1705 buf
->mt
= intel_miptree_create(brw
,
1711 mt
->logical_height0
,
1720 buf
->bo
= buf
->mt
->bo
;
1721 buf
->pitch
= buf
->mt
->pitch
;
1722 buf
->qpitch
= buf
->mt
->qpitch
;
1728 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1729 struct intel_mipmap_tree
*mt
)
1734 if (mt
->hiz_buf
!= NULL
)
1737 if (mt
->disable_aux_buffers
)
1740 switch (mt
->format
) {
1741 case MESA_FORMAT_Z_FLOAT32
:
1742 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1743 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1744 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1745 case MESA_FORMAT_Z_UNORM16
:
1753 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1754 struct intel_mipmap_tree
*mt
)
1756 assert(mt
->hiz_buf
== NULL
);
1757 assert(!mt
->disable_aux_buffers
);
1759 if (brw
->gen
== 7) {
1760 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1761 } else if (brw
->gen
>= 8) {
1762 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1764 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1770 /* Mark that all slices need a HiZ resolve. */
1771 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1772 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1775 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1776 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1777 exec_node_init(&m
->link
);
1780 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1782 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1790 * Does the miptree slice have hiz enabled?
1793 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1795 intel_miptree_check_level_layer(mt
, level
, 0);
1796 return mt
->level
[level
].has_hiz
;
1800 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1804 if (!intel_miptree_level_has_hiz(mt
, level
))
1807 intel_resolve_map_set(&mt
->hiz_map
,
1808 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1813 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1817 if (!intel_miptree_level_has_hiz(mt
, level
))
1820 intel_resolve_map_set(&mt
->hiz_map
,
1821 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1825 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1829 uint32_t end_layer
= mt
->level
[level
].depth
;
1831 for (layer
= 0; layer
< end_layer
; layer
++) {
1832 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1837 intel_miptree_slice_resolve(struct brw_context
*brw
,
1838 struct intel_mipmap_tree
*mt
,
1841 enum gen6_hiz_op need
)
1843 intel_miptree_check_level_layer(mt
, level
, layer
);
1845 struct intel_resolve_map
*item
=
1846 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1848 if (!item
|| item
->need
!= need
)
1851 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1852 intel_resolve_map_remove(item
);
1857 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1858 struct intel_mipmap_tree
*mt
,
1862 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1863 GEN6_HIZ_OP_HIZ_RESOLVE
);
1867 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1868 struct intel_mipmap_tree
*mt
,
1872 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1873 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1877 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1878 struct intel_mipmap_tree
*mt
,
1879 enum gen6_hiz_op need
)
1881 bool did_resolve
= false;
1883 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
1884 if (map
->need
!= need
)
1887 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
1888 intel_resolve_map_remove(map
);
1896 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1897 struct intel_mipmap_tree
*mt
)
1899 return intel_miptree_all_slices_resolve(brw
, mt
,
1900 GEN6_HIZ_OP_HIZ_RESOLVE
);
1904 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1905 struct intel_mipmap_tree
*mt
)
1907 return intel_miptree_all_slices_resolve(brw
, mt
,
1908 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1913 intel_miptree_resolve_color(struct brw_context
*brw
,
1914 struct intel_mipmap_tree
*mt
)
1916 switch (mt
->fast_clear_state
) {
1917 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1918 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1919 /* No resolve needed */
1921 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1922 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1923 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1924 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1925 brw_meta_resolve_color(brw
, mt
);
1932 * Make it possible to share the BO backing the given miptree with another
1933 * process or another miptree.
1935 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1936 * then discard the MCS buffer, if present. We also set the fast_clear_state
1937 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1938 * allocated in the future.
1941 intel_miptree_make_shareable(struct brw_context
*brw
,
1942 struct intel_mipmap_tree
*mt
)
1944 /* MCS buffers are also used for multisample buffers, but we can't resolve
1945 * away a multisample MCS buffer because it's an integral part of how the
1946 * pixel data is stored. Fortunately this code path should never be
1947 * reached for multisample buffers.
1949 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1952 intel_miptree_resolve_color(brw
, mt
);
1953 intel_miptree_release(&mt
->mcs_mt
);
1954 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
1960 * \brief Get pointer offset into stencil buffer.
1962 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1963 * must decode the tile's layout in software.
1966 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1968 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1970 * Even though the returned offset is always positive, the return type is
1972 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1973 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1976 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1978 uint32_t tile_size
= 4096;
1979 uint32_t tile_width
= 64;
1980 uint32_t tile_height
= 64;
1981 uint32_t row_size
= 64 * stride
;
1983 uint32_t tile_x
= x
/ tile_width
;
1984 uint32_t tile_y
= y
/ tile_height
;
1986 /* The byte's address relative to the tile's base addres. */
1987 uint32_t byte_x
= x
% tile_width
;
1988 uint32_t byte_y
= y
% tile_height
;
1990 uintptr_t u
= tile_y
* row_size
1991 + tile_x
* tile_size
1992 + 512 * (byte_x
/ 8)
1994 + 32 * ((byte_y
/ 4) % 2)
1995 + 16 * ((byte_x
/ 4) % 2)
1996 + 8 * ((byte_y
/ 2) % 2)
1997 + 4 * ((byte_x
/ 2) % 2)
2002 /* adjust for bit6 swizzling */
2003 if (((byte_x
/ 8) % 2) == 1) {
2004 if (((byte_y
/ 8) % 2) == 0) {
2016 intel_miptree_updownsample(struct brw_context
*brw
,
2017 struct intel_mipmap_tree
*src
,
2018 struct intel_mipmap_tree
*dst
)
2021 brw_blorp_blit_miptrees(brw
,
2022 src
, 0 /* level */, 0 /* layer */, src
->format
,
2023 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2025 src
->logical_width0
, src
->logical_height0
,
2027 dst
->logical_width0
, dst
->logical_height0
,
2028 GL_NEAREST
, false, false /*mirror x, y*/);
2029 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
2030 brw_meta_stencil_updownsample(brw
, src
, dst
);
2032 brw_meta_updownsample(brw
, src
, dst
);
2035 if (src
->stencil_mt
) {
2036 if (brw
->gen
>= 8) {
2037 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
2041 brw_blorp_blit_miptrees(brw
,
2042 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2043 src
->stencil_mt
->format
,
2044 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2045 dst
->stencil_mt
->format
,
2047 src
->logical_width0
, src
->logical_height0
,
2049 dst
->logical_width0
, dst
->logical_height0
,
2050 GL_NEAREST
, false, false /*mirror x, y*/);
2055 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2057 /* CPU accesses to color buffers don't understand fast color clears, so
2058 * resolve any pending fast color clears before we map.
2060 intel_miptree_resolve_color(brw
, mt
);
2062 drm_intel_bo
*bo
= mt
->bo
;
2064 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2065 intel_batchbuffer_flush(brw
);
2067 if (mt
->tiling
!= I915_TILING_NONE
)
2068 brw_bo_map_gtt(brw
, bo
, "miptree");
2070 brw_bo_map(brw
, bo
, true, "miptree");
2076 intel_miptree_unmap_raw(struct brw_context
*brw
,
2077 struct intel_mipmap_tree
*mt
)
2079 drm_intel_bo_unmap(mt
->bo
);
2083 intel_miptree_map_gtt(struct brw_context
*brw
,
2084 struct intel_mipmap_tree
*mt
,
2085 struct intel_miptree_map
*map
,
2086 unsigned int level
, unsigned int slice
)
2088 unsigned int bw
, bh
;
2090 unsigned int image_x
, image_y
;
2091 intptr_t x
= map
->x
;
2092 intptr_t y
= map
->y
;
2094 /* For compressed formats, the stride is the number of bytes per
2095 * row of blocks. intel_miptree_get_image_offset() already does
2098 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2099 assert(y
% bh
== 0);
2100 assert(x
% bw
== 0);
2104 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2109 /* Note that in the case of cube maps, the caller must have passed the
2110 * slice number referencing the face.
2112 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2116 map
->stride
= mt
->pitch
;
2117 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2120 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2121 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2122 map
->x
, map
->y
, map
->w
, map
->h
,
2123 mt
, _mesa_get_format_name(mt
->format
),
2124 x
, y
, map
->ptr
, map
->stride
);
2128 intel_miptree_unmap_gtt(struct brw_context
*brw
,
2129 struct intel_mipmap_tree
*mt
,
2130 struct intel_miptree_map
*map
,
2134 intel_miptree_unmap_raw(brw
, mt
);
2138 intel_miptree_map_blit(struct brw_context
*brw
,
2139 struct intel_mipmap_tree
*mt
,
2140 struct intel_miptree_map
*map
,
2141 unsigned int level
, unsigned int slice
)
2143 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2146 0, MIPTREE_LAYOUT_TILING_NONE
);
2149 fprintf(stderr
, "Failed to allocate blit temporary\n");
2152 map
->stride
= map
->mt
->pitch
;
2154 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2155 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2156 * invalidate is set, since we'll be writing the whole rectangle from our
2157 * temporary buffer back out.
2159 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2160 if (!intel_miptree_blit(brw
,
2162 map
->x
, map
->y
, false,
2165 map
->w
, map
->h
, GL_COPY
)) {
2166 fprintf(stderr
, "Failed to blit\n");
2171 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
2173 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2174 map
->x
, map
->y
, map
->w
, map
->h
,
2175 mt
, _mesa_get_format_name(mt
->format
),
2176 level
, slice
, map
->ptr
, map
->stride
);
2181 intel_miptree_release(&map
->mt
);
2187 intel_miptree_unmap_blit(struct brw_context
*brw
,
2188 struct intel_mipmap_tree
*mt
,
2189 struct intel_miptree_map
*map
,
2193 struct gl_context
*ctx
= &brw
->ctx
;
2195 intel_miptree_unmap_raw(brw
, map
->mt
);
2197 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2198 bool ok
= intel_miptree_blit(brw
,
2202 map
->x
, map
->y
, false,
2203 map
->w
, map
->h
, GL_COPY
);
2204 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2207 intel_miptree_release(&map
->mt
);
2211 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2213 #if defined(USE_SSE41)
2215 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2216 struct intel_mipmap_tree
*mt
,
2217 struct intel_miptree_map
*map
,
2218 unsigned int level
, unsigned int slice
)
2220 assert(map
->mode
& GL_MAP_READ_BIT
);
2221 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2223 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2224 map
->x
, map
->y
, map
->w
, map
->h
,
2225 mt
, _mesa_get_format_name(mt
->format
),
2226 level
, slice
, map
->ptr
, map
->stride
);
2228 /* Map the original image */
2231 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2235 void *src
= intel_miptree_map_raw(brw
, mt
);
2238 src
+= image_y
* mt
->pitch
;
2239 src
+= image_x
* mt
->cpp
;
2241 /* Due to the pixel offsets for the particular image being mapped, our
2242 * src pointer may not be 16-byte aligned. However, if the pitch is
2243 * divisible by 16, then the amount by which it's misaligned will remain
2244 * consistent from row to row.
2246 assert((mt
->pitch
% 16) == 0);
2247 const int misalignment
= ((uintptr_t) src
) & 15;
2249 /* Create an untiled temporary buffer for the mapping. */
2250 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2252 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2254 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2255 /* Offset the destination so it has the same misalignment as src. */
2256 map
->ptr
= map
->buffer
+ misalignment
;
2258 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2260 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2261 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2262 void *src_ptr
= src
+ y
* mt
->pitch
;
2264 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2267 intel_miptree_unmap_raw(brw
, mt
);
2271 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2272 struct intel_mipmap_tree
*mt
,
2273 struct intel_miptree_map
*map
,
2277 _mesa_align_free(map
->buffer
);
2284 intel_miptree_map_s8(struct brw_context
*brw
,
2285 struct intel_mipmap_tree
*mt
,
2286 struct intel_miptree_map
*map
,
2287 unsigned int level
, unsigned int slice
)
2289 map
->stride
= map
->w
;
2290 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2294 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2295 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2296 * invalidate is set, since we'll be writing the whole rectangle from our
2297 * temporary buffer back out.
2299 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2300 uint8_t *untiled_s8_map
= map
->ptr
;
2301 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2302 unsigned int image_x
, image_y
;
2304 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2306 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2307 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2308 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2309 x
+ image_x
+ map
->x
,
2310 y
+ image_y
+ map
->y
,
2311 brw
->has_swizzling
);
2312 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2316 intel_miptree_unmap_raw(brw
, mt
);
2318 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2319 map
->x
, map
->y
, map
->w
, map
->h
,
2320 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2322 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2323 map
->x
, map
->y
, map
->w
, map
->h
,
2324 mt
, map
->ptr
, map
->stride
);
2329 intel_miptree_unmap_s8(struct brw_context
*brw
,
2330 struct intel_mipmap_tree
*mt
,
2331 struct intel_miptree_map
*map
,
2335 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2336 unsigned int image_x
, image_y
;
2337 uint8_t *untiled_s8_map
= map
->ptr
;
2338 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2340 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2342 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2343 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2344 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2347 brw
->has_swizzling
);
2348 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2352 intel_miptree_unmap_raw(brw
, mt
);
2359 intel_miptree_map_etc(struct brw_context
*brw
,
2360 struct intel_mipmap_tree
*mt
,
2361 struct intel_miptree_map
*map
,
2365 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2366 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2367 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2370 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2371 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2373 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2374 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2375 map
->w
, map
->h
, 1));
2376 map
->ptr
= map
->buffer
;
2380 intel_miptree_unmap_etc(struct brw_context
*brw
,
2381 struct intel_mipmap_tree
*mt
,
2382 struct intel_miptree_map
*map
,
2388 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2393 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2394 + image_y
* mt
->pitch
2395 + image_x
* mt
->cpp
;
2397 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2398 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2399 map
->ptr
, map
->stride
,
2402 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2403 map
->ptr
, map
->stride
,
2404 map
->w
, map
->h
, mt
->etc_format
);
2406 intel_miptree_unmap_raw(brw
, mt
);
2411 * Mapping function for packed depth/stencil miptrees backed by real separate
2412 * miptrees for depth and stencil.
2414 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2415 * separate from the depth buffer. Yet at the GL API level, we have to expose
2416 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2417 * be able to map that memory for texture storage and glReadPixels-type
2418 * operations. We give Mesa core that access by mallocing a temporary and
2419 * copying the data between the actual backing store and the temporary.
2422 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2423 struct intel_mipmap_tree
*mt
,
2424 struct intel_miptree_map
*map
,
2425 unsigned int level
, unsigned int slice
)
2427 struct intel_mipmap_tree
*z_mt
= mt
;
2428 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2429 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2430 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2432 map
->stride
= map
->w
* packed_bpp
;
2433 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2437 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2438 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2439 * invalidate is set, since we'll be writing the whole rectangle from our
2440 * temporary buffer back out.
2442 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2443 uint32_t *packed_map
= map
->ptr
;
2444 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2445 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2446 unsigned int s_image_x
, s_image_y
;
2447 unsigned int z_image_x
, z_image_y
;
2449 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2450 &s_image_x
, &s_image_y
);
2451 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2452 &z_image_x
, &z_image_y
);
2454 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2455 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2456 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2457 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2460 brw
->has_swizzling
);
2461 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2463 (map_x
+ z_image_x
));
2464 uint8_t s
= s_map
[s_offset
];
2465 uint32_t z
= z_map
[z_offset
];
2467 if (map_z32f_x24s8
) {
2468 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2469 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2471 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2476 intel_miptree_unmap_raw(brw
, s_mt
);
2477 intel_miptree_unmap_raw(brw
, z_mt
);
2479 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2481 map
->x
, map
->y
, map
->w
, map
->h
,
2482 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2483 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2484 map
->ptr
, map
->stride
);
2486 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2487 map
->x
, map
->y
, map
->w
, map
->h
,
2488 mt
, map
->ptr
, map
->stride
);
2493 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2494 struct intel_mipmap_tree
*mt
,
2495 struct intel_miptree_map
*map
,
2499 struct intel_mipmap_tree
*z_mt
= mt
;
2500 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2501 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2503 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2504 uint32_t *packed_map
= map
->ptr
;
2505 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2506 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2507 unsigned int s_image_x
, s_image_y
;
2508 unsigned int z_image_x
, z_image_y
;
2510 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2511 &s_image_x
, &s_image_y
);
2512 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2513 &z_image_x
, &z_image_y
);
2515 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2516 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2517 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2518 x
+ s_image_x
+ map
->x
,
2519 y
+ s_image_y
+ map
->y
,
2520 brw
->has_swizzling
);
2521 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2523 (x
+ z_image_x
+ map
->x
));
2525 if (map_z32f_x24s8
) {
2526 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2527 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2529 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2530 s_map
[s_offset
] = packed
>> 24;
2531 z_map
[z_offset
] = packed
;
2536 intel_miptree_unmap_raw(brw
, s_mt
);
2537 intel_miptree_unmap_raw(brw
, z_mt
);
2539 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2541 map
->x
, map
->y
, map
->w
, map
->h
,
2542 z_mt
, _mesa_get_format_name(z_mt
->format
),
2543 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2544 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2545 map
->ptr
, map
->stride
);
2552 * Create and attach a map to the miptree at (level, slice). Return the
2555 static struct intel_miptree_map
*
2556 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2565 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2570 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2571 mt
->level
[level
].slice
[slice
].map
= map
;
2583 * Release the map at (level, slice).
2586 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2590 struct intel_miptree_map
**map
;
2592 map
= &mt
->level
[level
].slice
[slice
].map
;
2598 can_blit_slice(struct intel_mipmap_tree
*mt
,
2599 unsigned int level
, unsigned int slice
)
2603 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2604 if (image_x
>= 32768 || image_y
>= 32768)
2607 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2608 if (mt
->pitch
>= 32768)
2615 use_intel_mipree_map_blit(struct brw_context
*brw
,
2616 struct intel_mipmap_tree
*mt
,
2622 /* It's probably not worth swapping to the blit ring because of
2623 * all the overhead involved.
2625 !(mode
& GL_MAP_WRITE_BIT
) &&
2627 (mt
->tiling
== I915_TILING_X
||
2628 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2629 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
)) &&
2630 can_blit_slice(mt
, level
, slice
))
2633 if (mt
->tiling
!= I915_TILING_NONE
&&
2634 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2635 assert(can_blit_slice(mt
, level
, slice
));
2643 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2644 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2645 * arithmetic overflow.
2647 * If you call this function and use \a out_stride, then you're doing pointer
2648 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2649 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2650 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2651 * which usually have type uint32_t or GLuint.
2654 intel_miptree_map(struct brw_context
*brw
,
2655 struct intel_mipmap_tree
*mt
,
2664 ptrdiff_t *out_stride
)
2666 struct intel_miptree_map
*map
;
2668 assert(mt
->num_samples
<= 1);
2670 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2677 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2678 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2679 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2682 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2683 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2684 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2685 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2686 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2687 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2688 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2689 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2690 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2691 #if defined(USE_SSE41)
2692 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
2693 !mt
->compressed
&& cpu_has_sse4_1
&&
2694 (mt
->pitch
% 16 == 0)) {
2695 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2698 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2701 *out_ptr
= map
->ptr
;
2702 *out_stride
= map
->stride
;
2704 if (map
->ptr
== NULL
)
2705 intel_miptree_release_map(mt
, level
, slice
);
2709 intel_miptree_unmap(struct brw_context
*brw
,
2710 struct intel_mipmap_tree
*mt
,
2714 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2716 assert(mt
->num_samples
<= 1);
2721 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
2722 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2724 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2725 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2726 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2727 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2728 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2729 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2730 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2731 } else if (map
->mt
) {
2732 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2733 #if defined(USE_SSE41)
2734 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2735 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2738 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2741 intel_miptree_release_map(mt
, level
, slice
);