2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
28 #include <drm_fourcc.h>
30 #include "intel_batchbuffer.h"
31 #include "intel_image.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_tex.h"
34 #include "intel_blit.h"
35 #include "intel_fbo.h"
37 #include "brw_blorp.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
48 #include "x86/common_x86_asm.h"
50 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
52 static void *intel_miptree_map_raw(struct brw_context
*brw
,
53 struct intel_mipmap_tree
*mt
,
56 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
59 intel_miptree_alloc_aux(struct brw_context
*brw
,
60 struct intel_mipmap_tree
*mt
);
63 intel_miptree_supports_mcs(struct brw_context
*brw
,
64 const struct intel_mipmap_tree
*mt
)
66 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
68 /* MCS compression only applies to multisampled miptrees */
69 if (mt
->surf
.samples
<= 1)
72 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
76 /* See isl_surf_get_mcs_surf for details. */
77 if (mt
->surf
.samples
== 16 && mt
->surf
.logical_level0_px
.width
> 8192)
80 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
81 switch (_mesa_get_format_base_format(mt
->format
)) {
82 case GL_DEPTH_COMPONENT
:
83 case GL_STENCIL_INDEX
:
84 case GL_DEPTH_STENCIL
:
87 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
89 * This field must be set to 0 for all SINT MSRTs when all RT channels
92 * In practice this means that we have to disable MCS for all signed
93 * integer MSAA buffers. The alternative, to disable MCS only when one
94 * of the render target channels is disabled, is impractical because it
95 * would require converting between CMS and UMS MSAA layouts on the fly,
98 if (devinfo
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
107 intel_tiling_supports_ccs(const struct brw_context
*brw
,
108 enum isl_tiling tiling
)
110 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
112 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
113 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
115 * - Support is limited to tiled render targets.
117 * Gen9 changes the restriction to Y-tile only.
119 if (devinfo
->gen
>= 9)
120 return tiling
== ISL_TILING_Y0
;
121 else if (devinfo
->gen
>= 7)
122 return tiling
!= ISL_TILING_LINEAR
;
128 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
129 * can be used. This doesn't (and should not) inspect any of the properties of
132 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
133 * beneath the "Fast Color Clear" bullet (p326):
135 * - Support is for non-mip-mapped and non-array surface types only.
137 * And then later, on p327:
139 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
142 * From the Skylake documentation, it is made clear that X-tiling is no longer
145 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
149 intel_miptree_supports_ccs(struct brw_context
*brw
,
150 const struct intel_mipmap_tree
*mt
)
152 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
154 /* MCS support does not exist prior to Gen7 */
155 if (devinfo
->gen
< 7)
158 /* This function applies only to non-multisampled render targets. */
159 if (mt
->surf
.samples
> 1)
162 /* MCS is only supported for color buffers */
163 switch (_mesa_get_format_base_format(mt
->format
)) {
164 case GL_DEPTH_COMPONENT
:
165 case GL_DEPTH_STENCIL
:
166 case GL_STENCIL_INDEX
:
170 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
173 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
174 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
175 mt
->surf
.logical_level0_px
.depth
> 1;
178 /* Multisample surfaces with the CMS layout are not layered surfaces,
179 * yet still have physical_depth0 > 1. Assert that we don't
180 * accidentally reject a multisampled surface here. We should have
181 * rejected it earlier by explicitly checking the sample count.
183 assert(mt
->surf
.samples
== 1);
186 /* Handle the hardware restrictions...
188 * All GENs have the following restriction: "MCS buffer for non-MSRT is
189 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
191 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
192 * Non-MultiSampler Render Target Restrictions) Support is for
193 * non-mip-mapped and non-array surface types only.
195 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
196 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
197 * surfaces are supported with MCS buffer layout with these alignments in
198 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
200 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
201 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
202 * surfaces are supported with MCS buffer layout with these alignments in
203 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
205 if (devinfo
->gen
< 8 && (mip_mapped
|| arrayed
))
208 /* There's no point in using an MCS buffer if the surface isn't in a
211 if (!brw
->mesa_format_supports_render
[mt
->format
])
218 intel_tiling_supports_hiz(const struct brw_context
*brw
,
219 enum isl_tiling tiling
)
221 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
223 if (devinfo
->gen
< 6)
226 return tiling
== ISL_TILING_Y0
;
230 intel_miptree_supports_hiz(const struct brw_context
*brw
,
231 const struct intel_mipmap_tree
*mt
)
236 switch (mt
->format
) {
237 case MESA_FORMAT_Z_FLOAT32
:
238 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
239 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
240 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
241 case MESA_FORMAT_Z_UNORM16
:
249 * Return true if the format that will be used to access the miptree is
250 * CCS_E-compatible with the miptree's linear/non-sRGB format.
252 * Why use the linear format? Well, although the miptree may be specified with
253 * an sRGB format, the usage of that color space/format can be toggled. Since
254 * our HW tends to support more linear formats than sRGB ones, we use this
255 * format variant for check for CCS_E compatibility.
258 format_ccs_e_compat_with_miptree(const struct gen_device_info
*devinfo
,
259 const struct intel_mipmap_tree
*mt
,
260 enum isl_format access_format
)
262 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
264 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
265 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
266 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
270 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
271 const struct intel_mipmap_tree
*mt
)
273 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
275 if (devinfo
->gen
< 9)
278 /* For now compression is only enabled for integer formats even though
279 * there exist supported floating point formats also. This is a heuristic
280 * decision based on current public benchmarks. In none of the cases these
281 * formats provided any improvement but a few cases were seen to regress.
282 * Hence these are left to to be enabled in the future when they are known
285 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
288 if (!intel_miptree_supports_ccs(brw
, mt
))
291 /* Many window system buffers are sRGB even if they are never rendered as
292 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
293 * surface is used as sRGB, we fall back to CCS_D.
295 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
296 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
297 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
301 * Determine depth format corresponding to a depth+stencil format,
302 * for separate stencil.
305 intel_depth_format_for_depthstencil_format(mesa_format format
) {
307 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
308 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
309 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
310 return MESA_FORMAT_Z_FLOAT32
;
317 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
318 unsigned depth0
, struct intel_mipmap_level
*table
)
320 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
322 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
324 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
325 if (!table
[level
].slice
)
332 for (unsigned level
= first_level
; level
<= last_level
; level
++)
333 free(table
[level
].slice
);
339 needs_separate_stencil(const struct brw_context
*brw
,
340 struct intel_mipmap_tree
*mt
,
343 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
345 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
348 if (devinfo
->must_use_separate_stencil
)
351 return brw
->has_separate_stencil
&&
352 intel_miptree_supports_hiz(brw
, mt
);
356 * Choose the aux usage for this miptree. This function must be called fairly
357 * late in the miptree create process after we have a tiling.
360 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
361 struct intel_mipmap_tree
*mt
)
363 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
365 if (intel_miptree_supports_mcs(brw
, mt
)) {
366 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
367 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
368 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
369 intel_miptree_supports_ccs(brw
, mt
)) {
370 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
371 intel_miptree_supports_ccs_e(brw
, mt
)) {
372 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
374 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
376 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
377 intel_miptree_supports_hiz(brw
, mt
)) {
378 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
381 /* We can do fast-clear on all auxiliary surface types that are
382 * allocated through the normal texture creation paths.
384 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
385 mt
->supports_fast_clear
= true;
390 * Choose an appropriate uncompressed format for a requested
391 * compressed format, if unsupported.
394 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
396 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
398 /* No need to lower ETC formats on these platforms,
399 * they are supported natively.
401 if (devinfo
->gen
>= 8 || devinfo
->is_baytrail
)
405 case MESA_FORMAT_ETC1_RGB8
:
406 return MESA_FORMAT_R8G8B8X8_UNORM
;
407 case MESA_FORMAT_ETC2_RGB8
:
408 return MESA_FORMAT_R8G8B8X8_UNORM
;
409 case MESA_FORMAT_ETC2_SRGB8
:
410 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
411 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
412 return MESA_FORMAT_B8G8R8A8_SRGB
;
413 case MESA_FORMAT_ETC2_RGBA8_EAC
:
414 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
415 return MESA_FORMAT_R8G8B8A8_UNORM
;
416 case MESA_FORMAT_ETC2_R11_EAC
:
417 return MESA_FORMAT_R_UNORM16
;
418 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
419 return MESA_FORMAT_R_SNORM16
;
420 case MESA_FORMAT_ETC2_RG11_EAC
:
421 return MESA_FORMAT_R16G16_UNORM
;
422 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
423 return MESA_FORMAT_R16G16_SNORM
;
425 /* Non ETC1 / ETC2 format */
431 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
433 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
434 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
436 return mt
->surf
.logical_level0_px
.array_len
;
439 UNUSED
static unsigned
440 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
442 /* In case of physical dimensions one needs to consider also the layout.
443 * See isl_calc_phys_level0_extent_sa().
445 if (surf
->dim
!= ISL_SURF_DIM_3D
)
446 return surf
->phys_level0_sa
.array_len
;
448 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
449 return minify(surf
->phys_level0_sa
.array_len
, level
);
451 return minify(surf
->phys_level0_sa
.depth
, level
);
454 /** \brief Assert that the level and layer are valid for the miptree. */
456 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
464 assert(level
>= mt
->first_level
);
465 assert(level
<= mt
->last_level
);
466 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
469 static enum isl_aux_state
**
470 create_aux_state_map(struct intel_mipmap_tree
*mt
,
471 enum isl_aux_state initial
)
473 const uint32_t levels
= mt
->last_level
+ 1;
475 uint32_t total_slices
= 0;
476 for (uint32_t level
= 0; level
< levels
; level
++)
477 total_slices
+= brw_get_num_logical_layers(mt
, level
);
479 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
481 /* We're going to allocate a single chunk of data for both the per-level
482 * reference array and the arrays of aux_state. This makes cleanup
483 * significantly easier.
485 const size_t total_size
= per_level_array_size
+
486 total_slices
* sizeof(enum isl_aux_state
);
487 void *data
= malloc(total_size
);
491 enum isl_aux_state
**per_level_arr
= data
;
492 enum isl_aux_state
*s
= data
+ per_level_array_size
;
493 for (uint32_t level
= 0; level
< levels
; level
++) {
494 per_level_arr
[level
] = s
;
495 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
496 for (uint32_t a
= 0; a
< level_layers
; a
++)
499 assert((void *)s
== data
+ total_size
);
501 return per_level_arr
;
505 free_aux_state_map(enum isl_aux_state
**state
)
511 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
512 enum isl_tiling tiling
, unsigned samples
)
517 if (tiling
== ISL_TILING_LINEAR
)
520 /* If the width is much smaller than a tile, don't bother tiling. */
524 if (ALIGN(row_pitch
, 512) >= 32768) {
525 perf_debug("row pitch %u too large to blit, falling back to untiled",
534 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
535 enum isl_tiling tiling
)
537 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
539 /* If the BO is too large to fit in the aperture, we need to use the
540 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
541 * handle Y-tiling, so we need to fall back to X.
543 if (devinfo
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
544 tiling
== ISL_TILING_Y0
)
550 static struct intel_mipmap_tree
*
551 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
552 unsigned first_level
, unsigned last_level
,
553 unsigned width0
, unsigned height0
, unsigned depth0
,
554 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
555 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
556 unsigned row_pitch
, struct brw_bo
*bo
)
558 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
562 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
570 if (target
== GL_TEXTURE_CUBE_MAP
||
571 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
572 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
574 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
576 _mesa_enum_to_string(target
),
577 _mesa_get_format_name(format
),
578 num_samples
, width0
, height0
, depth0
,
579 first_level
, last_level
, mt
);
581 struct isl_surf_init_info init_info
= {
582 .dim
= get_isl_surf_dim(target
),
583 .format
= translate_tex_format(brw
, format
, false),
586 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
587 .levels
= last_level
- first_level
+ 1,
588 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
589 .samples
= num_samples
,
590 .row_pitch
= row_pitch
,
591 .usage
= isl_usage_flags
,
592 .tiling_flags
= tiling_flags
,
595 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
598 /* Depth surfaces are always Y-tiled and stencil is always W-tiled, although
599 * on gen7 platforms we also need to create Y-tiled copies of stencil for
600 * texturing since the hardware can't sample from W-tiled surfaces. For
601 * everything else, check for corner cases needing special treatment.
603 bool is_depth_stencil
=
604 mt
->surf
.usage
& (ISL_SURF_USAGE_STENCIL_BIT
| ISL_SURF_USAGE_DEPTH_BIT
);
605 if (!is_depth_stencil
) {
606 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
607 mt
->surf
.tiling
, mt
->surf
.samples
)) {
608 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
609 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
611 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
612 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
613 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
618 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
619 * the size may not be multiple of row_pitch.
620 * See isl_apply_surface_padding().
622 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
623 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
626 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
628 isl_tiling_to_i915_tiling(
630 mt
->surf
.row_pitch
, alloc_flags
);
637 mt
->first_level
= first_level
;
638 mt
->last_level
= last_level
;
641 mt
->aux_state
= NULL
;
642 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
643 mt
->compressed
= _mesa_is_format_compressed(format
);
644 mt
->drm_modifier
= DRM_FORMAT_MOD_INVALID
;
649 intel_miptree_release(&mt
);
654 make_separate_stencil_surface(struct brw_context
*brw
,
655 struct intel_mipmap_tree
*mt
)
657 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
658 0, mt
->surf
.levels
- 1,
659 mt
->surf
.logical_level0_px
.width
,
660 mt
->surf
.logical_level0_px
.height
,
661 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
662 mt
->surf
.logical_level0_px
.depth
:
663 mt
->surf
.logical_level0_px
.array_len
,
664 mt
->surf
.samples
, ISL_TILING_W_BIT
,
665 ISL_SURF_USAGE_STENCIL_BIT
|
666 ISL_SURF_USAGE_TEXTURE_BIT
,
667 BO_ALLOC_BUSY
, 0, NULL
);
672 mt
->stencil_mt
->r8stencil_needs_update
= true;
677 static struct intel_mipmap_tree
*
678 miptree_create(struct brw_context
*brw
,
687 enum intel_miptree_create_flags flags
)
689 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
691 if (format
== MESA_FORMAT_S_UINT8
)
692 return make_surface(brw
, target
, format
, first_level
, last_level
,
693 width0
, height0
, depth0
, num_samples
,
695 ISL_SURF_USAGE_STENCIL_BIT
|
696 ISL_SURF_USAGE_TEXTURE_BIT
,
701 const GLenum base_format
= _mesa_get_format_base_format(format
);
702 if ((base_format
== GL_DEPTH_COMPONENT
||
703 base_format
== GL_DEPTH_STENCIL
) &&
704 !(flags
& MIPTREE_CREATE_LINEAR
)) {
705 /* Fix up the Z miptree format for how we're splitting out separate
706 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
708 const mesa_format depth_only_format
=
709 intel_depth_format_for_depthstencil_format(format
);
710 struct intel_mipmap_tree
*mt
= make_surface(
711 brw
, target
, devinfo
->gen
>= 6 ? depth_only_format
: format
,
712 first_level
, last_level
,
713 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
714 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
715 BO_ALLOC_BUSY
, 0, NULL
);
717 if (needs_separate_stencil(brw
, mt
, format
) &&
718 !make_separate_stencil_surface(brw
, mt
)) {
719 intel_miptree_release(&mt
);
723 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
724 intel_miptree_choose_aux_usage(brw
, mt
);
729 mesa_format tex_format
= format
;
730 mesa_format etc_format
= MESA_FORMAT_NONE
;
731 uint32_t alloc_flags
= 0;
733 format
= intel_lower_compressed_format(brw
, format
);
735 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
737 if (flags
& MIPTREE_CREATE_BUSY
)
738 alloc_flags
|= BO_ALLOC_BUSY
;
740 isl_tiling_flags_t tiling_flags
= (flags
& MIPTREE_CREATE_LINEAR
) ?
741 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
743 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
744 if (devinfo
->gen
< 6)
745 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
747 struct intel_mipmap_tree
*mt
= make_surface(
749 first_level
, last_level
,
750 width0
, height0
, depth0
,
751 num_samples
, tiling_flags
,
752 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
753 ISL_SURF_USAGE_TEXTURE_BIT
,
754 alloc_flags
, 0, NULL
);
758 mt
->etc_format
= etc_format
;
760 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
761 intel_miptree_choose_aux_usage(brw
, mt
);
766 struct intel_mipmap_tree
*
767 intel_miptree_create(struct brw_context
*brw
,
776 enum intel_miptree_create_flags flags
)
778 assert(num_samples
> 0);
780 struct intel_mipmap_tree
*mt
= miptree_create(
782 first_level
, last_level
,
783 width0
, height0
, depth0
, num_samples
,
790 if (!intel_miptree_alloc_aux(brw
, mt
)) {
791 intel_miptree_release(&mt
);
798 struct intel_mipmap_tree
*
799 intel_miptree_create_for_bo(struct brw_context
*brw
,
807 enum intel_miptree_create_flags flags
)
809 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
810 struct intel_mipmap_tree
*mt
;
811 uint32_t tiling
, swizzle
;
812 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
813 const GLenum base_format
= _mesa_get_format_base_format(format
);
815 if ((base_format
== GL_DEPTH_COMPONENT
||
816 base_format
== GL_DEPTH_STENCIL
)) {
817 const mesa_format depth_only_format
=
818 intel_depth_format_for_depthstencil_format(format
);
819 mt
= make_surface(brw
, target
,
820 devinfo
->gen
>= 6 ? depth_only_format
: format
,
821 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
822 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
823 BO_ALLOC_BUSY
, pitch
, bo
);
827 brw_bo_reference(bo
);
829 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
830 intel_miptree_choose_aux_usage(brw
, mt
);
833 } else if (format
== MESA_FORMAT_S_UINT8
) {
834 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
835 0, 0, width
, height
, depth
, 1,
837 ISL_SURF_USAGE_STENCIL_BIT
|
838 ISL_SURF_USAGE_TEXTURE_BIT
,
839 BO_ALLOC_BUSY
, pitch
, bo
);
843 assert(bo
->size
>= mt
->surf
.size
);
845 brw_bo_reference(bo
);
849 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
851 /* Nothing will be able to use this miptree with the BO if the offset isn't
854 if (tiling
!= I915_TILING_NONE
)
855 assert(offset
% 4096 == 0);
857 /* miptrees can't handle negative pitch. If you need flipping of images,
858 * that's outside of the scope of the mt.
862 /* The BO already has a tiling format and we shouldn't confuse the lower
863 * layers by making it try to find a tiling format again.
865 assert((flags
& MIPTREE_CREATE_LINEAR
) == 0);
867 mt
= make_surface(brw
, target
, format
,
868 0, 0, width
, height
, depth
, 1,
869 1lu << isl_tiling_from_i915_tiling(tiling
),
870 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
871 ISL_SURF_USAGE_TEXTURE_BIT
,
876 brw_bo_reference(bo
);
880 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
881 intel_miptree_choose_aux_usage(brw
, mt
);
883 if (!intel_miptree_alloc_aux(brw
, mt
)) {
884 intel_miptree_release(&mt
);
892 static struct intel_mipmap_tree
*
893 miptree_create_for_planar_image(struct brw_context
*brw
,
894 __DRIimage
*image
, GLenum target
)
896 const struct intel_image_format
*f
= image
->planar_format
;
897 struct intel_mipmap_tree
*planar_mt
= NULL
;
899 for (int i
= 0; i
< f
->nplanes
; i
++) {
900 const int index
= f
->planes
[i
].buffer_index
;
901 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
902 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
903 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
904 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
906 /* Disable creation of the texture's aux buffers because the driver
907 * exposes no EGL API to manage them. That is, there is no API for
908 * resolving the aux buffer's content to the main buffer nor for
909 * invalidating the aux buffer's content.
911 struct intel_mipmap_tree
*mt
=
912 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
913 image
->offsets
[index
],
915 image
->strides
[index
],
916 MIPTREE_CREATE_NO_AUX
);
925 planar_mt
->plane
[i
- 1] = mt
;
928 planar_mt
->drm_modifier
= image
->modifier
;
934 create_ccs_buf_for_image(struct brw_context
*brw
,
936 struct intel_mipmap_tree
*mt
,
937 enum isl_aux_state initial_state
)
939 struct isl_surf temp_ccs_surf
;
941 /* CCS is only supported for very simple miptrees */
942 assert(image
->aux_offset
!= 0 && image
->aux_pitch
!= 0);
943 assert(image
->tile_x
== 0 && image
->tile_y
== 0);
944 assert(mt
->surf
.samples
== 1);
945 assert(mt
->surf
.levels
== 1);
946 assert(mt
->surf
.logical_level0_px
.depth
== 1);
947 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
948 assert(mt
->first_level
== 0);
949 assert(mt
->last_level
== 0);
951 /* We shouldn't already have a CCS */
952 assert(!mt
->mcs_buf
);
954 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
,
958 assert(image
->aux_offset
< image
->bo
->size
);
959 assert(temp_ccs_surf
.size
<= image
->bo
->size
- image
->aux_offset
);
961 mt
->mcs_buf
= calloc(sizeof(*mt
->mcs_buf
), 1);
962 if (mt
->mcs_buf
== NULL
)
965 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
966 if (!mt
->aux_state
) {
972 mt
->mcs_buf
->bo
= image
->bo
;
973 brw_bo_reference(image
->bo
);
975 mt
->mcs_buf
->offset
= image
->aux_offset
;
976 mt
->mcs_buf
->size
= image
->bo
->size
- image
->aux_offset
;
977 mt
->mcs_buf
->pitch
= image
->aux_pitch
;
978 mt
->mcs_buf
->qpitch
= 0;
979 mt
->mcs_buf
->surf
= temp_ccs_surf
;
984 struct intel_mipmap_tree
*
985 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
986 __DRIimage
*image
, GLenum target
,
988 bool is_winsys_image
)
990 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1)
991 return miptree_create_for_planar_image(brw
, image
, target
);
993 if (image
->planar_format
)
994 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
996 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
997 /* The texture storage paths in core Mesa detect if the driver does not
998 * support the user-requested format, and then searches for a
999 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1000 * do the fallbacks here for important formats.
1002 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1003 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1004 * the Chrome OS compositor consumes as dma_buf EGLImages.
1006 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1009 if (!brw
->ctx
.TextureFormatSupported
[format
])
1012 const struct isl_drm_modifier_info
*mod_info
=
1013 isl_drm_modifier_get_info(image
->modifier
);
1015 enum intel_miptree_create_flags mt_create_flags
= 0;
1017 /* If this image comes in from a window system, we have different
1018 * requirements than if it comes in via an EGL import operation. Window
1019 * system images can use any form of auxiliary compression we wish because
1020 * they get "flushed" before being handed off to the window system and we
1021 * have the opportunity to do resolves. Non window-system images, on the
1022 * other hand, have no resolve point so we can't have aux without a
1025 if (!is_winsys_image
)
1026 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1028 /* If we have a modifier which specifies aux, don't create one yet */
1029 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
1030 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1032 /* Disable creation of the texture's aux buffers because the driver exposes
1033 * no EGL API to manage them. That is, there is no API for resolving the aux
1034 * buffer's content to the main buffer nor for invalidating the aux buffer's
1037 struct intel_mipmap_tree
*mt
=
1038 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1039 image
->offset
, image
->width
, image
->height
, 1,
1040 image
->pitch
, mt_create_flags
);
1044 mt
->target
= target
;
1045 mt
->level
[0].level_x
= image
->tile_x
;
1046 mt
->level
[0].level_y
= image
->tile_y
;
1047 mt
->drm_modifier
= image
->modifier
;
1049 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1050 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1051 * trouble resolving back to destination image due to alignment issues.
1053 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1054 if (!devinfo
->has_surface_tile_offset
) {
1055 uint32_t draw_x
, draw_y
;
1056 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1058 if (draw_x
!= 0 || draw_y
!= 0) {
1059 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1060 intel_miptree_release(&mt
);
1065 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1066 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1068 mt
->aux_usage
= mod_info
->aux_usage
;
1069 /* If we are a window system buffer, then we can support fast-clears
1070 * even if the modifier doesn't support them by doing a partial resolve
1071 * as part of the flush operation.
1073 mt
->supports_fast_clear
=
1074 is_winsys_image
|| mod_info
->supports_clear_color
;
1076 /* We don't know the actual state of the surface when we get it but we
1077 * can make a pretty good guess based on the modifier. What we do know
1078 * for sure is that it isn't in the AUX_INVALID state, so we just assume
1079 * a worst case of compression.
1081 enum isl_aux_state initial_state
=
1082 isl_drm_modifier_get_default_aux_state(image
->modifier
);
1084 if (!create_ccs_buf_for_image(brw
, image
, mt
, initial_state
)) {
1085 intel_miptree_release(&mt
);
1090 /* Don't assume coherency for imported EGLimages. We don't know what
1091 * external clients are going to do with it. They may scan it out.
1093 image
->bo
->cache_coherent
= false;
1099 * For a singlesample renderbuffer, this simply wraps the given BO with a
1102 * For a multisample renderbuffer, this wraps the window system's
1103 * (singlesample) BO with a singlesample miptree attached to the
1104 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1105 * that will contain the actual rendering (which is lazily resolved to
1106 * irb->singlesample_mt).
1109 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1110 struct intel_renderbuffer
*irb
,
1111 struct intel_mipmap_tree
*singlesample_mt
,
1112 uint32_t width
, uint32_t height
,
1115 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1116 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1117 mesa_format format
= rb
->Format
;
1118 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1120 /* Only the front and back buffers, which are color buffers, are allocated
1121 * through the image loader.
1123 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1124 _mesa_get_format_base_format(format
) == GL_RGBA
);
1126 assert(singlesample_mt
);
1128 if (num_samples
== 1) {
1129 intel_miptree_release(&irb
->mt
);
1130 irb
->mt
= singlesample_mt
;
1132 assert(!irb
->singlesample_mt
);
1134 intel_miptree_release(&irb
->singlesample_mt
);
1135 irb
->singlesample_mt
= singlesample_mt
;
1138 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1139 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1140 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1145 if (!multisample_mt
)
1148 irb
->need_downsample
= false;
1149 intel_miptree_release(&irb
->mt
);
1150 irb
->mt
= multisample_mt
;
1156 intel_miptree_release(&irb
->mt
);
1160 struct intel_mipmap_tree
*
1161 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1165 uint32_t num_samples
)
1167 struct intel_mipmap_tree
*mt
;
1169 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1171 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1172 width
, height
, depth
, num_samples
,
1173 MIPTREE_CREATE_BUSY
);
1180 intel_miptree_release(&mt
);
1185 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1186 struct intel_mipmap_tree
*src
)
1191 intel_miptree_release(dst
);
1195 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1202 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1204 if (aux_buf
== NULL
)
1207 brw_bo_unreference(aux_buf
->bo
);
1213 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1218 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1219 if (--(*mt
)->refcount
<= 0) {
1222 DBG("%s deleting %p\n", __func__
, *mt
);
1224 brw_bo_unreference((*mt
)->bo
);
1225 intel_miptree_release(&(*mt
)->stencil_mt
);
1226 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1227 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1228 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1229 free_aux_state_map((*mt
)->aux_state
);
1231 intel_miptree_release(&(*mt
)->plane
[0]);
1232 intel_miptree_release(&(*mt
)->plane
[1]);
1234 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1235 free((*mt
)->level
[i
].slice
);
1245 intel_get_image_dims(struct gl_texture_image
*image
,
1246 int *width
, int *height
, int *depth
)
1248 switch (image
->TexObject
->Target
) {
1249 case GL_TEXTURE_1D_ARRAY
:
1250 /* For a 1D Array texture the OpenGL API will treat the image height as
1251 * the number of array slices. For Intel hardware, we treat the 1D array
1252 * as a 2D Array with a height of 1. So, here we want to swap image
1255 assert(image
->Depth
== 1);
1256 *width
= image
->Width
;
1258 *depth
= image
->Height
;
1260 case GL_TEXTURE_CUBE_MAP
:
1261 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1262 * though we really have 6 slices.
1264 assert(image
->Depth
== 1);
1265 *width
= image
->Width
;
1266 *height
= image
->Height
;
1270 *width
= image
->Width
;
1271 *height
= image
->Height
;
1272 *depth
= image
->Depth
;
1278 * Can the image be pulled into a unified mipmap tree? This mirrors
1279 * the completeness test in a lot of ways.
1281 * Not sure whether I want to pass gl_texture_image here.
1284 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1285 struct gl_texture_image
*image
)
1287 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1288 GLuint level
= intelImage
->base
.Base
.Level
;
1289 int width
, height
, depth
;
1291 /* glTexImage* choose the texture object based on the target passed in, and
1292 * objects can't change targets over their lifetimes, so this should be
1295 assert(image
->TexObject
->Target
== mt
->target
);
1297 mesa_format mt_format
= mt
->format
;
1298 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1299 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1300 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1301 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1302 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1303 mt_format
= mt
->etc_format
;
1305 if (image
->TexFormat
!= mt_format
)
1308 intel_get_image_dims(image
, &width
, &height
, &depth
);
1310 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1313 if (level
>= mt
->surf
.levels
)
1316 const unsigned level_depth
=
1317 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1318 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1319 mt
->surf
.logical_level0_px
.array_len
;
1321 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1322 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1323 depth
== level_depth
&&
1324 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1328 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1329 GLuint level
, GLuint slice
,
1330 GLuint
*x
, GLuint
*y
)
1332 if (level
== 0 && slice
== 0) {
1333 *x
= mt
->level
[0].level_x
;
1334 *y
= mt
->level
[0].level_y
;
1338 uint32_t x_offset_sa
, y_offset_sa
;
1340 /* Miptree itself can have an offset only if it represents a single
1341 * slice in an imported buffer object.
1342 * See intel_miptree_create_for_dri_image().
1344 assert(mt
->level
[0].level_x
== 0);
1345 assert(mt
->level
[0].level_y
== 0);
1347 /* Given level is relative to level zero while the miptree may be
1348 * represent just a subset of all levels starting from 'first_level'.
1350 assert(level
>= mt
->first_level
);
1351 level
-= mt
->first_level
;
1353 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1354 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1355 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1356 &x_offset_sa
, &y_offset_sa
);
1364 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1365 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1366 * and tile_h is set to 1.
1369 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1370 uint32_t *tile_w
, uint32_t *tile_h
)
1381 case ISL_TILING_LINEAR
:
1386 unreachable("not reached");
1392 * This function computes masks that may be used to select the bits of the X
1393 * and Y coordinates that indicate the offset within a tile. If the BO is
1394 * untiled, the masks are set to 0.
1397 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1398 uint32_t *mask_x
, uint32_t *mask_y
)
1400 uint32_t tile_w_bytes
, tile_h
;
1402 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1404 *mask_x
= tile_w_bytes
/ cpp
- 1;
1405 *mask_y
= tile_h
- 1;
1409 * Compute the offset (in bytes) from the start of the BO to the given x
1410 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1411 * multiples of the tile size.
1414 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1415 uint32_t x
, uint32_t y
)
1418 uint32_t pitch
= mt
->surf
.row_pitch
;
1420 switch (mt
->surf
.tiling
) {
1422 unreachable("not reached");
1423 case ISL_TILING_LINEAR
:
1424 return y
* pitch
+ x
* cpp
;
1426 assert((x
% (512 / cpp
)) == 0);
1427 assert((y
% 8) == 0);
1428 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1430 assert((x
% (128 / cpp
)) == 0);
1431 assert((y
% 32) == 0);
1432 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1437 * Rendering with tiled buffers requires that the base address of the buffer
1438 * be aligned to a page boundary. For renderbuffers, and sometimes with
1439 * textures, we may want the surface to point at a texture image level that
1440 * isn't at a page boundary.
1442 * This function returns an appropriately-aligned base offset
1443 * according to the tiling restrictions, plus any required x/y offset
1447 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1448 GLuint level
, GLuint slice
,
1453 uint32_t mask_x
, mask_y
;
1455 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1456 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1458 *tile_x
= x
& mask_x
;
1459 *tile_y
= y
& mask_y
;
1461 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1465 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1466 struct intel_mipmap_tree
*src_mt
,
1467 unsigned src_level
, unsigned src_layer
,
1468 struct intel_mipmap_tree
*dst_mt
,
1469 unsigned dst_level
, unsigned dst_layer
,
1470 unsigned width
, unsigned height
)
1473 ptrdiff_t src_stride
, dst_stride
;
1474 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1476 intel_miptree_map(brw
, src_mt
,
1477 src_level
, src_layer
,
1480 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1483 intel_miptree_map(brw
, dst_mt
,
1484 dst_level
, dst_layer
,
1487 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1491 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1492 _mesa_get_format_name(src_mt
->format
),
1493 src_mt
, src
, src_stride
,
1494 _mesa_get_format_name(dst_mt
->format
),
1495 dst_mt
, dst
, dst_stride
,
1498 int row_size
= cpp
* width
;
1499 if (src_stride
== row_size
&&
1500 dst_stride
== row_size
) {
1501 memcpy(dst
, src
, row_size
* height
);
1503 for (int i
= 0; i
< height
; i
++) {
1504 memcpy(dst
, src
, row_size
);
1510 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1511 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1513 /* Don't forget to copy the stencil data over, too. We could have skipped
1514 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1515 * shuffling the two data sources in/out of temporary storage instead of
1516 * the direct mapping we get this way.
1518 if (dst_mt
->stencil_mt
) {
1519 assert(src_mt
->stencil_mt
);
1520 intel_miptree_copy_slice_sw(brw
,
1521 src_mt
->stencil_mt
, src_level
, src_layer
,
1522 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1528 intel_miptree_copy_slice(struct brw_context
*brw
,
1529 struct intel_mipmap_tree
*src_mt
,
1530 unsigned src_level
, unsigned src_layer
,
1531 struct intel_mipmap_tree
*dst_mt
,
1532 unsigned dst_level
, unsigned dst_layer
)
1535 mesa_format format
= src_mt
->format
;
1536 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1537 src_level
- src_mt
->first_level
);
1538 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1539 src_level
- src_mt
->first_level
);
1541 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1542 src_level
- src_mt
->first_level
));
1544 assert(src_mt
->format
== dst_mt
->format
);
1546 if (dst_mt
->compressed
) {
1548 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1549 height
= ALIGN_NPOT(height
, j
) / j
;
1550 width
= ALIGN_NPOT(width
, i
) / i
;
1553 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1554 * below won't apply since we can't do the depth's Y tiling or the
1555 * stencil's W tiling in the blitter.
1557 if (src_mt
->stencil_mt
) {
1558 intel_miptree_copy_slice_sw(brw
,
1559 src_mt
, src_level
, src_layer
,
1560 dst_mt
, dst_level
, dst_layer
,
1565 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1566 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1568 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1571 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1572 _mesa_get_format_name(src_mt
->format
),
1573 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1574 _mesa_get_format_name(dst_mt
->format
),
1575 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1578 if (!intel_miptree_blit(brw
,
1579 src_mt
, src_level
, src_layer
, 0, 0, false,
1580 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1581 width
, height
, GL_COPY
)) {
1582 perf_debug("miptree validate blit for %s failed\n",
1583 _mesa_get_format_name(format
));
1585 intel_miptree_copy_slice_sw(brw
,
1586 src_mt
, src_level
, src_layer
,
1587 dst_mt
, dst_level
, dst_layer
,
1593 * Copies the image's current data to the given miptree, and associates that
1594 * miptree with the image.
1597 intel_miptree_copy_teximage(struct brw_context
*brw
,
1598 struct intel_texture_image
*intelImage
,
1599 struct intel_mipmap_tree
*dst_mt
)
1601 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1602 struct intel_texture_object
*intel_obj
=
1603 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1604 int level
= intelImage
->base
.Base
.Level
;
1605 const unsigned face
= intelImage
->base
.Base
.Face
;
1606 unsigned start_layer
, end_layer
;
1608 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1610 assert(intelImage
->base
.Base
.Height
);
1612 end_layer
= intelImage
->base
.Base
.Height
- 1;
1613 } else if (face
> 0) {
1617 assert(intelImage
->base
.Base
.Depth
);
1619 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1622 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1623 intel_miptree_copy_slice(brw
,
1628 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1629 intel_obj
->needs_validate
= true;
1633 intel_miptree_init_mcs(struct brw_context
*brw
,
1634 struct intel_mipmap_tree
*mt
,
1637 assert(mt
->mcs_buf
!= NULL
);
1639 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1641 * When MCS buffer is enabled and bound to MSRT, it is required that it
1642 * is cleared prior to any rendering.
1644 * Since we don't use the MCS buffer for any purpose other than rendering,
1645 * it makes sense to just clear it immediately upon allocation.
1647 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1649 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1650 if (unlikely(map
== NULL
)) {
1651 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1652 brw_bo_unreference(mt
->mcs_buf
->bo
);
1657 memset(data
, init_value
, mt
->mcs_buf
->size
);
1658 brw_bo_unmap(mt
->mcs_buf
->bo
);
1661 static struct intel_miptree_aux_buffer
*
1662 intel_alloc_aux_buffer(struct brw_context
*brw
,
1664 const struct isl_surf
*aux_surf
,
1665 uint32_t alloc_flags
,
1666 struct intel_mipmap_tree
*mt
)
1668 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1672 buf
->size
= aux_surf
->size
;
1673 buf
->pitch
= aux_surf
->row_pitch
;
1674 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1676 /* ISL has stricter set of alignment rules then the drm allocator.
1677 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1678 * trying to recalculate based on different format block sizes.
1680 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1681 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1687 buf
->surf
= *aux_surf
;
1693 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1694 struct intel_mipmap_tree
*mt
,
1697 assert(brw
->screen
->devinfo
.gen
>= 7); /* MCS only used on Gen7+ */
1698 assert(mt
->mcs_buf
== NULL
);
1699 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1701 /* Multisampled miptrees are only supported for single level. */
1702 assert(mt
->first_level
== 0);
1703 enum isl_aux_state
**aux_state
=
1704 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1708 struct isl_surf temp_mcs_surf
;
1710 MAYBE_UNUSED
bool ok
=
1711 isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_mcs_surf
);
1714 /* Buffer needs to be initialised requiring the buffer to be immediately
1715 * mapped to cpu space for writing. Therefore do not use the gpu access
1716 * flag which can cause an unnecessary delay if the backing pages happened
1717 * to be just used by the GPU.
1719 const uint32_t alloc_flags
= 0;
1720 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1721 &temp_mcs_surf
, alloc_flags
, mt
);
1727 mt
->aux_state
= aux_state
;
1729 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1735 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1736 struct intel_mipmap_tree
*mt
)
1738 assert(mt
->mcs_buf
== NULL
);
1739 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1740 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1742 struct isl_surf temp_ccs_surf
;
1744 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
, 0))
1747 assert(temp_ccs_surf
.size
&&
1748 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1750 enum isl_aux_state
**aux_state
=
1751 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1755 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1756 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1758 * "If Software wants to enable Color Compression without Fast clear,
1759 * Software needs to initialize MCS with zeros."
1761 * A CCS value of 0 indicates that the corresponding block is in the
1762 * pass-through state which is what we want.
1764 * For CCS_D, on the other hand, we don't care as we're about to perform a
1765 * fast-clear operation. In that case, being hot in caches more useful.
1767 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1768 BO_ALLOC_ZEROED
: BO_ALLOC_BUSY
;
1769 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1770 &temp_ccs_surf
, alloc_flags
, mt
);
1776 mt
->aux_state
= aux_state
;
1782 * Helper for intel_miptree_alloc_hiz() that sets
1783 * \c mt->level[level].has_hiz. Return true if and only if
1784 * \c has_hiz was set.
1787 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1788 struct intel_mipmap_tree
*mt
,
1791 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1793 assert(mt
->hiz_buf
);
1794 assert(mt
->surf
.size
> 0);
1796 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
1797 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1798 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1800 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1801 * and the height is 4 aligned. This allows our HiZ support
1802 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1803 * we can grow the width & height to allow the HiZ op to
1804 * force the proper size alignments.
1806 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1807 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1812 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1813 mt
->level
[level
].has_hiz
= true;
1818 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1819 struct intel_mipmap_tree
*mt
)
1821 assert(mt
->hiz_buf
== NULL
);
1822 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1824 enum isl_aux_state
**aux_state
=
1825 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1829 struct isl_surf temp_hiz_surf
;
1831 MAYBE_UNUSED
bool ok
=
1832 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
1835 const uint32_t alloc_flags
= BO_ALLOC_BUSY
;
1836 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1837 &temp_hiz_surf
, alloc_flags
, mt
);
1844 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1845 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1847 mt
->aux_state
= aux_state
;
1854 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1856 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1857 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1858 * compress clear color so we wait until an actual fast-clear to allocate it.
1861 intel_miptree_alloc_aux(struct brw_context
*brw
,
1862 struct intel_mipmap_tree
*mt
)
1864 switch (mt
->aux_usage
) {
1865 case ISL_AUX_USAGE_NONE
:
1868 case ISL_AUX_USAGE_HIZ
:
1869 assert(!_mesa_is_format_color_format(mt
->format
));
1870 if (!intel_miptree_alloc_hiz(brw
, mt
))
1874 case ISL_AUX_USAGE_MCS
:
1875 assert(_mesa_is_format_color_format(mt
->format
));
1876 assert(mt
->surf
.samples
> 1);
1877 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
1881 case ISL_AUX_USAGE_CCS_D
:
1882 /* Since CCS_D can only compress clear color so we wait until an actual
1883 * fast-clear to allocate it.
1887 case ISL_AUX_USAGE_CCS_E
:
1888 assert(_mesa_is_format_color_format(mt
->format
));
1889 assert(mt
->surf
.samples
== 1);
1890 if (!intel_miptree_alloc_ccs(brw
, mt
))
1895 unreachable("Invalid aux usage");
1900 * Can the miptree sample using the hiz buffer?
1903 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1904 struct intel_mipmap_tree
*mt
)
1906 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1908 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1909 * so keep things conservative for now and never enable it unless we're SKL+.
1911 if (devinfo
->gen
< 9) {
1919 /* It seems the hardware won't fallback to the depth buffer if some of the
1920 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1921 * of the texture to be HiZ enabled.
1923 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1924 if (!intel_miptree_level_has_hiz(mt
, level
))
1928 /* If compressed multisampling is enabled, then we use it for the auxiliary
1931 * From the BDW PRM (Volume 2d: Command Reference: Structures
1932 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1934 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1935 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1937 * There is no such blurb for 1D textures, but there is sufficient evidence
1938 * that this is broken on SKL+.
1940 return (mt
->surf
.samples
== 1 &&
1941 mt
->target
!= GL_TEXTURE_3D
&&
1942 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1946 * Does the miptree slice have hiz enabled?
1949 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1951 intel_miptree_check_level_layer(mt
, level
, 0);
1952 return mt
->level
[level
].has_hiz
;
1955 static inline uint32_t
1956 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1957 uint32_t start_level
, uint32_t num_levels
)
1959 assert(start_level
>= mt
->first_level
);
1960 assert(start_level
<= mt
->last_level
);
1962 if (num_levels
== INTEL_REMAINING_LAYERS
)
1963 num_levels
= mt
->last_level
- start_level
+ 1;
1964 /* Check for overflow */
1965 assert(start_level
+ num_levels
>= start_level
);
1966 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
1971 static inline uint32_t
1972 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
1973 uint32_t start_layer
, uint32_t num_layers
)
1975 assert(level
<= mt
->last_level
);
1977 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
1978 assert(start_layer
< total_num_layers
);
1979 if (num_layers
== INTEL_REMAINING_LAYERS
)
1980 num_layers
= total_num_layers
- start_layer
;
1981 /* Check for overflow */
1982 assert(start_layer
+ num_layers
>= start_layer
);
1983 assert(start_layer
+ num_layers
<= total_num_layers
);
1989 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1990 unsigned start_level
, unsigned num_levels
,
1991 unsigned start_layer
, unsigned num_layers
)
1993 assert(_mesa_is_format_color_format(mt
->format
));
1998 /* Clamp the level range to fit the miptree */
1999 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2001 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2002 const uint32_t level
= start_level
+ l
;
2003 const uint32_t level_layers
=
2004 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2005 for (unsigned a
= 0; a
< level_layers
; a
++) {
2006 enum isl_aux_state aux_state
=
2007 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2008 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2009 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2018 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2019 const struct intel_mipmap_tree
*mt
,
2020 unsigned level
, unsigned layer
)
2025 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2026 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2027 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2029 /* Compression of arrayed msaa surfaces is supported. */
2030 if (mt
->surf
.samples
> 1)
2033 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2034 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2036 mt
->surf
.logical_level0_px
.depth
== 1 &&
2037 mt
->surf
.logical_level0_px
.array_len
== 1));
2043 static enum blorp_fast_clear_op
2044 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2045 enum isl_aux_usage aux_usage
,
2046 bool fast_clear_supported
)
2048 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
2050 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
2052 assert(ccs_supported
== fast_clear_supported
);
2054 switch (aux_state
) {
2055 case ISL_AUX_STATE_CLEAR
:
2056 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2058 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2060 return BLORP_FAST_CLEAR_OP_NONE
;
2062 case ISL_AUX_STATE_PASS_THROUGH
:
2063 return BLORP_FAST_CLEAR_OP_NONE
;
2065 case ISL_AUX_STATE_RESOLVED
:
2066 case ISL_AUX_STATE_AUX_INVALID
:
2067 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2068 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2072 unreachable("Invalid aux state for CCS_D");
2075 static enum blorp_fast_clear_op
2076 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2077 enum isl_aux_usage aux_usage
,
2078 bool fast_clear_supported
)
2080 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
2081 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2082 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2083 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2085 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
2086 assert(fast_clear_supported
);
2088 switch (aux_state
) {
2089 case ISL_AUX_STATE_CLEAR
:
2090 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2091 if (fast_clear_supported
)
2092 return BLORP_FAST_CLEAR_OP_NONE
;
2093 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
2094 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2096 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2098 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2099 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2100 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2101 else if (!fast_clear_supported
)
2102 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2104 return BLORP_FAST_CLEAR_OP_NONE
;
2106 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2107 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2108 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2110 return BLORP_FAST_CLEAR_OP_NONE
;
2112 case ISL_AUX_STATE_PASS_THROUGH
:
2113 return BLORP_FAST_CLEAR_OP_NONE
;
2115 case ISL_AUX_STATE_RESOLVED
:
2116 case ISL_AUX_STATE_AUX_INVALID
:
2120 unreachable("Invalid aux state for CCS_E");
2124 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2125 struct intel_mipmap_tree
*mt
,
2126 uint32_t level
, uint32_t layer
,
2127 enum isl_aux_usage aux_usage
,
2128 bool fast_clear_supported
)
2130 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2132 enum blorp_fast_clear_op resolve_op
;
2133 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2134 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2135 fast_clear_supported
);
2137 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2138 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2139 fast_clear_supported
);
2142 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2143 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2144 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2146 switch (resolve_op
) {
2147 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2148 /* The CCS full resolve operation destroys the CCS and sets it to the
2149 * pass-through state. (You can also think of this as being both a
2150 * resolve and an ambiguate in one operation.)
2152 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2153 ISL_AUX_STATE_PASS_THROUGH
);
2156 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2157 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2158 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2162 unreachable("Invalid resolve op");
2168 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2169 struct intel_mipmap_tree
*mt
,
2170 uint32_t level
, uint32_t layer
,
2171 enum isl_aux_usage aux_usage
)
2173 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2174 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2175 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2177 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2179 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2180 switch (aux_state
) {
2181 case ISL_AUX_STATE_CLEAR
:
2182 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2183 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2184 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2186 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2187 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2188 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2189 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2190 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2191 ISL_AUX_STATE_PARTIAL_CLEAR
);
2195 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2196 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2197 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2198 break; /* Nothing to do */
2200 case ISL_AUX_STATE_PASS_THROUGH
:
2201 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2202 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2203 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2209 case ISL_AUX_STATE_RESOLVED
:
2210 case ISL_AUX_STATE_AUX_INVALID
:
2211 unreachable("Invalid aux state for CCS_E");
2214 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2215 /* CCS_D is a bit simpler */
2216 switch (aux_state
) {
2217 case ISL_AUX_STATE_CLEAR
:
2218 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2219 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2220 ISL_AUX_STATE_PARTIAL_CLEAR
);
2223 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2224 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2225 break; /* Nothing to do */
2227 case ISL_AUX_STATE_PASS_THROUGH
:
2231 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2232 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2233 case ISL_AUX_STATE_RESOLVED
:
2234 case ISL_AUX_STATE_AUX_INVALID
:
2235 unreachable("Invalid aux state for CCS_D");
2241 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2242 struct intel_mipmap_tree
*mt
,
2244 enum isl_aux_usage aux_usage
,
2245 bool fast_clear_supported
)
2247 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2249 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2250 case ISL_AUX_STATE_CLEAR
:
2251 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2252 if (!fast_clear_supported
) {
2253 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2254 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2255 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2259 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2260 break; /* Nothing to do */
2262 case ISL_AUX_STATE_RESOLVED
:
2263 case ISL_AUX_STATE_PASS_THROUGH
:
2264 case ISL_AUX_STATE_AUX_INVALID
:
2265 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2266 unreachable("Invalid aux state for MCS");
2271 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2272 struct intel_mipmap_tree
*mt
,
2274 enum isl_aux_usage aux_usage
)
2276 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2278 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2279 case ISL_AUX_STATE_CLEAR
:
2280 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2281 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2284 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2285 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2286 break; /* Nothing to do */
2288 case ISL_AUX_STATE_RESOLVED
:
2289 case ISL_AUX_STATE_PASS_THROUGH
:
2290 case ISL_AUX_STATE_AUX_INVALID
:
2291 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2292 unreachable("Invalid aux state for MCS");
2297 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2298 struct intel_mipmap_tree
*mt
,
2299 uint32_t level
, uint32_t layer
,
2300 enum isl_aux_usage aux_usage
,
2301 bool fast_clear_supported
)
2303 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2305 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2306 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2307 case ISL_AUX_STATE_CLEAR
:
2308 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2309 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2310 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2313 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2314 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2315 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2318 case ISL_AUX_STATE_PASS_THROUGH
:
2319 case ISL_AUX_STATE_RESOLVED
:
2322 case ISL_AUX_STATE_AUX_INVALID
:
2323 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2324 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2327 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2328 unreachable("Invalid HiZ state");
2331 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2332 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2335 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2336 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2337 ISL_AUX_STATE_RESOLVED
);
2340 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2341 /* The HiZ resolve operation is actually an ambiguate */
2342 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2343 ISL_AUX_STATE_PASS_THROUGH
);
2347 unreachable("Invalid HiZ op");
2353 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2354 struct intel_mipmap_tree
*mt
,
2355 uint32_t level
, uint32_t layer
,
2356 enum isl_aux_usage aux_usage
)
2358 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2360 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2361 case ISL_AUX_STATE_CLEAR
:
2362 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2363 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2364 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2367 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2368 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2369 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2370 break; /* Nothing to do */
2372 case ISL_AUX_STATE_RESOLVED
:
2373 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2374 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2375 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2377 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2378 ISL_AUX_STATE_AUX_INVALID
);
2382 case ISL_AUX_STATE_PASS_THROUGH
:
2383 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2384 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2385 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2389 case ISL_AUX_STATE_AUX_INVALID
:
2390 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2393 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2394 unreachable("Invalid HiZ state");
2399 intel_miptree_prepare_access(struct brw_context
*brw
,
2400 struct intel_mipmap_tree
*mt
,
2401 uint32_t start_level
, uint32_t num_levels
,
2402 uint32_t start_layer
, uint32_t num_layers
,
2403 enum isl_aux_usage aux_usage
,
2404 bool fast_clear_supported
)
2406 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2408 switch (mt
->aux_usage
) {
2409 case ISL_AUX_USAGE_NONE
:
2413 case ISL_AUX_USAGE_MCS
:
2414 assert(mt
->mcs_buf
);
2415 assert(start_level
== 0 && num_levels
== 1);
2416 const uint32_t level_layers
=
2417 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2418 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2419 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2420 aux_usage
, fast_clear_supported
);
2424 case ISL_AUX_USAGE_CCS_D
:
2425 case ISL_AUX_USAGE_CCS_E
:
2429 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2430 const uint32_t level
= start_level
+ l
;
2431 const uint32_t level_layers
=
2432 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2433 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2434 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2436 aux_usage
, fast_clear_supported
);
2441 case ISL_AUX_USAGE_HIZ
:
2442 assert(mt
->hiz_buf
);
2443 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2444 const uint32_t level
= start_level
+ l
;
2445 if (!intel_miptree_level_has_hiz(mt
, level
))
2448 const uint32_t level_layers
=
2449 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2450 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2451 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2452 aux_usage
, fast_clear_supported
);
2458 unreachable("Invalid aux usage");
2463 intel_miptree_finish_write(struct brw_context
*brw
,
2464 struct intel_mipmap_tree
*mt
, uint32_t level
,
2465 uint32_t start_layer
, uint32_t num_layers
,
2466 enum isl_aux_usage aux_usage
)
2468 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2470 switch (mt
->aux_usage
) {
2471 case ISL_AUX_USAGE_NONE
:
2475 case ISL_AUX_USAGE_MCS
:
2476 assert(mt
->mcs_buf
);
2477 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2478 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2483 case ISL_AUX_USAGE_CCS_D
:
2484 case ISL_AUX_USAGE_CCS_E
:
2488 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2489 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2494 case ISL_AUX_USAGE_HIZ
:
2495 if (!intel_miptree_level_has_hiz(mt
, level
))
2498 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2499 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2505 unreachable("Invavlid aux usage");
2510 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2511 uint32_t level
, uint32_t layer
)
2513 intel_miptree_check_level_layer(mt
, level
, layer
);
2515 if (_mesa_is_format_color_format(mt
->format
)) {
2516 assert(mt
->mcs_buf
!= NULL
);
2517 assert(mt
->surf
.samples
== 1 ||
2518 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2519 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2520 unreachable("Cannot get aux state for stencil");
2522 assert(intel_miptree_level_has_hiz(mt
, level
));
2525 return mt
->aux_state
[level
][layer
];
2529 intel_miptree_set_aux_state(struct brw_context
*brw
,
2530 struct intel_mipmap_tree
*mt
, uint32_t level
,
2531 uint32_t start_layer
, uint32_t num_layers
,
2532 enum isl_aux_state aux_state
)
2534 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2536 if (_mesa_is_format_color_format(mt
->format
)) {
2537 assert(mt
->mcs_buf
!= NULL
);
2538 assert(mt
->surf
.samples
== 1 ||
2539 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2540 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2541 unreachable("Cannot get aux state for stencil");
2543 assert(intel_miptree_level_has_hiz(mt
, level
));
2546 for (unsigned a
= 0; a
< num_layers
; a
++) {
2547 if (mt
->aux_state
[level
][start_layer
+ a
] != aux_state
) {
2548 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2549 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2554 /* On Gen9 color buffers may be compressed by the hardware (lossless
2555 * compression). There are, however, format restrictions and care needs to be
2556 * taken that the sampler engine is capable for re-interpreting a buffer with
2557 * format different the buffer was originally written with.
2559 * For example, SRGB formats are not compressible and the sampler engine isn't
2560 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2561 * color buffer needs to be resolved so that the sampling surface can be
2562 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2566 can_texture_with_ccs(struct brw_context
*brw
,
2567 struct intel_mipmap_tree
*mt
,
2568 enum isl_format view_format
)
2570 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2573 /* TODO: Replace with format_ccs_e_compat_with_miptree for better perf. */
2574 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2575 mt
->surf
.format
, view_format
)) {
2576 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2577 isl_format_get_layout(view_format
)->name
,
2578 _mesa_get_format_name(mt
->format
));
2586 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2587 struct intel_mipmap_tree
*mt
,
2588 enum isl_format view_format
)
2590 switch (mt
->aux_usage
) {
2591 case ISL_AUX_USAGE_HIZ
:
2592 if (intel_miptree_sample_with_hiz(brw
, mt
))
2593 return ISL_AUX_USAGE_HIZ
;
2596 case ISL_AUX_USAGE_MCS
:
2597 return ISL_AUX_USAGE_MCS
;
2599 case ISL_AUX_USAGE_CCS_D
:
2600 case ISL_AUX_USAGE_CCS_E
:
2602 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2603 return ISL_AUX_USAGE_NONE
;
2606 /* If we don't have any unresolved color, report an aux usage of
2607 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
2608 * aux surface and we can save some bandwidth.
2610 if (!intel_miptree_has_color_unresolved(mt
, 0, INTEL_REMAINING_LEVELS
,
2611 0, INTEL_REMAINING_LAYERS
))
2612 return ISL_AUX_USAGE_NONE
;
2614 if (can_texture_with_ccs(brw
, mt
, view_format
))
2615 return ISL_AUX_USAGE_CCS_E
;
2622 return ISL_AUX_USAGE_NONE
;
2626 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2628 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2629 * values so sRGB curve application was a no-op for all fast-clearable
2632 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2633 * values, the hardware interprets the floats, not as what would be
2634 * returned from the sampler (or written by the shader), but as being
2635 * between format conversion and sRGB curve application. This means that
2636 * we can switch between sRGB and UNORM without having to whack the clear
2639 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2643 intel_miptree_prepare_texture(struct brw_context
*brw
,
2644 struct intel_mipmap_tree
*mt
,
2645 enum isl_format view_format
,
2646 uint32_t start_level
, uint32_t num_levels
,
2647 uint32_t start_layer
, uint32_t num_layers
,
2650 enum isl_aux_usage aux_usage
= disable_aux
? ISL_AUX_USAGE_NONE
:
2651 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2652 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2654 /* Clear color is specified as ints or floats and the conversion is done by
2655 * the sampler. If we have a texture view, we would have to perform the
2656 * clear color conversion manually. Just disable clear color.
2658 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2659 clear_supported
= false;
2661 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2662 start_layer
, num_layers
,
2663 aux_usage
, clear_supported
);
2667 intel_miptree_prepare_image(struct brw_context
*brw
,
2668 struct intel_mipmap_tree
*mt
)
2670 /* The data port doesn't understand any compression */
2671 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2672 0, INTEL_REMAINING_LAYERS
,
2673 ISL_AUX_USAGE_NONE
, false);
2677 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2678 struct intel_mipmap_tree
*mt
,
2679 enum isl_format render_format
,
2682 switch (mt
->aux_usage
) {
2683 case ISL_AUX_USAGE_MCS
:
2684 assert(mt
->mcs_buf
);
2685 return ISL_AUX_USAGE_MCS
;
2687 case ISL_AUX_USAGE_CCS_D
:
2688 return mt
->mcs_buf
? ISL_AUX_USAGE_CCS_D
: ISL_AUX_USAGE_NONE
;
2690 case ISL_AUX_USAGE_CCS_E
: {
2691 /* If the format supports CCS_E and is compatible with the miptree,
2692 * then we can use it.
2694 if (format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2696 return ISL_AUX_USAGE_CCS_E
;
2698 /* Otherwise, we have to fall back to CCS_D */
2700 /* gen9 hardware technically supports non-0/1 clear colors with sRGB
2701 * formats. However, there are issues with blending where it doesn't
2702 * properly apply the sRGB curve to the clear color when blending.
2704 if (blend_enabled
&& isl_format_is_srgb(render_format
) &&
2705 !isl_color_value_is_zero_one(mt
->fast_clear_color
, render_format
))
2706 return ISL_AUX_USAGE_NONE
;
2708 return ISL_AUX_USAGE_CCS_D
;
2712 return ISL_AUX_USAGE_NONE
;
2717 intel_miptree_prepare_render(struct brw_context
*brw
,
2718 struct intel_mipmap_tree
*mt
, uint32_t level
,
2719 uint32_t start_layer
, uint32_t layer_count
,
2720 enum isl_format render_format
,
2723 enum isl_aux_usage aux_usage
=
2724 intel_miptree_render_aux_usage(brw
, mt
, render_format
, blend_enabled
);
2725 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2726 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2730 intel_miptree_finish_render(struct brw_context
*brw
,
2731 struct intel_mipmap_tree
*mt
, uint32_t level
,
2732 uint32_t start_layer
, uint32_t layer_count
,
2733 enum isl_format render_format
,
2736 assert(_mesa_is_format_color_format(mt
->format
));
2738 enum isl_aux_usage aux_usage
=
2739 intel_miptree_render_aux_usage(brw
, mt
, render_format
, blend_enabled
);
2740 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2745 intel_miptree_prepare_depth(struct brw_context
*brw
,
2746 struct intel_mipmap_tree
*mt
, uint32_t level
,
2747 uint32_t start_layer
, uint32_t layer_count
)
2749 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2750 mt
->aux_usage
, mt
->hiz_buf
!= NULL
);
2754 intel_miptree_finish_depth(struct brw_context
*brw
,
2755 struct intel_mipmap_tree
*mt
, uint32_t level
,
2756 uint32_t start_layer
, uint32_t layer_count
,
2759 if (depth_written
) {
2760 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2761 mt
->hiz_buf
!= NULL
);
2766 intel_miptree_prepare_external(struct brw_context
*brw
,
2767 struct intel_mipmap_tree
*mt
)
2769 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
2770 bool supports_fast_clear
= false;
2772 const struct isl_drm_modifier_info
*mod_info
=
2773 isl_drm_modifier_get_info(mt
->drm_modifier
);
2775 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
2776 /* CCS_E is the only supported aux for external images and it's only
2777 * supported on very simple images.
2779 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
2780 assert(_mesa_is_format_color_format(mt
->format
));
2781 assert(mt
->first_level
== 0 && mt
->last_level
== 0);
2782 assert(mt
->surf
.logical_level0_px
.depth
== 1);
2783 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
2784 assert(mt
->surf
.samples
== 1);
2785 assert(mt
->mcs_buf
!= NULL
);
2787 aux_usage
= mod_info
->aux_usage
;
2788 supports_fast_clear
= mod_info
->supports_clear_color
;
2791 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2792 0, INTEL_REMAINING_LAYERS
,
2793 aux_usage
, supports_fast_clear
);
2797 * Make it possible to share the BO backing the given miptree with another
2798 * process or another miptree.
2800 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2801 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2802 * ensure that no MCS buffer gets allocated in the future.
2804 * HiZ is similarly unsafe with shared buffers.
2807 intel_miptree_make_shareable(struct brw_context
*brw
,
2808 struct intel_mipmap_tree
*mt
)
2810 /* MCS buffers are also used for multisample buffers, but we can't resolve
2811 * away a multisample MCS buffer because it's an integral part of how the
2812 * pixel data is stored. Fortunately this code path should never be
2813 * reached for multisample buffers.
2815 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2816 mt
->surf
.samples
== 1);
2818 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2819 0, INTEL_REMAINING_LAYERS
,
2820 ISL_AUX_USAGE_NONE
, false);
2823 brw_bo_unreference(mt
->mcs_buf
->bo
);
2827 /* Any pending MCS/CCS operations are no longer needed. Trying to
2828 * execute any will likely crash due to the missing aux buffer. So let's
2829 * delete all pending ops.
2831 free(mt
->aux_state
);
2832 mt
->aux_state
= NULL
;
2833 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2837 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2840 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2841 mt
->level
[l
].has_hiz
= false;
2844 /* Any pending HiZ operations are no longer needed. Trying to execute
2845 * any will likely crash due to the missing aux buffer. So let's delete
2848 free(mt
->aux_state
);
2849 mt
->aux_state
= NULL
;
2850 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2853 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2854 mt
->supports_fast_clear
= false;
2859 * \brief Get pointer offset into stencil buffer.
2861 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2862 * must decode the tile's layout in software.
2865 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2867 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2869 * Even though the returned offset is always positive, the return type is
2871 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2872 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2875 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2877 uint32_t tile_size
= 4096;
2878 uint32_t tile_width
= 64;
2879 uint32_t tile_height
= 64;
2880 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2882 uint32_t tile_x
= x
/ tile_width
;
2883 uint32_t tile_y
= y
/ tile_height
;
2885 /* The byte's address relative to the tile's base addres. */
2886 uint32_t byte_x
= x
% tile_width
;
2887 uint32_t byte_y
= y
% tile_height
;
2889 uintptr_t u
= tile_y
* row_size
2890 + tile_x
* tile_size
2891 + 512 * (byte_x
/ 8)
2893 + 32 * ((byte_y
/ 4) % 2)
2894 + 16 * ((byte_x
/ 4) % 2)
2895 + 8 * ((byte_y
/ 2) % 2)
2896 + 4 * ((byte_x
/ 2) % 2)
2901 /* adjust for bit6 swizzling */
2902 if (((byte_x
/ 8) % 2) == 1) {
2903 if (((byte_y
/ 8) % 2) == 0) {
2915 intel_miptree_updownsample(struct brw_context
*brw
,
2916 struct intel_mipmap_tree
*src
,
2917 struct intel_mipmap_tree
*dst
)
2919 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2920 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2921 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2922 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2924 brw_blorp_blit_miptrees(brw
,
2925 src
, 0 /* level */, 0 /* layer */,
2926 src
->format
, SWIZZLE_XYZW
,
2927 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2930 GL_NEAREST
, false, false /*mirror x, y*/,
2933 if (src
->stencil_mt
) {
2934 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2935 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2936 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2937 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2939 brw_blorp_blit_miptrees(brw
,
2940 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2941 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2942 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2943 dst
->stencil_mt
->format
,
2946 GL_NEAREST
, false, false /*mirror x, y*/,
2947 false, false /* decode/encode srgb */);
2952 intel_update_r8stencil(struct brw_context
*brw
,
2953 struct intel_mipmap_tree
*mt
)
2955 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2957 assert(devinfo
->gen
>= 7);
2958 struct intel_mipmap_tree
*src
=
2959 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2960 if (!src
|| devinfo
->gen
>= 8 || !src
->r8stencil_needs_update
)
2963 assert(src
->surf
.size
> 0);
2965 if (!mt
->r8stencil_mt
) {
2966 assert(devinfo
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2967 mt
->r8stencil_mt
= make_surface(
2970 MESA_FORMAT_R_UINT8
,
2971 src
->first_level
, src
->last_level
,
2972 src
->surf
.logical_level0_px
.width
,
2973 src
->surf
.logical_level0_px
.height
,
2974 src
->surf
.dim
== ISL_SURF_DIM_3D
?
2975 src
->surf
.logical_level0_px
.depth
:
2976 src
->surf
.logical_level0_px
.array_len
,
2979 ISL_SURF_USAGE_TEXTURE_BIT
,
2980 BO_ALLOC_BUSY
, 0, NULL
);
2981 assert(mt
->r8stencil_mt
);
2984 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2986 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2987 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
2988 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
2989 src
->surf
.phys_level0_sa
.array_len
;
2991 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2992 brw_blorp_copy_miptrees(brw
,
2996 minify(src
->surf
.logical_level0_px
.width
,
2998 minify(src
->surf
.logical_level0_px
.height
,
3003 brw_cache_flush_for_read(brw
, dst
->bo
);
3004 src
->r8stencil_needs_update
= false;
3008 intel_miptree_map_raw(struct brw_context
*brw
,
3009 struct intel_mipmap_tree
*mt
,
3012 struct brw_bo
*bo
= mt
->bo
;
3014 if (brw_batch_references(&brw
->batch
, bo
))
3015 intel_batchbuffer_flush(brw
);
3017 return brw_bo_map(brw
, bo
, mode
);
3021 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3023 brw_bo_unmap(mt
->bo
);
3027 intel_miptree_map_gtt(struct brw_context
*brw
,
3028 struct intel_mipmap_tree
*mt
,
3029 struct intel_miptree_map
*map
,
3030 unsigned int level
, unsigned int slice
)
3032 unsigned int bw
, bh
;
3034 unsigned int image_x
, image_y
;
3035 intptr_t x
= map
->x
;
3036 intptr_t y
= map
->y
;
3038 /* For compressed formats, the stride is the number of bytes per
3039 * row of blocks. intel_miptree_get_image_offset() already does
3042 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3043 assert(y
% bh
== 0);
3044 assert(x
% bw
== 0);
3048 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3055 /* Note that in the case of cube maps, the caller must have passed the
3056 * slice number referencing the face.
3058 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3062 map
->stride
= mt
->surf
.row_pitch
;
3063 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3066 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3067 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3068 map
->x
, map
->y
, map
->w
, map
->h
,
3069 mt
, _mesa_get_format_name(mt
->format
),
3070 x
, y
, map
->ptr
, map
->stride
);
3074 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3076 intel_miptree_unmap_raw(mt
);
3080 intel_miptree_map_blit(struct brw_context
*brw
,
3081 struct intel_mipmap_tree
*mt
,
3082 struct intel_miptree_map
*map
,
3083 unsigned int level
, unsigned int slice
)
3085 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3086 /* first_level */ 0,
3090 MIPTREE_CREATE_LINEAR
);
3092 if (!map
->linear_mt
) {
3093 fprintf(stderr
, "Failed to allocate blit temporary\n");
3096 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3098 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3099 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3100 * invalidate is set, since we'll be writing the whole rectangle from our
3101 * temporary buffer back out.
3103 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3104 if (!intel_miptree_copy(brw
,
3105 mt
, level
, slice
, map
->x
, map
->y
,
3106 map
->linear_mt
, 0, 0, 0, 0,
3108 fprintf(stderr
, "Failed to blit\n");
3113 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3115 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3116 map
->x
, map
->y
, map
->w
, map
->h
,
3117 mt
, _mesa_get_format_name(mt
->format
),
3118 level
, slice
, map
->ptr
, map
->stride
);
3123 intel_miptree_release(&map
->linear_mt
);
3129 intel_miptree_unmap_blit(struct brw_context
*brw
,
3130 struct intel_mipmap_tree
*mt
,
3131 struct intel_miptree_map
*map
,
3135 struct gl_context
*ctx
= &brw
->ctx
;
3137 intel_miptree_unmap_raw(map
->linear_mt
);
3139 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3140 bool ok
= intel_miptree_copy(brw
,
3141 map
->linear_mt
, 0, 0, 0, 0,
3142 mt
, level
, slice
, map
->x
, map
->y
,
3144 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3147 intel_miptree_release(&map
->linear_mt
);
3151 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3153 #if defined(USE_SSE41)
3155 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3156 struct intel_mipmap_tree
*mt
,
3157 struct intel_miptree_map
*map
,
3158 unsigned int level
, unsigned int slice
)
3160 assert(map
->mode
& GL_MAP_READ_BIT
);
3161 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3163 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3164 map
->x
, map
->y
, map
->w
, map
->h
,
3165 mt
, _mesa_get_format_name(mt
->format
),
3166 level
, slice
, map
->ptr
, map
->stride
);
3168 /* Map the original image */
3171 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3175 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3181 src
+= image_y
* mt
->surf
.row_pitch
;
3182 src
+= image_x
* mt
->cpp
;
3184 /* Due to the pixel offsets for the particular image being mapped, our
3185 * src pointer may not be 16-byte aligned. However, if the pitch is
3186 * divisible by 16, then the amount by which it's misaligned will remain
3187 * consistent from row to row.
3189 assert((mt
->surf
.row_pitch
% 16) == 0);
3190 const int misalignment
= ((uintptr_t) src
) & 15;
3192 /* Create an untiled temporary buffer for the mapping. */
3193 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3195 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3197 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3198 /* Offset the destination so it has the same misalignment as src. */
3199 map
->ptr
= map
->buffer
+ misalignment
;
3201 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3203 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3204 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3205 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3207 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3210 intel_miptree_unmap_raw(mt
);
3214 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3215 struct intel_mipmap_tree
*mt
,
3216 struct intel_miptree_map
*map
,
3220 _mesa_align_free(map
->buffer
);
3227 intel_miptree_map_s8(struct brw_context
*brw
,
3228 struct intel_mipmap_tree
*mt
,
3229 struct intel_miptree_map
*map
,
3230 unsigned int level
, unsigned int slice
)
3232 map
->stride
= map
->w
;
3233 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3237 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3238 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3239 * invalidate is set, since we'll be writing the whole rectangle from our
3240 * temporary buffer back out.
3242 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3243 uint8_t *untiled_s8_map
= map
->ptr
;
3244 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3245 unsigned int image_x
, image_y
;
3247 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3249 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3250 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3251 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3252 x
+ image_x
+ map
->x
,
3253 y
+ image_y
+ map
->y
,
3254 brw
->has_swizzling
);
3255 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3259 intel_miptree_unmap_raw(mt
);
3261 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3262 map
->x
, map
->y
, map
->w
, map
->h
,
3263 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3265 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3266 map
->x
, map
->y
, map
->w
, map
->h
,
3267 mt
, map
->ptr
, map
->stride
);
3272 intel_miptree_unmap_s8(struct brw_context
*brw
,
3273 struct intel_mipmap_tree
*mt
,
3274 struct intel_miptree_map
*map
,
3278 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3279 unsigned int image_x
, image_y
;
3280 uint8_t *untiled_s8_map
= map
->ptr
;
3281 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3283 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3285 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3286 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3287 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3288 image_x
+ x
+ map
->x
,
3289 image_y
+ y
+ map
->y
,
3290 brw
->has_swizzling
);
3291 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3295 intel_miptree_unmap_raw(mt
);
3302 intel_miptree_map_etc(struct brw_context
*brw
,
3303 struct intel_mipmap_tree
*mt
,
3304 struct intel_miptree_map
*map
,
3308 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3309 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3310 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3313 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3314 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3316 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3317 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3318 map
->w
, map
->h
, 1));
3319 map
->ptr
= map
->buffer
;
3323 intel_miptree_unmap_etc(struct brw_context
*brw
,
3324 struct intel_mipmap_tree
*mt
,
3325 struct intel_miptree_map
*map
,
3331 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3336 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3337 + image_y
* mt
->surf
.row_pitch
3338 + image_x
* mt
->cpp
;
3340 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3341 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3342 map
->ptr
, map
->stride
,
3345 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3346 map
->ptr
, map
->stride
,
3347 map
->w
, map
->h
, mt
->etc_format
);
3349 intel_miptree_unmap_raw(mt
);
3354 * Mapping function for packed depth/stencil miptrees backed by real separate
3355 * miptrees for depth and stencil.
3357 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3358 * separate from the depth buffer. Yet at the GL API level, we have to expose
3359 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3360 * be able to map that memory for texture storage and glReadPixels-type
3361 * operations. We give Mesa core that access by mallocing a temporary and
3362 * copying the data between the actual backing store and the temporary.
3365 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3366 struct intel_mipmap_tree
*mt
,
3367 struct intel_miptree_map
*map
,
3368 unsigned int level
, unsigned int slice
)
3370 struct intel_mipmap_tree
*z_mt
= mt
;
3371 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3372 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3373 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3375 map
->stride
= map
->w
* packed_bpp
;
3376 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3380 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3381 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3382 * invalidate is set, since we'll be writing the whole rectangle from our
3383 * temporary buffer back out.
3385 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3386 uint32_t *packed_map
= map
->ptr
;
3387 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3388 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3389 unsigned int s_image_x
, s_image_y
;
3390 unsigned int z_image_x
, z_image_y
;
3392 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3393 &s_image_x
, &s_image_y
);
3394 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3395 &z_image_x
, &z_image_y
);
3397 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3398 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3399 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3400 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3403 brw
->has_swizzling
);
3404 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3405 (z_mt
->surf
.row_pitch
/ 4) +
3406 (map_x
+ z_image_x
));
3407 uint8_t s
= s_map
[s_offset
];
3408 uint32_t z
= z_map
[z_offset
];
3410 if (map_z32f_x24s8
) {
3411 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3412 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3414 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3419 intel_miptree_unmap_raw(s_mt
);
3420 intel_miptree_unmap_raw(z_mt
);
3422 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3424 map
->x
, map
->y
, map
->w
, map
->h
,
3425 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3426 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3427 map
->ptr
, map
->stride
);
3429 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3430 map
->x
, map
->y
, map
->w
, map
->h
,
3431 mt
, map
->ptr
, map
->stride
);
3436 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3437 struct intel_mipmap_tree
*mt
,
3438 struct intel_miptree_map
*map
,
3442 struct intel_mipmap_tree
*z_mt
= mt
;
3443 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3444 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3446 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3447 uint32_t *packed_map
= map
->ptr
;
3448 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3449 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3450 unsigned int s_image_x
, s_image_y
;
3451 unsigned int z_image_x
, z_image_y
;
3453 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3454 &s_image_x
, &s_image_y
);
3455 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3456 &z_image_x
, &z_image_y
);
3458 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3459 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3460 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3461 x
+ s_image_x
+ map
->x
,
3462 y
+ s_image_y
+ map
->y
,
3463 brw
->has_swizzling
);
3464 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3465 (z_mt
->surf
.row_pitch
/ 4) +
3466 (x
+ z_image_x
+ map
->x
));
3468 if (map_z32f_x24s8
) {
3469 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3470 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3472 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3473 s_map
[s_offset
] = packed
>> 24;
3474 z_map
[z_offset
] = packed
;
3479 intel_miptree_unmap_raw(s_mt
);
3480 intel_miptree_unmap_raw(z_mt
);
3482 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3484 map
->x
, map
->y
, map
->w
, map
->h
,
3485 z_mt
, _mesa_get_format_name(z_mt
->format
),
3486 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3487 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3488 map
->ptr
, map
->stride
);
3495 * Create and attach a map to the miptree at (level, slice). Return the
3498 static struct intel_miptree_map
*
3499 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3508 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3513 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3514 mt
->level
[level
].slice
[slice
].map
= map
;
3526 * Release the map at (level, slice).
3529 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3533 struct intel_miptree_map
**map
;
3535 map
= &mt
->level
[level
].slice
[slice
].map
;
3541 can_blit_slice(struct intel_mipmap_tree
*mt
,
3542 unsigned int level
, unsigned int slice
)
3544 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3545 if (mt
->surf
.row_pitch
>= 32768)
3552 use_intel_mipree_map_blit(struct brw_context
*brw
,
3553 struct intel_mipmap_tree
*mt
,
3558 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3560 if (devinfo
->has_llc
&&
3561 /* It's probably not worth swapping to the blit ring because of
3562 * all the overhead involved.
3564 !(mode
& GL_MAP_WRITE_BIT
) &&
3566 (mt
->surf
.tiling
== ISL_TILING_X
||
3567 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3568 (devinfo
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3569 /* Fast copy blit on skl+ supports all tiling formats. */
3570 devinfo
->gen
>= 9) &&
3571 can_blit_slice(mt
, level
, slice
))
3574 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3575 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3576 assert(can_blit_slice(mt
, level
, slice
));
3584 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3585 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3586 * arithmetic overflow.
3588 * If you call this function and use \a out_stride, then you're doing pointer
3589 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3590 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3591 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3592 * which usually have type uint32_t or GLuint.
3595 intel_miptree_map(struct brw_context
*brw
,
3596 struct intel_mipmap_tree
*mt
,
3605 ptrdiff_t *out_stride
)
3607 struct intel_miptree_map
*map
;
3609 assert(mt
->surf
.samples
== 1);
3611 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3618 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3619 map
->mode
& GL_MAP_WRITE_BIT
);
3621 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3622 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3623 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3624 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3625 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3626 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3627 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3628 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3629 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3630 #if defined(USE_SSE41)
3631 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3632 !mt
->compressed
&& cpu_has_sse4_1
&&
3633 (mt
->surf
.row_pitch
% 16 == 0)) {
3634 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3637 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3640 *out_ptr
= map
->ptr
;
3641 *out_stride
= map
->stride
;
3643 if (map
->ptr
== NULL
)
3644 intel_miptree_release_map(mt
, level
, slice
);
3648 intel_miptree_unmap(struct brw_context
*brw
,
3649 struct intel_mipmap_tree
*mt
,
3653 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3655 assert(mt
->surf
.samples
== 1);
3660 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3661 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3663 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3664 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3665 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3666 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3667 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3668 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3669 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3670 } else if (map
->linear_mt
) {
3671 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3672 #if defined(USE_SSE41)
3673 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3674 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3677 intel_miptree_unmap_gtt(mt
);
3680 intel_miptree_release_map(mt
, level
, slice
);
3684 get_isl_surf_dim(GLenum target
)
3688 case GL_TEXTURE_1D_ARRAY
:
3689 return ISL_SURF_DIM_1D
;
3692 case GL_TEXTURE_2D_ARRAY
:
3693 case GL_TEXTURE_RECTANGLE
:
3694 case GL_TEXTURE_CUBE_MAP
:
3695 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3696 case GL_TEXTURE_2D_MULTISAMPLE
:
3697 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3698 case GL_TEXTURE_EXTERNAL_OES
:
3699 return ISL_SURF_DIM_2D
;
3702 return ISL_SURF_DIM_3D
;
3705 unreachable("Invalid texture target");
3709 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3710 enum isl_tiling tiling
, GLenum target
)
3714 case GL_TEXTURE_1D_ARRAY
:
3715 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3716 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3719 case GL_TEXTURE_2D_ARRAY
:
3720 case GL_TEXTURE_RECTANGLE
:
3721 case GL_TEXTURE_2D_MULTISAMPLE
:
3722 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3723 case GL_TEXTURE_EXTERNAL_OES
:
3724 return ISL_DIM_LAYOUT_GEN4_2D
;
3726 case GL_TEXTURE_CUBE_MAP
:
3727 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3728 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3729 ISL_DIM_LAYOUT_GEN4_2D
);
3732 return (devinfo
->gen
>= 9 ?
3733 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3736 unreachable("Invalid texture target");
3740 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3741 const struct intel_mipmap_tree
*mt
)
3744 return ISL_AUX_USAGE_HIZ
;
3747 return ISL_AUX_USAGE_NONE
;
3749 return mt
->aux_usage
;