2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_resolve_map.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
39 #include "main/enums.h"
40 #include "main/fbobject.h"
41 #include "main/formats.h"
42 #include "main/glformats.h"
43 #include "main/texcompress_etc.h"
44 #include "main/teximage.h"
45 #include "main/streaming-load-memcpy.h"
46 #include "x86/common_x86_asm.h"
48 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
50 static void *intel_miptree_map_raw(struct brw_context
*brw
,
51 struct intel_mipmap_tree
*mt
);
53 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
56 intel_miptree_alloc_mcs(struct brw_context
*brw
,
57 struct intel_mipmap_tree
*mt
,
61 * Determine which MSAA layout should be used by the MSAA surface being
62 * created, based on the chip generation and the surface type.
64 static enum intel_msaa_layout
65 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
66 bool disable_aux_buffers
)
68 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
70 return INTEL_MSAA_LAYOUT_IMS
;
72 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
73 switch (_mesa_get_format_base_format(format
)) {
74 case GL_DEPTH_COMPONENT
:
75 case GL_STENCIL_INDEX
:
76 case GL_DEPTH_STENCIL
:
77 return INTEL_MSAA_LAYOUT_IMS
;
79 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
81 * This field must be set to 0 for all SINT MSRTs when all RT channels
84 * In practice this means that we have to disable MCS for all signed
85 * integer MSAA buffers. The alternative, to disable MCS only when one
86 * of the render target channels is disabled, is impractical because it
87 * would require converting between CMS and UMS MSAA layouts on the fly,
90 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
91 return INTEL_MSAA_LAYOUT_UMS
;
92 } else if (disable_aux_buffers
) {
93 /* We can't use the CMS layout because it uses an aux buffer, the MCS
94 * buffer. So fallback to UMS, which is identical to CMS without the
96 return INTEL_MSAA_LAYOUT_UMS
;
98 return INTEL_MSAA_LAYOUT_CMS
;
105 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
106 * scaled-down bitfield representation of the color buffer which is capable of
107 * recording when blocks of the color buffer are equal to the clear value.
108 * This function returns the block size that will be used by the MCS buffer
109 * corresponding to a certain color miptree.
111 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
112 * beneath the "Fast Color Clear" bullet (p327):
114 * The following table describes the RT alignment
128 * This alignment has the following uses:
130 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
131 * buffer contains 128 blocks horizontally and 256 blocks vertically.
133 * - For figuring out alignment restrictions for a fast clear operation. Fast
134 * clear operations must always clear aligned multiples of 16 blocks
135 * horizontally and 32 blocks vertically.
137 * - For scaling down the coordinates sent through the render pipeline during
138 * a fast clear. X coordinates must be scaled down by 8 times the block
139 * width, and Y coordinates by 16 times the block height.
141 * - For scaling down the coordinates sent through the render pipeline during
142 * a "Render Target Resolve" operation. X coordinates must be scaled down
143 * by half the block width, and Y coordinates by half the block height.
146 intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree
*mt
,
147 unsigned *width_px
, unsigned *height
)
149 switch (mt
->tiling
) {
151 unreachable("Non-MSRT MCS requires X or Y tiling");
152 /* In release builds, fall through */
154 *width_px
= 32 / mt
->cpp
;
158 *width_px
= 64 / mt
->cpp
;
164 intel_tiling_supports_non_msrt_mcs(struct brw_context
*brw
, unsigned tiling
)
166 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
167 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
169 * - Support is limited to tiled render targets.
171 * Gen9 changes the restriction to Y-tile only.
174 return tiling
== I915_TILING_Y
;
175 else if (brw
->gen
>= 7)
176 return tiling
!= I915_TILING_NONE
;
182 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
183 * can be used. This doesn't (and should not) inspect any of the properties of
186 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
187 * beneath the "Fast Color Clear" bullet (p326):
189 * - Support is for non-mip-mapped and non-array surface types only.
191 * And then later, on p327:
193 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
197 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
198 struct intel_mipmap_tree
*mt
)
200 /* MCS support does not exist prior to Gen7 */
204 if (mt
->disable_aux_buffers
)
207 /* This function applies only to non-multisampled render targets. */
208 if (mt
->num_samples
> 1)
211 /* MCS is only supported for color buffers */
212 switch (_mesa_get_format_base_format(mt
->format
)) {
213 case GL_DEPTH_COMPONENT
:
214 case GL_DEPTH_STENCIL
:
215 case GL_STENCIL_INDEX
:
219 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
221 if (mt
->first_level
!= 0 || mt
->last_level
!= 0) {
223 perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
224 mt
->logical_width0
, mt
->logical_height0
, mt
->last_level
);
230 /* Check for layered surfaces. */
231 if (mt
->physical_depth0
!= 1) {
232 /* Multisample surfaces with the CMS layout are not layered surfaces,
233 * yet still have physical_depth0 > 1. Assert that we don't
234 * accidentally reject a multisampled surface here. We should have
235 * rejected it earlier by explicitly checking the sample count.
237 assert(mt
->num_samples
<= 1);
240 perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
241 mt
->logical_width0
, mt
->logical_height0
,
242 mt
->physical_depth0
);
248 /* There's no point in using an MCS buffer if the surface isn't in a
251 if (!brw
->format_supported_as_render_target
[mt
->format
])
259 * Determine depth format corresponding to a depth+stencil format,
260 * for separate stencil.
263 intel_depth_format_for_depthstencil_format(mesa_format format
) {
265 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
266 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
267 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
268 return MESA_FORMAT_Z_FLOAT32
;
276 * @param for_bo Indicates that the caller is
277 * intel_miptree_create_for_bo(). If true, then do not create
280 static struct intel_mipmap_tree
*
281 intel_miptree_create_layout(struct brw_context
*brw
,
290 uint32_t layout_flags
)
292 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
296 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
297 _mesa_enum_to_string(target
),
298 _mesa_get_format_name(format
),
299 first_level
, last_level
, depth0
, mt
);
301 if (target
== GL_TEXTURE_1D_ARRAY
) {
302 /* For a 1D Array texture the OpenGL API will treat the height0
303 * parameter as the number of array slices. For Intel hardware, we treat
304 * the 1D array as a 2D Array with a height of 1.
306 * So, when we first come through this path to create a 1D Array
307 * texture, height0 stores the number of slices, and depth0 is 1. In
308 * this case, we want to swap height0 and depth0.
310 * Since some miptrees will be created based on the base miptree, we may
311 * come through this path and see height0 as 1 and depth0 being the
312 * number of slices. In this case we don't need to do the swap.
314 assert(height0
== 1 || depth0
== 1);
323 mt
->first_level
= first_level
;
324 mt
->last_level
= last_level
;
325 mt
->logical_width0
= width0
;
326 mt
->logical_height0
= height0
;
327 mt
->logical_depth0
= depth0
;
328 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
329 mt
->disable_aux_buffers
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0;
330 exec_list_make_empty(&mt
->hiz_map
);
331 mt
->cpp
= _mesa_get_format_bytes(format
);
332 mt
->num_samples
= num_samples
;
333 mt
->compressed
= _mesa_is_format_compressed(format
);
334 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
337 if (num_samples
> 1) {
338 /* Adjust width/height/depth for MSAA */
339 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
340 mt
->disable_aux_buffers
);
341 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
342 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
343 * "If the surface is multisampled and it is a depth or stencil
344 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
345 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
348 * +----------------------------------------------------------------+
349 * | Num Multisamples | W_l = | H_l = |
350 * +----------------------------------------------------------------+
351 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
352 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
353 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
354 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
355 * +----------------------------------------------------------------+
358 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
359 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
360 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
362 * Another more complicated explanation for these adjustments comes
363 * from the Sandybridge PRM, volume 4, part 1, page 31:
365 * "Any of the other messages (sample*, LOD, load4) used with a
366 * (4x) multisampled surface will in-effect sample a surface with
367 * double the height and width as that indicated in the surface
368 * state. Each pixel position on the original-sized surface is
369 * replaced with a 2x2 of samples with the following arrangement:
374 * Thus, when sampling from a multisampled texture, it behaves as
375 * though the layout in memory for (x,y,sample) is:
377 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
378 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
380 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
381 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
383 * However, the actual layout of multisampled data in memory is:
385 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
386 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
388 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
389 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
391 * This pattern repeats for each 2x2 pixel block.
393 * As a result, when calculating the size of our 4-sample buffer for
394 * an odd width or height, we have to align before scaling up because
395 * sample 3 is in that bottom right 2x2 block.
397 switch (num_samples
) {
399 assert(brw
->gen
>= 8);
400 width0
= ALIGN(width0
, 2) * 2;
401 height0
= ALIGN(height0
, 2);
404 width0
= ALIGN(width0
, 2) * 2;
405 height0
= ALIGN(height0
, 2) * 2;
408 width0
= ALIGN(width0
, 2) * 4;
409 height0
= ALIGN(height0
, 2) * 2;
412 /* num_samples should already have been quantized to 0, 1, 2, 4, or
415 unreachable("not reached");
418 /* Non-interleaved */
419 depth0
*= num_samples
;
423 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
424 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
425 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
426 * used on Gen8 to make it pick a qpitch value which doesn't include space
427 * for the mipmaps. On Gen9 this is not necessary because it will
428 * automatically pick a packed qpitch value whenever mt->first_level ==
430 * TODO: can we use it elsewhere?
431 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
434 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
436 switch (mt
->msaa_layout
) {
437 case INTEL_MSAA_LAYOUT_NONE
:
438 case INTEL_MSAA_LAYOUT_IMS
:
439 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
441 case INTEL_MSAA_LAYOUT_UMS
:
442 case INTEL_MSAA_LAYOUT_CMS
:
443 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
448 if (target
== GL_TEXTURE_CUBE_MAP
) {
453 mt
->physical_width0
= width0
;
454 mt
->physical_height0
= height0
;
455 mt
->physical_depth0
= depth0
;
457 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
458 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
459 (brw
->must_use_separate_stencil
||
460 (brw
->has_separate_stencil
&&
461 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
462 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
464 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
|
465 MIPTREE_LAYOUT_TILING_ANY
;
468 mt
->stencil_mt
= intel_miptree_create(brw
,
479 if (!mt
->stencil_mt
) {
480 intel_miptree_release(&mt
);
484 /* Fix up the Z miptree format for how we're splitting out separate
485 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
487 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
490 if (format
== mt
->format
) {
491 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
492 _mesa_get_format_name(mt
->format
));
496 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
497 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
500 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
501 * multisampled or have an AUX buffer attached to it.
503 * GEN | MSRT | AUX_CCS_* or AUX_MCS
504 * -------------------------------------------
505 * 9 | HALIGN_16 | HALIGN_16
506 * 8 | HALIGN_ANY | HALIGN_16
510 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
511 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
512 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
513 } else if (brw
->gen
>= 9 && num_samples
> 1) {
514 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
516 /* For now, nothing else has this requirement */
517 assert((layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
520 brw_miptree_layout(brw
, mt
, layout_flags
);
522 if (mt
->disable_aux_buffers
)
523 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
530 * Choose an appropriate uncompressed format for a requested
531 * compressed format, if unsupported.
534 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
536 /* No need to lower ETC formats on these platforms,
537 * they are supported natively.
539 if (brw
->gen
>= 8 || brw
->is_baytrail
)
543 case MESA_FORMAT_ETC1_RGB8
:
544 return MESA_FORMAT_R8G8B8X8_UNORM
;
545 case MESA_FORMAT_ETC2_RGB8
:
546 return MESA_FORMAT_R8G8B8X8_UNORM
;
547 case MESA_FORMAT_ETC2_SRGB8
:
548 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
549 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
550 return MESA_FORMAT_B8G8R8A8_SRGB
;
551 case MESA_FORMAT_ETC2_RGBA8_EAC
:
552 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
553 return MESA_FORMAT_R8G8B8A8_UNORM
;
554 case MESA_FORMAT_ETC2_R11_EAC
:
555 return MESA_FORMAT_R_UNORM16
;
556 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
557 return MESA_FORMAT_R_SNORM16
;
558 case MESA_FORMAT_ETC2_RG11_EAC
:
559 return MESA_FORMAT_R16G16_UNORM
;
560 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
561 return MESA_FORMAT_R16G16_SNORM
;
563 /* Non ETC1 / ETC2 format */
568 /* This function computes Yf/Ys tiled bo size, alignment and pitch. */
570 intel_get_yf_ys_bo_size(struct intel_mipmap_tree
*mt
, unsigned *alignment
,
571 unsigned long *pitch
)
573 uint32_t tile_width
, tile_height
;
574 unsigned long stride
, size
, aligned_y
;
576 assert(mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
);
577 intel_get_tile_dims(mt
->tiling
, mt
->tr_mode
, mt
->cpp
,
578 &tile_width
, &tile_height
);
580 aligned_y
= ALIGN(mt
->total_height
, tile_height
);
581 stride
= mt
->total_width
* mt
->cpp
;
582 stride
= ALIGN(stride
, tile_width
);
583 size
= stride
* aligned_y
;
585 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
) {
586 assert(size
% 4096 == 0);
589 assert(size
% (64 * 1024) == 0);
590 *alignment
= 64 * 1024;
596 struct intel_mipmap_tree
*
597 intel_miptree_create(struct brw_context
*brw
,
606 uint32_t layout_flags
)
608 struct intel_mipmap_tree
*mt
;
609 mesa_format tex_format
= format
;
610 mesa_format etc_format
= MESA_FORMAT_NONE
;
611 GLuint total_width
, total_height
;
612 uint32_t alloc_flags
= 0;
614 format
= intel_lower_compressed_format(brw
, format
);
616 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
618 assert((layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) == 0);
619 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
620 mt
= intel_miptree_create_layout(brw
, target
, format
,
621 first_level
, last_level
, width0
,
622 height0
, depth0
, num_samples
,
625 * pitch == 0 || height == 0 indicates the null texture
627 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
628 intel_miptree_release(&mt
);
632 total_width
= mt
->total_width
;
633 total_height
= mt
->total_height
;
635 if (format
== MESA_FORMAT_S_UINT8
) {
636 /* Align to size of W tile, 64x64. */
637 total_width
= ALIGN(total_width
, 64);
638 total_height
= ALIGN(total_height
, 64);
643 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
)) {
645 mt
->tiling
= I915_TILING_Y
;
648 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
649 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
652 mt
->etc_format
= etc_format
;
654 if (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
655 unsigned alignment
= 0;
657 size
= intel_get_yf_ys_bo_size(mt
, &alignment
, &pitch
);
659 mt
->bo
= drm_intel_bo_alloc_for_render(brw
->bufmgr
, "miptree",
662 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
663 total_width
, total_height
, mt
->cpp
,
670 /* If the BO is too large to fit in the aperture, we need to use the
671 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
672 * handle Y-tiling, so we need to fall back to X.
674 if (brw
->gen
< 6 && y_or_x
&& mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
675 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
676 mt
->total_width
, mt
->total_height
);
678 mt
->tiling
= I915_TILING_X
;
679 drm_intel_bo_unreference(mt
->bo
);
680 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
681 total_width
, total_height
, mt
->cpp
,
682 &mt
->tiling
, &pitch
, alloc_flags
);
689 intel_miptree_release(&mt
);
694 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
695 assert(mt
->num_samples
> 1);
696 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
697 intel_miptree_release(&mt
);
702 /* If this miptree is capable of supporting fast color clears, set
703 * fast_clear_state appropriately to ensure that fast clears will occur.
704 * Allocation of the MCS miptree will be deferred until the first fast
705 * clear actually occurs.
707 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
708 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
709 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
710 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
716 struct intel_mipmap_tree
*
717 intel_miptree_create_for_bo(struct brw_context
*brw
,
725 uint32_t layout_flags
)
727 struct intel_mipmap_tree
*mt
;
728 uint32_t tiling
, swizzle
;
731 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
733 /* Nothing will be able to use this miptree with the BO if the offset isn't
736 if (tiling
!= I915_TILING_NONE
)
737 assert(offset
% 4096 == 0);
739 /* miptrees can't handle negative pitch. If you need flipping of images,
740 * that's outside of the scope of the mt.
744 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
746 /* The BO already has a tiling format and we shouldn't confuse the lower
747 * layers by making it try to find a tiling format again.
749 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
750 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
752 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
753 mt
= intel_miptree_create_layout(brw
, target
, format
,
755 width
, height
, depth
, 0,
760 drm_intel_bo_reference(bo
);
770 * For a singlesample renderbuffer, this simply wraps the given BO with a
773 * For a multisample renderbuffer, this wraps the window system's
774 * (singlesample) BO with a singlesample miptree attached to the
775 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
776 * that will contain the actual rendering (which is lazily resolved to
777 * irb->singlesample_mt).
780 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
781 struct intel_renderbuffer
*irb
,
783 uint32_t width
, uint32_t height
,
786 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
787 struct intel_mipmap_tree
*multisample_mt
= NULL
;
788 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
789 mesa_format format
= rb
->Format
;
790 int num_samples
= rb
->NumSamples
;
792 /* Only the front and back buffers, which are color buffers, are allocated
793 * through the image loader.
795 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
796 _mesa_get_format_base_format(format
) == GL_RGBA
);
798 singlesample_mt
= intel_miptree_create_for_bo(intel
,
807 if (!singlesample_mt
)
810 /* If this miptree is capable of supporting fast color clears, set
811 * mcs_state appropriately to ensure that fast clears will occur.
812 * Allocation of the MCS miptree will be deferred until the first fast
813 * clear actually occurs.
815 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
816 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
817 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
820 if (num_samples
== 0) {
821 intel_miptree_release(&irb
->mt
);
822 irb
->mt
= singlesample_mt
;
824 assert(!irb
->singlesample_mt
);
826 intel_miptree_release(&irb
->singlesample_mt
);
827 irb
->singlesample_mt
= singlesample_mt
;
830 irb
->mt
->logical_width0
!= width
||
831 irb
->mt
->logical_height0
!= height
) {
832 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
840 irb
->need_downsample
= false;
841 intel_miptree_release(&irb
->mt
);
842 irb
->mt
= multisample_mt
;
848 intel_miptree_release(&irb
->singlesample_mt
);
849 intel_miptree_release(&irb
->mt
);
853 struct intel_mipmap_tree
*
854 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
858 uint32_t num_samples
)
860 struct intel_mipmap_tree
*mt
;
863 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
864 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
865 MIPTREE_LAYOUT_TILING_ANY
;
868 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
869 width
, height
, depth
, num_samples
,
874 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
875 ok
= intel_miptree_alloc_hiz(brw
, mt
);
883 intel_miptree_release(&mt
);
888 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
889 struct intel_mipmap_tree
*src
)
894 intel_miptree_release(dst
);
898 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
906 intel_miptree_release(struct intel_mipmap_tree
**mt
)
911 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
912 if (--(*mt
)->refcount
<= 0) {
915 DBG("%s deleting %p\n", __func__
, *mt
);
917 drm_intel_bo_unreference((*mt
)->bo
);
918 intel_miptree_release(&(*mt
)->stencil_mt
);
919 if ((*mt
)->hiz_buf
) {
920 if ((*mt
)->hiz_buf
->mt
)
921 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
923 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
924 free((*mt
)->hiz_buf
);
926 intel_miptree_release(&(*mt
)->mcs_mt
);
927 intel_resolve_map_clear(&(*mt
)->hiz_map
);
929 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
930 free((*mt
)->level
[i
].slice
);
940 intel_get_image_dims(struct gl_texture_image
*image
,
941 int *width
, int *height
, int *depth
)
943 switch (image
->TexObject
->Target
) {
944 case GL_TEXTURE_1D_ARRAY
:
945 /* For a 1D Array texture the OpenGL API will treat the image height as
946 * the number of array slices. For Intel hardware, we treat the 1D array
947 * as a 2D Array with a height of 1. So, here we want to swap image
950 *width
= image
->Width
;
952 *depth
= image
->Height
;
955 *width
= image
->Width
;
956 *height
= image
->Height
;
957 *depth
= image
->Depth
;
963 * Can the image be pulled into a unified mipmap tree? This mirrors
964 * the completeness test in a lot of ways.
966 * Not sure whether I want to pass gl_texture_image here.
969 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
970 struct gl_texture_image
*image
)
972 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
973 GLuint level
= intelImage
->base
.Base
.Level
;
974 int width
, height
, depth
;
976 /* glTexImage* choose the texture object based on the target passed in, and
977 * objects can't change targets over their lifetimes, so this should be
980 assert(image
->TexObject
->Target
== mt
->target
);
982 mesa_format mt_format
= mt
->format
;
983 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
984 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
985 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
986 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
987 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
988 mt_format
= mt
->etc_format
;
990 if (image
->TexFormat
!= mt_format
)
993 intel_get_image_dims(image
, &width
, &height
, &depth
);
995 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
998 int level_depth
= mt
->level
[level
].depth
;
999 if (mt
->num_samples
> 1) {
1000 switch (mt
->msaa_layout
) {
1001 case INTEL_MSAA_LAYOUT_NONE
:
1002 case INTEL_MSAA_LAYOUT_IMS
:
1004 case INTEL_MSAA_LAYOUT_UMS
:
1005 case INTEL_MSAA_LAYOUT_CMS
:
1006 level_depth
/= mt
->num_samples
;
1011 /* Test image dimensions against the base level image adjusted for
1012 * minification. This will also catch images not present in the
1013 * tree, changed targets, etc.
1015 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1016 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1017 depth
!= level_depth
) {
1021 if (image
->NumSamples
!= mt
->num_samples
)
1029 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1031 GLuint x
, GLuint y
, GLuint d
)
1033 mt
->level
[level
].depth
= d
;
1034 mt
->level
[level
].level_x
= x
;
1035 mt
->level
[level
].level_y
= y
;
1037 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1040 assert(mt
->level
[level
].slice
== NULL
);
1042 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1043 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1044 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1049 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1050 GLuint level
, GLuint img
,
1053 if (img
== 0 && level
== 0)
1054 assert(x
== 0 && y
== 0);
1056 assert(img
< mt
->level
[level
].depth
);
1058 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1059 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1061 DBG("%s level %d img %d pos %d,%d\n",
1062 __func__
, level
, img
,
1063 mt
->level
[level
].slice
[img
].x_offset
,
1064 mt
->level
[level
].slice
[img
].y_offset
);
1068 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1069 GLuint level
, GLuint slice
,
1070 GLuint
*x
, GLuint
*y
)
1072 assert(slice
< mt
->level
[level
].depth
);
1074 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1075 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1080 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1081 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1082 * and tile_h is set to 1.
1085 intel_get_tile_dims(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1086 uint32_t *tile_w
, uint32_t *tile_h
)
1088 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
) {
1098 case I915_TILING_NONE
:
1103 unreachable("not reached");
1106 uint32_t aspect_ratio
= 1;
1107 assert(_mesa_is_pow_two(cpp
));
1122 unreachable("not reached");
1125 if (cpp
== 2 || cpp
== 8)
1128 if (tr_mode
== INTEL_MIPTREE_TRMODE_YS
)
1131 *tile_w
= *tile_h
* aspect_ratio
* cpp
;
1137 * This function computes masks that may be used to select the bits of the X
1138 * and Y coordinates that indicate the offset within a tile. If the BO is
1139 * untiled, the masks are set to 0.
1142 intel_get_tile_masks(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1143 bool map_stencil_as_y_tiled
,
1144 uint32_t *mask_x
, uint32_t *mask_y
)
1146 uint32_t tile_w_bytes
, tile_h
;
1147 if (map_stencil_as_y_tiled
)
1148 tiling
= I915_TILING_Y
;
1150 intel_get_tile_dims(tiling
, tr_mode
, cpp
, &tile_w_bytes
, &tile_h
);
1152 *mask_x
= tile_w_bytes
/ cpp
- 1;
1153 *mask_y
= tile_h
- 1;
1157 * Compute the offset (in bytes) from the start of the BO to the given x
1158 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1159 * multiples of the tile size.
1162 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1163 uint32_t x
, uint32_t y
,
1164 bool map_stencil_as_y_tiled
)
1167 uint32_t pitch
= mt
->pitch
;
1168 uint32_t tiling
= mt
->tiling
;
1170 if (map_stencil_as_y_tiled
) {
1171 tiling
= I915_TILING_Y
;
1173 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1174 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1175 * the resulting surface is twice the pitch of the original miptree,
1176 * since each row in the Y-tiled view corresponds to two rows in the
1177 * actual W-tiled surface. So we need to correct the pitch before
1178 * computing the offsets.
1185 unreachable("not reached");
1186 case I915_TILING_NONE
:
1187 return y
* pitch
+ x
* cpp
;
1189 assert((x
% (512 / cpp
)) == 0);
1190 assert((y
% 8) == 0);
1191 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1193 assert((x
% (128 / cpp
)) == 0);
1194 assert((y
% 32) == 0);
1195 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1200 * Rendering with tiled buffers requires that the base address of the buffer
1201 * be aligned to a page boundary. For renderbuffers, and sometimes with
1202 * textures, we may want the surface to point at a texture image level that
1203 * isn't at a page boundary.
1205 * This function returns an appropriately-aligned base offset
1206 * according to the tiling restrictions, plus any required x/y offset
1210 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1211 GLuint level
, GLuint slice
,
1216 uint32_t mask_x
, mask_y
;
1218 intel_get_tile_masks(mt
->tiling
, mt
->tr_mode
, mt
->cpp
, false, &mask_x
, &mask_y
);
1219 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1221 *tile_x
= x
& mask_x
;
1222 *tile_y
= y
& mask_y
;
1224 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1228 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1229 struct intel_mipmap_tree
*dst_mt
,
1230 struct intel_mipmap_tree
*src_mt
,
1237 ptrdiff_t src_stride
, dst_stride
;
1238 int cpp
= dst_mt
->cpp
;
1240 intel_miptree_map(brw
, src_mt
,
1244 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1247 intel_miptree_map(brw
, dst_mt
,
1251 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1255 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1256 _mesa_get_format_name(src_mt
->format
),
1257 src_mt
, src
, src_stride
,
1258 _mesa_get_format_name(dst_mt
->format
),
1259 dst_mt
, dst
, dst_stride
,
1262 int row_size
= cpp
* width
;
1263 if (src_stride
== row_size
&&
1264 dst_stride
== row_size
) {
1265 memcpy(dst
, src
, row_size
* height
);
1267 for (int i
= 0; i
< height
; i
++) {
1268 memcpy(dst
, src
, row_size
);
1274 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1275 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1277 /* Don't forget to copy the stencil data over, too. We could have skipped
1278 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1279 * shuffling the two data sources in/out of temporary storage instead of
1280 * the direct mapping we get this way.
1282 if (dst_mt
->stencil_mt
) {
1283 assert(src_mt
->stencil_mt
);
1284 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1285 level
, slice
, width
, height
);
1290 intel_miptree_copy_slice(struct brw_context
*brw
,
1291 struct intel_mipmap_tree
*dst_mt
,
1292 struct intel_mipmap_tree
*src_mt
,
1298 mesa_format format
= src_mt
->format
;
1299 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1300 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1308 assert(depth
< src_mt
->level
[level
].depth
);
1309 assert(src_mt
->format
== dst_mt
->format
);
1311 if (dst_mt
->compressed
) {
1313 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1314 height
= ALIGN_NPOT(height
, j
) / j
;
1315 width
= ALIGN_NPOT(width
, i
) / i
;
1318 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1319 * below won't apply since we can't do the depth's Y tiling or the
1320 * stencil's W tiling in the blitter.
1322 if (src_mt
->stencil_mt
) {
1323 intel_miptree_copy_slice_sw(brw
,
1330 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1331 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1332 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1334 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1335 _mesa_get_format_name(src_mt
->format
),
1336 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1337 _mesa_get_format_name(dst_mt
->format
),
1338 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1341 if (!intel_miptree_blit(brw
,
1342 src_mt
, level
, slice
, 0, 0, false,
1343 dst_mt
, level
, slice
, 0, 0, false,
1344 width
, height
, GL_COPY
)) {
1345 perf_debug("miptree validate blit for %s failed\n",
1346 _mesa_get_format_name(format
));
1348 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1354 * Copies the image's current data to the given miptree, and associates that
1355 * miptree with the image.
1357 * If \c invalidate is true, then the actual image data does not need to be
1358 * copied, but the image still needs to be associated to the new miptree (this
1359 * is set to true if we're about to clear the image).
1362 intel_miptree_copy_teximage(struct brw_context
*brw
,
1363 struct intel_texture_image
*intelImage
,
1364 struct intel_mipmap_tree
*dst_mt
,
1367 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1368 struct intel_texture_object
*intel_obj
=
1369 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1370 int level
= intelImage
->base
.Base
.Level
;
1371 int face
= intelImage
->base
.Base
.Face
;
1374 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1375 depth
= intelImage
->base
.Base
.Height
;
1377 depth
= intelImage
->base
.Base
.Depth
;
1380 for (int slice
= 0; slice
< depth
; slice
++) {
1381 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1385 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1386 intel_obj
->needs_validate
= true;
1390 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1391 struct intel_mipmap_tree
*mt
,
1394 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1395 assert(mt
->mcs_mt
== NULL
);
1396 assert(!mt
->disable_aux_buffers
);
1398 /* Choose the correct format for the MCS buffer. All that really matters
1399 * is that we allocate the right buffer size, since we'll always be
1400 * accessing this miptree using MCS-specific hardware mechanisms, which
1401 * infer the correct format based on num_samples.
1404 switch (num_samples
) {
1407 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1410 format
= MESA_FORMAT_R_UNORM8
;
1413 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1414 * for each sample, plus 8 padding bits).
1416 format
= MESA_FORMAT_R_UINT32
;
1419 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1422 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1424 * "The MCS surface must be stored as Tile Y."
1426 const uint32_t mcs_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1427 MIPTREE_LAYOUT_TILING_Y
;
1428 mt
->mcs_mt
= intel_miptree_create(brw
,
1434 mt
->logical_height0
,
1436 0 /* num_samples */,
1439 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1441 * When MCS buffer is enabled and bound to MSRT, it is required that it
1442 * is cleared prior to any rendering.
1444 * Since we don't use the MCS buffer for any purpose other than rendering,
1445 * it makes sense to just clear it immediately upon allocation.
1447 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1449 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1450 memset(data
, 0xff, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1451 intel_miptree_unmap_raw(mt
->mcs_mt
);
1452 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1459 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1460 struct intel_mipmap_tree
*mt
)
1462 assert(mt
->mcs_mt
== NULL
);
1463 assert(!mt
->disable_aux_buffers
);
1465 /* The format of the MCS buffer is opaque to the driver; all that matters
1466 * is that we get its size and pitch right. We'll pretend that the format
1467 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1468 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1469 * the block width and then a further factor of 4. Since an MCS tile
1470 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1471 * we'll need to scale the height down by the block height and then a
1472 * further factor of 8.
1474 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1475 unsigned block_width_px
;
1476 unsigned block_height
;
1477 intel_get_non_msrt_mcs_alignment(mt
, &block_width_px
, &block_height
);
1478 unsigned width_divisor
= block_width_px
* 4;
1479 unsigned height_divisor
= block_height
* 8;
1480 unsigned mcs_width
=
1481 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1482 unsigned mcs_height
=
1483 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1484 assert(mt
->logical_depth0
== 1);
1485 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1486 MIPTREE_LAYOUT_TILING_Y
;
1487 if (brw
->gen
>= 8) {
1488 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
1490 mt
->mcs_mt
= intel_miptree_create(brw
,
1498 0 /* num_samples */,
1506 * Helper for intel_miptree_alloc_hiz() that sets
1507 * \c mt->level[level].has_hiz. Return true if and only if
1508 * \c has_hiz was set.
1511 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1512 struct intel_mipmap_tree
*mt
,
1515 assert(mt
->hiz_buf
);
1517 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1518 uint32_t width
= minify(mt
->physical_width0
, level
);
1519 uint32_t height
= minify(mt
->physical_height0
, level
);
1521 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1522 * and the height is 4 aligned. This allows our HiZ support
1523 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1524 * we can grow the width & height to allow the HiZ op to
1525 * force the proper size alignments.
1527 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1528 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1533 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1534 mt
->level
[level
].has_hiz
= true;
1540 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1541 * buffer dimensions and allocates a bo for the hiz buffer.
1543 static struct intel_miptree_aux_buffer
*
1544 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1545 struct intel_mipmap_tree
*mt
)
1547 unsigned z_width
= mt
->logical_width0
;
1548 unsigned z_height
= mt
->logical_height0
;
1549 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1550 unsigned hz_width
, hz_height
;
1551 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1556 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1557 * adjustments required for Z_Height and Z_Width based on multisampling.
1559 switch (mt
->num_samples
) {
1573 unreachable("unsupported sample count");
1576 const unsigned vertical_align
= 8; /* 'j' in the docs */
1577 const unsigned H0
= z_height
;
1578 const unsigned h0
= ALIGN(H0
, vertical_align
);
1579 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1580 const unsigned Z0
= z_depth
;
1582 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1583 hz_width
= ALIGN(z_width
, 16);
1585 if (mt
->target
== GL_TEXTURE_3D
) {
1589 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1590 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1591 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1592 hz_height
+= h_i
* Z_i
;
1593 H_i
= minify(H_i
, 1);
1594 Z_i
= minify(Z_i
, 1);
1597 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1599 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1601 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1602 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1603 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1604 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth * 6/2) /8 ) * 8 */
1605 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
* 6, 2 * 8) * 8;
1607 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1608 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1612 unsigned long pitch
;
1613 uint32_t tiling
= I915_TILING_Y
;
1614 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1615 hz_width
, hz_height
, 1,
1617 BO_ALLOC_FOR_RENDER
);
1621 } else if (tiling
!= I915_TILING_Y
) {
1622 drm_intel_bo_unreference(buf
->bo
);
1634 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1635 * buffer dimensions and allocates a bo for the hiz buffer.
1637 static struct intel_miptree_aux_buffer
*
1638 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1639 struct intel_mipmap_tree
*mt
)
1641 unsigned z_width
= mt
->logical_width0
;
1642 unsigned z_height
= mt
->logical_height0
;
1643 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1644 unsigned hz_width
, hz_height
;
1645 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1650 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1651 * adjustments required for Z_Height and Z_Width based on multisampling.
1654 switch (mt
->num_samples
) {
1668 unreachable("unsupported sample count");
1672 const unsigned vertical_align
= 8; /* 'j' in the docs */
1673 const unsigned H0
= z_height
;
1674 const unsigned h0
= ALIGN(H0
, vertical_align
);
1675 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1676 const unsigned Z0
= z_depth
;
1678 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1679 hz_width
= ALIGN(z_width
, 16);
1683 unsigned sum_h_i
= 0;
1684 unsigned hz_height_3d_sum
= 0;
1685 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1686 unsigned i
= level
- mt
->first_level
;
1687 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1688 /* sum(i=2 to m; h_i) */
1692 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1693 hz_height_3d_sum
+= h_i
* Z_i
;
1694 H_i
= minify(H_i
, 1);
1695 Z_i
= minify(Z_i
, 1);
1697 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1698 buf
->qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1700 if (mt
->target
== GL_TEXTURE_3D
) {
1701 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1702 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1704 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1705 hz_height
= DIV_ROUND_UP(buf
->qpitch
, 2 * 8) * 8 * Z0
;
1706 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1707 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1708 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * 6 * Z_Depth
1710 * We can can just take our hz_height calculation from above, and
1711 * multiply by 6 for the cube map and cube map array types.
1717 unsigned long pitch
;
1718 uint32_t tiling
= I915_TILING_Y
;
1719 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1720 hz_width
, hz_height
, 1,
1722 BO_ALLOC_FOR_RENDER
);
1726 } else if (tiling
!= I915_TILING_Y
) {
1727 drm_intel_bo_unreference(buf
->bo
);
1738 static struct intel_miptree_aux_buffer
*
1739 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1740 struct intel_mipmap_tree
*mt
)
1742 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1743 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1746 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1751 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1752 buf
->mt
= intel_miptree_create(brw
,
1758 mt
->logical_height0
,
1767 buf
->bo
= buf
->mt
->bo
;
1768 buf
->pitch
= buf
->mt
->pitch
;
1769 buf
->qpitch
= buf
->mt
->qpitch
;
1775 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1776 struct intel_mipmap_tree
*mt
)
1781 if (mt
->hiz_buf
!= NULL
)
1784 if (mt
->disable_aux_buffers
)
1787 switch (mt
->format
) {
1788 case MESA_FORMAT_Z_FLOAT32
:
1789 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1790 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1791 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1792 case MESA_FORMAT_Z_UNORM16
:
1800 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1801 struct intel_mipmap_tree
*mt
)
1803 assert(mt
->hiz_buf
== NULL
);
1804 assert(!mt
->disable_aux_buffers
);
1806 if (brw
->gen
== 7) {
1807 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1808 } else if (brw
->gen
>= 8) {
1809 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1811 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1817 /* Mark that all slices need a HiZ resolve. */
1818 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1819 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1822 for (unsigned layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1823 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1824 exec_node_init(&m
->link
);
1827 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1829 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1837 * Does the miptree slice have hiz enabled?
1840 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1842 intel_miptree_check_level_layer(mt
, level
, 0);
1843 return mt
->level
[level
].has_hiz
;
1847 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1851 if (!intel_miptree_level_has_hiz(mt
, level
))
1854 intel_resolve_map_set(&mt
->hiz_map
,
1855 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1860 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1864 if (!intel_miptree_level_has_hiz(mt
, level
))
1867 intel_resolve_map_set(&mt
->hiz_map
,
1868 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1872 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1876 uint32_t end_layer
= mt
->level
[level
].depth
;
1878 for (layer
= 0; layer
< end_layer
; layer
++) {
1879 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1884 intel_miptree_slice_resolve(struct brw_context
*brw
,
1885 struct intel_mipmap_tree
*mt
,
1888 enum gen6_hiz_op need
)
1890 intel_miptree_check_level_layer(mt
, level
, layer
);
1892 struct intel_resolve_map
*item
=
1893 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1895 if (!item
|| item
->need
!= need
)
1898 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1899 intel_resolve_map_remove(item
);
1904 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1905 struct intel_mipmap_tree
*mt
,
1909 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1910 GEN6_HIZ_OP_HIZ_RESOLVE
);
1914 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1915 struct intel_mipmap_tree
*mt
,
1919 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1920 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1924 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1925 struct intel_mipmap_tree
*mt
,
1926 enum gen6_hiz_op need
)
1928 bool did_resolve
= false;
1930 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
1931 if (map
->need
!= need
)
1934 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
1935 intel_resolve_map_remove(map
);
1943 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1944 struct intel_mipmap_tree
*mt
)
1946 return intel_miptree_all_slices_resolve(brw
, mt
,
1947 GEN6_HIZ_OP_HIZ_RESOLVE
);
1951 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1952 struct intel_mipmap_tree
*mt
)
1954 return intel_miptree_all_slices_resolve(brw
, mt
,
1955 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1960 intel_miptree_resolve_color(struct brw_context
*brw
,
1961 struct intel_mipmap_tree
*mt
)
1963 switch (mt
->fast_clear_state
) {
1964 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1965 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1966 /* No resolve needed */
1968 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1969 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1970 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1971 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1972 brw_meta_resolve_color(brw
, mt
);
1979 * Make it possible to share the BO backing the given miptree with another
1980 * process or another miptree.
1982 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1983 * then discard the MCS buffer, if present. We also set the fast_clear_state
1984 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1985 * allocated in the future.
1988 intel_miptree_make_shareable(struct brw_context
*brw
,
1989 struct intel_mipmap_tree
*mt
)
1991 /* MCS buffers are also used for multisample buffers, but we can't resolve
1992 * away a multisample MCS buffer because it's an integral part of how the
1993 * pixel data is stored. Fortunately this code path should never be
1994 * reached for multisample buffers.
1996 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1999 intel_miptree_resolve_color(brw
, mt
);
2000 intel_miptree_release(&mt
->mcs_mt
);
2001 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
2007 * \brief Get pointer offset into stencil buffer.
2009 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2010 * must decode the tile's layout in software.
2013 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2015 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2017 * Even though the returned offset is always positive, the return type is
2019 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2020 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2023 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2025 uint32_t tile_size
= 4096;
2026 uint32_t tile_width
= 64;
2027 uint32_t tile_height
= 64;
2028 uint32_t row_size
= 64 * stride
;
2030 uint32_t tile_x
= x
/ tile_width
;
2031 uint32_t tile_y
= y
/ tile_height
;
2033 /* The byte's address relative to the tile's base addres. */
2034 uint32_t byte_x
= x
% tile_width
;
2035 uint32_t byte_y
= y
% tile_height
;
2037 uintptr_t u
= tile_y
* row_size
2038 + tile_x
* tile_size
2039 + 512 * (byte_x
/ 8)
2041 + 32 * ((byte_y
/ 4) % 2)
2042 + 16 * ((byte_x
/ 4) % 2)
2043 + 8 * ((byte_y
/ 2) % 2)
2044 + 4 * ((byte_x
/ 2) % 2)
2049 /* adjust for bit6 swizzling */
2050 if (((byte_x
/ 8) % 2) == 1) {
2051 if (((byte_y
/ 8) % 2) == 0) {
2063 intel_miptree_updownsample(struct brw_context
*brw
,
2064 struct intel_mipmap_tree
*src
,
2065 struct intel_mipmap_tree
*dst
)
2068 brw_blorp_blit_miptrees(brw
,
2069 src
, 0 /* level */, 0 /* layer */, src
->format
,
2070 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2072 src
->logical_width0
, src
->logical_height0
,
2074 dst
->logical_width0
, dst
->logical_height0
,
2075 GL_NEAREST
, false, false /*mirror x, y*/);
2076 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
2077 brw_meta_stencil_updownsample(brw
, src
, dst
);
2079 brw_meta_updownsample(brw
, src
, dst
);
2082 if (src
->stencil_mt
) {
2083 if (brw
->gen
>= 8) {
2084 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
2088 brw_blorp_blit_miptrees(brw
,
2089 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2090 src
->stencil_mt
->format
,
2091 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2092 dst
->stencil_mt
->format
,
2094 src
->logical_width0
, src
->logical_height0
,
2096 dst
->logical_width0
, dst
->logical_height0
,
2097 GL_NEAREST
, false, false /*mirror x, y*/);
2102 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2104 /* CPU accesses to color buffers don't understand fast color clears, so
2105 * resolve any pending fast color clears before we map.
2107 intel_miptree_resolve_color(brw
, mt
);
2109 drm_intel_bo
*bo
= mt
->bo
;
2111 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2112 intel_batchbuffer_flush(brw
);
2114 if (mt
->tiling
!= I915_TILING_NONE
)
2115 brw_bo_map_gtt(brw
, bo
, "miptree");
2117 brw_bo_map(brw
, bo
, true, "miptree");
2123 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2125 drm_intel_bo_unmap(mt
->bo
);
2129 intel_miptree_map_gtt(struct brw_context
*brw
,
2130 struct intel_mipmap_tree
*mt
,
2131 struct intel_miptree_map
*map
,
2132 unsigned int level
, unsigned int slice
)
2134 unsigned int bw
, bh
;
2136 unsigned int image_x
, image_y
;
2137 intptr_t x
= map
->x
;
2138 intptr_t y
= map
->y
;
2140 /* For compressed formats, the stride is the number of bytes per
2141 * row of blocks. intel_miptree_get_image_offset() already does
2144 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2145 assert(y
% bh
== 0);
2146 assert(x
% bw
== 0);
2150 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2155 /* Note that in the case of cube maps, the caller must have passed the
2156 * slice number referencing the face.
2158 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2162 map
->stride
= mt
->pitch
;
2163 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2166 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2167 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2168 map
->x
, map
->y
, map
->w
, map
->h
,
2169 mt
, _mesa_get_format_name(mt
->format
),
2170 x
, y
, map
->ptr
, map
->stride
);
2174 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2176 intel_miptree_unmap_raw(mt
);
2180 intel_miptree_map_blit(struct brw_context
*brw
,
2181 struct intel_mipmap_tree
*mt
,
2182 struct intel_miptree_map
*map
,
2183 unsigned int level
, unsigned int slice
)
2185 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2186 /* first_level */ 0,
2190 MIPTREE_LAYOUT_TILING_NONE
);
2192 if (!map
->linear_mt
) {
2193 fprintf(stderr
, "Failed to allocate blit temporary\n");
2196 map
->stride
= map
->linear_mt
->pitch
;
2198 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2199 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2200 * invalidate is set, since we'll be writing the whole rectangle from our
2201 * temporary buffer back out.
2203 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2204 if (!intel_miptree_blit(brw
,
2206 map
->x
, map
->y
, false,
2207 map
->linear_mt
, 0, 0,
2209 map
->w
, map
->h
, GL_COPY
)) {
2210 fprintf(stderr
, "Failed to blit\n");
2215 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
);
2217 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2218 map
->x
, map
->y
, map
->w
, map
->h
,
2219 mt
, _mesa_get_format_name(mt
->format
),
2220 level
, slice
, map
->ptr
, map
->stride
);
2225 intel_miptree_release(&map
->linear_mt
);
2231 intel_miptree_unmap_blit(struct brw_context
*brw
,
2232 struct intel_mipmap_tree
*mt
,
2233 struct intel_miptree_map
*map
,
2237 struct gl_context
*ctx
= &brw
->ctx
;
2239 intel_miptree_unmap_raw(map
->linear_mt
);
2241 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2242 bool ok
= intel_miptree_blit(brw
,
2243 map
->linear_mt
, 0, 0,
2246 map
->x
, map
->y
, false,
2247 map
->w
, map
->h
, GL_COPY
);
2248 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2251 intel_miptree_release(&map
->linear_mt
);
2255 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2257 #if defined(USE_SSE41)
2259 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2260 struct intel_mipmap_tree
*mt
,
2261 struct intel_miptree_map
*map
,
2262 unsigned int level
, unsigned int slice
)
2264 assert(map
->mode
& GL_MAP_READ_BIT
);
2265 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2267 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2268 map
->x
, map
->y
, map
->w
, map
->h
,
2269 mt
, _mesa_get_format_name(mt
->format
),
2270 level
, slice
, map
->ptr
, map
->stride
);
2272 /* Map the original image */
2275 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2279 void *src
= intel_miptree_map_raw(brw
, mt
);
2282 src
+= image_y
* mt
->pitch
;
2283 src
+= image_x
* mt
->cpp
;
2285 /* Due to the pixel offsets for the particular image being mapped, our
2286 * src pointer may not be 16-byte aligned. However, if the pitch is
2287 * divisible by 16, then the amount by which it's misaligned will remain
2288 * consistent from row to row.
2290 assert((mt
->pitch
% 16) == 0);
2291 const int misalignment
= ((uintptr_t) src
) & 15;
2293 /* Create an untiled temporary buffer for the mapping. */
2294 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2296 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2298 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2299 /* Offset the destination so it has the same misalignment as src. */
2300 map
->ptr
= map
->buffer
+ misalignment
;
2302 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2304 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2305 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2306 void *src_ptr
= src
+ y
* mt
->pitch
;
2308 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2311 intel_miptree_unmap_raw(mt
);
2315 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2316 struct intel_mipmap_tree
*mt
,
2317 struct intel_miptree_map
*map
,
2321 _mesa_align_free(map
->buffer
);
2328 intel_miptree_map_s8(struct brw_context
*brw
,
2329 struct intel_mipmap_tree
*mt
,
2330 struct intel_miptree_map
*map
,
2331 unsigned int level
, unsigned int slice
)
2333 map
->stride
= map
->w
;
2334 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2338 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2339 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2340 * invalidate is set, since we'll be writing the whole rectangle from our
2341 * temporary buffer back out.
2343 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2344 uint8_t *untiled_s8_map
= map
->ptr
;
2345 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2346 unsigned int image_x
, image_y
;
2348 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2350 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2351 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2352 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2353 x
+ image_x
+ map
->x
,
2354 y
+ image_y
+ map
->y
,
2355 brw
->has_swizzling
);
2356 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2360 intel_miptree_unmap_raw(mt
);
2362 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2363 map
->x
, map
->y
, map
->w
, map
->h
,
2364 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2366 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2367 map
->x
, map
->y
, map
->w
, map
->h
,
2368 mt
, map
->ptr
, map
->stride
);
2373 intel_miptree_unmap_s8(struct brw_context
*brw
,
2374 struct intel_mipmap_tree
*mt
,
2375 struct intel_miptree_map
*map
,
2379 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2380 unsigned int image_x
, image_y
;
2381 uint8_t *untiled_s8_map
= map
->ptr
;
2382 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2384 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2386 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2387 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2388 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2391 brw
->has_swizzling
);
2392 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2396 intel_miptree_unmap_raw(mt
);
2403 intel_miptree_map_etc(struct brw_context
*brw
,
2404 struct intel_mipmap_tree
*mt
,
2405 struct intel_miptree_map
*map
,
2409 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2410 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2411 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2414 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2415 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2417 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2418 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2419 map
->w
, map
->h
, 1));
2420 map
->ptr
= map
->buffer
;
2424 intel_miptree_unmap_etc(struct brw_context
*brw
,
2425 struct intel_mipmap_tree
*mt
,
2426 struct intel_miptree_map
*map
,
2432 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2437 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2438 + image_y
* mt
->pitch
2439 + image_x
* mt
->cpp
;
2441 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2442 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2443 map
->ptr
, map
->stride
,
2446 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2447 map
->ptr
, map
->stride
,
2448 map
->w
, map
->h
, mt
->etc_format
);
2450 intel_miptree_unmap_raw(mt
);
2455 * Mapping function for packed depth/stencil miptrees backed by real separate
2456 * miptrees for depth and stencil.
2458 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2459 * separate from the depth buffer. Yet at the GL API level, we have to expose
2460 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2461 * be able to map that memory for texture storage and glReadPixels-type
2462 * operations. We give Mesa core that access by mallocing a temporary and
2463 * copying the data between the actual backing store and the temporary.
2466 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2467 struct intel_mipmap_tree
*mt
,
2468 struct intel_miptree_map
*map
,
2469 unsigned int level
, unsigned int slice
)
2471 struct intel_mipmap_tree
*z_mt
= mt
;
2472 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2473 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2474 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2476 map
->stride
= map
->w
* packed_bpp
;
2477 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2481 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2482 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2483 * invalidate is set, since we'll be writing the whole rectangle from our
2484 * temporary buffer back out.
2486 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2487 uint32_t *packed_map
= map
->ptr
;
2488 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2489 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2490 unsigned int s_image_x
, s_image_y
;
2491 unsigned int z_image_x
, z_image_y
;
2493 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2494 &s_image_x
, &s_image_y
);
2495 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2496 &z_image_x
, &z_image_y
);
2498 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2499 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2500 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2501 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2504 brw
->has_swizzling
);
2505 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2507 (map_x
+ z_image_x
));
2508 uint8_t s
= s_map
[s_offset
];
2509 uint32_t z
= z_map
[z_offset
];
2511 if (map_z32f_x24s8
) {
2512 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2513 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2515 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2520 intel_miptree_unmap_raw(s_mt
);
2521 intel_miptree_unmap_raw(z_mt
);
2523 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2525 map
->x
, map
->y
, map
->w
, map
->h
,
2526 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2527 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2528 map
->ptr
, map
->stride
);
2530 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2531 map
->x
, map
->y
, map
->w
, map
->h
,
2532 mt
, map
->ptr
, map
->stride
);
2537 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2538 struct intel_mipmap_tree
*mt
,
2539 struct intel_miptree_map
*map
,
2543 struct intel_mipmap_tree
*z_mt
= mt
;
2544 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2545 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2547 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2548 uint32_t *packed_map
= map
->ptr
;
2549 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2550 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2551 unsigned int s_image_x
, s_image_y
;
2552 unsigned int z_image_x
, z_image_y
;
2554 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2555 &s_image_x
, &s_image_y
);
2556 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2557 &z_image_x
, &z_image_y
);
2559 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2560 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2561 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2562 x
+ s_image_x
+ map
->x
,
2563 y
+ s_image_y
+ map
->y
,
2564 brw
->has_swizzling
);
2565 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2567 (x
+ z_image_x
+ map
->x
));
2569 if (map_z32f_x24s8
) {
2570 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2571 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2573 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2574 s_map
[s_offset
] = packed
>> 24;
2575 z_map
[z_offset
] = packed
;
2580 intel_miptree_unmap_raw(s_mt
);
2581 intel_miptree_unmap_raw(z_mt
);
2583 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2585 map
->x
, map
->y
, map
->w
, map
->h
,
2586 z_mt
, _mesa_get_format_name(z_mt
->format
),
2587 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2588 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2589 map
->ptr
, map
->stride
);
2596 * Create and attach a map to the miptree at (level, slice). Return the
2599 static struct intel_miptree_map
*
2600 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2609 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2614 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2615 mt
->level
[level
].slice
[slice
].map
= map
;
2627 * Release the map at (level, slice).
2630 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2634 struct intel_miptree_map
**map
;
2636 map
= &mt
->level
[level
].slice
[slice
].map
;
2642 can_blit_slice(struct intel_mipmap_tree
*mt
,
2643 unsigned int level
, unsigned int slice
)
2647 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2648 if (image_x
>= 32768 || image_y
>= 32768)
2651 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2652 if (mt
->pitch
>= 32768)
2659 use_intel_mipree_map_blit(struct brw_context
*brw
,
2660 struct intel_mipmap_tree
*mt
,
2666 /* It's probably not worth swapping to the blit ring because of
2667 * all the overhead involved.
2669 !(mode
& GL_MAP_WRITE_BIT
) &&
2671 (mt
->tiling
== I915_TILING_X
||
2672 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2673 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
)) &&
2674 can_blit_slice(mt
, level
, slice
))
2677 if (mt
->tiling
!= I915_TILING_NONE
&&
2678 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2679 assert(can_blit_slice(mt
, level
, slice
));
2687 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2688 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2689 * arithmetic overflow.
2691 * If you call this function and use \a out_stride, then you're doing pointer
2692 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2693 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2694 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2695 * which usually have type uint32_t or GLuint.
2698 intel_miptree_map(struct brw_context
*brw
,
2699 struct intel_mipmap_tree
*mt
,
2708 ptrdiff_t *out_stride
)
2710 struct intel_miptree_map
*map
;
2712 assert(mt
->num_samples
<= 1);
2714 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2721 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2722 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2723 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2726 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2727 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2728 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2729 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2730 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2731 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2732 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2733 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2734 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2735 #if defined(USE_SSE41)
2736 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
2737 !mt
->compressed
&& cpu_has_sse4_1
&&
2738 (mt
->pitch
% 16 == 0)) {
2739 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2742 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2745 *out_ptr
= map
->ptr
;
2746 *out_stride
= map
->stride
;
2748 if (map
->ptr
== NULL
)
2749 intel_miptree_release_map(mt
, level
, slice
);
2753 intel_miptree_unmap(struct brw_context
*brw
,
2754 struct intel_mipmap_tree
*mt
,
2758 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2760 assert(mt
->num_samples
<= 1);
2765 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
2766 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2768 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2769 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2770 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2771 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2772 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2773 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2774 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2775 } else if (map
->linear_mt
) {
2776 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2777 #if defined(USE_SSE41)
2778 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2779 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2782 intel_miptree_unmap_gtt(mt
);
2785 intel_miptree_release_map(mt
, level
, slice
);