src/mesa/drivers/dri/i965/intel_mipmap_tree.h

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  27
  28 /** @file intel_mipmap_tree.h
  29  *
  30  * This file defines the structure that wraps a BO and describes how the
  31  * mipmap levels and slices of a texture are laid out.
  32  *
  33  * The hardware has a fixed layout of a texture depending on parameters such
  34  * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
  35  * mipmap levels.  The individual level/layer slices are each 2D rectangles of
  36  * pixels at some x/y offset from the start of the drm_intel_bo.
  37  *
  38  * Original OpenGL allowed texture miplevels to be specified in arbitrary
  39  * order, and a texture may change size over time.  Thus, each
  40  * intel_texture_image has a reference to a miptree that contains the pixel
  41  * data sized appropriately for it, which will later be referenced by/copied
  42  * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
  43  * that there's a single miptree for the complete texture.
  44  */
  45
  46 #ifndef INTEL_MIPMAP_TREE_H
  47 #define INTEL_MIPMAP_TREE_H
  48
  49 #include <assert.h>
  50
  51 #include "main/mtypes.h"
  52 #include "intel_bufmgr.h"
  53 #include "intel_resolve_map.h"
  54 #include <GL/internal/dri_interface.h>
  55
  56 #ifdef __cplusplus
  57 extern "C" {
  58 #endif
  59
  60 struct brw_context;
  61 struct intel_renderbuffer;
  62
  63 struct intel_resolve_map;
  64 struct intel_texture_image;
  65
  66 /**
  67  * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
  68  * depthstencil-split-to-separate-stencil miptree, we'll normally make a
  69  * tmeporary and recreate the kind of data requested by Mesa core, since we're
  70  * satisfying some glGetTexImage() request or something.
  71  *
  72  * However, occasionally you want to actually map the miptree's current data
  73  * without transcoding back.  This flag to intel_miptree_map() gets you that.
  74  */
  75 #define BRW_MAP_DIRECT_BIT      0x80000000
  76
  77 struct intel_miptree_map {
  78    /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
  79    GLbitfield mode;
  80    /** Region of interest for the map. */
  81    int x, y, w, h;
  82    /** Possibly malloced temporary buffer for the mapping. */
  83    void *buffer;
  84    /** Possible pointer to a temporary linear miptree for the mapping. */
  85    struct intel_mipmap_tree *mt;
  86    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  87    void *ptr;
  88    /** Stride of the mapping. */
  89    int stride;
  90 };
  91
  92 /**
  93  * Describes the location of each texture image within a miptree.
  94  */
  95 struct intel_mipmap_level
  96 {
  97    /** Offset to this miptree level, used in computing x_offset. */
  98    GLuint level_x;
  99    /** Offset to this miptree level, used in computing y_offset. */
 100    GLuint level_y;
 101
 102    /**
 103     * \brief Number of 2D slices in this miplevel.
 104     *
 105     * The exact semantics of depth varies according to the texture target:
 106     *    - For GL_TEXTURE_CUBE_MAP, depth is 6.
 107     *    - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
 108     *      identical for all miplevels in the texture.
 109     *    - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
 110     *      value, like width and height, varies with miplevel.
 111     *    - For other texture types, depth is 1.
 112     *    - Additionally, for UMS and CMS miptrees, depth is multiplied by
 113     *      sample count.
 114     */
 115    GLuint depth;
 116
 117    /**
 118     * \brief Is HiZ enabled for this level?
 119     *
 120     * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
 121     * allocated and (2) the HiZ memory for the slices in this level reside at
 122     * \c mt->hiz_mt->level[l].
 123     */
 124    bool has_hiz;
 125
 126    /**
 127     * \brief List of 2D images in this mipmap level.
 128     *
 129     * This may be a list of cube faces, array slices in 2D array texture, or
 130     * layers in a 3D texture. The list's length is \c depth.
 131     */
 132    struct intel_mipmap_slice {
 133       /**
 134        * \name Offset to slice
 135        * \{
 136        *
 137        * Hardware formats are so diverse that that there is no unified way to
 138        * compute the slice offsets, so we store them in this table.
 139        *
 140        * The (x, y) offset to slice \c s at level \c l relative the miptrees
 141        * base address is
 142        * \code
 143        *     x = mt->level[l].slice[s].x_offset
 144        *     y = mt->level[l].slice[s].y_offset
 145        */
 146       GLuint x_offset;
 147       GLuint y_offset;
 148       /** \} */
 149
 150       /**
 151        * Mapping information. Persistent for the duration of
 152        * intel_miptree_map/unmap on this slice.
 153        */
 154       struct intel_miptree_map *map;
 155    } *slice;
 156 };
 157
 158 /**
 159  * Enum for keeping track of the different MSAA layouts supported by Gen7.
 160  */
 161 enum intel_msaa_layout
 162 {
 163    /**
 164     * Ordinary surface with no MSAA.
 165     */
 166    INTEL_MSAA_LAYOUT_NONE,
 167
 168    /**
 169     * Interleaved Multisample Surface.  The additional samples are
 170     * accommodated by scaling up the width and the height of the surface so
 171     * that all the samples corresponding to a pixel are located at nearby
 172     * memory locations.
 173     */
 174    INTEL_MSAA_LAYOUT_IMS,
 175
 176    /**
 177     * Uncompressed Multisample Surface.  The surface is stored as a 2D array,
 178     * with array slice n containing all pixel data for sample n.
 179     */
 180    INTEL_MSAA_LAYOUT_UMS,
 181
 182    /**
 183     * Compressed Multisample Surface.  The surface is stored as in
 184     * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
 185     * (Multisample Control Surface) buffer.  Each pixel in the MCS buffer
 186     * indicates the mapping from sample number to array slice.  This allows
 187     * the common case (where all samples constituting a pixel have the same
 188     * color value) to be stored efficiently by just using a single array
 189     * slice.
 190     */
 191    INTEL_MSAA_LAYOUT_CMS,
 192 };
 193
 194
 195 /**
 196  * Enum for keeping track of the fast clear state of a buffer associated with
 197  * a miptree.
 198  *
 199  * Fast clear works by deferring the memory writes that would be used to clear
 200  * the buffer, so that instead of performing them at the time of the clear
 201  * operation, the hardware automatically performs them at the time that the
 202  * buffer is later accessed for rendering.  The MCS buffer keeps track of
 203  * which regions of the buffer still have pending clear writes.
 204  *
 205  * This enum keeps track of the driver's knowledge of pending fast clears in
 206  * the MCS buffer.
 207  *
 208  * MCS buffers only exist on Gen7+.
 209  */
 210 enum intel_fast_clear_state
 211 {
 212    /**
 213     * There is no MCS buffer for this miptree, and one should never be
 214     * allocated.
 215     */
 216    INTEL_FAST_CLEAR_STATE_NO_MCS,
 217
 218    /**
 219     * No deferred clears are pending for this miptree, and the contents of the
 220     * color buffer are entirely correct.  An MCS buffer may or may not exist
 221     * for this miptree.  If it does exist, it is entirely in the "no deferred
 222     * clears pending" state.  If it does not exist, it will be created the
 223     * first time a fast color clear is executed.
 224     *
 225     * In this state, the color buffer can be used for purposes other than
 226     * rendering without needing a render target resolve.
 227     *
 228     * Since there is no such thing as a "fast color clear resolve" for MSAA
 229     * buffers, an MSAA buffer will never be in this state.
 230     */
 231    INTEL_FAST_CLEAR_STATE_RESOLVED,
 232
 233    /**
 234     * An MCS buffer exists for this miptree, and deferred clears are pending
 235     * for some regions of the color buffer, as indicated by the MCS buffer.
 236     * The contents of the color buffer are only correct for the regions where
 237     * the MCS buffer doesn't indicate a deferred clear.
 238     *
 239     * If a single-sample buffer is in this state, a render target resolve must
 240     * be performed before it can be used for purposes other than rendering.
 241     */
 242    INTEL_FAST_CLEAR_STATE_UNRESOLVED,
 243
 244    /**
 245     * An MCS buffer exists for this miptree, and deferred clears are pending
 246     * for the entire color buffer, and the contents of the MCS buffer reflect
 247     * this.  The contents of the color buffer are undefined.
 248     *
 249     * If a single-sample buffer is in this state, a render target resolve must
 250     * be performed before it can be used for purposes other than rendering.
 251     *
 252     * If the client attempts to clear a buffer which is already in this state,
 253     * the clear can be safely skipped, since the buffer is already clear.
 254     */
 255    INTEL_FAST_CLEAR_STATE_CLEAR,
 256 };
 257
 258 enum miptree_array_layout {
 259    /* Each array slice contains all miplevels packed together.
 260     *
 261     * Gen hardware usually wants multilevel miptrees configured this way.
 262     *
 263     * A 2D Array texture with 2 slices and multiple LODs using
 264     * ALL_LOD_IN_EACH_SLICE would look somewhat like this:
 265     *
 266     *   +----------+
 267     *   |          |
 268     *   |          |
 269     *   +----------+
 270     *   +---+ +-+
 271     *   |   | +-+
 272     *   +---+ *
 273     *   +----------+
 274     *   |          |
 275     *   |          |
 276     *   +----------+
 277     *   +---+ +-+
 278     *   |   | +-+
 279     *   +---+ *
 280     */
 281    ALL_LOD_IN_EACH_SLICE,
 282
 283    /* Each LOD contains all slices of that LOD packed together.
 284     *
 285     * In some situations, Gen7+ hardware can use the array_spacing_lod0
 286     * feature to save space when the surface only contains LOD 0.
 287     *
 288     * Gen6 uses this for separate stencil and hiz since gen6 does not support
 289     * multiple LODs for separate stencil and hiz.
 290     *
 291     * A 2D Array texture with 2 slices and multiple LODs using
 292     * ALL_SLICES_AT_EACH_LOD would look somewhat like this:
 293     *
 294     *   +----------+
 295     *   |          |
 296     *   |          |
 297     *   +----------+
 298     *   |          |
 299     *   |          |
 300     *   +----------+
 301     *   +---+ +-+
 302     *   |   | +-+
 303     *   +---+ +-+
 304     *   |   | :
 305     *   +---+
 306     */
 307    ALL_SLICES_AT_EACH_LOD,
 308 };
 309
 310 /**
 311  * Miptree aux buffer. These buffers are associated with a miptree, but the
 312  * format is managed by the hardware.
 313  *
 314  * For Gen7+, we always give the hardware the start of the buffer, and let it
 315  * handle all accesses to the buffer. Therefore we don't need the full miptree
 316  * layout structure for this buffer.
 317  *
 318  * For Gen6, we need a hiz miptree structure for this buffer so we can program
 319  * offsets to slices & miplevels.
 320  */
 321 struct intel_miptree_aux_buffer
 322 {
 323    /** Buffer object containing the pixel data. */
 324    drm_intel_bo *bo;
 325
 326    uint32_t pitch; /**< pitch in bytes. */
 327
 328    uint32_t qpitch; /**< The distance in rows between array slices. */
 329
 330    struct intel_mipmap_tree *mt; /**< hiz miptree used with Gen6 */
 331 };
 332
 333 struct intel_mipmap_tree
 334 {
 335    /** Buffer object containing the pixel data. */
 336    drm_intel_bo *bo;
 337
 338    uint32_t pitch; /**< pitch in bytes. */
 339
 340    uint32_t tiling; /**< One of the I915_TILING_* flags */
 341
 342    /* Effectively the key:
 343     */
 344    GLenum target;
 345
 346    /**
 347     * Generally, this is just the same as the gl_texture_image->TexFormat or
 348     * gl_renderbuffer->Format.
 349     *
 350     * However, for textures and renderbuffers with packed depth/stencil formats
 351     * on hardware where we want or need to use separate stencil, there will be
 352     * two miptrees for storing the data.  If the depthstencil texture or rb is
 353     * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
 354     * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
 355     * MESA_FORMAT_Z24_UNORM_X8_UINT.
 356     *
 357     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
 358     * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
 359     */
 360    mesa_format format;
 361
 362    /** This variable stores the value of ETC compressed texture format */
 363    mesa_format etc_format;
 364
 365    /**
 366     * The X offset of each image in the miptree must be aligned to this.
 367     * See the comments in brw_tex_layout.c.
 368     */
 369    unsigned int align_w;
 370    unsigned int align_h; /**< \see align_w */
 371
 372    GLuint first_level;
 373    GLuint last_level;
 374
 375    /**
 376     * Level zero image dimensions.  These dimensions correspond to the
 377     * physical layout of data in memory.  Accordingly, they account for the
 378     * extra width, height, and or depth that must be allocated in order to
 379     * accommodate multisample formats, and they account for the extra factor
 380     * of 6 in depth that must be allocated in order to accommodate cubemap
 381     * textures.
 382     */
 383    GLuint physical_width0, physical_height0, physical_depth0;
 384
 385    GLuint cpp; /**< bytes per pixel */
 386    GLuint num_samples;
 387    bool compressed;
 388
 389    /**
 390     * Level zero image dimensions.  These dimensions correspond to the
 391     * logical width, height, and depth of the texture as seen by client code.
 392     * Accordingly, they do not account for the extra width, height, and/or
 393     * depth that must be allocated in order to accommodate multisample
 394     * formats, nor do they account for the extra factor of 6 in depth that
 395     * must be allocated in order to accommodate cubemap textures.
 396     */
 397    uint32_t logical_width0, logical_height0, logical_depth0;
 398
 399    /**
 400     * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
 401     * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
 402     */
 403    enum miptree_array_layout array_layout;
 404
 405    /**
 406     * The distance in rows between array slices in an uncompressed surface.
 407     *
 408     * For compressed surfaces, slices are stored closer together physically;
 409     * the real distance is (qpitch / block height).
 410     */
 411    uint32_t qpitch;
 412
 413    /**
 414     * MSAA layout used by this buffer.
 415     */
 416    enum intel_msaa_layout msaa_layout;
 417
 418    /* Derived from the above:
 419     */
 420    GLuint total_width;
 421    GLuint total_height;
 422
 423    /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to
 424     * this depth mipmap tree, if any.
 425     */
 426    uint32_t depth_clear_value;
 427
 428    /* Includes image offset tables:
 429     */
 430    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 431
 432    /* Offset into bo where miptree starts:
 433     */
 434    uint32_t offset;
 435
 436    /**
 437     * \brief HiZ aux buffer
 438     *
 439     * The hiz miptree contains the miptree's hiz buffer. To allocate the hiz
 440     * buffer, use intel_miptree_alloc_hiz().
 441     *
 442     * To determine if hiz is enabled, do not check this pointer. Instead, use
 443     * intel_miptree_slice_has_hiz().
 444     */
 445    struct intel_miptree_aux_buffer *hiz_buf;
 446
 447    /**
 448     * \brief Map of miptree slices to needed resolves.
 449     *
 450     * This is used only when the miptree has a child HiZ miptree.
 451     *
 452     * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
 453     * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
 454     * mt->hiz_mt->hiz_map, is unused.
 455     */
 456    struct exec_list hiz_map; /* List of intel_resolve_map. */
 457
 458    /**
 459     * \brief Stencil miptree for depthstencil textures.
 460     *
 461     * This miptree is used for depthstencil textures and renderbuffers that
 462     * require separate stencil.  It always has the true copy of the stencil
 463     * bits, regardless of mt->format.
 464     *
 465     * \see intel_miptree_map_depthstencil()
 466     * \see intel_miptree_unmap_depthstencil()
 467     */
 468    struct intel_mipmap_tree *stencil_mt;
 469
 470    /**
 471     * \brief MCS miptree.
 472     *
 473     * This miptree contains the "multisample control surface", which stores
 474     * the necessary information to implement compressed MSAA
 475     * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
 476     *
 477     * NULL if no MCS miptree is in use for this surface.
 478     */
 479    struct intel_mipmap_tree *mcs_mt;
 480
 481    /**
 482     * Fast clear state for this buffer.
 483     */
 484    enum intel_fast_clear_state fast_clear_state;
 485
 486    /**
 487     * The SURFACE_STATE bits associated with the last fast color clear to this
 488     * color mipmap tree, if any.
 489     *
 490     * This value will only ever contain ones in bits 28-31, so it is safe to
 491     * OR into dword 7 of SURFACE_STATE.
 492     */
 493    uint32_t fast_clear_color_value;
 494
 495    /**
 496     * Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS
 497     * buffer. This is useful for sharing the miptree bo with an external client
 498     * that doesn't understand auxiliary buffers.
 499     */
 500    bool disable_aux_buffers;
 501
 502    /* These are also refcounted:
 503     */
 504    GLuint refcount;
 505 };
 506
 507 enum intel_miptree_tiling_mode {
 508    INTEL_MIPTREE_TILING_ANY,
 509    INTEL_MIPTREE_TILING_Y,
 510    INTEL_MIPTREE_TILING_NONE,
 511 };
 512
 513 bool
 514 intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
 515                                        struct intel_mipmap_tree *mt);
 516
 517 void
 518 intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
 519                                  struct intel_mipmap_tree *mt,
 520                                  unsigned *width_px, unsigned *height);
 521
 522 bool
 523 intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
 524                                  struct intel_mipmap_tree *mt);
 525
 526 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
 527                                                GLenum target,
 528                                                mesa_format format,
 529                                                GLuint first_level,
 530                                                GLuint last_level,
 531                                                GLuint width0,
 532                                                GLuint height0,
 533                                                GLuint depth0,
 534                                                bool expect_accelerated_upload,
 535                                                GLuint num_samples,
 536                                                enum intel_miptree_tiling_mode,
 537                                                bool force_all_slices_at_each_lod);
 538
 539 struct intel_mipmap_tree *
 540 intel_miptree_create_for_bo(struct brw_context *brw,
 541                             drm_intel_bo *bo,
 542                             mesa_format format,
 543                             uint32_t offset,
 544                             uint32_t width,
 545                             uint32_t height,
 546                             uint32_t depth,
 547                             int pitch);
 548
 549 void
 550 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
 551                                          struct intel_renderbuffer *irb,
 552                                          drm_intel_bo *bo,
 553                                          uint32_t width, uint32_t height,
 554                                          uint32_t pitch);
 555
 556 /**
 557  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 558  * The miptree has the following properties:
 559  *     - The target is GL_TEXTURE_2D.
 560  *     - There are no levels other than the base level 0.
 561  *     - Depth is 1.
 562  */
 563 struct intel_mipmap_tree*
 564 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
 565                                       mesa_format format,
 566                                       uint32_t width,
 567                                       uint32_t height,
 568                                       uint32_t num_samples);
 569
 570 mesa_format
 571 intel_depth_format_for_depthstencil_format(mesa_format format);
 572
 573 mesa_format
 574 intel_lower_compressed_format(struct brw_context *brw, mesa_format format);
 575
 576 /** \brief Assert that the level and layer are valid for the miptree. */
 577 static inline void
 578 intel_miptree_check_level_layer(struct intel_mipmap_tree *mt,
 579                                 uint32_t level,
 580                                 uint32_t layer)
 581 {
 582    assert(level >= mt->first_level);
 583    assert(level <= mt->last_level);
 584    assert(layer < mt->level[level].depth);
 585 }
 586
 587 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 588                              struct intel_mipmap_tree *src);
 589
 590 void intel_miptree_release(struct intel_mipmap_tree **mt);
 591
 592 /* Check if an image fits an existing mipmap tree layout
 593  */
 594 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 595                                     struct gl_texture_image *image);
 596
 597 void
 598 intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt,
 599                                GLuint level, GLuint slice,
 600                                GLuint *x, GLuint *y);
 601
 602 void
 603 intel_miptree_get_dimensions_for_image(struct gl_texture_image *image,
 604                                        int *width, int *height, int *depth);
 605
 606 void
 607 intel_miptree_get_tile_masks(const struct intel_mipmap_tree *mt,
 608                              uint32_t *mask_x, uint32_t *mask_y,
 609                              bool map_stencil_as_y_tiled);
 610
 611 uint32_t
 612 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
 613                                GLuint level, GLuint slice,
 614                                uint32_t *tile_x,
 615                                uint32_t *tile_y);
 616 uint32_t
 617 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
 618                                  uint32_t x, uint32_t y,
 619                                  bool map_stencil_as_y_tiled);
 620
 621 void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
 622                                   GLuint level,
 623                                   GLuint x, GLuint y, GLuint d);
 624
 625 void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
 626                                     GLuint level,
 627                                     GLuint img, GLuint x, GLuint y);
 628
 629 void
 630 intel_miptree_copy_teximage(struct brw_context *brw,
 631                             struct intel_texture_image *intelImage,
 632                             struct intel_mipmap_tree *dst_mt, bool invalidate);
 633
 634 /**
 635  * \name Miptree HiZ functions
 636  * \{
 637  *
 638  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 639  * functions on a miptree without HiZ. In that case, each function is a no-op.
 640  */
 641
 642 bool
 643 intel_miptree_wants_hiz_buffer(struct brw_context *brw,
 644                                struct intel_mipmap_tree *mt);
 645
 646 /**
 647  * \brief Allocate the miptree's embedded HiZ miptree.
 648  * \see intel_mipmap_tree:hiz_mt
 649  * \return false if allocation failed
 650  */
 651 bool
 652 intel_miptree_alloc_hiz(struct brw_context *brw,
 653                         struct intel_mipmap_tree *mt);
 654
 655 bool
 656 intel_miptree_level_has_hiz(struct intel_mipmap_tree *mt, uint32_t level);
 657
 658 void
 659 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt,
 660                                           uint32_t level,
 661                                           uint32_t depth);
 662 void
 663 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt,
 664                                             uint32_t level,
 665                                             uint32_t depth);
 666
 667 void
 668 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree *mt,
 669                                                 uint32_t level);
 670
 671 /**
 672  * \return false if no resolve was needed
 673  */
 674 bool
 675 intel_miptree_slice_resolve_hiz(struct brw_context *brw,
 676                                 struct intel_mipmap_tree *mt,
 677                                 unsigned int level,
 678                                 unsigned int depth);
 679
 680 /**
 681  * \return false if no resolve was needed
 682  */
 683 bool
 684 intel_miptree_slice_resolve_depth(struct brw_context *brw,
 685                                   struct intel_mipmap_tree *mt,
 686                                   unsigned int level,
 687                                   unsigned int depth);
 688
 689 /**
 690  * \return false if no resolve was needed
 691  */
 692 bool
 693 intel_miptree_all_slices_resolve_hiz(struct brw_context *brw,
 694                                      struct intel_mipmap_tree *mt);
 695
 696 /**
 697  * \return false if no resolve was needed
 698  */
 699 bool
 700 intel_miptree_all_slices_resolve_depth(struct brw_context *brw,
 701                                        struct intel_mipmap_tree *mt);
 702
 703 /**\}*/
 704
 705 /**
 706  * Update the fast clear state for a miptree to indicate that it has been used
 707  * for rendering.
 708  */
 709 static inline void
 710 intel_miptree_used_for_rendering(struct intel_mipmap_tree *mt)
 711 {
 712    /* If the buffer was previously in fast clear state, change it to
 713     * unresolved state, since it won't be guaranteed to be clear after
 714     * rendering occurs.
 715     */
 716    if (mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR)
 717       mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
 718 }
 719
 720 void
 721 intel_miptree_resolve_color(struct brw_context *brw,
 722                             struct intel_mipmap_tree *mt);
 723
 724 void
 725 intel_miptree_make_shareable(struct brw_context *brw,
 726                              struct intel_mipmap_tree *mt);
 727
 728 void
 729 intel_miptree_updownsample(struct brw_context *brw,
 730                            struct intel_mipmap_tree *src,
 731                            struct intel_mipmap_tree *dst);
 732
 733 void brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt);
 734
 735 void *intel_miptree_map_raw(struct brw_context *brw,
 736                             struct intel_mipmap_tree *mt);
 737
 738 void intel_miptree_unmap_raw(struct brw_context *brw,
 739                              struct intel_mipmap_tree *mt);
 740
 741 void
 742 intel_miptree_map(struct brw_context *brw,
 743                   struct intel_mipmap_tree *mt,
 744                   unsigned int level,
 745                   unsigned int slice,
 746                   unsigned int x,
 747                   unsigned int y,
 748                   unsigned int w,
 749                   unsigned int h,
 750                   GLbitfield mode,
 751                   void **out_ptr,
 752                   ptrdiff_t *out_stride);
 753
 754 void
 755 intel_miptree_unmap(struct brw_context *brw,
 756                     struct intel_mipmap_tree *mt,
 757                     unsigned int level,
 758                     unsigned int slice);
 759
 760 void
 761 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 762                unsigned int level, unsigned int layer, enum gen6_hiz_op op);
 763
 764 #ifdef __cplusplus
 765 }
 766 #endif
 767
 768 #endif