src/mesa/drivers/dri/i965/intel_mipmap_tree.h

   1 /*
   2  * Copyright 2006 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 /** @file intel_mipmap_tree.h
  27  *
  28  * This file defines the structure that wraps a BO and describes how the
  29  * mipmap levels and slices of a texture are laid out.
  30  *
  31  * The hardware has a fixed layout of a texture depending on parameters such
  32  * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
  33  * mipmap levels.  The individual level/layer slices are each 2D rectangles of
  34  * pixels at some x/y offset from the start of the brw_bo.
  35  *
  36  * Original OpenGL allowed texture miplevels to be specified in arbitrary
  37  * order, and a texture may change size over time.  Thus, each
  38  * intel_texture_image has a reference to a miptree that contains the pixel
  39  * data sized appropriately for it, which will later be referenced by/copied
  40  * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
  41  * that there's a single miptree for the complete texture.
  42  */
  43
  44 #ifndef INTEL_MIPMAP_TREE_H
  45 #define INTEL_MIPMAP_TREE_H
  46
  47 #include <assert.h>
  48
  49 #include "main/mtypes.h"
  50 #include "isl/isl.h"
  51 #include "blorp/blorp.h"
  52 #include "brw_bufmgr.h"
  53 #include "brw_context.h"
  54 #include <GL/internal/dri_interface.h>
  55
  56 #ifdef __cplusplus
  57 extern "C" {
  58 #endif
  59
  60 struct brw_context;
  61 struct intel_renderbuffer;
  62
  63 struct intel_texture_image;
  64
  65 /**
  66  * This bit extends the set of GL_MAP_*_BIT enums.
  67  *
  68  * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
  69  * depthstencil-split-to-separate-stencil miptree, we'll normally make a
  70  * temporary and recreate the kind of data requested by Mesa core, since we're
  71  * satisfying some glGetTexImage() request or something.
  72  *
  73  * However, occasionally you want to actually map the miptree's current data
  74  * without transcoding back.  This flag to intel_miptree_map() gets you that.
  75  */
  76 #define BRW_MAP_DIRECT_BIT      0x80000000
  77
  78 struct intel_miptree_map {
  79    /** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */
  80    GLbitfield mode;
  81    /** Region of interest for the map. */
  82    int x, y, w, h;
  83    /** Possibly malloced temporary buffer for the mapping. */
  84    void *buffer;
  85    /** Possible pointer to a temporary linear miptree for the mapping. */
  86    struct intel_mipmap_tree *linear_mt;
  87    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  88    void *ptr;
  89    /** Stride of the mapping. */
  90    int stride;
  91
  92    void (*unmap)(struct brw_context *brw,
  93                  struct intel_mipmap_tree *mt,
  94                  struct intel_miptree_map *map,
  95                  unsigned int level,
  96                  unsigned int slice);
  97 };
  98
  99 /**
 100  * Describes the location of each texture image within a miptree.
 101  */
 102 struct intel_mipmap_level
 103 {
 104    /** Offset to this miptree level, used in computing x_offset. */
 105    GLuint level_x;
 106    /** Offset to this miptree level, used in computing y_offset. */
 107    GLuint level_y;
 108
 109    /**
 110     * \brief Is HiZ enabled for this level?
 111     *
 112     * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
 113     * allocated and (2) the HiZ memory for the slices in this level reside at
 114     * \c mt->hiz_mt->level[l].
 115     */
 116    bool has_hiz;
 117
 118    /**
 119     * \brief List of 2D images in this mipmap level.
 120     *
 121     * This may be a list of cube faces, array slices in 2D array texture, or
 122     * layers in a 3D texture. The list's length is \c depth.
 123     */
 124    struct intel_mipmap_slice {
 125       /**
 126        * Mapping information. Persistent for the duration of
 127        * intel_miptree_map/unmap on this slice.
 128        */
 129       struct intel_miptree_map *map;
 130    } *slice;
 131 };
 132
 133 /**
 134  * Miptree aux buffer. These buffers are associated with a miptree, but the
 135  * format is managed by the hardware.
 136  *
 137  * For Gen7+, we always give the hardware the start of the buffer, and let it
 138  * handle all accesses to the buffer. Therefore we don't need the full miptree
 139  * layout structure for this buffer.
 140  */
 141 struct intel_miptree_aux_buffer
 142 {
 143    struct isl_surf surf;
 144
 145    /**
 146     * Buffer object containing the pixel data.
 147     *
 148     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 149     * @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
 150     */
 151    struct brw_bo *bo;
 152
 153    /**
 154     * Offset into bo where the surface starts.
 155     *
 156     * @see intel_mipmap_aux_buffer::bo
 157     *
 158     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 159     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 160     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 161     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 162     */
 163    uint32_t offset;
 164
 165    /**
 166     * Buffer object containing the indirect clear color.
 167     *
 168     * @see create_ccs_buf_for_image
 169     * @see RENDER_SURFACE_STATE.ClearValueAddress
 170     */
 171    struct brw_bo *clear_color_bo;
 172
 173    /**
 174     * Offset into bo where the clear color can be found.
 175     *
 176     * @see create_ccs_buf_for_image
 177     * @see RENDER_SURFACE_STATE.ClearValueAddress
 178     */
 179    uint32_t clear_color_offset;
 180 };
 181
 182 struct intel_mipmap_tree
 183 {
 184    struct isl_surf surf;
 185
 186    /**
 187     * Buffer object containing the surface.
 188     *
 189     * @see intel_mipmap_tree::offset
 190     * @see RENDER_SURFACE_STATE.SurfaceBaseAddress
 191     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 192     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 193     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 194     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 195     */
 196    struct brw_bo *bo;
 197
 198    /**
 199     * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
 200     *
 201     * @see RENDER_SURFACE_STATE.SurfaceType
 202     * @see RENDER_SURFACE_STATE.SurfaceArray
 203     * @see 3DSTATE_DEPTH_BUFFER.SurfaceType
 204     */
 205    GLenum target;
 206
 207    /**
 208     * Generally, this is just the same as the gl_texture_image->TexFormat or
 209     * gl_renderbuffer->Format.
 210     *
 211     * However, for textures and renderbuffers with packed depth/stencil formats
 212     * on hardware where we want or need to use separate stencil, there will be
 213     * two miptrees for storing the data.  If the depthstencil texture or rb is
 214     * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
 215     * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
 216     * MESA_FORMAT_Z24_UNORM_X8_UINT.
 217     *
 218     * @see RENDER_SURFACE_STATE.SurfaceFormat
 219     * @see 3DSTATE_DEPTH_BUFFER.SurfaceFormat
 220     */
 221    mesa_format format;
 222
 223    GLuint first_level;
 224    GLuint last_level;
 225
 226    /** Bytes per pixel (or bytes per block if compressed) */
 227    GLuint cpp;
 228
 229    bool compressed;
 230
 231    /* Includes image offset tables: */
 232    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 233
 234    /**
 235     * Offset into bo where the surface starts.
 236     *
 237     * @see intel_mipmap_tree::bo
 238     *
 239     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 240     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 241     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 242     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 243     */
 244    uint32_t offset;
 245
 246    /**
 247     * \brief The type of auxiliary compression used by this miptree.
 248     *
 249     * This describes the type of auxiliary compression that is intended to be
 250     * used by this miptree.  An aux usage of ISL_AUX_USAGE_NONE means that
 251     * auxiliary compression is permanently disabled.  An aux usage other than
 252     * ISL_AUX_USAGE_NONE does not imply that the auxiliary buffer has actually
 253     * been allocated nor does it imply that auxiliary compression will always
 254     * be enabled for this surface.  For instance, with CCS_D, we may allocate
 255     * the CCS on-the-fly and it may not be used for texturing if the miptree
 256     * is fully resolved.
 257     */
 258    enum isl_aux_usage aux_usage;
 259
 260    /**
 261     * \brief Whether or not this miptree supports fast clears.
 262     */
 263    bool supports_fast_clear;
 264
 265    /**
 266     * \brief Maps miptree slices to their current aux state
 267     *
 268     * This two-dimensional array is indexed as [level][layer] and stores an
 269     * aux state for each slice.
 270     */
 271    enum isl_aux_state **aux_state;
 272
 273    /**
 274     * \brief Stencil miptree for depthstencil textures.
 275     *
 276     * This miptree is used for depthstencil textures and renderbuffers that
 277     * require separate stencil.  It always has the true copy of the stencil
 278     * bits, regardless of mt->format.
 279     *
 280     * \see 3DSTATE_STENCIL_BUFFER
 281     * \see intel_miptree_map_depthstencil()
 282     * \see intel_miptree_unmap_depthstencil()
 283     */
 284    struct intel_mipmap_tree *stencil_mt;
 285
 286    /**
 287     * \brief Shadow miptree for sampling when the main isn't supported by HW.
 288     *
 289     * To workaround various sampler bugs and limitations, we blit the main
 290     * texture into a new texture that can be sampled.
 291     *
 292     * This miptree may be used for:
 293     * - Stencil texturing (pre-BDW) as required by GL_ARB_stencil_texturing.
 294     * - To store the decompressed ETC/EAC data in case we emulate the ETC
 295     *   compression on Gen 7 or earlier GPUs.
 296     */
 297    struct intel_mipmap_tree *shadow_mt;
 298    bool shadow_needs_update;
 299
 300    /**
 301     * \brief CCS, MCS, or HiZ auxiliary buffer.
 302     *
 303     * NULL if no auxiliary buffer is in use for this surface.
 304     *
 305     * For single-sampled color miptrees:
 306     *    This buffer contains the Color Control Surface, which stores the
 307     *    necessary information to implement lossless color compression (CCS_E)
 308     *    and "fast color clear" (CCS_D) behaviour.
 309     *
 310     * For multi-sampled color miptrees:
 311     *    This buffer contains the Multisample Control Surface, which stores the
 312     *    necessary information to implement compressed MSAA
 313     *    (INTEL_MSAA_FORMAT_CMS).
 314     *
 315     * For depth miptrees:
 316     *    This buffer contains the Hierarchical Depth Buffer, which stores the
 317     *    necessary information to implement lossless depth compression and fast
 318     *    depth clear behavior.
 319     *
 320     *    To determine if HiZ is enabled, do not check this pointer. Instead,
 321     *    use intel_miptree_level_has_hiz().
 322     */
 323    struct intel_miptree_aux_buffer *aux_buf;
 324
 325    /**
 326     * Planes 1 and 2 in case this is a planar surface.
 327     */
 328    struct intel_mipmap_tree *plane[2];
 329
 330    /**
 331     * Fast clear color for this surface.  For depth surfaces, the clear value
 332     * is stored as a float32 in the red component.
 333     */
 334    union isl_color_value fast_clear_color;
 335
 336    /**
 337     * For external surfaces, this is DRM format modifier that was used to
 338     * create or import the surface.  For internal surfaces, this will always
 339     * be DRM_FORMAT_MOD_INVALID.
 340     */
 341    uint64_t drm_modifier;
 342
 343    /* These are also refcounted:
 344     */
 345    GLuint refcount;
 346 };
 347
 348 bool
 349 intel_miptree_alloc_aux(struct brw_context *brw,
 350                         struct intel_mipmap_tree *mt);
 351
 352 enum intel_miptree_create_flags {
 353    /** No miptree create flags */
 354    MIPTREE_CREATE_DEFAULT  = 0,
 355
 356    /** Miptree creation should try to allocate a currently busy BO
 357     *
 358     * This may be advantageous if we know the next thing to touch the BO will
 359     * be the GPU because the BO will likely already be in the GTT and maybe
 360     * even in some caches.  If there is a chance that the next thing to touch
 361     * the miptree BO will be the CPU, this flag should not be set.
 362     */
 363    MIPTREE_CREATE_BUSY     = 1 << 0,
 364
 365    /** Create the miptree with auxiliary compression disabled
 366     *
 367     * This does not prevent the caller of intel_miptree_create from coming
 368     * along later and turning auxiliary compression back on but it does mean
 369     * that the miptree will be created with mt->aux_usage == NONE.
 370     */
 371    MIPTREE_CREATE_NO_AUX   = 1 << 1,
 372 };
 373
 374 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
 375                                                GLenum target,
 376                                                mesa_format format,
 377                                                GLuint first_level,
 378                                                GLuint last_level,
 379                                                GLuint width0,
 380                                                GLuint height0,
 381                                                GLuint depth0,
 382                                                GLuint num_samples,
 383                                                enum intel_miptree_create_flags flags);
 384
 385 struct intel_mipmap_tree *
 386 intel_miptree_create_for_bo(struct brw_context *brw,
 387                             struct brw_bo *bo,
 388                             mesa_format format,
 389                             uint32_t offset,
 390                             uint32_t width,
 391                             uint32_t height,
 392                             uint32_t depth,
 393                             int pitch,
 394                             enum isl_tiling tiling,
 395                             enum intel_miptree_create_flags flags);
 396
 397 struct intel_mipmap_tree *
 398 intel_miptree_create_for_dri_image(struct brw_context *brw,
 399                                    __DRIimage *image,
 400                                    GLenum target,
 401                                    mesa_format format,
 402                                    bool allow_internal_aux);
 403
 404 bool
 405 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
 406                                          struct intel_renderbuffer *irb,
 407                                          struct intel_mipmap_tree *singlesample_mt,
 408                                          uint32_t width, uint32_t height,
 409                                          uint32_t pitch);
 410
 411 /**
 412  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 413  * The miptree has the following properties:
 414  *     - The target is GL_TEXTURE_2D.
 415  *     - There are no levels other than the base level 0.
 416  *     - Depth is 1.
 417  */
 418 struct intel_mipmap_tree*
 419 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
 420                                       mesa_format format,
 421                                       uint32_t width,
 422                                       uint32_t height,
 423                                       uint32_t num_samples);
 424
 425 mesa_format
 426 intel_depth_format_for_depthstencil_format(mesa_format format);
 427
 428 mesa_format
 429 intel_lower_compressed_format(struct brw_context *brw, mesa_format format);
 430
 431 unsigned
 432 brw_get_num_logical_layers(const struct intel_mipmap_tree *mt, unsigned level);
 433
 434 /** \brief Assert that the level and layer are valid for the miptree. */
 435 void
 436 intel_miptree_check_level_layer(const struct intel_mipmap_tree *mt,
 437                                 uint32_t level,
 438                                 uint32_t layer);
 439
 440 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 441                              struct intel_mipmap_tree *src);
 442
 443 void intel_miptree_release(struct intel_mipmap_tree **mt);
 444
 445 /* Check if an image fits an existing mipmap tree layout
 446  */
 447 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 448                                     struct gl_texture_image *image);
 449
 450 void
 451 intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt,
 452                                GLuint level, GLuint slice,
 453                                GLuint *x, GLuint *y);
 454
 455 enum isl_surf_dim
 456 get_isl_surf_dim(GLenum target);
 457
 458 enum isl_dim_layout
 459 get_isl_dim_layout(const struct gen_device_info *devinfo,
 460                    enum isl_tiling tiling, GLenum target);
 461
 462 void
 463 intel_get_image_dims(struct gl_texture_image *image,
 464                      int *width, int *height, int *depth);
 465
 466 void
 467 intel_get_tile_masks(enum isl_tiling tiling, uint32_t cpp,
 468                      uint32_t *mask_x, uint32_t *mask_y);
 469
 470 void
 471 intel_get_tile_dims(enum isl_tiling tiling, uint32_t cpp,
 472                     uint32_t *tile_w, uint32_t *tile_h);
 473
 474 uint32_t
 475 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
 476                                GLuint level, GLuint slice,
 477                                uint32_t *tile_x,
 478                                uint32_t *tile_y);
 479 uint32_t
 480 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
 481                                  uint32_t x, uint32_t y);
 482
 483 void
 484 intel_miptree_copy_slice(struct brw_context *brw,
 485                          struct intel_mipmap_tree *src_mt,
 486                          unsigned src_level, unsigned src_layer,
 487                          struct intel_mipmap_tree *dst_mt,
 488                          unsigned dst_level, unsigned dst_layer);
 489
 490 void
 491 intel_miptree_copy_teximage(struct brw_context *brw,
 492                             struct intel_texture_image *intelImage,
 493                             struct intel_mipmap_tree *dst_mt);
 494
 495 /**
 496  * \name Miptree HiZ functions
 497  * \{
 498  *
 499  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 500  * functions on a miptree without HiZ. In that case, each function is a no-op.
 501  */
 502
 503 bool
 504 intel_miptree_level_has_hiz(const struct intel_mipmap_tree *mt, uint32_t level);
 505
 506 /**\}*/
 507
 508 bool
 509 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree *mt,
 510                                    unsigned start_level, unsigned num_levels,
 511                                    unsigned start_layer, unsigned num_layers);
 512
 513
 514 #define INTEL_REMAINING_LAYERS UINT32_MAX
 515 #define INTEL_REMAINING_LEVELS UINT32_MAX
 516
 517 /** Prepare a miptree for access
 518  *
 519  * This function should be called prior to any access to miptree in order to
 520  * perform any needed resolves.
 521  *
 522  * \param[in]  start_level    The first mip level to be accessed
 523  *
 524  * \param[in]  num_levels     The number of miplevels to be accessed or
 525  *                            INTEL_REMAINING_LEVELS to indicate every level
 526  *                            above start_level will be accessed
 527  *
 528  * \param[in]  start_layer    The first array slice or 3D layer to be accessed
 529  *
 530  * \param[in]  num_layers     The number of array slices or 3D layers be
 531  *                            accessed or INTEL_REMAINING_LAYERS to indicate
 532  *                            every layer above start_layer will be accessed
 533  *
 534  * \param[in]  aux_supported  Whether or not the access will support the
 535  *                            miptree's auxiliary compression format;  this
 536  *                            must be false for uncompressed miptrees
 537  *
 538  * \param[in]  fast_clear_supported Whether or not the access will support
 539  *                                  fast clears in the miptree's auxiliary
 540  *                                  compression format
 541  */
 542 void
 543 intel_miptree_prepare_access(struct brw_context *brw,
 544                              struct intel_mipmap_tree *mt,
 545                              uint32_t start_level, uint32_t num_levels,
 546                              uint32_t start_layer, uint32_t num_layers,
 547                              enum isl_aux_usage aux_usage,
 548                              bool fast_clear_supported);
 549
 550 /** Complete a write operation
 551  *
 552  * This function should be called after any operation writes to a miptree.
 553  * This will update the miptree's compression state so that future resolves
 554  * happen correctly.  Technically, this function can be called before the
 555  * write occurs but the caller must ensure that they don't interlace
 556  * intel_miptree_prepare_access and intel_miptree_finish_write calls to
 557  * overlapping layer/level ranges.
 558  *
 559  * \param[in]  level             The mip level that was written
 560  *
 561  * \param[in]  start_layer       The first array slice or 3D layer written
 562  *
 563  * \param[in]  num_layers        The number of array slices or 3D layers
 564  *                               written or INTEL_REMAINING_LAYERS to indicate
 565  *                               every layer above start_layer was written
 566  *
 567  * \param[in]  written_with_aux  Whether or not the write was done with
 568  *                               auxiliary compression enabled
 569  */
 570 void
 571 intel_miptree_finish_write(struct brw_context *brw,
 572                            struct intel_mipmap_tree *mt, uint32_t level,
 573                            uint32_t start_layer, uint32_t num_layers,
 574                            enum isl_aux_usage aux_usage);
 575
 576 /** Get the auxiliary compression state of a miptree slice */
 577 enum isl_aux_state
 578 intel_miptree_get_aux_state(const struct intel_mipmap_tree *mt,
 579                             uint32_t level, uint32_t layer);
 580
 581 /** Set the auxiliary compression state of a miptree slice range
 582  *
 583  * This function directly sets the auxiliary compression state of a slice
 584  * range of a miptree.  It only modifies data structures and does not do any
 585  * resolves.  This should only be called by code which directly performs
 586  * compression operations such as fast clears and resolves.  Most code should
 587  * use intel_miptree_prepare_access or intel_miptree_finish_write.
 588  */
 589 void
 590 intel_miptree_set_aux_state(struct brw_context *brw,
 591                             struct intel_mipmap_tree *mt, uint32_t level,
 592                             uint32_t start_layer, uint32_t num_layers,
 593                             enum isl_aux_state aux_state);
 594
 595 /**
 596  * Prepare a miptree for raw access
 597  *
 598  * This helper prepares the miptree for access that knows nothing about any
 599  * sort of compression whatsoever.  This is useful when mapping the surface or
 600  * using it with the blitter.
 601  */
 602 static inline void
 603 intel_miptree_access_raw(struct brw_context *brw,
 604                          struct intel_mipmap_tree *mt,
 605                          uint32_t level, uint32_t layer,
 606                          bool write)
 607 {
 608    intel_miptree_prepare_access(brw, mt, level, 1, layer, 1,
 609                                 ISL_AUX_USAGE_NONE, false);
 610    if (write)
 611       intel_miptree_finish_write(brw, mt, level, layer, 1, ISL_AUX_USAGE_NONE);
 612 }
 613
 614 enum isl_aux_usage
 615 intel_miptree_texture_aux_usage(struct brw_context *brw,
 616                                 struct intel_mipmap_tree *mt,
 617                                 enum isl_format view_format,
 618                                 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits);
 619 void
 620 intel_miptree_prepare_texture(struct brw_context *brw,
 621                               struct intel_mipmap_tree *mt,
 622                               enum isl_format view_format,
 623                               uint32_t start_level, uint32_t num_levels,
 624                               uint32_t start_layer, uint32_t num_layers,
 625                               enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits);
 626 void
 627 intel_miptree_prepare_image(struct brw_context *brw,
 628                             struct intel_mipmap_tree *mt);
 629
 630 enum isl_aux_usage
 631 intel_miptree_render_aux_usage(struct brw_context *brw,
 632                                struct intel_mipmap_tree *mt,
 633                                enum isl_format render_format,
 634                                bool blend_enabled,
 635                                bool draw_aux_disabled);
 636 void
 637 intel_miptree_prepare_render(struct brw_context *brw,
 638                              struct intel_mipmap_tree *mt, uint32_t level,
 639                              uint32_t start_layer, uint32_t layer_count,
 640                              enum isl_aux_usage aux_usage);
 641 void
 642 intel_miptree_finish_render(struct brw_context *brw,
 643                             struct intel_mipmap_tree *mt, uint32_t level,
 644                             uint32_t start_layer, uint32_t layer_count,
 645                             enum isl_aux_usage aux_usage);
 646 void
 647 intel_miptree_prepare_depth(struct brw_context *brw,
 648                             struct intel_mipmap_tree *mt, uint32_t level,
 649                             uint32_t start_layer, uint32_t layer_count);
 650 void
 651 intel_miptree_finish_depth(struct brw_context *brw,
 652                            struct intel_mipmap_tree *mt, uint32_t level,
 653                            uint32_t start_layer, uint32_t layer_count,
 654                            bool depth_written);
 655 void
 656 intel_miptree_prepare_external(struct brw_context *brw,
 657                                struct intel_mipmap_tree *mt);
 658 void
 659 intel_miptree_finish_external(struct brw_context *brw,
 660                               struct intel_mipmap_tree *mt);
 661
 662 void
 663 intel_miptree_make_shareable(struct brw_context *brw,
 664                              struct intel_mipmap_tree *mt);
 665
 666 void
 667 intel_miptree_updownsample(struct brw_context *brw,
 668                            struct intel_mipmap_tree *src,
 669                            struct intel_mipmap_tree *dst);
 670
 671 void
 672 intel_update_r8stencil(struct brw_context *brw,
 673                        struct intel_mipmap_tree *mt);
 674
 675 void
 676 intel_miptree_map(struct brw_context *brw,
 677                   struct intel_mipmap_tree *mt,
 678                   unsigned int level,
 679                   unsigned int slice,
 680                   unsigned int x,
 681                   unsigned int y,
 682                   unsigned int w,
 683                   unsigned int h,
 684                   GLbitfield mode,
 685                   void **out_ptr,
 686                   ptrdiff_t *out_stride);
 687
 688 void
 689 intel_miptree_unmap(struct brw_context *brw,
 690                     struct intel_mipmap_tree *mt,
 691                     unsigned int level,
 692                     unsigned int slice);
 693
 694 bool
 695 intel_miptree_sample_with_hiz(struct brw_context *brw,
 696                               struct intel_mipmap_tree *mt);
 697
 698 bool
 699 intel_miptree_set_clear_color(struct brw_context *brw,
 700                               struct intel_mipmap_tree *mt,
 701                               union isl_color_value clear_color);
 702
 703 /* Get a clear color suitable for filling out an ISL surface state. */
 704 union isl_color_value
 705 intel_miptree_get_clear_color(const struct gen_device_info *devinfo,
 706                               const struct intel_mipmap_tree *mt,
 707                               enum isl_format view_format, bool sampling,
 708                               struct brw_bo **clear_color_bo,
 709                               uint64_t *clear_color_offset);
 710
 711
 712 static inline int
 713 intel_miptree_blt_pitch(struct intel_mipmap_tree *mt)
 714 {
 715    int pitch = mt->surf.row_pitch_B;
 716    if (mt->surf.tiling != ISL_TILING_LINEAR)
 717       pitch /= 4;
 718    return pitch;
 719 }
 720
 721 isl_memcpy_type
 722 intel_miptree_get_memcpy_type(mesa_format tiledFormat, GLenum format, GLenum type,
 723                               uint32_t *cpp);
 724
 725 static inline bool
 726 intel_miptree_needs_fake_etc(struct brw_context *brw,
 727                              struct intel_mipmap_tree *mt)
 728 {
 729    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 730    bool is_etc = _mesa_is_format_etc2(mt->format) ||
 731                  (mt->format == MESA_FORMAT_ETC1_RGB8);
 732
 733    return devinfo->gen < 8 && !devinfo->is_baytrail && is_etc;
 734 }
 735
 736 static inline bool
 737 intel_miptree_has_etc_shadow(struct brw_context *brw,
 738                              struct intel_mipmap_tree *mt)
 739 {
 740    return intel_miptree_needs_fake_etc(brw, mt) && mt->shadow_mt;
 741 }
 742
 743 void
 744 intel_miptree_update_etc_shadow_levels(struct brw_context *brw,
 745                                        struct intel_mipmap_tree *mt);
 746
 747 #ifdef __cplusplus
 748 }
 749 #endif
 750
 751 #endif