2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 /** @file intel_mipmap_tree.h
28 * This file defines the structure that wraps a BO and describes how the
29 * mipmap levels and slices of a texture are laid out.
31 * The hardware has a fixed layout of a texture depending on parameters such
32 * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
33 * mipmap levels. The individual level/layer slices are each 2D rectangles of
34 * pixels at some x/y offset from the start of the brw_bo.
36 * Original OpenGL allowed texture miplevels to be specified in arbitrary
37 * order, and a texture may change size over time. Thus, each
38 * intel_texture_image has a reference to a miptree that contains the pixel
39 * data sized appropriately for it, which will later be referenced by/copied
40 * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
41 * that there's a single miptree for the complete texture.
44 #ifndef INTEL_MIPMAP_TREE_H
45 #define INTEL_MIPMAP_TREE_H
49 #include "main/mtypes.h"
51 #include "blorp/blorp.h"
52 #include "brw_bufmgr.h"
53 #include <GL/internal/dri_interface.h>
60 struct intel_renderbuffer
;
62 struct intel_texture_image
;
65 * This bit extends the set of GL_MAP_*_BIT enums.
67 * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
68 * depthstencil-split-to-separate-stencil miptree, we'll normally make a
69 * temporary and recreate the kind of data requested by Mesa core, since we're
70 * satisfying some glGetTexImage() request or something.
72 * However, occasionally you want to actually map the miptree's current data
73 * without transcoding back. This flag to intel_miptree_map() gets you that.
75 #define BRW_MAP_DIRECT_BIT 0x80000000
77 struct intel_miptree_map
{
78 /** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */
80 /** Region of interest for the map. */
82 /** Possibly malloced temporary buffer for the mapping. */
84 /** Possible pointer to a temporary linear miptree for the mapping. */
85 struct intel_mipmap_tree
*linear_mt
;
86 /** Pointer to the start of (map_x, map_y) returned by the mapping. */
88 /** Stride of the mapping. */
93 * Describes the location of each texture image within a miptree.
95 struct intel_mipmap_level
97 /** Offset to this miptree level, used in computing x_offset. */
99 /** Offset to this miptree level, used in computing y_offset. */
103 * \brief Number of 2D slices in this miplevel.
105 * The exact semantics of depth varies according to the texture target:
106 * - For GL_TEXTURE_CUBE_MAP, depth is 6.
107 * - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
108 * identical for all miplevels in the texture.
109 * - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
110 * value, like width and height, varies with miplevel.
111 * - For other texture types, depth is 1.
112 * - Additionally, for UMS and CMS miptrees, depth is multiplied by
118 * \brief Is HiZ enabled for this level?
120 * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
121 * allocated and (2) the HiZ memory for the slices in this level reside at
122 * \c mt->hiz_mt->level[l].
127 * \brief List of 2D images in this mipmap level.
129 * This may be a list of cube faces, array slices in 2D array texture, or
130 * layers in a 3D texture. The list's length is \c depth.
132 struct intel_mipmap_slice
{
134 * \name Offset to slice
137 * Hardware formats are so diverse that that there is no unified way to
138 * compute the slice offsets, so we store them in this table.
140 * The (x, y) offset to slice \c s at level \c l relative the miptrees
143 * x = mt->level[l].slice[s].x_offset
144 * y = mt->level[l].slice[s].y_offset
146 * On some hardware generations, we program these offsets into
147 * RENDER_SURFACE_STATE.XOffset and RENDER_SURFACE_STATE.YOffset.
154 * Mapping information. Persistent for the duration of
155 * intel_miptree_map/unmap on this slice.
157 struct intel_miptree_map
*map
;
162 * Enum for keeping track of the different MSAA layouts supported by Gen7.
164 enum intel_msaa_layout
167 * Ordinary surface with no MSAA.
169 INTEL_MSAA_LAYOUT_NONE
,
172 * Interleaved Multisample Surface. The additional samples are
173 * accommodated by scaling up the width and the height of the surface so
174 * that all the samples corresponding to a pixel are located at nearby
177 * @see PRM section "Interleaved Multisampled Surfaces"
179 INTEL_MSAA_LAYOUT_IMS
,
182 * Uncompressed Multisample Surface. The surface is stored as a 2D array,
183 * with array slice n containing all pixel data for sample n.
185 * @see PRM section "Uncompressed Multisampled Surfaces"
187 INTEL_MSAA_LAYOUT_UMS
,
190 * Compressed Multisample Surface. The surface is stored as in
191 * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
192 * (Multisample Control Surface) buffer. Each pixel in the MCS buffer
193 * indicates the mapping from sample number to array slice. This allows
194 * the common case (where all samples constituting a pixel have the same
195 * color value) to be stored efficiently by just using a single array
198 * @see PRM section "Compressed Multisampled Surfaces"
200 INTEL_MSAA_LAYOUT_CMS
,
203 enum miptree_array_layout
{
204 /* Each array slice contains all miplevels packed together.
206 * Gen hardware usually wants multilevel miptrees configured this way.
208 * A 2D Array texture with 2 slices and multiple LODs using
209 * ALL_LOD_IN_EACH_SLICE would look somewhat like this:
226 ALL_LOD_IN_EACH_SLICE
,
228 /* Each LOD contains all slices of that LOD packed together.
230 * In some situations, Gen7+ hardware can use the array_spacing_lod0
231 * feature to save space when the surface only contains LOD 0.
233 * Gen6 uses this for separate stencil and hiz since gen6 does not support
234 * multiple LODs for separate stencil and hiz.
236 * A 2D Array texture with 2 slices and multiple LODs using
237 * ALL_SLICES_AT_EACH_LOD would look somewhat like this:
252 ALL_SLICES_AT_EACH_LOD
,
254 /* On Sandy Bridge, HiZ and stencil buffers work the same as on Ivy Bridge
255 * except that they don't technically support mipmapping. That does not,
256 * however, stop us from doing it. As far as Sandy Bridge hardware is
257 * concerned, HiZ and stencil always operates on a single miplevel 2D
258 * (possibly array) image. The dimensions of that image are NOT minified.
260 * In order to implement HiZ and stencil on Sandy Bridge, we create one
261 * full-sized 2D (possibly array) image for every LOD with every image
262 * aligned to a page boundary. In order to save memory, we pretend that
263 * the width of each miplevel is minified and we place LOD1 and above below
264 * LOD0 but horizontally adjacent to each other. When considered as
265 * full-sized images, LOD1 and above technically overlap. However, since
266 * we only write to part of that image, the hardware will never notice the
269 * This layout looks something like this:
290 enum intel_aux_disable
{
291 INTEL_AUX_DISABLE_NONE
= 0,
292 INTEL_AUX_DISABLE_HIZ
= 1 << 1,
293 INTEL_AUX_DISABLE_MCS
= 1 << 2,
294 INTEL_AUX_DISABLE_CCS
= 1 << 3,
295 INTEL_AUX_DISABLE_ALL
= INTEL_AUX_DISABLE_HIZ
|
296 INTEL_AUX_DISABLE_MCS
|
297 INTEL_AUX_DISABLE_CCS
301 * Miptree aux buffer. These buffers are associated with a miptree, but the
302 * format is managed by the hardware.
304 * For Gen7+, we always give the hardware the start of the buffer, and let it
305 * handle all accesses to the buffer. Therefore we don't need the full miptree
306 * layout structure for this buffer.
308 struct intel_miptree_aux_buffer
311 * Buffer object containing the pixel data.
313 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
314 * @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
319 * Offset into bo where the surface starts.
321 * @see intel_mipmap_aux_buffer::bo
323 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
324 * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
325 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
326 * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
331 * Size of the MCS surface.
333 * This is needed when doing any gtt mapped operations on the buffer (which
334 * will be Y-tiled). It is possible that it will not be the same as bo->size
335 * when the drm allocator rounds up the requested size.
342 * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
343 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
348 * The distance in rows between array slices.
350 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch
351 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
356 * The HiZ buffer requires extra attributes on earlier GENs. This is easily
357 * contained within an intel_mipmap_tree. To make sure we do not abuse this, we
358 * keep the hiz datastructure separate.
360 struct intel_miptree_hiz_buffer
362 struct intel_miptree_aux_buffer aux_base
;
365 * Hiz miptree. Used only by Gen6.
367 struct intel_mipmap_tree
*mt
;
370 struct intel_mipmap_tree
372 struct isl_surf surf
;
375 * Buffer object containing the surface.
377 * @see intel_mipmap_tree::offset
378 * @see RENDER_SURFACE_STATE.SurfaceBaseAddress
379 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
380 * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
381 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
382 * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
389 * @see RENDER_SURFACE_STATE.SurfacePitch
390 * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
391 * @see 3DSTATE_DEPTH_BUFFER.SurfacePitch
392 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
393 * @see 3DSTATE_STENCIL_BUFFER.SurfacePitch
398 * One of the I915_TILING_* flags.
400 * @see RENDER_SURFACE_STATE.TileMode
401 * @see 3DSTATE_DEPTH_BUFFER.TileMode
406 * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
408 * @see RENDER_SURFACE_STATE.SurfaceType
409 * @see RENDER_SURFACE_STATE.SurfaceArray
410 * @see 3DSTATE_DEPTH_BUFFER.SurfaceType
415 * Generally, this is just the same as the gl_texture_image->TexFormat or
416 * gl_renderbuffer->Format.
418 * However, for textures and renderbuffers with packed depth/stencil formats
419 * on hardware where we want or need to use separate stencil, there will be
420 * two miptrees for storing the data. If the depthstencil texture or rb is
421 * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
422 * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
423 * MESA_FORMAT_Z24_UNORM_X8_UINT.
425 * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
426 * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
428 * @see RENDER_SURFACE_STATE.SurfaceFormat
429 * @see 3DSTATE_DEPTH_BUFFER.SurfaceFormat
434 * This variable stores the value of ETC compressed texture format
436 * @see RENDER_SURFACE_STATE.SurfaceFormat
438 mesa_format etc_format
;
441 * @name Surface Alignment
444 * This defines the alignment of the upperleft pixel of each "slice" in the
445 * surface. The alignment is in pixel coordinates relative to the surface's
446 * most upperleft pixel, which is the pixel at (x=0, y=0, layer=0,
449 * The hardware docs do not use the term "slice". We use "slice" to mean
450 * the pixels at a given miplevel and layer. For 2D surfaces, the layer is
451 * the array slice; for 3D surfaces, the layer is the z offset.
453 * In the surface layout equations found in the hardware docs, the
454 * horizontal and vertical surface alignments often appear as variables 'i'
458 /** @see RENDER_SURFACE_STATE.SurfaceHorizontalAlignment */
461 /** @see RENDER_SURFACE_STATE.SurfaceVerticalAlignment */
469 * Level zero image dimensions. These dimensions correspond to the
470 * physical layout of data in memory. Accordingly, they account for the
471 * extra width, height, and or depth that must be allocated in order to
472 * accommodate multisample formats, and they account for the extra factor
473 * of 6 in depth that must be allocated in order to accommodate cubemap
476 GLuint physical_width0
, physical_height0
, physical_depth0
;
478 /** Bytes per pixel (or bytes per block if compressed) */
482 * @see RENDER_SURFACE_STATE.NumberOfMultisamples
483 * @see 3DSTATE_MULTISAMPLE.NumberOfMultisamples
490 * @name Level zero image dimensions
493 * These dimensions correspond to the
494 * logical width, height, and depth of the texture as seen by client code.
495 * Accordingly, they do not account for the extra width, height, and/or
496 * depth that must be allocated in order to accommodate multisample
497 * formats, nor do they account for the extra factor of 6 in depth that
498 * must be allocated in order to accommodate cubemap textures.
502 * @see RENDER_SURFACE_STATE.Width
503 * @see 3DSTATE_DEPTH_BUFFER.Width
505 uint32_t logical_width0
;
508 * @see RENDER_SURFACE_STATE.Height
509 * @see 3DSTATE_DEPTH_BUFFER.Height
511 uint32_t logical_height0
;
514 * @see RENDER_SURFACE_STATE.Depth
515 * @see 3DSTATE_DEPTH_BUFFER.Depth
517 uint32_t logical_depth0
;
521 * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
522 * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
524 enum miptree_array_layout array_layout
;
527 * The distance in between array slices.
529 * The value is the one that is sent in the surface state. The actual
530 * meaning depends on certain criteria. Usually it is simply the number of
531 * uncompressed rows between each slice. However on Gen9+ for compressed
532 * surfaces it is the number of blocks. For 1D array surfaces that have the
533 * mipmap tree stored horizontally it is the number of pixels between each
536 * @see RENDER_SURFACE_STATE.SurfaceQPitch
537 * @see 3DSTATE_DEPTH_BUFFER.SurfaceQPitch
538 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
539 * @see 3DSTATE_STENCIL_BUFFER.SurfaceQPitch
544 * MSAA layout used by this buffer.
546 * @see RENDER_SURFACE_STATE.MultisampledSurfaceStorageFormat
548 enum intel_msaa_layout msaa_layout
;
550 /* Derived from the above:
555 /* Includes image offset tables: */
556 struct intel_mipmap_level level
[MAX_TEXTURE_LEVELS
];
559 * Offset into bo where the surface starts.
561 * @see intel_mipmap_tree::bo
563 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
564 * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
565 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
566 * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
571 * \brief HiZ aux buffer
573 * To allocate the hiz buffer, use intel_miptree_alloc_hiz().
575 * To determine if hiz is enabled, do not check this pointer. Instead, use
576 * intel_miptree_slice_has_hiz().
578 struct intel_miptree_hiz_buffer
*hiz_buf
;
581 * \brief Maps miptree slices to their current aux state
583 * This two-dimensional array is indexed as [level][layer] and stores an
584 * aux state for each slice.
586 enum isl_aux_state
**aux_state
;
589 * \brief Stencil miptree for depthstencil textures.
591 * This miptree is used for depthstencil textures and renderbuffers that
592 * require separate stencil. It always has the true copy of the stencil
593 * bits, regardless of mt->format.
595 * \see 3DSTATE_STENCIL_BUFFER
596 * \see intel_miptree_map_depthstencil()
597 * \see intel_miptree_unmap_depthstencil()
599 struct intel_mipmap_tree
*stencil_mt
;
602 * \brief Stencil texturing miptree for sampling from a stencil texture
604 * Some hardware doesn't support sampling from the stencil texture as
605 * required by the GL_ARB_stencil_texturing extenion. To workaround this we
606 * blit the texture into a new texture that can be sampled.
608 * \see intel_update_r8stencil()
610 struct intel_mipmap_tree
*r8stencil_mt
;
611 bool r8stencil_needs_update
;
614 * \brief MCS auxiliary buffer.
616 * This buffer contains the "multisample control surface", which stores
617 * the necessary information to implement compressed MSAA
618 * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
620 * NULL if no MCS buffer is in use for this surface.
622 struct intel_miptree_aux_buffer
*mcs_buf
;
625 * Planes 1 and 2 in case this is a planar surface.
627 struct intel_mipmap_tree
*plane
[2];
630 * Fast clear color for this surface. For depth surfaces, the clear value
631 * is stored as a float32 in the red component.
633 union isl_color_value fast_clear_color
;
636 * Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS
637 * buffer. This is useful for sharing the miptree bo with an external client
638 * that doesn't understand auxiliary buffers.
640 enum intel_aux_disable aux_disable
;
643 * Tells if the underlying buffer is to be also consumed by entities other
644 * than the driver. This allows logic to turn off features such as lossless
645 * compression which is not currently understood by client applications.
649 /* These are also refcounted:
655 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
656 const struct intel_mipmap_tree
*mt
);
659 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
663 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
664 const struct intel_mipmap_tree
*mt
);
667 intel_miptree_supports_lossless_compressed(struct brw_context
*brw
,
668 const struct intel_mipmap_tree
*mt
);
671 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
672 struct intel_mipmap_tree
*mt
,
673 bool is_lossless_compressed
);
676 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
= 1 << 0,
677 MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
= 1 << 1,
678 MIPTREE_LAYOUT_FOR_BO
= 1 << 2,
679 MIPTREE_LAYOUT_DISABLE_AUX
= 1 << 3,
680 MIPTREE_LAYOUT_FORCE_HALIGN16
= 1 << 4,
682 MIPTREE_LAYOUT_TILING_Y
= 1 << 5,
683 MIPTREE_LAYOUT_TILING_NONE
= 1 << 6,
684 MIPTREE_LAYOUT_TILING_ANY
= MIPTREE_LAYOUT_TILING_Y
|
685 MIPTREE_LAYOUT_TILING_NONE
,
687 MIPTREE_LAYOUT_FOR_SCANOUT
= 1 << 7,
690 struct intel_mipmap_tree
*intel_miptree_create(struct brw_context
*brw
,
701 struct intel_mipmap_tree
*
702 intel_miptree_create_for_bo(struct brw_context
*brw
,
710 uint32_t layout_flags
);
713 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
714 struct intel_renderbuffer
*irb
,
716 uint32_t width
, uint32_t height
,
720 * Create a miptree appropriate as the storage for a non-texture renderbuffer.
721 * The miptree has the following properties:
722 * - The target is GL_TEXTURE_2D.
723 * - There are no levels other than the base level 0.
726 struct intel_mipmap_tree
*
727 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
731 uint32_t num_samples
);
734 intel_depth_format_for_depthstencil_format(mesa_format format
);
737 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
);
739 /** \brief Assert that the level and layer are valid for the miptree. */
741 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
749 assert(level
>= mt
->first_level
);
750 assert(level
<= mt
->last_level
);
751 assert(layer
< mt
->level
[level
].depth
);
754 void intel_miptree_reference(struct intel_mipmap_tree
**dst
,
755 struct intel_mipmap_tree
*src
);
757 void intel_miptree_release(struct intel_mipmap_tree
**mt
);
759 /* Check if an image fits an existing mipmap tree layout
761 bool intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
762 struct gl_texture_image
*image
);
765 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
766 GLuint level
, GLuint slice
,
767 GLuint
*x
, GLuint
*y
);
770 get_isl_surf_dim(GLenum target
);
773 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
774 GLenum target
, enum miptree_array_layout array_layout
);
777 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
);
780 intel_miptree_get_isl_surf(struct brw_context
*brw
,
781 const struct intel_mipmap_tree
*mt
,
782 struct isl_surf
*surf
);
784 intel_miptree_get_aux_isl_surf(struct brw_context
*brw
,
785 const struct intel_mipmap_tree
*mt
,
786 struct isl_surf
*surf
,
787 enum isl_aux_usage
*usage
);
790 intel_get_image_dims(struct gl_texture_image
*image
,
791 int *width
, int *height
, int *depth
);
794 intel_get_tile_masks(uint32_t tiling
, uint32_t cpp
,
795 uint32_t *mask_x
, uint32_t *mask_y
);
798 intel_get_tile_dims(uint32_t tiling
, uint32_t cpp
,
799 uint32_t *tile_w
, uint32_t *tile_h
);
802 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
803 GLuint level
, GLuint slice
,
807 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
808 uint32_t x
, uint32_t y
);
810 void intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
812 GLuint x
, GLuint y
, GLuint d
);
814 void intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
816 GLuint img
, GLuint x
, GLuint y
);
819 intel_miptree_copy_slice(struct brw_context
*brw
,
820 struct intel_mipmap_tree
*src_mt
,
821 unsigned src_level
, unsigned src_layer
,
822 struct intel_mipmap_tree
*dst_mt
,
823 unsigned dst_level
, unsigned dst_layer
);
826 intel_miptree_copy_teximage(struct brw_context
*brw
,
827 struct intel_texture_image
*intelImage
,
828 struct intel_mipmap_tree
*dst_mt
, bool invalidate
);
831 * \name Miptree HiZ functions
834 * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
835 * functions on a miptree without HiZ. In that case, each function is a no-op.
839 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
840 struct intel_mipmap_tree
*mt
);
843 * \brief Allocate the miptree's embedded HiZ miptree.
844 * \see intel_mipmap_tree:hiz_mt
845 * \return false if allocation failed
848 intel_miptree_alloc_hiz(struct brw_context
*brw
,
849 struct intel_mipmap_tree
*mt
);
852 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
);
857 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
858 unsigned start_level
, unsigned num_levels
,
859 unsigned start_layer
, unsigned num_layers
);
862 #define INTEL_REMAINING_LAYERS UINT32_MAX
863 #define INTEL_REMAINING_LEVELS UINT32_MAX
865 /** Prepare a miptree for access
867 * This function should be called prior to any access to miptree in order to
868 * perform any needed resolves.
870 * \param[in] start_level The first mip level to be accessed
872 * \param[in] num_levels The number of miplevels to be accessed or
873 * INTEL_REMAINING_LEVELS to indicate every level
874 * above start_level will be accessed
876 * \param[in] start_layer The first array slice or 3D layer to be accessed
878 * \param[in] num_layers The number of array slices or 3D layers be
879 * accessed or INTEL_REMAINING_LAYERS to indicate
880 * every layer above start_layer will be accessed
882 * \param[in] aux_supported Whether or not the access will support the
883 * miptree's auxiliary compression format; this
884 * must be false for uncompressed miptrees
886 * \param[in] fast_clear_supported Whether or not the access will support
887 * fast clears in the miptree's auxiliary
891 intel_miptree_prepare_access(struct brw_context
*brw
,
892 struct intel_mipmap_tree
*mt
,
893 uint32_t start_level
, uint32_t num_levels
,
894 uint32_t start_layer
, uint32_t num_layers
,
895 bool aux_supported
, bool fast_clear_supported
);
897 /** Complete a write operation
899 * This function should be called after any operation writes to a miptree.
900 * This will update the miptree's compression state so that future resolves
901 * happen correctly. Technically, this function can be called before the
902 * write occurs but the caller must ensure that they don't interlace
903 * intel_miptree_prepare_access and intel_miptree_finish_write calls to
904 * overlapping layer/level ranges.
906 * \param[in] level The mip level that was written
908 * \param[in] start_layer The first array slice or 3D layer written
910 * \param[in] num_layers The number of array slices or 3D layers
911 * written or INTEL_REMAINING_LAYERS to indicate
912 * every layer above start_layer was written
914 * \param[in] written_with_aux Whether or not the write was done with
915 * auxiliary compression enabled
918 intel_miptree_finish_write(struct brw_context
*brw
,
919 struct intel_mipmap_tree
*mt
, uint32_t level
,
920 uint32_t start_layer
, uint32_t num_layers
,
921 bool written_with_aux
);
923 /** Get the auxiliary compression state of a miptree slice */
925 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
926 uint32_t level
, uint32_t layer
);
928 /** Set the auxiliary compression state of a miptree slice range
930 * This function directly sets the auxiliary compression state of a slice
931 * range of a miptree. It only modifies data structures and does not do any
932 * resolves. This should only be called by code which directly performs
933 * compression operations such as fast clears and resolves. Most code should
934 * use intel_miptree_prepare_access or intel_miptree_finish_write.
937 intel_miptree_set_aux_state(struct brw_context
*brw
,
938 struct intel_mipmap_tree
*mt
, uint32_t level
,
939 uint32_t start_layer
, uint32_t num_layers
,
940 enum isl_aux_state aux_state
);
943 * Prepare a miptree for raw access
945 * This helper prepares the miptree for access that knows nothing about any
946 * sort of compression whatsoever. This is useful when mapping the surface or
947 * using it with the blitter.
950 intel_miptree_access_raw(struct brw_context
*brw
,
951 struct intel_mipmap_tree
*mt
,
952 uint32_t level
, uint32_t layer
,
955 intel_miptree_prepare_access(brw
, mt
, level
, 1, layer
, 1, false, false);
957 intel_miptree_finish_write(brw
, mt
, level
, layer
, 1, false);
961 intel_miptree_prepare_texture(struct brw_context
*brw
,
962 struct intel_mipmap_tree
*mt
,
963 mesa_format view_format
,
964 bool *aux_supported_out
);
966 intel_miptree_prepare_image(struct brw_context
*brw
,
967 struct intel_mipmap_tree
*mt
);
969 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
970 struct intel_mipmap_tree
*mt
, uint32_t level
,
971 uint32_t start_layer
, uint32_t num_layers
);
973 intel_miptree_prepare_render(struct brw_context
*brw
,
974 struct intel_mipmap_tree
*mt
, uint32_t level
,
975 uint32_t start_layer
, uint32_t layer_count
,
978 intel_miptree_finish_render(struct brw_context
*brw
,
979 struct intel_mipmap_tree
*mt
, uint32_t level
,
980 uint32_t start_layer
, uint32_t layer_count
);
982 intel_miptree_prepare_depth(struct brw_context
*brw
,
983 struct intel_mipmap_tree
*mt
, uint32_t level
,
984 uint32_t start_layer
, uint32_t layer_count
);
986 intel_miptree_finish_depth(struct brw_context
*brw
,
987 struct intel_mipmap_tree
*mt
, uint32_t level
,
988 uint32_t start_layer
, uint32_t layer_count
,
992 intel_miptree_make_shareable(struct brw_context
*brw
,
993 struct intel_mipmap_tree
*mt
);
996 intel_miptree_updownsample(struct brw_context
*brw
,
997 struct intel_mipmap_tree
*src
,
998 struct intel_mipmap_tree
*dst
);
1001 intel_update_r8stencil(struct brw_context
*brw
,
1002 struct intel_mipmap_tree
*mt
);
1005 * Horizontal distance from one slice to the next in the two-dimensional
1009 brw_miptree_get_horizontal_slice_pitch(const struct brw_context
*brw
,
1010 const struct intel_mipmap_tree
*mt
,
1014 * Vertical distance from one slice to the next in the two-dimensional miptree
1018 brw_miptree_get_vertical_slice_pitch(const struct brw_context
*brw
,
1019 const struct intel_mipmap_tree
*mt
,
1023 brw_miptree_layout(struct brw_context
*brw
,
1024 struct intel_mipmap_tree
*mt
,
1025 uint32_t layout_flags
);
1028 intel_miptree_map(struct brw_context
*brw
,
1029 struct intel_mipmap_tree
*mt
,
1038 ptrdiff_t *out_stride
);
1041 intel_miptree_unmap(struct brw_context
*brw
,
1042 struct intel_mipmap_tree
*mt
,
1044 unsigned int slice
);
1047 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1048 struct intel_mipmap_tree
*mt
);