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26 /** @file intel_mipmap_tree.h
28 * This file defines the structure that wraps a BO and describes how the
29 * mipmap levels and slices of a texture are laid out.
31 * The hardware has a fixed layout of a texture depending on parameters such
32 * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
33 * mipmap levels. The individual level/layer slices are each 2D rectangles of
34 * pixels at some x/y offset from the start of the drm_intel_bo.
36 * Original OpenGL allowed texture miplevels to be specified in arbitrary
37 * order, and a texture may change size over time. Thus, each
38 * intel_texture_image has a reference to a miptree that contains the pixel
39 * data sized appropriately for it, which will later be referenced by/copied
40 * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
41 * that there's a single miptree for the complete texture.
44 #ifndef INTEL_MIPMAP_TREE_H
45 #define INTEL_MIPMAP_TREE_H
49 #include "main/mtypes.h"
50 #include "intel_bufmgr.h"
51 #include "intel_resolve_map.h"
52 #include <GL/internal/dri_interface.h>
59 struct intel_renderbuffer
;
61 struct intel_resolve_map
;
62 struct intel_texture_image
;
65 * This bit extends the set of GL_MAP_*_BIT enums.
67 * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
68 * depthstencil-split-to-separate-stencil miptree, we'll normally make a
69 * temporary and recreate the kind of data requested by Mesa core, since we're
70 * satisfying some glGetTexImage() request or something.
72 * However, occasionally you want to actually map the miptree's current data
73 * without transcoding back. This flag to intel_miptree_map() gets you that.
75 #define BRW_MAP_DIRECT_BIT 0x80000000
77 struct intel_miptree_map
{
78 /** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */
80 /** Region of interest for the map. */
82 /** Possibly malloced temporary buffer for the mapping. */
84 /** Possible pointer to a temporary linear miptree for the mapping. */
85 struct intel_mipmap_tree
*linear_mt
;
86 /** Pointer to the start of (map_x, map_y) returned by the mapping. */
88 /** Stride of the mapping. */
93 * Describes the location of each texture image within a miptree.
95 struct intel_mipmap_level
97 /** Offset to this miptree level, used in computing x_offset. */
99 /** Offset to this miptree level, used in computing y_offset. */
103 * \brief Number of 2D slices in this miplevel.
105 * The exact semantics of depth varies according to the texture target:
106 * - For GL_TEXTURE_CUBE_MAP, depth is 6.
107 * - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
108 * identical for all miplevels in the texture.
109 * - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
110 * value, like width and height, varies with miplevel.
111 * - For other texture types, depth is 1.
112 * - Additionally, for UMS and CMS miptrees, depth is multiplied by
118 * \brief Is HiZ enabled for this level?
120 * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
121 * allocated and (2) the HiZ memory for the slices in this level reside at
122 * \c mt->hiz_mt->level[l].
127 * \brief List of 2D images in this mipmap level.
129 * This may be a list of cube faces, array slices in 2D array texture, or
130 * layers in a 3D texture. The list's length is \c depth.
132 struct intel_mipmap_slice
{
134 * \name Offset to slice
137 * Hardware formats are so diverse that that there is no unified way to
138 * compute the slice offsets, so we store them in this table.
140 * The (x, y) offset to slice \c s at level \c l relative the miptrees
143 * x = mt->level[l].slice[s].x_offset
144 * y = mt->level[l].slice[s].y_offset
146 * On some hardware generations, we program these offsets into
147 * RENDER_SURFACE_STATE.XOffset and RENDER_SURFACE_STATE.YOffset.
154 * Mapping information. Persistent for the duration of
155 * intel_miptree_map/unmap on this slice.
157 struct intel_miptree_map
*map
;
162 * Enum for keeping track of the different MSAA layouts supported by Gen7.
164 enum intel_msaa_layout
167 * Ordinary surface with no MSAA.
169 INTEL_MSAA_LAYOUT_NONE
,
172 * Interleaved Multisample Surface. The additional samples are
173 * accommodated by scaling up the width and the height of the surface so
174 * that all the samples corresponding to a pixel are located at nearby
177 * @see PRM section "Interleaved Multisampled Surfaces"
179 INTEL_MSAA_LAYOUT_IMS
,
182 * Uncompressed Multisample Surface. The surface is stored as a 2D array,
183 * with array slice n containing all pixel data for sample n.
185 * @see PRM section "Uncompressed Multisampled Surfaces"
187 INTEL_MSAA_LAYOUT_UMS
,
190 * Compressed Multisample Surface. The surface is stored as in
191 * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
192 * (Multisample Control Surface) buffer. Each pixel in the MCS buffer
193 * indicates the mapping from sample number to array slice. This allows
194 * the common case (where all samples constituting a pixel have the same
195 * color value) to be stored efficiently by just using a single array
198 * @see PRM section "Compressed Multisampled Surfaces"
200 INTEL_MSAA_LAYOUT_CMS
,
205 * Enum for keeping track of the fast clear state of a buffer associated with
208 * Fast clear works by deferring the memory writes that would be used to clear
209 * the buffer, so that instead of performing them at the time of the clear
210 * operation, the hardware automatically performs them at the time that the
211 * buffer is later accessed for rendering. The MCS buffer keeps track of
212 * which regions of the buffer still have pending clear writes.
214 * This enum keeps track of the driver's knowledge of pending fast clears in
217 * MCS buffers only exist on Gen7+.
219 enum intel_fast_clear_state
222 * There is no MCS buffer for this miptree, and one should never be
225 INTEL_FAST_CLEAR_STATE_NO_MCS
,
228 * No deferred clears are pending for this miptree, and the contents of the
229 * color buffer are entirely correct. An MCS buffer may or may not exist
230 * for this miptree. If it does exist, it is entirely in the "no deferred
231 * clears pending" state. If it does not exist, it will be created the
232 * first time a fast color clear is executed.
234 * In this state, the color buffer can be used for purposes other than
235 * rendering without needing a render target resolve.
237 * Since there is no such thing as a "fast color clear resolve" for MSAA
238 * buffers, an MSAA buffer will never be in this state.
240 INTEL_FAST_CLEAR_STATE_RESOLVED
,
243 * An MCS buffer exists for this miptree, and deferred clears are pending
244 * for some regions of the color buffer, as indicated by the MCS buffer.
245 * The contents of the color buffer are only correct for the regions where
246 * the MCS buffer doesn't indicate a deferred clear.
248 * If a single-sample buffer is in this state, a render target resolve must
249 * be performed before it can be used for purposes other than rendering.
251 INTEL_FAST_CLEAR_STATE_UNRESOLVED
,
254 * An MCS buffer exists for this miptree, and deferred clears are pending
255 * for the entire color buffer, and the contents of the MCS buffer reflect
256 * this. The contents of the color buffer are undefined.
258 * If a single-sample buffer is in this state, a render target resolve must
259 * be performed before it can be used for purposes other than rendering.
261 * If the client attempts to clear a buffer which is already in this state,
262 * the clear can be safely skipped, since the buffer is already clear.
264 INTEL_FAST_CLEAR_STATE_CLEAR
,
267 enum miptree_array_layout
{
268 /* Each array slice contains all miplevels packed together.
270 * Gen hardware usually wants multilevel miptrees configured this way.
272 * A 2D Array texture with 2 slices and multiple LODs using
273 * ALL_LOD_IN_EACH_SLICE would look somewhat like this:
290 ALL_LOD_IN_EACH_SLICE
,
292 /* Each LOD contains all slices of that LOD packed together.
294 * In some situations, Gen7+ hardware can use the array_spacing_lod0
295 * feature to save space when the surface only contains LOD 0.
297 * Gen6 uses this for separate stencil and hiz since gen6 does not support
298 * multiple LODs for separate stencil and hiz.
300 * A 2D Array texture with 2 slices and multiple LODs using
301 * ALL_SLICES_AT_EACH_LOD would look somewhat like this:
316 ALL_SLICES_AT_EACH_LOD
,
320 * Miptree aux buffer. These buffers are associated with a miptree, but the
321 * format is managed by the hardware.
323 * For Gen7+, we always give the hardware the start of the buffer, and let it
324 * handle all accesses to the buffer. Therefore we don't need the full miptree
325 * layout structure for this buffer.
327 * For Gen6, we need a hiz miptree structure for this buffer so we can program
328 * offsets to slices & miplevels.
330 struct intel_miptree_aux_buffer
333 * Buffer object containing the pixel data.
335 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
336 * @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
343 * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
344 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
349 * The distance in rows between array slices.
351 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch
352 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
357 * Hiz miptree. Used only by Gen6.
359 struct intel_mipmap_tree
*mt
;
362 /* Tile resource modes */
363 enum intel_miptree_tr_mode
{
364 INTEL_MIPTREE_TRMODE_NONE
,
365 INTEL_MIPTREE_TRMODE_YF
,
366 INTEL_MIPTREE_TRMODE_YS
369 struct intel_mipmap_tree
372 * Buffer object containing the surface.
374 * @see intel_mipmap_tree::offset
375 * @see RENDER_SURFACE_STATE.SurfaceBaseAddress
376 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
377 * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
378 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
379 * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
386 * @see RENDER_SURFACE_STATE.SurfacePitch
387 * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
388 * @see 3DSTATE_DEPTH_BUFFER.SurfacePitch
389 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
390 * @see 3DSTATE_STENCIL_BUFFER.SurfacePitch
395 * One of the I915_TILING_* flags.
397 * @see RENDER_SURFACE_STATE.TileMode
398 * @see 3DSTATE_DEPTH_BUFFER.TileMode
403 * @see RENDER_SURFACE_STATE.TiledResourceMode
404 * @see 3DSTATE_DEPTH_BUFFER.TiledResourceMode
406 enum intel_miptree_tr_mode tr_mode
;
409 * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
411 * @see RENDER_SURFACE_STATE.SurfaceType
412 * @see RENDER_SURFACE_STATE.SurfaceArray
413 * @see 3DSTATE_DEPTH_BUFFER.SurfaceType
418 * Generally, this is just the same as the gl_texture_image->TexFormat or
419 * gl_renderbuffer->Format.
421 * However, for textures and renderbuffers with packed depth/stencil formats
422 * on hardware where we want or need to use separate stencil, there will be
423 * two miptrees for storing the data. If the depthstencil texture or rb is
424 * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
425 * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
426 * MESA_FORMAT_Z24_UNORM_X8_UINT.
428 * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
429 * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
431 * @see RENDER_SURFACE_STATE.SurfaceFormat
432 * @see 3DSTATE_DEPTH_BUFFER.SurfaceFormat
437 * This variable stores the value of ETC compressed texture format
439 * @see RENDER_SURFACE_STATE.SurfaceFormat
441 mesa_format etc_format
;
444 * @name Surface Alignment
447 * This defines the alignment of the upperleft pixel of each "slice" in the
448 * surface. The alignment is in pixel coordinates relative to the surface's
449 * most upperleft pixel, which is the pixel at (x=0, y=0, layer=0,
452 * The hardware docs do not use the term "slice". We use "slice" to mean
453 * the pixels at a given miplevel and layer. For 2D surfaces, the layer is
454 * the array slice; for 3D surfaces, the layer is the z offset.
456 * In the surface layout equations found in the hardware docs, the
457 * horizontal and vertical surface alignments often appear as variables 'i'
461 /** @see RENDER_SURFACE_STATE.SurfaceHorizontalAlignment */
464 /** @see RENDER_SURFACE_STATE.SurfaceVerticalAlignment */
472 * Level zero image dimensions. These dimensions correspond to the
473 * physical layout of data in memory. Accordingly, they account for the
474 * extra width, height, and or depth that must be allocated in order to
475 * accommodate multisample formats, and they account for the extra factor
476 * of 6 in depth that must be allocated in order to accommodate cubemap
479 GLuint physical_width0
, physical_height0
, physical_depth0
;
481 /** Bytes per pixel (or bytes per block if compressed) */
485 * @see RENDER_SURFACE_STATE.NumberOfMultisamples
486 * @see 3DSTATE_MULTISAMPLE.NumberOfMultisamples
493 * @name Level zero image dimensions
496 * These dimensions correspond to the
497 * logical width, height, and depth of the texture as seen by client code.
498 * Accordingly, they do not account for the extra width, height, and/or
499 * depth that must be allocated in order to accommodate multisample
500 * formats, nor do they account for the extra factor of 6 in depth that
501 * must be allocated in order to accommodate cubemap textures.
505 * @see RENDER_SURFACE_STATE.Width
506 * @see 3DSTATE_DEPTH_BUFFER.Width
508 uint32_t logical_width0
;
511 * @see RENDER_SURFACE_STATE.Height
512 * @see 3DSTATE_DEPTH_BUFFER.Height
514 uint32_t logical_height0
;
517 * @see RENDER_SURFACE_STATE.Depth
518 * @see 3DSTATE_DEPTH_BUFFER.Depth
520 uint32_t logical_depth0
;
524 * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
525 * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
527 enum miptree_array_layout array_layout
;
530 * The distance in between array slices.
532 * The value is the one that is sent in the surface state. The actual
533 * meaning depends on certain criteria. Usually it is simply the number of
534 * uncompressed rows between each slice. However on Gen9+ for compressed
535 * surfaces it is the number of blocks. For 1D array surfaces that have the
536 * mipmap tree stored horizontally it is the number of pixels between each
539 * @see RENDER_SURFACE_STATE.SurfaceQPitch
540 * @see 3DSTATE_DEPTH_BUFFER.SurfaceQPitch
541 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
542 * @see 3DSTATE_STENCIL_BUFFER.SurfaceQPitch
547 * MSAA layout used by this buffer.
549 * @see RENDER_SURFACE_STATE.MultisampledSurfaceStorageFormat
551 enum intel_msaa_layout msaa_layout
;
553 /* Derived from the above:
559 * The depth value used during the most recent fast depth clear performed
560 * on the surface. This field is invalid only if surface has never
561 * underwent a fast depth clear.
563 * @see 3DSTATE_CLEAR_PARAMS.DepthClearValue
565 uint32_t depth_clear_value
;
567 /* Includes image offset tables: */
568 struct intel_mipmap_level level
[MAX_TEXTURE_LEVELS
];
571 * Offset into bo where the surface starts.
573 * @see intel_mipmap_tree::bo
575 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
576 * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
577 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
578 * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
583 * \brief HiZ aux buffer
585 * To allocate the hiz buffer, use intel_miptree_alloc_hiz().
587 * To determine if hiz is enabled, do not check this pointer. Instead, use
588 * intel_miptree_slice_has_hiz().
590 struct intel_miptree_aux_buffer
*hiz_buf
;
593 * \brief Map of miptree slices to needed resolves.
595 * This is used only when the miptree has a child HiZ miptree.
597 * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
598 * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
599 * mt->hiz_mt->hiz_map, is unused.
601 struct exec_list hiz_map
; /* List of intel_resolve_map. */
604 * \brief Stencil miptree for depthstencil textures.
606 * This miptree is used for depthstencil textures and renderbuffers that
607 * require separate stencil. It always has the true copy of the stencil
608 * bits, regardless of mt->format.
610 * \see 3DSTATE_STENCIL_BUFFER
611 * \see intel_miptree_map_depthstencil()
612 * \see intel_miptree_unmap_depthstencil()
614 struct intel_mipmap_tree
*stencil_mt
;
617 * \brief MCS miptree.
619 * This miptree contains the "multisample control surface", which stores
620 * the necessary information to implement compressed MSAA
621 * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
623 * NULL if no MCS miptree is in use for this surface.
625 struct intel_mipmap_tree
*mcs_mt
;
628 * Fast clear state for this buffer.
630 enum intel_fast_clear_state fast_clear_state
;
633 * The SURFACE_STATE bits associated with the last fast color clear to this
634 * color mipmap tree, if any.
636 * Prior to GEN9 there is a single bit for RGBA clear values which gives you
637 * the option of 2^4 clear colors. Each bit determines if the color channel
638 * is fully saturated or unsaturated (Cherryview does add a 32b value per
639 * channel, but it is globally applied instead of being part of the render
640 * surface state). Starting with GEN9, the surface state accepts a 32b value
641 * for each color channel.
643 * @see RENDER_SURFACE_STATE.RedClearColor
644 * @see RENDER_SURFACE_STATE.GreenClearColor
645 * @see RENDER_SURFACE_STATE.BlueClearColor
646 * @see RENDER_SURFACE_STATE.AlphaClearColor
649 uint32_t fast_clear_color_value
;
650 union gl_color_union gen9_fast_clear_color
;
654 * Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS
655 * buffer. This is useful for sharing the miptree bo with an external client
656 * that doesn't understand auxiliary buffers.
658 bool disable_aux_buffers
;
660 /* These are also refcounted:
666 intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree
*mt
,
667 unsigned *width_px
, unsigned *height
);
670 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
671 struct intel_mipmap_tree
*mt
);
674 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
= 1 << 0,
675 MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
= 1 << 1,
676 MIPTREE_LAYOUT_FOR_BO
= 1 << 2,
677 MIPTREE_LAYOUT_DISABLE_AUX
= 1 << 3,
678 MIPTREE_LAYOUT_FORCE_HALIGN16
= 1 << 4,
680 MIPTREE_LAYOUT_TILING_Y
= 1 << 5,
681 MIPTREE_LAYOUT_TILING_NONE
= 1 << 6,
682 MIPTREE_LAYOUT_TILING_ANY
= MIPTREE_LAYOUT_TILING_Y
|
683 MIPTREE_LAYOUT_TILING_NONE
,
686 struct intel_mipmap_tree
*intel_miptree_create(struct brw_context
*brw
,
697 struct intel_mipmap_tree
*
698 intel_miptree_create_for_bo(struct brw_context
*brw
,
706 uint32_t layout_flags
);
709 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
710 struct intel_renderbuffer
*irb
,
712 uint32_t width
, uint32_t height
,
716 * Create a miptree appropriate as the storage for a non-texture renderbuffer.
717 * The miptree has the following properties:
718 * - The target is GL_TEXTURE_2D.
719 * - There are no levels other than the base level 0.
722 struct intel_mipmap_tree
*
723 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
727 uint32_t num_samples
);
730 intel_depth_format_for_depthstencil_format(mesa_format format
);
733 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
);
735 /** \brief Assert that the level and layer are valid for the miptree. */
737 intel_miptree_check_level_layer(struct intel_mipmap_tree
*mt
,
745 assert(level
>= mt
->first_level
);
746 assert(level
<= mt
->last_level
);
747 assert(layer
< mt
->level
[level
].depth
);
750 void intel_miptree_reference(struct intel_mipmap_tree
**dst
,
751 struct intel_mipmap_tree
*src
);
753 void intel_miptree_release(struct intel_mipmap_tree
**mt
);
755 /* Check if an image fits an existing mipmap tree layout
757 bool intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
758 struct gl_texture_image
*image
);
761 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
762 GLuint level
, GLuint slice
,
763 GLuint
*x
, GLuint
*y
);
766 intel_get_image_dims(struct gl_texture_image
*image
,
767 int *width
, int *height
, int *depth
);
770 intel_get_tile_masks(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
771 bool map_stencil_as_y_tiled
,
772 uint32_t *mask_x
, uint32_t *mask_y
);
775 intel_get_tile_dims(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
776 uint32_t *tile_w
, uint32_t *tile_h
);
779 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
780 GLuint level
, GLuint slice
,
784 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
785 uint32_t x
, uint32_t y
,
786 bool map_stencil_as_y_tiled
);
788 void intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
790 GLuint x
, GLuint y
, GLuint d
);
792 void intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
794 GLuint img
, GLuint x
, GLuint y
);
797 intel_miptree_copy_teximage(struct brw_context
*brw
,
798 struct intel_texture_image
*intelImage
,
799 struct intel_mipmap_tree
*dst_mt
, bool invalidate
);
802 * \name Miptree HiZ functions
805 * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
806 * functions on a miptree without HiZ. In that case, each function is a no-op.
810 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
811 struct intel_mipmap_tree
*mt
);
814 * \brief Allocate the miptree's embedded HiZ miptree.
815 * \see intel_mipmap_tree:hiz_mt
816 * \return false if allocation failed
819 intel_miptree_alloc_hiz(struct brw_context
*brw
,
820 struct intel_mipmap_tree
*mt
);
823 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
);
826 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
830 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
835 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
839 * \return false if no resolve was needed
842 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
843 struct intel_mipmap_tree
*mt
,
848 * \return false if no resolve was needed
851 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
852 struct intel_mipmap_tree
*mt
,
857 * \return false if no resolve was needed
860 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
861 struct intel_mipmap_tree
*mt
);
864 * \return false if no resolve was needed
867 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
868 struct intel_mipmap_tree
*mt
);
873 * Update the fast clear state for a miptree to indicate that it has been used
877 intel_miptree_used_for_rendering(struct intel_mipmap_tree
*mt
)
879 /* If the buffer was previously in fast clear state, change it to
880 * unresolved state, since it won't be guaranteed to be clear after
883 if (mt
->fast_clear_state
== INTEL_FAST_CLEAR_STATE_CLEAR
)
884 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_UNRESOLVED
;
888 intel_miptree_resolve_color(struct brw_context
*brw
,
889 struct intel_mipmap_tree
*mt
);
892 intel_miptree_make_shareable(struct brw_context
*brw
,
893 struct intel_mipmap_tree
*mt
);
896 intel_miptree_updownsample(struct brw_context
*brw
,
897 struct intel_mipmap_tree
*src
,
898 struct intel_mipmap_tree
*dst
);
901 * Horizontal distance from one slice to the next in the two-dimensional
905 brw_miptree_get_horizontal_slice_pitch(const struct brw_context
*brw
,
906 const struct intel_mipmap_tree
*mt
,
910 * Vertical distance from one slice to the next in the two-dimensional miptree
914 brw_miptree_get_vertical_slice_pitch(const struct brw_context
*brw
,
915 const struct intel_mipmap_tree
*mt
,
919 brw_miptree_layout(struct brw_context
*brw
,
920 struct intel_mipmap_tree
*mt
,
921 uint32_t layout_flags
);
924 intel_miptree_map(struct brw_context
*brw
,
925 struct intel_mipmap_tree
*mt
,
934 ptrdiff_t *out_stride
);
937 intel_miptree_unmap(struct brw_context
*brw
,
938 struct intel_mipmap_tree
*mt
,
943 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
944 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);