src/mesa/drivers/dri/i965/intel_mipmap_tree.h

   1 /*
   2  * Copyright 2006 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 /** @file intel_mipmap_tree.h
  27  *
  28  * This file defines the structure that wraps a BO and describes how the
  29  * mipmap levels and slices of a texture are laid out.
  30  *
  31  * The hardware has a fixed layout of a texture depending on parameters such
  32  * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
  33  * mipmap levels.  The individual level/layer slices are each 2D rectangles of
  34  * pixels at some x/y offset from the start of the brw_bo.
  35  *
  36  * Original OpenGL allowed texture miplevels to be specified in arbitrary
  37  * order, and a texture may change size over time.  Thus, each
  38  * intel_texture_image has a reference to a miptree that contains the pixel
  39  * data sized appropriately for it, which will later be referenced by/copied
  40  * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
  41  * that there's a single miptree for the complete texture.
  42  */
  43
  44 #ifndef INTEL_MIPMAP_TREE_H
  45 #define INTEL_MIPMAP_TREE_H
  46
  47 #include <assert.h>
  48
  49 #include "main/mtypes.h"
  50 #include "isl/isl.h"
  51 #include "brw_bufmgr.h"
  52 #include "intel_resolve_map.h"
  53 #include <GL/internal/dri_interface.h>
  54
  55 #ifdef __cplusplus
  56 extern "C" {
  57 #endif
  58
  59 struct brw_context;
  60 struct intel_renderbuffer;
  61
  62 struct intel_resolve_map;
  63 struct intel_texture_image;
  64
  65 /**
  66  * This bit extends the set of GL_MAP_*_BIT enums.
  67  *
  68  * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
  69  * depthstencil-split-to-separate-stencil miptree, we'll normally make a
  70  * temporary and recreate the kind of data requested by Mesa core, since we're
  71  * satisfying some glGetTexImage() request or something.
  72  *
  73  * However, occasionally you want to actually map the miptree's current data
  74  * without transcoding back.  This flag to intel_miptree_map() gets you that.
  75  */
  76 #define BRW_MAP_DIRECT_BIT      0x80000000
  77
  78 struct intel_miptree_map {
  79    /** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */
  80    GLbitfield mode;
  81    /** Region of interest for the map. */
  82    int x, y, w, h;
  83    /** Possibly malloced temporary buffer for the mapping. */
  84    void *buffer;
  85    /** Possible pointer to a temporary linear miptree for the mapping. */
  86    struct intel_mipmap_tree *linear_mt;
  87    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  88    void *ptr;
  89    /** Stride of the mapping. */
  90    int stride;
  91 };
  92
  93 /**
  94  * Describes the location of each texture image within a miptree.
  95  */
  96 struct intel_mipmap_level
  97 {
  98    /** Offset to this miptree level, used in computing x_offset. */
  99    GLuint level_x;
 100    /** Offset to this miptree level, used in computing y_offset. */
 101    GLuint level_y;
 102
 103    /**
 104     * \brief Number of 2D slices in this miplevel.
 105     *
 106     * The exact semantics of depth varies according to the texture target:
 107     *    - For GL_TEXTURE_CUBE_MAP, depth is 6.
 108     *    - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
 109     *      identical for all miplevels in the texture.
 110     *    - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
 111     *      value, like width and height, varies with miplevel.
 112     *    - For other texture types, depth is 1.
 113     *    - Additionally, for UMS and CMS miptrees, depth is multiplied by
 114     *      sample count.
 115     */
 116    GLuint depth;
 117
 118    /**
 119     * \brief Is HiZ enabled for this level?
 120     *
 121     * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
 122     * allocated and (2) the HiZ memory for the slices in this level reside at
 123     * \c mt->hiz_mt->level[l].
 124     */
 125    bool has_hiz;
 126
 127    /**
 128     * \brief List of 2D images in this mipmap level.
 129     *
 130     * This may be a list of cube faces, array slices in 2D array texture, or
 131     * layers in a 3D texture. The list's length is \c depth.
 132     */
 133    struct intel_mipmap_slice {
 134       /**
 135        * \name Offset to slice
 136        * \{
 137        *
 138        * Hardware formats are so diverse that that there is no unified way to
 139        * compute the slice offsets, so we store them in this table.
 140        *
 141        * The (x, y) offset to slice \c s at level \c l relative the miptrees
 142        * base address is
 143        * \code
 144        *     x = mt->level[l].slice[s].x_offset
 145        *     y = mt->level[l].slice[s].y_offset
 146        *
 147        * On some hardware generations, we program these offsets into
 148        * RENDER_SURFACE_STATE.XOffset and RENDER_SURFACE_STATE.YOffset.
 149        */
 150       GLuint x_offset;
 151       GLuint y_offset;
 152       /** \} */
 153
 154       /**
 155        * Mapping information. Persistent for the duration of
 156        * intel_miptree_map/unmap on this slice.
 157        */
 158       struct intel_miptree_map *map;
 159    } *slice;
 160 };
 161
 162 /**
 163  * Enum for keeping track of the different MSAA layouts supported by Gen7.
 164  */
 165 enum intel_msaa_layout
 166 {
 167    /**
 168     * Ordinary surface with no MSAA.
 169     */
 170    INTEL_MSAA_LAYOUT_NONE,
 171
 172    /**
 173     * Interleaved Multisample Surface.  The additional samples are
 174     * accommodated by scaling up the width and the height of the surface so
 175     * that all the samples corresponding to a pixel are located at nearby
 176     * memory locations.
 177     *
 178     * @see PRM section "Interleaved Multisampled Surfaces"
 179     */
 180    INTEL_MSAA_LAYOUT_IMS,
 181
 182    /**
 183     * Uncompressed Multisample Surface.  The surface is stored as a 2D array,
 184     * with array slice n containing all pixel data for sample n.
 185     *
 186     * @see PRM section "Uncompressed Multisampled Surfaces"
 187     */
 188    INTEL_MSAA_LAYOUT_UMS,
 189
 190    /**
 191     * Compressed Multisample Surface.  The surface is stored as in
 192     * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
 193     * (Multisample Control Surface) buffer.  Each pixel in the MCS buffer
 194     * indicates the mapping from sample number to array slice.  This allows
 195     * the common case (where all samples constituting a pixel have the same
 196     * color value) to be stored efficiently by just using a single array
 197     * slice.
 198     *
 199     * @see PRM section "Compressed Multisampled Surfaces"
 200     */
 201    INTEL_MSAA_LAYOUT_CMS,
 202 };
 203
 204 enum miptree_array_layout {
 205    /* Each array slice contains all miplevels packed together.
 206     *
 207     * Gen hardware usually wants multilevel miptrees configured this way.
 208     *
 209     * A 2D Array texture with 2 slices and multiple LODs using
 210     * ALL_LOD_IN_EACH_SLICE would look somewhat like this:
 211     *
 212     *   +----------+
 213     *   |          |
 214     *   |          |
 215     *   +----------+
 216     *   +---+ +-+
 217     *   |   | +-+
 218     *   +---+ *
 219     *   +----------+
 220     *   |          |
 221     *   |          |
 222     *   +----------+
 223     *   +---+ +-+
 224     *   |   | +-+
 225     *   +---+ *
 226     */
 227    ALL_LOD_IN_EACH_SLICE,
 228
 229    /* Each LOD contains all slices of that LOD packed together.
 230     *
 231     * In some situations, Gen7+ hardware can use the array_spacing_lod0
 232     * feature to save space when the surface only contains LOD 0.
 233     *
 234     * Gen6 uses this for separate stencil and hiz since gen6 does not support
 235     * multiple LODs for separate stencil and hiz.
 236     *
 237     * A 2D Array texture with 2 slices and multiple LODs using
 238     * ALL_SLICES_AT_EACH_LOD would look somewhat like this:
 239     *
 240     *   +----------+
 241     *   |          |
 242     *   |          |
 243     *   +----------+
 244     *   |          |
 245     *   |          |
 246     *   +----------+
 247     *   +---+ +-+
 248     *   |   | +-+
 249     *   +---+ +-+
 250     *   |   | :
 251     *   +---+
 252     */
 253    ALL_SLICES_AT_EACH_LOD,
 254 };
 255
 256 enum intel_aux_disable {
 257    INTEL_AUX_DISABLE_NONE = 0,
 258    INTEL_AUX_DISABLE_HIZ  = 1 << 1,
 259    INTEL_AUX_DISABLE_MCS  = 1 << 2,
 260    INTEL_AUX_DISABLE_CCS  = 1 << 3,
 261    INTEL_AUX_DISABLE_ALL  = INTEL_AUX_DISABLE_HIZ |
 262                             INTEL_AUX_DISABLE_MCS |
 263                             INTEL_AUX_DISABLE_CCS
 264 };
 265
 266 /**
 267  * Miptree aux buffer. These buffers are associated with a miptree, but the
 268  * format is managed by the hardware.
 269  *
 270  * For Gen7+, we always give the hardware the start of the buffer, and let it
 271  * handle all accesses to the buffer. Therefore we don't need the full miptree
 272  * layout structure for this buffer.
 273  */
 274 struct intel_miptree_aux_buffer
 275 {
 276    /**
 277     * Buffer object containing the pixel data.
 278     *
 279     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 280     * @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
 281     */
 282    struct brw_bo *bo;
 283
 284    /**
 285     * Offset into bo where the surface starts.
 286     *
 287     * @see intel_mipmap_aux_buffer::bo
 288     *
 289     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 290     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 291     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 292     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 293     */
 294    uint32_t offset;
 295
 296    /*
 297     * Size of the MCS surface.
 298     *
 299     * This is needed when doing any gtt mapped operations on the buffer (which
 300     * will be Y-tiled). It is possible that it will not be the same as bo->size
 301     * when the drm allocator rounds up the requested size.
 302     */
 303    size_t size;
 304
 305    /**
 306     * Pitch in bytes.
 307     *
 308     * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
 309     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
 310     */
 311    uint32_t pitch;
 312
 313    /**
 314     * The distance in rows between array slices.
 315     *
 316     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch
 317     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
 318     */
 319    uint32_t qpitch;
 320 };
 321 /**
 322  * The HiZ buffer requires extra attributes on earlier GENs. This is easily
 323  * contained within an intel_mipmap_tree. To make sure we do not abuse this, we
 324  * keep the hiz datastructure separate.
 325  */
 326 struct intel_miptree_hiz_buffer
 327 {
 328    struct intel_miptree_aux_buffer aux_base;
 329
 330    /**
 331     * Hiz miptree. Used only by Gen6.
 332     */
 333    struct intel_mipmap_tree *mt;
 334 };
 335
 336 struct intel_mipmap_tree
 337 {
 338    /**
 339     * Buffer object containing the surface.
 340     *
 341     * @see intel_mipmap_tree::offset
 342     * @see RENDER_SURFACE_STATE.SurfaceBaseAddress
 343     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 344     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 345     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 346     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 347     */
 348    struct brw_bo *bo;
 349
 350    /**
 351     * Pitch in bytes.
 352     *
 353     * @see RENDER_SURFACE_STATE.SurfacePitch
 354     * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
 355     * @see 3DSTATE_DEPTH_BUFFER.SurfacePitch
 356     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
 357     * @see 3DSTATE_STENCIL_BUFFER.SurfacePitch
 358     */
 359    uint32_t pitch;
 360
 361    /**
 362     * One of the I915_TILING_* flags.
 363     *
 364     * @see RENDER_SURFACE_STATE.TileMode
 365     * @see 3DSTATE_DEPTH_BUFFER.TileMode
 366     */
 367    uint32_t tiling;
 368
 369    /**
 370     * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
 371     *
 372     * @see RENDER_SURFACE_STATE.SurfaceType
 373     * @see RENDER_SURFACE_STATE.SurfaceArray
 374     * @see 3DSTATE_DEPTH_BUFFER.SurfaceType
 375     */
 376    GLenum target;
 377
 378    /**
 379     * Generally, this is just the same as the gl_texture_image->TexFormat or
 380     * gl_renderbuffer->Format.
 381     *
 382     * However, for textures and renderbuffers with packed depth/stencil formats
 383     * on hardware where we want or need to use separate stencil, there will be
 384     * two miptrees for storing the data.  If the depthstencil texture or rb is
 385     * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
 386     * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
 387     * MESA_FORMAT_Z24_UNORM_X8_UINT.
 388     *
 389     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
 390     * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
 391     *
 392     * @see RENDER_SURFACE_STATE.SurfaceFormat
 393     * @see 3DSTATE_DEPTH_BUFFER.SurfaceFormat
 394     */
 395    mesa_format format;
 396
 397    /**
 398     * This variable stores the value of ETC compressed texture format
 399     *
 400     * @see RENDER_SURFACE_STATE.SurfaceFormat
 401     */
 402    mesa_format etc_format;
 403
 404    /**
 405     * @name Surface Alignment
 406     * @{
 407     *
 408     * This defines the alignment of the upperleft pixel of each "slice" in the
 409     * surface. The alignment is in pixel coordinates relative to the surface's
 410     * most upperleft pixel, which is the pixel at (x=0, y=0, layer=0,
 411     * level=0).
 412     *
 413     * The hardware docs do not use the term "slice".  We use "slice" to mean
 414     * the pixels at a given miplevel and layer. For 2D surfaces, the layer is
 415     * the array slice; for 3D surfaces, the layer is the z offset.
 416     *
 417     * In the surface layout equations found in the hardware docs, the
 418     * horizontal and vertical surface alignments often appear as variables 'i'
 419     * and 'j'.
 420     */
 421
 422    /** @see RENDER_SURFACE_STATE.SurfaceHorizontalAlignment */
 423    uint32_t halign;
 424
 425    /** @see RENDER_SURFACE_STATE.SurfaceVerticalAlignment */
 426    uint32_t valign;
 427    /** @} */
 428
 429    GLuint first_level;
 430    GLuint last_level;
 431
 432    /**
 433     * Level zero image dimensions.  These dimensions correspond to the
 434     * physical layout of data in memory.  Accordingly, they account for the
 435     * extra width, height, and or depth that must be allocated in order to
 436     * accommodate multisample formats, and they account for the extra factor
 437     * of 6 in depth that must be allocated in order to accommodate cubemap
 438     * textures.
 439     */
 440    GLuint physical_width0, physical_height0, physical_depth0;
 441
 442    /** Bytes per pixel (or bytes per block if compressed) */
 443    GLuint cpp;
 444
 445    /**
 446     * @see RENDER_SURFACE_STATE.NumberOfMultisamples
 447     * @see 3DSTATE_MULTISAMPLE.NumberOfMultisamples
 448     */
 449    GLuint num_samples;
 450
 451    bool compressed;
 452
 453    /**
 454     * @name Level zero image dimensions
 455     * @{
 456     *
 457     * These dimensions correspond to the
 458     * logical width, height, and depth of the texture as seen by client code.
 459     * Accordingly, they do not account for the extra width, height, and/or
 460     * depth that must be allocated in order to accommodate multisample
 461     * formats, nor do they account for the extra factor of 6 in depth that
 462     * must be allocated in order to accommodate cubemap textures.
 463     */
 464
 465    /**
 466     * @see RENDER_SURFACE_STATE.Width
 467     * @see 3DSTATE_DEPTH_BUFFER.Width
 468     */
 469    uint32_t logical_width0;
 470
 471    /**
 472     * @see RENDER_SURFACE_STATE.Height
 473     * @see 3DSTATE_DEPTH_BUFFER.Height
 474     */
 475    uint32_t logical_height0;
 476
 477    /**
 478     * @see RENDER_SURFACE_STATE.Depth
 479     * @see 3DSTATE_DEPTH_BUFFER.Depth
 480     */
 481    uint32_t logical_depth0;
 482    /** @} */
 483
 484    /**
 485     * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
 486     * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
 487     */
 488    enum miptree_array_layout array_layout;
 489
 490    /**
 491     * The distance in between array slices.
 492     *
 493     * The value is the one that is sent in the surface state. The actual
 494     * meaning depends on certain criteria. Usually it is simply the number of
 495     * uncompressed rows between each slice. However on Gen9+ for compressed
 496     * surfaces it is the number of blocks. For 1D array surfaces that have the
 497     * mipmap tree stored horizontally it is the number of pixels between each
 498     * slice.
 499     *
 500     * @see RENDER_SURFACE_STATE.SurfaceQPitch
 501     * @see 3DSTATE_DEPTH_BUFFER.SurfaceQPitch
 502     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
 503     * @see 3DSTATE_STENCIL_BUFFER.SurfaceQPitch
 504     */
 505    uint32_t qpitch;
 506
 507    /**
 508     * MSAA layout used by this buffer.
 509     *
 510     * @see RENDER_SURFACE_STATE.MultisampledSurfaceStorageFormat
 511     */
 512    enum intel_msaa_layout msaa_layout;
 513
 514    /* Derived from the above:
 515     */
 516    GLuint total_width;
 517    GLuint total_height;
 518
 519    /**
 520     * The depth value used during the most recent fast depth clear performed
 521     * on the surface. This field is invalid only if surface has never
 522     * underwent a fast depth clear.
 523     *
 524     * @see 3DSTATE_CLEAR_PARAMS.DepthClearValue
 525     */
 526    uint32_t depth_clear_value;
 527
 528    /* Includes image offset tables: */
 529    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 530
 531    /**
 532     * Offset into bo where the surface starts.
 533     *
 534     * @see intel_mipmap_tree::bo
 535     *
 536     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 537     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 538     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 539     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 540     */
 541    uint32_t offset;
 542
 543    /**
 544     * \brief HiZ aux buffer
 545     *
 546     * To allocate the hiz buffer, use intel_miptree_alloc_hiz().
 547     *
 548     * To determine if hiz is enabled, do not check this pointer. Instead, use
 549     * intel_miptree_slice_has_hiz().
 550     */
 551    struct intel_miptree_hiz_buffer *hiz_buf;
 552
 553    /**
 554     * \brief Maps of miptree slices to needed resolves.
 555     *
 556     * hiz_map is used only when the miptree has a child HiZ miptree.
 557     *
 558     * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
 559     * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
 560     * mt->hiz_mt->hiz_map, is unused.
 561     *
 562     *
 563     * color_resolve_map is used only when the miptree uses fast clear (Gen7+)
 564     * lossless compression (Gen9+). It should be noted that absence in the
 565     * map means implicitly RESOLVED state. If item is found it always
 566     * indicates state other than RESOLVED.
 567     */
 568    struct exec_list hiz_map; /* List of intel_resolve_map. */
 569    struct exec_list color_resolve_map; /* List of intel_resolve_map. */
 570
 571    /**
 572     * \brief Stencil miptree for depthstencil textures.
 573     *
 574     * This miptree is used for depthstencil textures and renderbuffers that
 575     * require separate stencil.  It always has the true copy of the stencil
 576     * bits, regardless of mt->format.
 577     *
 578     * \see 3DSTATE_STENCIL_BUFFER
 579     * \see intel_miptree_map_depthstencil()
 580     * \see intel_miptree_unmap_depthstencil()
 581     */
 582    struct intel_mipmap_tree *stencil_mt;
 583
 584    /**
 585     * \brief Stencil texturing miptree for sampling from a stencil texture
 586     *
 587     * Some hardware doesn't support sampling from the stencil texture as
 588     * required by the GL_ARB_stencil_texturing extenion. To workaround this we
 589     * blit the texture into a new texture that can be sampled.
 590     *
 591     * \see intel_update_r8stencil()
 592     */
 593    struct intel_mipmap_tree *r8stencil_mt;
 594    bool r8stencil_needs_update;
 595
 596    /**
 597     * \brief MCS auxiliary buffer.
 598     *
 599     * This buffer contains the "multisample control surface", which stores
 600     * the necessary information to implement compressed MSAA
 601     * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
 602     *
 603     * NULL if no MCS buffer is in use for this surface.
 604     */
 605    struct intel_miptree_aux_buffer *mcs_buf;
 606
 607    /**
 608     * Planes 1 and 2 in case this is a planar surface.
 609     */
 610    struct intel_mipmap_tree *plane[2];
 611
 612    /**
 613     * The SURFACE_STATE bits associated with the last fast color clear to this
 614     * color mipmap tree, if any.
 615     *
 616     * Prior to GEN9 there is a single bit for RGBA clear values which gives you
 617     * the option of 2^4 clear colors. Each bit determines if the color channel
 618     * is fully saturated or unsaturated (Cherryview does add a 32b value per
 619     * channel, but it is globally applied instead of being part of the render
 620     * surface state). Starting with GEN9, the surface state accepts a 32b value
 621     * for each color channel.
 622     *
 623     * @see RENDER_SURFACE_STATE.RedClearColor
 624     * @see RENDER_SURFACE_STATE.GreenClearColor
 625     * @see RENDER_SURFACE_STATE.BlueClearColor
 626     * @see RENDER_SURFACE_STATE.AlphaClearColor
 627     */
 628    union {
 629       uint32_t fast_clear_color_value;
 630       union gl_color_union gen9_fast_clear_color;
 631    };
 632
 633    /**
 634     * Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS
 635     * buffer. This is useful for sharing the miptree bo with an external client
 636     * that doesn't understand auxiliary buffers.
 637     */
 638    enum intel_aux_disable aux_disable;
 639
 640    /**
 641     * Tells if the underlying buffer is to be also consumed by entities other
 642     * than the driver. This allows logic to turn off features such as lossless
 643     * compression which is not currently understood by client applications.
 644     */
 645    bool is_scanout;
 646
 647    /* These are also refcounted:
 648     */
 649    GLuint refcount;
 650 };
 651
 652 bool
 653 intel_miptree_is_lossless_compressed(const struct brw_context *brw,
 654                                      const struct intel_mipmap_tree *mt);
 655
 656 bool
 657 intel_tiling_supports_non_msrt_mcs(const struct brw_context *brw,
 658                                    unsigned tiling);
 659
 660 bool
 661 intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw,
 662                                            const struct intel_mipmap_tree *mt);
 663
 664 bool
 665 intel_miptree_supports_lossless_compressed(struct brw_context *brw,
 666                                            const struct intel_mipmap_tree *mt);
 667
 668 bool
 669 intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
 670                                  struct intel_mipmap_tree *mt,
 671                                  bool is_lossless_compressed);
 672
 673 enum {
 674    MIPTREE_LAYOUT_ACCELERATED_UPLOAD       = 1 << 0,
 675    MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD   = 1 << 1,
 676    MIPTREE_LAYOUT_FOR_BO                   = 1 << 2,
 677    MIPTREE_LAYOUT_DISABLE_AUX              = 1 << 3,
 678    MIPTREE_LAYOUT_FORCE_HALIGN16           = 1 << 4,
 679
 680    MIPTREE_LAYOUT_TILING_Y                 = 1 << 5,
 681    MIPTREE_LAYOUT_TILING_NONE              = 1 << 6,
 682    MIPTREE_LAYOUT_TILING_ANY               = MIPTREE_LAYOUT_TILING_Y |
 683                                              MIPTREE_LAYOUT_TILING_NONE,
 684
 685    MIPTREE_LAYOUT_FOR_SCANOUT              = 1 << 7,
 686 };
 687
 688 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
 689                                                GLenum target,
 690                                                mesa_format format,
 691                                                GLuint first_level,
 692                                                GLuint last_level,
 693                                                GLuint width0,
 694                                                GLuint height0,
 695                                                GLuint depth0,
 696                                                GLuint num_samples,
 697                                                uint32_t flags);
 698
 699 struct intel_mipmap_tree *
 700 intel_miptree_create_for_bo(struct brw_context *brw,
 701                             struct brw_bo *bo,
 702                             mesa_format format,
 703                             uint32_t offset,
 704                             uint32_t width,
 705                             uint32_t height,
 706                             uint32_t depth,
 707                             int pitch,
 708                             uint32_t layout_flags);
 709
 710 void
 711 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
 712                                          struct intel_renderbuffer *irb,
 713                                          struct brw_bo *bo,
 714                                          uint32_t width, uint32_t height,
 715                                          uint32_t pitch);
 716
 717 /**
 718  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 719  * The miptree has the following properties:
 720  *     - The target is GL_TEXTURE_2D.
 721  *     - There are no levels other than the base level 0.
 722  *     - Depth is 1.
 723  */
 724 struct intel_mipmap_tree*
 725 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
 726                                       mesa_format format,
 727                                       uint32_t width,
 728                                       uint32_t height,
 729                                       uint32_t num_samples);
 730
 731 mesa_format
 732 intel_depth_format_for_depthstencil_format(mesa_format format);
 733
 734 mesa_format
 735 intel_lower_compressed_format(struct brw_context *brw, mesa_format format);
 736
 737 /** \brief Assert that the level and layer are valid for the miptree. */
 738 static inline void
 739 intel_miptree_check_level_layer(const struct intel_mipmap_tree *mt,
 740                                 uint32_t level,
 741                                 uint32_t layer)
 742 {
 743    (void) mt;
 744    (void) level;
 745    (void) layer;
 746
 747    assert(level >= mt->first_level);
 748    assert(level <= mt->last_level);
 749    assert(layer < mt->level[level].depth);
 750 }
 751
 752 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 753                              struct intel_mipmap_tree *src);
 754
 755 void intel_miptree_release(struct intel_mipmap_tree **mt);
 756
 757 /* Check if an image fits an existing mipmap tree layout
 758  */
 759 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 760                                     struct gl_texture_image *image);
 761
 762 void
 763 intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt,
 764                                GLuint level, GLuint slice,
 765                                GLuint *x, GLuint *y);
 766
 767 enum isl_surf_dim
 768 get_isl_surf_dim(GLenum target);
 769
 770 enum isl_dim_layout
 771 get_isl_dim_layout(const struct gen_device_info *devinfo, uint32_t tiling,
 772                    GLenum target);
 773
 774 enum isl_tiling
 775 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree *mt);
 776
 777 void
 778 intel_miptree_get_isl_surf(struct brw_context *brw,
 779                            const struct intel_mipmap_tree *mt,
 780                            struct isl_surf *surf);
 781 void
 782 intel_miptree_get_aux_isl_surf(struct brw_context *brw,
 783                                const struct intel_mipmap_tree *mt,
 784                                struct isl_surf *surf,
 785                                enum isl_aux_usage *usage);
 786
 787 union isl_color_value
 788 intel_miptree_get_isl_clear_color(struct brw_context *brw,
 789                                   const struct intel_mipmap_tree *mt);
 790
 791 void
 792 intel_get_image_dims(struct gl_texture_image *image,
 793                      int *width, int *height, int *depth);
 794
 795 void
 796 intel_get_tile_masks(uint32_t tiling, uint32_t cpp,
 797                      uint32_t *mask_x, uint32_t *mask_y);
 798
 799 void
 800 intel_get_tile_dims(uint32_t tiling, uint32_t cpp,
 801                     uint32_t *tile_w, uint32_t *tile_h);
 802
 803 uint32_t
 804 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
 805                                GLuint level, GLuint slice,
 806                                uint32_t *tile_x,
 807                                uint32_t *tile_y);
 808 uint32_t
 809 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
 810                                  uint32_t x, uint32_t y);
 811
 812 void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
 813                                   GLuint level,
 814                                   GLuint x, GLuint y, GLuint d);
 815
 816 void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
 817                                     GLuint level,
 818                                     GLuint img, GLuint x, GLuint y);
 819
 820 void
 821 intel_miptree_copy_teximage(struct brw_context *brw,
 822                             struct intel_texture_image *intelImage,
 823                             struct intel_mipmap_tree *dst_mt, bool invalidate);
 824
 825 /**
 826  * \name Miptree HiZ functions
 827  * \{
 828  *
 829  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 830  * functions on a miptree without HiZ. In that case, each function is a no-op.
 831  */
 832
 833 bool
 834 intel_miptree_wants_hiz_buffer(struct brw_context *brw,
 835                                struct intel_mipmap_tree *mt);
 836
 837 /**
 838  * \brief Allocate the miptree's embedded HiZ miptree.
 839  * \see intel_mipmap_tree:hiz_mt
 840  * \return false if allocation failed
 841  */
 842 bool
 843 intel_miptree_alloc_hiz(struct brw_context *brw,
 844                         struct intel_mipmap_tree *mt);
 845
 846 bool
 847 intel_miptree_level_has_hiz(struct intel_mipmap_tree *mt, uint32_t level);
 848
 849 void
 850 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt,
 851                                           uint32_t level,
 852                                           uint32_t depth);
 853 void
 854 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt,
 855                                             uint32_t level,
 856                                             uint32_t depth);
 857
 858 void
 859 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree *mt,
 860                                                 uint32_t level);
 861
 862 /**
 863  * \return false if no resolve was needed
 864  */
 865 bool
 866 intel_miptree_slice_resolve_hiz(struct brw_context *brw,
 867                                 struct intel_mipmap_tree *mt,
 868                                 unsigned int level,
 869                                 unsigned int depth);
 870
 871 /**
 872  * \return false if no resolve was needed
 873  */
 874 bool
 875 intel_miptree_slice_resolve_depth(struct brw_context *brw,
 876                                   struct intel_mipmap_tree *mt,
 877                                   unsigned int level,
 878                                   unsigned int depth);
 879
 880 /**
 881  * \return false if no resolve was needed
 882  */
 883 bool
 884 intel_miptree_all_slices_resolve_hiz(struct brw_context *brw,
 885                                      struct intel_mipmap_tree *mt);
 886
 887 /**
 888  * \return false if no resolve was needed
 889  */
 890 bool
 891 intel_miptree_all_slices_resolve_depth(struct brw_context *brw,
 892                                        struct intel_mipmap_tree *mt);
 893
 894 /**\}*/
 895
 896 enum intel_fast_clear_state
 897 intel_miptree_get_fast_clear_state(const struct intel_mipmap_tree *mt,
 898                                    unsigned level, unsigned layer);
 899
 900 void
 901 intel_miptree_set_fast_clear_state(const struct brw_context *brw,
 902                                    struct intel_mipmap_tree *mt,
 903                                    unsigned level,
 904                                    unsigned first_layer,
 905                                    unsigned num_layers,
 906                                    enum intel_fast_clear_state new_state);
 907
 908 bool
 909 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree *mt,
 910                                    unsigned start_level, unsigned num_levels,
 911                                    unsigned start_layer, unsigned num_layers);
 912
 913 /**
 914  * Update the fast clear state for a miptree to indicate that it has been used
 915  * for rendering.
 916  */
 917 void
 918 intel_miptree_used_for_rendering(const struct brw_context *brw,
 919                                  struct intel_mipmap_tree *mt, unsigned level,
 920                                  unsigned start_layer, unsigned num_layers);
 921
 922 /**
 923  * Flag values telling color resolve pass which special types of buffers
 924  * can be ignored.
 925  *
 926  * INTEL_MIPTREE_IGNORE_CCS_E:   Lossless compressed (single-sample
 927  *                               compression scheme since gen9)
 928  */
 929 #define INTEL_MIPTREE_IGNORE_CCS_E (1 << 0)
 930
 931 bool
 932 intel_miptree_resolve_color(struct brw_context *brw,
 933                             struct intel_mipmap_tree *mt, unsigned level,
 934                             unsigned start_layer, unsigned num_layers,
 935                             int flags);
 936
 937 void
 938 intel_miptree_all_slices_resolve_color(struct brw_context *brw,
 939                                        struct intel_mipmap_tree *mt,
 940                                        int flags);
 941
 942 void
 943 intel_miptree_make_shareable(struct brw_context *brw,
 944                              struct intel_mipmap_tree *mt);
 945
 946 void
 947 intel_miptree_updownsample(struct brw_context *brw,
 948                            struct intel_mipmap_tree *src,
 949                            struct intel_mipmap_tree *dst);
 950
 951 void
 952 intel_update_r8stencil(struct brw_context *brw,
 953                        struct intel_mipmap_tree *mt);
 954
 955 /**
 956  * Horizontal distance from one slice to the next in the two-dimensional
 957  * miptree layout.
 958  */
 959 unsigned
 960 brw_miptree_get_horizontal_slice_pitch(const struct brw_context *brw,
 961                                        const struct intel_mipmap_tree *mt,
 962                                        unsigned level);
 963
 964 /**
 965  * Vertical distance from one slice to the next in the two-dimensional miptree
 966  * layout.
 967  */
 968 unsigned
 969 brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw,
 970                                      const struct intel_mipmap_tree *mt,
 971                                      unsigned level);
 972
 973 bool
 974 brw_miptree_layout(struct brw_context *brw,
 975                    struct intel_mipmap_tree *mt,
 976                    uint32_t layout_flags);
 977
 978 void
 979 intel_miptree_map(struct brw_context *brw,
 980                   struct intel_mipmap_tree *mt,
 981                   unsigned int level,
 982                   unsigned int slice,
 983                   unsigned int x,
 984                   unsigned int y,
 985                   unsigned int w,
 986                   unsigned int h,
 987                   GLbitfield mode,
 988                   void **out_ptr,
 989                   ptrdiff_t *out_stride);
 990
 991 void
 992 intel_miptree_unmap(struct brw_context *brw,
 993                     struct intel_mipmap_tree *mt,
 994                     unsigned int level,
 995                     unsigned int slice);
 996
 997 void
 998 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 999                unsigned int level, unsigned int layer, enum blorp_hiz_op op);
1000
1001 bool
1002 intel_miptree_sample_with_hiz(struct brw_context *brw,
1003                               struct intel_mipmap_tree *mt);
1004
1005 #ifdef __cplusplus
1006 }
1007 #endif
1008
1009 #endif