src/mesa/drivers/dri/i965/intel_mipmap_tree.h

   1 /*
   2  * Copyright 2006 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 /** @file intel_mipmap_tree.h
  27  *
  28  * This file defines the structure that wraps a BO and describes how the
  29  * mipmap levels and slices of a texture are laid out.
  30  *
  31  * The hardware has a fixed layout of a texture depending on parameters such
  32  * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
  33  * mipmap levels.  The individual level/layer slices are each 2D rectangles of
  34  * pixels at some x/y offset from the start of the drm_intel_bo.
  35  *
  36  * Original OpenGL allowed texture miplevels to be specified in arbitrary
  37  * order, and a texture may change size over time.  Thus, each
  38  * intel_texture_image has a reference to a miptree that contains the pixel
  39  * data sized appropriately for it, which will later be referenced by/copied
  40  * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
  41  * that there's a single miptree for the complete texture.
  42  */
  43
  44 #ifndef INTEL_MIPMAP_TREE_H
  45 #define INTEL_MIPMAP_TREE_H
  46
  47 #include <assert.h>
  48
  49 #include "main/mtypes.h"
  50 #include "intel_bufmgr.h"
  51 #include "intel_resolve_map.h"
  52 #include <GL/internal/dri_interface.h>
  53
  54 #ifdef __cplusplus
  55 extern "C" {
  56 #endif
  57
  58 struct brw_context;
  59 struct intel_renderbuffer;
  60
  61 struct intel_resolve_map;
  62 struct intel_texture_image;
  63
  64 /**
  65  * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
  66  * depthstencil-split-to-separate-stencil miptree, we'll normally make a
  67  * tmeporary and recreate the kind of data requested by Mesa core, since we're
  68  * satisfying some glGetTexImage() request or something.
  69  *
  70  * However, occasionally you want to actually map the miptree's current data
  71  * without transcoding back.  This flag to intel_miptree_map() gets you that.
  72  */
  73 #define BRW_MAP_DIRECT_BIT      0x80000000
  74
  75 struct intel_miptree_map {
  76    /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
  77    GLbitfield mode;
  78    /** Region of interest for the map. */
  79    int x, y, w, h;
  80    /** Possibly malloced temporary buffer for the mapping. */
  81    void *buffer;
  82    /** Possible pointer to a temporary linear miptree for the mapping. */
  83    struct intel_mipmap_tree *mt;
  84    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  85    void *ptr;
  86    /** Stride of the mapping. */
  87    int stride;
  88 };
  89
  90 /**
  91  * Describes the location of each texture image within a miptree.
  92  */
  93 struct intel_mipmap_level
  94 {
  95    /** Offset to this miptree level, used in computing x_offset. */
  96    GLuint level_x;
  97    /** Offset to this miptree level, used in computing y_offset. */
  98    GLuint level_y;
  99
 100    /**
 101     * \brief Number of 2D slices in this miplevel.
 102     *
 103     * The exact semantics of depth varies according to the texture target:
 104     *    - For GL_TEXTURE_CUBE_MAP, depth is 6.
 105     *    - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
 106     *      identical for all miplevels in the texture.
 107     *    - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
 108     *      value, like width and height, varies with miplevel.
 109     *    - For other texture types, depth is 1.
 110     *    - Additionally, for UMS and CMS miptrees, depth is multiplied by
 111     *      sample count.
 112     */
 113    GLuint depth;
 114
 115    /**
 116     * \brief Is HiZ enabled for this level?
 117     *
 118     * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
 119     * allocated and (2) the HiZ memory for the slices in this level reside at
 120     * \c mt->hiz_mt->level[l].
 121     */
 122    bool has_hiz;
 123
 124    /**
 125     * \brief List of 2D images in this mipmap level.
 126     *
 127     * This may be a list of cube faces, array slices in 2D array texture, or
 128     * layers in a 3D texture. The list's length is \c depth.
 129     */
 130    struct intel_mipmap_slice {
 131       /**
 132        * \name Offset to slice
 133        * \{
 134        *
 135        * Hardware formats are so diverse that that there is no unified way to
 136        * compute the slice offsets, so we store them in this table.
 137        *
 138        * The (x, y) offset to slice \c s at level \c l relative the miptrees
 139        * base address is
 140        * \code
 141        *     x = mt->level[l].slice[s].x_offset
 142        *     y = mt->level[l].slice[s].y_offset
 143        */
 144       GLuint x_offset;
 145       GLuint y_offset;
 146       /** \} */
 147
 148       /**
 149        * Mapping information. Persistent for the duration of
 150        * intel_miptree_map/unmap on this slice.
 151        */
 152       struct intel_miptree_map *map;
 153    } *slice;
 154 };
 155
 156 /**
 157  * Enum for keeping track of the different MSAA layouts supported by Gen7.
 158  */
 159 enum intel_msaa_layout
 160 {
 161    /**
 162     * Ordinary surface with no MSAA.
 163     */
 164    INTEL_MSAA_LAYOUT_NONE,
 165
 166    /**
 167     * Interleaved Multisample Surface.  The additional samples are
 168     * accommodated by scaling up the width and the height of the surface so
 169     * that all the samples corresponding to a pixel are located at nearby
 170     * memory locations.
 171     */
 172    INTEL_MSAA_LAYOUT_IMS,
 173
 174    /**
 175     * Uncompressed Multisample Surface.  The surface is stored as a 2D array,
 176     * with array slice n containing all pixel data for sample n.
 177     */
 178    INTEL_MSAA_LAYOUT_UMS,
 179
 180    /**
 181     * Compressed Multisample Surface.  The surface is stored as in
 182     * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
 183     * (Multisample Control Surface) buffer.  Each pixel in the MCS buffer
 184     * indicates the mapping from sample number to array slice.  This allows
 185     * the common case (where all samples constituting a pixel have the same
 186     * color value) to be stored efficiently by just using a single array
 187     * slice.
 188     */
 189    INTEL_MSAA_LAYOUT_CMS,
 190 };
 191
 192
 193 /**
 194  * Enum for keeping track of the fast clear state of a buffer associated with
 195  * a miptree.
 196  *
 197  * Fast clear works by deferring the memory writes that would be used to clear
 198  * the buffer, so that instead of performing them at the time of the clear
 199  * operation, the hardware automatically performs them at the time that the
 200  * buffer is later accessed for rendering.  The MCS buffer keeps track of
 201  * which regions of the buffer still have pending clear writes.
 202  *
 203  * This enum keeps track of the driver's knowledge of pending fast clears in
 204  * the MCS buffer.
 205  *
 206  * MCS buffers only exist on Gen7+.
 207  */
 208 enum intel_fast_clear_state
 209 {
 210    /**
 211     * There is no MCS buffer for this miptree, and one should never be
 212     * allocated.
 213     */
 214    INTEL_FAST_CLEAR_STATE_NO_MCS,
 215
 216    /**
 217     * No deferred clears are pending for this miptree, and the contents of the
 218     * color buffer are entirely correct.  An MCS buffer may or may not exist
 219     * for this miptree.  If it does exist, it is entirely in the "no deferred
 220     * clears pending" state.  If it does not exist, it will be created the
 221     * first time a fast color clear is executed.
 222     *
 223     * In this state, the color buffer can be used for purposes other than
 224     * rendering without needing a render target resolve.
 225     *
 226     * Since there is no such thing as a "fast color clear resolve" for MSAA
 227     * buffers, an MSAA buffer will never be in this state.
 228     */
 229    INTEL_FAST_CLEAR_STATE_RESOLVED,
 230
 231    /**
 232     * An MCS buffer exists for this miptree, and deferred clears are pending
 233     * for some regions of the color buffer, as indicated by the MCS buffer.
 234     * The contents of the color buffer are only correct for the regions where
 235     * the MCS buffer doesn't indicate a deferred clear.
 236     *
 237     * If a single-sample buffer is in this state, a render target resolve must
 238     * be performed before it can be used for purposes other than rendering.
 239     */
 240    INTEL_FAST_CLEAR_STATE_UNRESOLVED,
 241
 242    /**
 243     * An MCS buffer exists for this miptree, and deferred clears are pending
 244     * for the entire color buffer, and the contents of the MCS buffer reflect
 245     * this.  The contents of the color buffer are undefined.
 246     *
 247     * If a single-sample buffer is in this state, a render target resolve must
 248     * be performed before it can be used for purposes other than rendering.
 249     *
 250     * If the client attempts to clear a buffer which is already in this state,
 251     * the clear can be safely skipped, since the buffer is already clear.
 252     */
 253    INTEL_FAST_CLEAR_STATE_CLEAR,
 254 };
 255
 256 enum miptree_array_layout {
 257    /* Each array slice contains all miplevels packed together.
 258     *
 259     * Gen hardware usually wants multilevel miptrees configured this way.
 260     *
 261     * A 2D Array texture with 2 slices and multiple LODs using
 262     * ALL_LOD_IN_EACH_SLICE would look somewhat like this:
 263     *
 264     *   +----------+
 265     *   |          |
 266     *   |          |
 267     *   +----------+
 268     *   +---+ +-+
 269     *   |   | +-+
 270     *   +---+ *
 271     *   +----------+
 272     *   |          |
 273     *   |          |
 274     *   +----------+
 275     *   +---+ +-+
 276     *   |   | +-+
 277     *   +---+ *
 278     */
 279    ALL_LOD_IN_EACH_SLICE,
 280
 281    /* Each LOD contains all slices of that LOD packed together.
 282     *
 283     * In some situations, Gen7+ hardware can use the array_spacing_lod0
 284     * feature to save space when the surface only contains LOD 0.
 285     *
 286     * Gen6 uses this for separate stencil and hiz since gen6 does not support
 287     * multiple LODs for separate stencil and hiz.
 288     *
 289     * A 2D Array texture with 2 slices and multiple LODs using
 290     * ALL_SLICES_AT_EACH_LOD would look somewhat like this:
 291     *
 292     *   +----------+
 293     *   |          |
 294     *   |          |
 295     *   +----------+
 296     *   |          |
 297     *   |          |
 298     *   +----------+
 299     *   +---+ +-+
 300     *   |   | +-+
 301     *   +---+ +-+
 302     *   |   | :
 303     *   +---+
 304     */
 305    ALL_SLICES_AT_EACH_LOD,
 306 };
 307
 308 /**
 309  * Miptree aux buffer. These buffers are associated with a miptree, but the
 310  * format is managed by the hardware.
 311  *
 312  * For Gen7+, we always give the hardware the start of the buffer, and let it
 313  * handle all accesses to the buffer. Therefore we don't need the full miptree
 314  * layout structure for this buffer.
 315  *
 316  * For Gen6, we need a hiz miptree structure for this buffer so we can program
 317  * offsets to slices & miplevels.
 318  */
 319 struct intel_miptree_aux_buffer
 320 {
 321    /** Buffer object containing the pixel data. */
 322    drm_intel_bo *bo;
 323
 324    uint32_t pitch; /**< pitch in bytes. */
 325
 326    uint32_t qpitch; /**< The distance in rows between array slices. */
 327
 328    struct intel_mipmap_tree *mt; /**< hiz miptree used with Gen6 */
 329 };
 330
 331 /* Tile resource modes */
 332 enum intel_miptree_tr_mode {
 333    INTEL_MIPTREE_TRMODE_NONE,
 334    INTEL_MIPTREE_TRMODE_YF,
 335    INTEL_MIPTREE_TRMODE_YS
 336 };
 337
 338 struct intel_mipmap_tree
 339 {
 340    /** Buffer object containing the pixel data. */
 341    drm_intel_bo *bo;
 342
 343    uint32_t pitch; /**< pitch in bytes. */
 344
 345    uint32_t tiling; /**< One of the I915_TILING_* flags */
 346    enum intel_miptree_tr_mode tr_mode;
 347
 348    /* Effectively the key:
 349     */
 350    GLenum target;
 351
 352    /**
 353     * Generally, this is just the same as the gl_texture_image->TexFormat or
 354     * gl_renderbuffer->Format.
 355     *
 356     * However, for textures and renderbuffers with packed depth/stencil formats
 357     * on hardware where we want or need to use separate stencil, there will be
 358     * two miptrees for storing the data.  If the depthstencil texture or rb is
 359     * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
 360     * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
 361     * MESA_FORMAT_Z24_UNORM_X8_UINT.
 362     *
 363     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
 364     * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
 365     */
 366    mesa_format format;
 367
 368    /** This variable stores the value of ETC compressed texture format */
 369    mesa_format etc_format;
 370
 371    /**
 372     * The X offset of each image in the miptree must be aligned to this.
 373     * See the comments in brw_tex_layout.c.
 374     */
 375    unsigned int align_w;
 376    unsigned int align_h; /**< \see align_w */
 377
 378    GLuint first_level;
 379    GLuint last_level;
 380
 381    /**
 382     * Level zero image dimensions.  These dimensions correspond to the
 383     * physical layout of data in memory.  Accordingly, they account for the
 384     * extra width, height, and or depth that must be allocated in order to
 385     * accommodate multisample formats, and they account for the extra factor
 386     * of 6 in depth that must be allocated in order to accommodate cubemap
 387     * textures.
 388     */
 389    GLuint physical_width0, physical_height0, physical_depth0;
 390
 391    GLuint cpp; /**< bytes per pixel (or bytes per block if compressed) */
 392    GLuint num_samples;
 393    bool compressed;
 394
 395    /**
 396     * Level zero image dimensions.  These dimensions correspond to the
 397     * logical width, height, and depth of the texture as seen by client code.
 398     * Accordingly, they do not account for the extra width, height, and/or
 399     * depth that must be allocated in order to accommodate multisample
 400     * formats, nor do they account for the extra factor of 6 in depth that
 401     * must be allocated in order to accommodate cubemap textures.
 402     */
 403    uint32_t logical_width0, logical_height0, logical_depth0;
 404
 405    /**
 406     * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
 407     * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
 408     */
 409    enum miptree_array_layout array_layout;
 410
 411    /**
 412     * The distance in between array slices.
 413     *
 414     * The value is the one that is sent in the surface state. The actual
 415     * meaning depends on certain criteria. Usually it is simply the number of
 416     * uncompressed rows between each slice. However on Gen9+ for compressed
 417     * surfaces it is the number of blocks. For 1D array surfaces that have the
 418     * mipmap tree stored horizontally it is the number of pixels between each
 419     * slice.
 420     */
 421    uint32_t qpitch;
 422
 423    /**
 424     * MSAA layout used by this buffer.
 425     */
 426    enum intel_msaa_layout msaa_layout;
 427
 428    /* Derived from the above:
 429     */
 430    GLuint total_width;
 431    GLuint total_height;
 432
 433    /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to
 434     * this depth mipmap tree, if any.
 435     */
 436    uint32_t depth_clear_value;
 437
 438    /* Includes image offset tables:
 439     */
 440    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 441
 442    /* Offset into bo where miptree starts:
 443     */
 444    uint32_t offset;
 445
 446    /**
 447     * \brief HiZ aux buffer
 448     *
 449     * The hiz miptree contains the miptree's hiz buffer. To allocate the hiz
 450     * buffer, use intel_miptree_alloc_hiz().
 451     *
 452     * To determine if hiz is enabled, do not check this pointer. Instead, use
 453     * intel_miptree_slice_has_hiz().
 454     */
 455    struct intel_miptree_aux_buffer *hiz_buf;
 456
 457    /**
 458     * \brief Map of miptree slices to needed resolves.
 459     *
 460     * This is used only when the miptree has a child HiZ miptree.
 461     *
 462     * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
 463     * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
 464     * mt->hiz_mt->hiz_map, is unused.
 465     */
 466    struct exec_list hiz_map; /* List of intel_resolve_map. */
 467
 468    /**
 469     * \brief Stencil miptree for depthstencil textures.
 470     *
 471     * This miptree is used for depthstencil textures and renderbuffers that
 472     * require separate stencil.  It always has the true copy of the stencil
 473     * bits, regardless of mt->format.
 474     *
 475     * \see intel_miptree_map_depthstencil()
 476     * \see intel_miptree_unmap_depthstencil()
 477     */
 478    struct intel_mipmap_tree *stencil_mt;
 479
 480    /**
 481     * \brief MCS miptree.
 482     *
 483     * This miptree contains the "multisample control surface", which stores
 484     * the necessary information to implement compressed MSAA
 485     * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
 486     *
 487     * NULL if no MCS miptree is in use for this surface.
 488     */
 489    struct intel_mipmap_tree *mcs_mt;
 490
 491    /**
 492     * Fast clear state for this buffer.
 493     */
 494    enum intel_fast_clear_state fast_clear_state;
 495
 496    /**
 497     * The SURFACE_STATE bits associated with the last fast color clear to this
 498     * color mipmap tree, if any.
 499     *
 500     * This value will only ever contain ones in bits 28-31, so it is safe to
 501     * OR into dword 7 of SURFACE_STATE.
 502     */
 503    uint32_t fast_clear_color_value;
 504
 505    /**
 506     * Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS
 507     * buffer. This is useful for sharing the miptree bo with an external client
 508     * that doesn't understand auxiliary buffers.
 509     */
 510    bool disable_aux_buffers;
 511
 512    /* These are also refcounted:
 513     */
 514    GLuint refcount;
 515 };
 516
 517 void
 518 intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
 519                                  struct intel_mipmap_tree *mt,
 520                                  unsigned *width_px, unsigned *height);
 521 bool
 522 intel_tiling_supports_non_msrt_mcs(struct brw_context *brw, unsigned tiling);
 523 bool
 524 intel_miptree_is_fast_clear_capable(struct brw_context *brw,
 525                                     struct intel_mipmap_tree *mt);
 526 bool
 527 intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
 528                                  struct intel_mipmap_tree *mt);
 529
 530 enum {
 531    MIPTREE_LAYOUT_ACCELERATED_UPLOAD       = 1 << 0,
 532    MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD   = 1 << 1,
 533    MIPTREE_LAYOUT_FOR_BO                   = 1 << 2,
 534    MIPTREE_LAYOUT_DISABLE_AUX              = 1 << 3,
 535    MIPTREE_LAYOUT_FORCE_HALIGN16           = 1 << 4,
 536
 537    MIPTREE_LAYOUT_TILING_Y                 = 1 << 5,
 538    MIPTREE_LAYOUT_TILING_NONE              = 1 << 6,
 539    MIPTREE_LAYOUT_TILING_ANY               = MIPTREE_LAYOUT_TILING_Y |
 540                                              MIPTREE_LAYOUT_TILING_NONE,
 541 };
 542
 543 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
 544                                                GLenum target,
 545                                                mesa_format format,
 546                                                GLuint first_level,
 547                                                GLuint last_level,
 548                                                GLuint width0,
 549                                                GLuint height0,
 550                                                GLuint depth0,
 551                                                GLuint num_samples,
 552                                                uint32_t flags);
 553
 554 struct intel_mipmap_tree *
 555 intel_miptree_create_for_bo(struct brw_context *brw,
 556                             drm_intel_bo *bo,
 557                             mesa_format format,
 558                             uint32_t offset,
 559                             uint32_t width,
 560                             uint32_t height,
 561                             uint32_t depth,
 562                             int pitch,
 563                             uint32_t layout_flags);
 564
 565 void
 566 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
 567                                          struct intel_renderbuffer *irb,
 568                                          drm_intel_bo *bo,
 569                                          uint32_t width, uint32_t height,
 570                                          uint32_t pitch);
 571
 572 /**
 573  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 574  * The miptree has the following properties:
 575  *     - The target is GL_TEXTURE_2D.
 576  *     - There are no levels other than the base level 0.
 577  *     - Depth is 1.
 578  */
 579 struct intel_mipmap_tree*
 580 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
 581                                       mesa_format format,
 582                                       uint32_t width,
 583                                       uint32_t height,
 584                                       uint32_t num_samples);
 585
 586 mesa_format
 587 intel_depth_format_for_depthstencil_format(mesa_format format);
 588
 589 mesa_format
 590 intel_lower_compressed_format(struct brw_context *brw, mesa_format format);
 591
 592 /** \brief Assert that the level and layer are valid for the miptree. */
 593 static inline void
 594 intel_miptree_check_level_layer(struct intel_mipmap_tree *mt,
 595                                 uint32_t level,
 596                                 uint32_t layer)
 597 {
 598    assert(level >= mt->first_level);
 599    assert(level <= mt->last_level);
 600    assert(layer < mt->level[level].depth);
 601 }
 602
 603 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 604                              struct intel_mipmap_tree *src);
 605
 606 void intel_miptree_release(struct intel_mipmap_tree **mt);
 607
 608 /* Check if an image fits an existing mipmap tree layout
 609  */
 610 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 611                                     struct gl_texture_image *image);
 612
 613 void
 614 intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt,
 615                                GLuint level, GLuint slice,
 616                                GLuint *x, GLuint *y);
 617
 618 void
 619 intel_miptree_get_dimensions_for_image(struct gl_texture_image *image,
 620                                        int *width, int *height, int *depth);
 621
 622 void
 623 intel_miptree_get_tile_masks(const struct intel_mipmap_tree *mt,
 624                              uint32_t *mask_x, uint32_t *mask_y,
 625                              bool map_stencil_as_y_tiled);
 626
 627 uint32_t
 628 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
 629                                GLuint level, GLuint slice,
 630                                uint32_t *tile_x,
 631                                uint32_t *tile_y);
 632 uint32_t
 633 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
 634                                  uint32_t x, uint32_t y,
 635                                  bool map_stencil_as_y_tiled);
 636
 637 void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
 638                                   GLuint level,
 639                                   GLuint x, GLuint y, GLuint d);
 640
 641 void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
 642                                     GLuint level,
 643                                     GLuint img, GLuint x, GLuint y);
 644
 645 void
 646 intel_miptree_copy_teximage(struct brw_context *brw,
 647                             struct intel_texture_image *intelImage,
 648                             struct intel_mipmap_tree *dst_mt, bool invalidate);
 649
 650 /**
 651  * \name Miptree HiZ functions
 652  * \{
 653  *
 654  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 655  * functions on a miptree without HiZ. In that case, each function is a no-op.
 656  */
 657
 658 bool
 659 intel_miptree_wants_hiz_buffer(struct brw_context *brw,
 660                                struct intel_mipmap_tree *mt);
 661
 662 /**
 663  * \brief Allocate the miptree's embedded HiZ miptree.
 664  * \see intel_mipmap_tree:hiz_mt
 665  * \return false if allocation failed
 666  */
 667 bool
 668 intel_miptree_alloc_hiz(struct brw_context *brw,
 669                         struct intel_mipmap_tree *mt);
 670
 671 bool
 672 intel_miptree_level_has_hiz(struct intel_mipmap_tree *mt, uint32_t level);
 673
 674 void
 675 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt,
 676                                           uint32_t level,
 677                                           uint32_t depth);
 678 void
 679 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt,
 680                                             uint32_t level,
 681                                             uint32_t depth);
 682
 683 void
 684 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree *mt,
 685                                                 uint32_t level);
 686
 687 /**
 688  * \return false if no resolve was needed
 689  */
 690 bool
 691 intel_miptree_slice_resolve_hiz(struct brw_context *brw,
 692                                 struct intel_mipmap_tree *mt,
 693                                 unsigned int level,
 694                                 unsigned int depth);
 695
 696 /**
 697  * \return false if no resolve was needed
 698  */
 699 bool
 700 intel_miptree_slice_resolve_depth(struct brw_context *brw,
 701                                   struct intel_mipmap_tree *mt,
 702                                   unsigned int level,
 703                                   unsigned int depth);
 704
 705 /**
 706  * \return false if no resolve was needed
 707  */
 708 bool
 709 intel_miptree_all_slices_resolve_hiz(struct brw_context *brw,
 710                                      struct intel_mipmap_tree *mt);
 711
 712 /**
 713  * \return false if no resolve was needed
 714  */
 715 bool
 716 intel_miptree_all_slices_resolve_depth(struct brw_context *brw,
 717                                        struct intel_mipmap_tree *mt);
 718
 719 /**\}*/
 720
 721 /**
 722  * Update the fast clear state for a miptree to indicate that it has been used
 723  * for rendering.
 724  */
 725 static inline void
 726 intel_miptree_used_for_rendering(struct intel_mipmap_tree *mt)
 727 {
 728    /* If the buffer was previously in fast clear state, change it to
 729     * unresolved state, since it won't be guaranteed to be clear after
 730     * rendering occurs.
 731     */
 732    if (mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR)
 733       mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
 734 }
 735
 736 void
 737 intel_miptree_resolve_color(struct brw_context *brw,
 738                             struct intel_mipmap_tree *mt);
 739
 740 void
 741 intel_miptree_make_shareable(struct brw_context *brw,
 742                              struct intel_mipmap_tree *mt);
 743
 744 void
 745 intel_miptree_updownsample(struct brw_context *brw,
 746                            struct intel_mipmap_tree *src,
 747                            struct intel_mipmap_tree *dst);
 748
 749 /**
 750  * Horizontal distance from one slice to the next in the two-dimensional
 751  * miptree layout.
 752  */
 753 unsigned
 754 brw_miptree_get_horizontal_slice_pitch(const struct brw_context *brw,
 755                                        const struct intel_mipmap_tree *mt,
 756                                        unsigned level);
 757
 758 /**
 759  * Vertical distance from one slice to the next in the two-dimensional miptree
 760  * layout.
 761  */
 762 unsigned
 763 brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw,
 764                                      const struct intel_mipmap_tree *mt,
 765                                      unsigned level);
 766
 767 void
 768 brw_miptree_layout(struct brw_context *brw,
 769                    struct intel_mipmap_tree *mt,
 770                    uint32_t layout_flags);
 771
 772 void *intel_miptree_map_raw(struct brw_context *brw,
 773                             struct intel_mipmap_tree *mt);
 774
 775 void intel_miptree_unmap_raw(struct brw_context *brw,
 776                              struct intel_mipmap_tree *mt);
 777
 778 void
 779 intel_miptree_map(struct brw_context *brw,
 780                   struct intel_mipmap_tree *mt,
 781                   unsigned int level,
 782                   unsigned int slice,
 783                   unsigned int x,
 784                   unsigned int y,
 785                   unsigned int w,
 786                   unsigned int h,
 787                   GLbitfield mode,
 788                   void **out_ptr,
 789                   ptrdiff_t *out_stride);
 790
 791 void
 792 intel_miptree_unmap(struct brw_context *brw,
 793                     struct intel_mipmap_tree *mt,
 794                     unsigned int level,
 795                     unsigned int slice);
 796
 797 void
 798 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 799                unsigned int level, unsigned int layer, enum gen6_hiz_op op);
 800
 801 #ifdef __cplusplus
 802 }
 803 #endif
 804
 805 #endif