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26 /** @file intel_mipmap_tree.h
28 * This file defines the structure that wraps a BO and describes how the
29 * mipmap levels and slices of a texture are laid out.
31 * The hardware has a fixed layout of a texture depending on parameters such
32 * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
33 * mipmap levels. The individual level/layer slices are each 2D rectangles of
34 * pixels at some x/y offset from the start of the brw_bo.
36 * Original OpenGL allowed texture miplevels to be specified in arbitrary
37 * order, and a texture may change size over time. Thus, each
38 * intel_texture_image has a reference to a miptree that contains the pixel
39 * data sized appropriately for it, which will later be referenced by/copied
40 * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
41 * that there's a single miptree for the complete texture.
44 #ifndef INTEL_MIPMAP_TREE_H
45 #define INTEL_MIPMAP_TREE_H
49 #include "main/mtypes.h"
51 #include "blorp/blorp.h"
52 #include "brw_bufmgr.h"
53 #include <GL/internal/dri_interface.h>
60 struct intel_renderbuffer
;
62 struct intel_texture_image
;
65 * This bit extends the set of GL_MAP_*_BIT enums.
67 * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
68 * depthstencil-split-to-separate-stencil miptree, we'll normally make a
69 * temporary and recreate the kind of data requested by Mesa core, since we're
70 * satisfying some glGetTexImage() request or something.
72 * However, occasionally you want to actually map the miptree's current data
73 * without transcoding back. This flag to intel_miptree_map() gets you that.
75 #define BRW_MAP_DIRECT_BIT 0x80000000
77 struct intel_miptree_map
{
78 /** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */
80 /** Region of interest for the map. */
82 /** Possibly malloced temporary buffer for the mapping. */
84 /** Possible pointer to a temporary linear miptree for the mapping. */
85 struct intel_mipmap_tree
*linear_mt
;
86 /** Pointer to the start of (map_x, map_y) returned by the mapping. */
88 /** Stride of the mapping. */
93 * Describes the location of each texture image within a miptree.
95 struct intel_mipmap_level
97 /** Offset to this miptree level, used in computing x_offset. */
99 /** Offset to this miptree level, used in computing y_offset. */
103 * \brief Number of 2D slices in this miplevel.
105 * The exact semantics of depth varies according to the texture target:
106 * - For GL_TEXTURE_CUBE_MAP, depth is 6.
107 * - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
108 * identical for all miplevels in the texture.
109 * - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
110 * value, like width and height, varies with miplevel.
111 * - For other texture types, depth is 1.
112 * - Additionally, for UMS and CMS miptrees, depth is multiplied by
118 * \brief Is HiZ enabled for this level?
120 * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
121 * allocated and (2) the HiZ memory for the slices in this level reside at
122 * \c mt->hiz_mt->level[l].
127 * \brief List of 2D images in this mipmap level.
129 * This may be a list of cube faces, array slices in 2D array texture, or
130 * layers in a 3D texture. The list's length is \c depth.
132 struct intel_mipmap_slice
{
134 * \name Offset to slice
137 * Hardware formats are so diverse that that there is no unified way to
138 * compute the slice offsets, so we store them in this table.
140 * The (x, y) offset to slice \c s at level \c l relative the miptrees
143 * x = mt->level[l].slice[s].x_offset
144 * y = mt->level[l].slice[s].y_offset
146 * On some hardware generations, we program these offsets into
147 * RENDER_SURFACE_STATE.XOffset and RENDER_SURFACE_STATE.YOffset.
154 * Mapping information. Persistent for the duration of
155 * intel_miptree_map/unmap on this slice.
157 struct intel_miptree_map
*map
;
162 * Enum for keeping track of the different MSAA layouts supported by Gen7.
164 enum intel_msaa_layout
167 * Ordinary surface with no MSAA.
169 INTEL_MSAA_LAYOUT_NONE
,
172 * Interleaved Multisample Surface. The additional samples are
173 * accommodated by scaling up the width and the height of the surface so
174 * that all the samples corresponding to a pixel are located at nearby
177 * @see PRM section "Interleaved Multisampled Surfaces"
179 INTEL_MSAA_LAYOUT_IMS
,
182 * Uncompressed Multisample Surface. The surface is stored as a 2D array,
183 * with array slice n containing all pixel data for sample n.
185 * @see PRM section "Uncompressed Multisampled Surfaces"
187 INTEL_MSAA_LAYOUT_UMS
,
190 * Compressed Multisample Surface. The surface is stored as in
191 * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
192 * (Multisample Control Surface) buffer. Each pixel in the MCS buffer
193 * indicates the mapping from sample number to array slice. This allows
194 * the common case (where all samples constituting a pixel have the same
195 * color value) to be stored efficiently by just using a single array
198 * @see PRM section "Compressed Multisampled Surfaces"
200 INTEL_MSAA_LAYOUT_CMS
,
203 enum miptree_array_layout
{
204 /* Each array slice contains all miplevels packed together.
206 * Gen hardware usually wants multilevel miptrees configured this way.
208 * A 2D Array texture with 2 slices and multiple LODs using
209 * ALL_LOD_IN_EACH_SLICE would look somewhat like this:
226 ALL_LOD_IN_EACH_SLICE
,
228 /* Each LOD contains all slices of that LOD packed together.
230 * In some situations, Gen7+ hardware can use the array_spacing_lod0
231 * feature to save space when the surface only contains LOD 0.
233 * Gen6 uses this for separate stencil and hiz since gen6 does not support
234 * multiple LODs for separate stencil and hiz.
236 * A 2D Array texture with 2 slices and multiple LODs using
237 * ALL_SLICES_AT_EACH_LOD would look somewhat like this:
252 ALL_SLICES_AT_EACH_LOD
,
254 /* On Sandy Bridge, HiZ and stencil buffers work the same as on Ivy Bridge
255 * except that they don't technically support mipmapping. That does not,
256 * however, stop us from doing it. As far as Sandy Bridge hardware is
257 * concerned, HiZ and stencil always operates on a single miplevel 2D
258 * (possibly array) image. The dimensions of that image are NOT minified.
260 * In order to implement HiZ and stencil on Sandy Bridge, we create one
261 * full-sized 2D (possibly array) image for every LOD with every image
262 * aligned to a page boundary. In order to save memory, we pretend that
263 * the width of each miplevel is minified and we place LOD1 and above below
264 * LOD0 but horizontally adjacent to each other. When considered as
265 * full-sized images, LOD1 and above technically overlap. However, since
266 * we only write to part of that image, the hardware will never notice the
269 * This layout looks something like this:
290 enum intel_aux_disable
{
291 INTEL_AUX_DISABLE_NONE
= 0,
292 INTEL_AUX_DISABLE_HIZ
= 1 << 1,
293 INTEL_AUX_DISABLE_MCS
= 1 << 2,
294 INTEL_AUX_DISABLE_CCS
= 1 << 3,
295 INTEL_AUX_DISABLE_ALL
= INTEL_AUX_DISABLE_HIZ
|
296 INTEL_AUX_DISABLE_MCS
|
297 INTEL_AUX_DISABLE_CCS
301 * Miptree aux buffer. These buffers are associated with a miptree, but the
302 * format is managed by the hardware.
304 * For Gen7+, we always give the hardware the start of the buffer, and let it
305 * handle all accesses to the buffer. Therefore we don't need the full miptree
306 * layout structure for this buffer.
308 struct intel_miptree_aux_buffer
310 struct isl_surf surf
;
313 * Buffer object containing the pixel data.
315 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
316 * @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
321 * Offset into bo where the surface starts.
323 * @see intel_mipmap_aux_buffer::bo
325 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
326 * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
327 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
328 * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
333 * Size of the MCS surface.
335 * This is needed when doing any gtt mapped operations on the buffer (which
336 * will be Y-tiled). It is possible that it will not be the same as bo->size
337 * when the drm allocator rounds up the requested size.
344 * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
345 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
350 * The distance in rows between array slices.
352 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch
353 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
358 struct intel_mipmap_tree
360 struct isl_surf surf
;
363 * Buffer object containing the surface.
365 * @see intel_mipmap_tree::offset
366 * @see RENDER_SURFACE_STATE.SurfaceBaseAddress
367 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
368 * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
369 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
370 * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
377 * @see RENDER_SURFACE_STATE.SurfacePitch
378 * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
379 * @see 3DSTATE_DEPTH_BUFFER.SurfacePitch
380 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
381 * @see 3DSTATE_STENCIL_BUFFER.SurfacePitch
386 * One of the I915_TILING_* flags.
388 * @see RENDER_SURFACE_STATE.TileMode
389 * @see 3DSTATE_DEPTH_BUFFER.TileMode
394 * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
396 * @see RENDER_SURFACE_STATE.SurfaceType
397 * @see RENDER_SURFACE_STATE.SurfaceArray
398 * @see 3DSTATE_DEPTH_BUFFER.SurfaceType
403 * Generally, this is just the same as the gl_texture_image->TexFormat or
404 * gl_renderbuffer->Format.
406 * However, for textures and renderbuffers with packed depth/stencil formats
407 * on hardware where we want or need to use separate stencil, there will be
408 * two miptrees for storing the data. If the depthstencil texture or rb is
409 * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
410 * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
411 * MESA_FORMAT_Z24_UNORM_X8_UINT.
413 * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
414 * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
416 * @see RENDER_SURFACE_STATE.SurfaceFormat
417 * @see 3DSTATE_DEPTH_BUFFER.SurfaceFormat
422 * This variable stores the value of ETC compressed texture format
424 * @see RENDER_SURFACE_STATE.SurfaceFormat
426 mesa_format etc_format
;
429 * @name Surface Alignment
432 * This defines the alignment of the upperleft pixel of each "slice" in the
433 * surface. The alignment is in pixel coordinates relative to the surface's
434 * most upperleft pixel, which is the pixel at (x=0, y=0, layer=0,
437 * The hardware docs do not use the term "slice". We use "slice" to mean
438 * the pixels at a given miplevel and layer. For 2D surfaces, the layer is
439 * the array slice; for 3D surfaces, the layer is the z offset.
441 * In the surface layout equations found in the hardware docs, the
442 * horizontal and vertical surface alignments often appear as variables 'i'
446 /** @see RENDER_SURFACE_STATE.SurfaceHorizontalAlignment */
449 /** @see RENDER_SURFACE_STATE.SurfaceVerticalAlignment */
457 * Level zero image dimensions. These dimensions correspond to the
458 * physical layout of data in memory. Accordingly, they account for the
459 * extra width, height, and or depth that must be allocated in order to
460 * accommodate multisample formats, and they account for the extra factor
461 * of 6 in depth that must be allocated in order to accommodate cubemap
464 GLuint physical_width0
, physical_height0
, physical_depth0
;
466 /** Bytes per pixel (or bytes per block if compressed) */
470 * @see RENDER_SURFACE_STATE.NumberOfMultisamples
471 * @see 3DSTATE_MULTISAMPLE.NumberOfMultisamples
478 * @name Level zero image dimensions
481 * These dimensions correspond to the
482 * logical width, height, and depth of the texture as seen by client code.
483 * Accordingly, they do not account for the extra width, height, and/or
484 * depth that must be allocated in order to accommodate multisample
485 * formats, nor do they account for the extra factor of 6 in depth that
486 * must be allocated in order to accommodate cubemap textures.
490 * @see RENDER_SURFACE_STATE.Width
491 * @see 3DSTATE_DEPTH_BUFFER.Width
493 uint32_t logical_width0
;
496 * @see RENDER_SURFACE_STATE.Height
497 * @see 3DSTATE_DEPTH_BUFFER.Height
499 uint32_t logical_height0
;
502 * @see RENDER_SURFACE_STATE.Depth
503 * @see 3DSTATE_DEPTH_BUFFER.Depth
505 uint32_t logical_depth0
;
509 * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
510 * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
512 enum miptree_array_layout array_layout
;
515 * The distance in between array slices.
517 * The value is the one that is sent in the surface state. The actual
518 * meaning depends on certain criteria. Usually it is simply the number of
519 * uncompressed rows between each slice. However on Gen9+ for compressed
520 * surfaces it is the number of blocks. For 1D array surfaces that have the
521 * mipmap tree stored horizontally it is the number of pixels between each
524 * @see RENDER_SURFACE_STATE.SurfaceQPitch
525 * @see 3DSTATE_DEPTH_BUFFER.SurfaceQPitch
526 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
527 * @see 3DSTATE_STENCIL_BUFFER.SurfaceQPitch
532 * MSAA layout used by this buffer.
534 * @see RENDER_SURFACE_STATE.MultisampledSurfaceStorageFormat
536 enum intel_msaa_layout msaa_layout
;
538 /* Derived from the above:
543 /* Includes image offset tables: */
544 struct intel_mipmap_level level
[MAX_TEXTURE_LEVELS
];
547 * Offset into bo where the surface starts.
549 * @see intel_mipmap_tree::bo
551 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
552 * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
553 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
554 * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
559 * \brief HiZ aux buffer
561 * To allocate the hiz buffer, use intel_miptree_alloc_hiz().
563 * To determine if hiz is enabled, do not check this pointer. Instead, use
564 * intel_miptree_level_has_hiz().
566 struct intel_miptree_aux_buffer
*hiz_buf
;
569 * \brief Maps miptree slices to their current aux state
571 * This two-dimensional array is indexed as [level][layer] and stores an
572 * aux state for each slice.
574 enum isl_aux_state
**aux_state
;
577 * \brief Stencil miptree for depthstencil textures.
579 * This miptree is used for depthstencil textures and renderbuffers that
580 * require separate stencil. It always has the true copy of the stencil
581 * bits, regardless of mt->format.
583 * \see 3DSTATE_STENCIL_BUFFER
584 * \see intel_miptree_map_depthstencil()
585 * \see intel_miptree_unmap_depthstencil()
587 struct intel_mipmap_tree
*stencil_mt
;
590 * \brief Stencil texturing miptree for sampling from a stencil texture
592 * Some hardware doesn't support sampling from the stencil texture as
593 * required by the GL_ARB_stencil_texturing extenion. To workaround this we
594 * blit the texture into a new texture that can be sampled.
596 * \see intel_update_r8stencil()
598 struct intel_mipmap_tree
*r8stencil_mt
;
599 bool r8stencil_needs_update
;
602 * \brief MCS auxiliary buffer.
604 * This buffer contains the "multisample control surface", which stores
605 * the necessary information to implement compressed MSAA
606 * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
608 * NULL if no MCS buffer is in use for this surface.
610 struct intel_miptree_aux_buffer
*mcs_buf
;
613 * Planes 1 and 2 in case this is a planar surface.
615 struct intel_mipmap_tree
*plane
[2];
618 * Fast clear color for this surface. For depth surfaces, the clear value
619 * is stored as a float32 in the red component.
621 union isl_color_value fast_clear_color
;
624 * Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS
625 * buffer. This is useful for sharing the miptree bo with an external client
626 * that doesn't understand auxiliary buffers.
628 enum intel_aux_disable aux_disable
;
631 * Tells if the underlying buffer is to be also consumed by entities other
632 * than the driver. This allows logic to turn off features such as lossless
633 * compression which is not currently understood by client applications.
637 /* These are also refcounted:
643 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
644 const struct intel_mipmap_tree
*mt
);
647 intel_miptree_alloc_ccs(struct brw_context
*brw
,
648 struct intel_mipmap_tree
*mt
,
652 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
= 1 << 0,
653 MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
= 1 << 1,
654 MIPTREE_LAYOUT_FOR_BO
= 1 << 2,
655 MIPTREE_LAYOUT_DISABLE_AUX
= 1 << 3,
656 MIPTREE_LAYOUT_FORCE_HALIGN16
= 1 << 4,
658 MIPTREE_LAYOUT_TILING_Y
= 1 << 5,
659 MIPTREE_LAYOUT_TILING_NONE
= 1 << 6,
660 MIPTREE_LAYOUT_TILING_ANY
= MIPTREE_LAYOUT_TILING_Y
|
661 MIPTREE_LAYOUT_TILING_NONE
,
663 MIPTREE_LAYOUT_FOR_SCANOUT
= 1 << 7,
666 struct intel_mipmap_tree
*intel_miptree_create(struct brw_context
*brw
,
677 struct intel_mipmap_tree
*
678 intel_miptree_create_for_bo(struct brw_context
*brw
,
686 uint32_t layout_flags
);
689 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
690 struct intel_renderbuffer
*irb
,
692 uint32_t width
, uint32_t height
,
696 * Create a miptree appropriate as the storage for a non-texture renderbuffer.
697 * The miptree has the following properties:
698 * - The target is GL_TEXTURE_2D.
699 * - There are no levels other than the base level 0.
702 struct intel_mipmap_tree
*
703 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
707 uint32_t num_samples
);
710 intel_depth_format_for_depthstencil_format(mesa_format format
);
713 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
);
715 /** \brief Assert that the level and layer are valid for the miptree. */
717 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
721 void intel_miptree_reference(struct intel_mipmap_tree
**dst
,
722 struct intel_mipmap_tree
*src
);
724 void intel_miptree_release(struct intel_mipmap_tree
**mt
);
726 /* Check if an image fits an existing mipmap tree layout
728 bool intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
729 struct gl_texture_image
*image
);
732 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
733 GLuint level
, GLuint slice
,
734 GLuint
*x
, GLuint
*y
);
737 get_isl_surf_dim(GLenum target
);
740 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
741 GLenum target
, enum miptree_array_layout array_layout
);
744 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
);
747 intel_miptree_get_isl_surf(struct brw_context
*brw
,
748 const struct intel_mipmap_tree
*mt
,
749 struct isl_surf
*surf
);
752 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
753 const struct intel_mipmap_tree
*mt
);
756 intel_get_image_dims(struct gl_texture_image
*image
,
757 int *width
, int *height
, int *depth
);
760 intel_get_tile_masks(uint32_t tiling
, uint32_t cpp
,
761 uint32_t *mask_x
, uint32_t *mask_y
);
764 intel_get_tile_dims(uint32_t tiling
, uint32_t cpp
,
765 uint32_t *tile_w
, uint32_t *tile_h
);
768 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
769 GLuint level
, GLuint slice
,
773 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
774 uint32_t x
, uint32_t y
);
776 void intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
778 GLuint x
, GLuint y
, GLuint d
);
780 void intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
782 GLuint img
, GLuint x
, GLuint y
);
785 intel_miptree_copy_slice(struct brw_context
*brw
,
786 struct intel_mipmap_tree
*src_mt
,
787 unsigned src_level
, unsigned src_layer
,
788 struct intel_mipmap_tree
*dst_mt
,
789 unsigned dst_level
, unsigned dst_layer
);
792 intel_miptree_copy_teximage(struct brw_context
*brw
,
793 struct intel_texture_image
*intelImage
,
794 struct intel_mipmap_tree
*dst_mt
, bool invalidate
);
797 * \name Miptree HiZ functions
800 * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
801 * functions on a miptree without HiZ. In that case, each function is a no-op.
805 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
806 struct intel_mipmap_tree
*mt
);
809 * \brief Allocate the miptree's embedded HiZ miptree.
810 * \see intel_mipmap_tree:hiz_mt
811 * \return false if allocation failed
814 intel_miptree_alloc_hiz(struct brw_context
*brw
,
815 struct intel_mipmap_tree
*mt
);
818 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
);
823 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
824 unsigned start_level
, unsigned num_levels
,
825 unsigned start_layer
, unsigned num_layers
);
828 #define INTEL_REMAINING_LAYERS UINT32_MAX
829 #define INTEL_REMAINING_LEVELS UINT32_MAX
831 /** Prepare a miptree for access
833 * This function should be called prior to any access to miptree in order to
834 * perform any needed resolves.
836 * \param[in] start_level The first mip level to be accessed
838 * \param[in] num_levels The number of miplevels to be accessed or
839 * INTEL_REMAINING_LEVELS to indicate every level
840 * above start_level will be accessed
842 * \param[in] start_layer The first array slice or 3D layer to be accessed
844 * \param[in] num_layers The number of array slices or 3D layers be
845 * accessed or INTEL_REMAINING_LAYERS to indicate
846 * every layer above start_layer will be accessed
848 * \param[in] aux_supported Whether or not the access will support the
849 * miptree's auxiliary compression format; this
850 * must be false for uncompressed miptrees
852 * \param[in] fast_clear_supported Whether or not the access will support
853 * fast clears in the miptree's auxiliary
857 intel_miptree_prepare_access(struct brw_context
*brw
,
858 struct intel_mipmap_tree
*mt
,
859 uint32_t start_level
, uint32_t num_levels
,
860 uint32_t start_layer
, uint32_t num_layers
,
861 bool aux_supported
, bool fast_clear_supported
);
863 /** Complete a write operation
865 * This function should be called after any operation writes to a miptree.
866 * This will update the miptree's compression state so that future resolves
867 * happen correctly. Technically, this function can be called before the
868 * write occurs but the caller must ensure that they don't interlace
869 * intel_miptree_prepare_access and intel_miptree_finish_write calls to
870 * overlapping layer/level ranges.
872 * \param[in] level The mip level that was written
874 * \param[in] start_layer The first array slice or 3D layer written
876 * \param[in] num_layers The number of array slices or 3D layers
877 * written or INTEL_REMAINING_LAYERS to indicate
878 * every layer above start_layer was written
880 * \param[in] written_with_aux Whether or not the write was done with
881 * auxiliary compression enabled
884 intel_miptree_finish_write(struct brw_context
*brw
,
885 struct intel_mipmap_tree
*mt
, uint32_t level
,
886 uint32_t start_layer
, uint32_t num_layers
,
887 bool written_with_aux
);
889 /** Get the auxiliary compression state of a miptree slice */
891 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
892 uint32_t level
, uint32_t layer
);
894 /** Set the auxiliary compression state of a miptree slice range
896 * This function directly sets the auxiliary compression state of a slice
897 * range of a miptree. It only modifies data structures and does not do any
898 * resolves. This should only be called by code which directly performs
899 * compression operations such as fast clears and resolves. Most code should
900 * use intel_miptree_prepare_access or intel_miptree_finish_write.
903 intel_miptree_set_aux_state(struct brw_context
*brw
,
904 struct intel_mipmap_tree
*mt
, uint32_t level
,
905 uint32_t start_layer
, uint32_t num_layers
,
906 enum isl_aux_state aux_state
);
909 * Prepare a miptree for raw access
911 * This helper prepares the miptree for access that knows nothing about any
912 * sort of compression whatsoever. This is useful when mapping the surface or
913 * using it with the blitter.
916 intel_miptree_access_raw(struct brw_context
*brw
,
917 struct intel_mipmap_tree
*mt
,
918 uint32_t level
, uint32_t layer
,
921 intel_miptree_prepare_access(brw
, mt
, level
, 1, layer
, 1, false, false);
923 intel_miptree_finish_write(brw
, mt
, level
, layer
, 1, false);
927 intel_miptree_prepare_texture(struct brw_context
*brw
,
928 struct intel_mipmap_tree
*mt
,
929 mesa_format view_format
,
930 bool *aux_supported_out
);
932 intel_miptree_prepare_image(struct brw_context
*brw
,
933 struct intel_mipmap_tree
*mt
);
935 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
936 struct intel_mipmap_tree
*mt
, uint32_t level
,
937 uint32_t start_layer
, uint32_t num_layers
);
939 intel_miptree_prepare_render(struct brw_context
*brw
,
940 struct intel_mipmap_tree
*mt
, uint32_t level
,
941 uint32_t start_layer
, uint32_t layer_count
,
944 intel_miptree_finish_render(struct brw_context
*brw
,
945 struct intel_mipmap_tree
*mt
, uint32_t level
,
946 uint32_t start_layer
, uint32_t layer_count
);
948 intel_miptree_prepare_depth(struct brw_context
*brw
,
949 struct intel_mipmap_tree
*mt
, uint32_t level
,
950 uint32_t start_layer
, uint32_t layer_count
);
952 intel_miptree_finish_depth(struct brw_context
*brw
,
953 struct intel_mipmap_tree
*mt
, uint32_t level
,
954 uint32_t start_layer
, uint32_t layer_count
,
958 intel_miptree_make_shareable(struct brw_context
*brw
,
959 struct intel_mipmap_tree
*mt
);
962 intel_miptree_updownsample(struct brw_context
*brw
,
963 struct intel_mipmap_tree
*src
,
964 struct intel_mipmap_tree
*dst
);
967 intel_update_r8stencil(struct brw_context
*brw
,
968 struct intel_mipmap_tree
*mt
);
971 * Horizontal distance from one slice to the next in the two-dimensional
975 brw_miptree_get_horizontal_slice_pitch(const struct brw_context
*brw
,
976 const struct intel_mipmap_tree
*mt
,
980 * Vertical distance from one slice to the next in the two-dimensional miptree
984 brw_miptree_get_vertical_slice_pitch(const struct brw_context
*brw
,
985 const struct intel_mipmap_tree
*mt
,
989 brw_miptree_layout(struct brw_context
*brw
,
990 struct intel_mipmap_tree
*mt
,
991 uint32_t layout_flags
);
994 intel_miptree_map(struct brw_context
*brw
,
995 struct intel_mipmap_tree
*mt
,
1004 ptrdiff_t *out_stride
);
1007 intel_miptree_unmap(struct brw_context
*brw
,
1008 struct intel_mipmap_tree
*mt
,
1010 unsigned int slice
);
1013 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1014 struct intel_mipmap_tree
*mt
);