src/mesa/drivers/dri/i965/intel_mipmap_tree.h

   1 /**************************************************************************
   2  *
   3  * Copyright 2006 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /** @file intel_mipmap_tree.h
  29  *
  30  * This file defines the structure that wraps a BO and describes how the
  31  * mipmap levels and slices of a texture are laid out.
  32  *
  33  * The hardware has a fixed layout of a texture depending on parameters such
  34  * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
  35  * mipmap levels.  The individual level/layer slices are each 2D rectangles of
  36  * pixels at some x/y offset from the start of the drm_intel_bo.
  37  *
  38  * Original OpenGL allowed texture miplevels to be specified in arbitrary
  39  * order, and a texture may change size over time.  Thus, each
  40  * intel_texture_image has a reference to a miptree that contains the pixel
  41  * data sized appropriately for it, which will later be referenced by/copied
  42  * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
  43  * that there's a single miptree for the complete texture.
  44  */
  45
  46 #ifndef INTEL_MIPMAP_TREE_H
  47 #define INTEL_MIPMAP_TREE_H
  48
  49 #include <assert.h>
  50
  51 #include "main/mtypes.h"
  52 #include "intel_bufmgr.h"
  53 #include "intel_resolve_map.h"
  54 #include <GL/internal/dri_interface.h>
  55
  56 #ifdef __cplusplus
  57 extern "C" {
  58 #endif
  59
  60 struct brw_context;
  61 struct intel_renderbuffer;
  62
  63 struct intel_resolve_map;
  64 struct intel_texture_image;
  65
  66 /**
  67  * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
  68  * depthstencil-split-to-separate-stencil miptree, we'll normally make a
  69  * tmeporary and recreate the kind of data requested by Mesa core, since we're
  70  * satisfying some glGetTexImage() request or something.
  71  *
  72  * However, occasionally you want to actually map the miptree's current data
  73  * without transcoding back.  This flag to intel_miptree_map() gets you that.
  74  */
  75 #define BRW_MAP_DIRECT_BIT      0x80000000
  76
  77 struct intel_miptree_map {
  78    /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
  79    GLbitfield mode;
  80    /** Region of interest for the map. */
  81    int x, y, w, h;
  82    /** Possibly malloced temporary buffer for the mapping. */
  83    void *buffer;
  84    /** Possible pointer to a temporary linear miptree for the mapping. */
  85    struct intel_mipmap_tree *mt;
  86    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  87    void *ptr;
  88    /** Stride of the mapping. */
  89    int stride;
  90 };
  91
  92 /**
  93  * Describes the location of each texture image within a miptree.
  94  */
  95 struct intel_mipmap_level
  96 {
  97    /** Offset to this miptree level, used in computing x_offset. */
  98    GLuint level_x;
  99    /** Offset to this miptree level, used in computing y_offset. */
 100    GLuint level_y;
 101
 102    /**
 103     * \brief Number of 2D slices in this miplevel.
 104     *
 105     * The exact semantics of depth varies according to the texture target:
 106     *    - For GL_TEXTURE_CUBE_MAP, depth is 6.
 107     *    - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
 108     *      identical for all miplevels in the texture.
 109     *    - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
 110     *      value, like width and height, varies with miplevel.
 111     *    - For other texture types, depth is 1.
 112     *    - Additionally, for UMS and CMS miptrees, depth is multiplied by
 113     *      sample count.
 114     */
 115    GLuint depth;
 116
 117    /**
 118     * \brief Is HiZ enabled for this level?
 119     *
 120     * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
 121     * allocated and (2) the HiZ memory for the slices in this level reside at
 122     * \c mt->hiz_mt->level[l].
 123     */
 124    bool has_hiz;
 125
 126    /**
 127     * \brief List of 2D images in this mipmap level.
 128     *
 129     * This may be a list of cube faces, array slices in 2D array texture, or
 130     * layers in a 3D texture. The list's length is \c depth.
 131     */
 132    struct intel_mipmap_slice {
 133       /**
 134        * \name Offset to slice
 135        * \{
 136        *
 137        * Hardware formats are so diverse that that there is no unified way to
 138        * compute the slice offsets, so we store them in this table.
 139        *
 140        * The (x, y) offset to slice \c s at level \c l relative the miptrees
 141        * base address is
 142        * \code
 143        *     x = mt->level[l].slice[s].x_offset
 144        *     y = mt->level[l].slice[s].y_offset
 145        */
 146       GLuint x_offset;
 147       GLuint y_offset;
 148       /** \} */
 149
 150       /**
 151        * Mapping information. Persistent for the duration of
 152        * intel_miptree_map/unmap on this slice.
 153        */
 154       struct intel_miptree_map *map;
 155    } *slice;
 156 };
 157
 158 /**
 159  * Enum for keeping track of the different MSAA layouts supported by Gen7.
 160  */
 161 enum intel_msaa_layout
 162 {
 163    /**
 164     * Ordinary surface with no MSAA.
 165     */
 166    INTEL_MSAA_LAYOUT_NONE,
 167
 168    /**
 169     * Interleaved Multisample Surface.  The additional samples are
 170     * accommodated by scaling up the width and the height of the surface so
 171     * that all the samples corresponding to a pixel are located at nearby
 172     * memory locations.
 173     */
 174    INTEL_MSAA_LAYOUT_IMS,
 175
 176    /**
 177     * Uncompressed Multisample Surface.  The surface is stored as a 2D array,
 178     * with array slice n containing all pixel data for sample n.
 179     */
 180    INTEL_MSAA_LAYOUT_UMS,
 181
 182    /**
 183     * Compressed Multisample Surface.  The surface is stored as in
 184     * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
 185     * (Multisample Control Surface) buffer.  Each pixel in the MCS buffer
 186     * indicates the mapping from sample number to array slice.  This allows
 187     * the common case (where all samples constituting a pixel have the same
 188     * color value) to be stored efficiently by just using a single array
 189     * slice.
 190     */
 191    INTEL_MSAA_LAYOUT_CMS,
 192 };
 193
 194
 195 /**
 196  * Enum for keeping track of the fast clear state of a buffer associated with
 197  * a miptree.
 198  *
 199  * Fast clear works by deferring the memory writes that would be used to clear
 200  * the buffer, so that instead of performing them at the time of the clear
 201  * operation, the hardware automatically performs them at the time that the
 202  * buffer is later accessed for rendering.  The MCS buffer keeps track of
 203  * which regions of the buffer still have pending clear writes.
 204  *
 205  * This enum keeps track of the driver's knowledge of pending fast clears in
 206  * the MCS buffer.
 207  *
 208  * MCS buffers only exist on Gen7+.
 209  */
 210 enum intel_fast_clear_state
 211 {
 212    /**
 213     * There is no MCS buffer for this miptree, and one should never be
 214     * allocated.
 215     */
 216    INTEL_FAST_CLEAR_STATE_NO_MCS,
 217
 218    /**
 219     * No deferred clears are pending for this miptree, and the contents of the
 220     * color buffer are entirely correct.  An MCS buffer may or may not exist
 221     * for this miptree.  If it does exist, it is entirely in the "no deferred
 222     * clears pending" state.  If it does not exist, it will be created the
 223     * first time a fast color clear is executed.
 224     *
 225     * In this state, the color buffer can be used for purposes other than
 226     * rendering without needing a render target resolve.
 227     *
 228     * Since there is no such thing as a "fast color clear resolve" for MSAA
 229     * buffers, an MSAA buffer will never be in this state.
 230     */
 231    INTEL_FAST_CLEAR_STATE_RESOLVED,
 232
 233    /**
 234     * An MCS buffer exists for this miptree, and deferred clears are pending
 235     * for some regions of the color buffer, as indicated by the MCS buffer.
 236     * The contents of the color buffer are only correct for the regions where
 237     * the MCS buffer doesn't indicate a deferred clear.
 238     *
 239     * If a single-sample buffer is in this state, a render target resolve must
 240     * be performed before it can be used for purposes other than rendering.
 241     */
 242    INTEL_FAST_CLEAR_STATE_UNRESOLVED,
 243
 244    /**
 245     * An MCS buffer exists for this miptree, and deferred clears are pending
 246     * for the entire color buffer, and the contents of the MCS buffer reflect
 247     * this.  The contents of the color buffer are undefined.
 248     *
 249     * If a single-sample buffer is in this state, a render target resolve must
 250     * be performed before it can be used for purposes other than rendering.
 251     *
 252     * If the client attempts to clear a buffer which is already in this state,
 253     * the clear can be safely skipped, since the buffer is already clear.
 254     */
 255    INTEL_FAST_CLEAR_STATE_CLEAR,
 256 };
 257
 258 struct intel_mipmap_tree
 259 {
 260    /** Buffer object containing the pixel data. */
 261    drm_intel_bo *bo;
 262
 263    uint32_t pitch; /**< pitch in bytes. */
 264
 265    uint32_t tiling; /**< One of the I915_TILING_* flags */
 266
 267    /* Effectively the key:
 268     */
 269    GLenum target;
 270
 271    /**
 272     * Generally, this is just the same as the gl_texture_image->TexFormat or
 273     * gl_renderbuffer->Format.
 274     *
 275     * However, for textures and renderbuffers with packed depth/stencil formats
 276     * on hardware where we want or need to use separate stencil, there will be
 277     * two miptrees for storing the data.  If the depthstencil texture or rb is
 278     * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
 279     * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
 280     * MESA_FORMAT_Z24_UNORM_X8_UINT.
 281     *
 282     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
 283     * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
 284     */
 285    mesa_format format;
 286
 287    /** This variable stores the value of ETC compressed texture format */
 288    mesa_format etc_format;
 289
 290    /**
 291     * The X offset of each image in the miptree must be aligned to this.
 292     * See the comments in brw_tex_layout.c.
 293     */
 294    unsigned int align_w;
 295    unsigned int align_h; /**< \see align_w */
 296
 297    GLuint first_level;
 298    GLuint last_level;
 299
 300    /**
 301     * Level zero image dimensions.  These dimensions correspond to the
 302     * physical layout of data in memory.  Accordingly, they account for the
 303     * extra width, height, and or depth that must be allocated in order to
 304     * accommodate multisample formats, and they account for the extra factor
 305     * of 6 in depth that must be allocated in order to accommodate cubemap
 306     * textures.
 307     */
 308    GLuint physical_width0, physical_height0, physical_depth0;
 309
 310    GLuint cpp; /**< bytes per pixel */
 311    GLuint num_samples;
 312    bool compressed;
 313
 314    /**
 315     * Level zero image dimensions.  These dimensions correspond to the
 316     * logical width, height, and depth of the texture as seen by client code.
 317     * Accordingly, they do not account for the extra width, height, and/or
 318     * depth that must be allocated in order to accommodate multisample
 319     * formats, nor do they account for the extra factor of 6 in depth that
 320     * must be allocated in order to accommodate cubemap textures.
 321     */
 322    uint32_t logical_width0, logical_height0, logical_depth0;
 323
 324    /**
 325     * For 1D array, 2D array, cube, and 2D multisampled surfaces on Gen7: true
 326     * if the surface only contains LOD 0, and hence no space is for LOD's
 327     * other than 0 in between array slices.
 328     *
 329     * Corresponds to the surface_array_spacing bit in gen7_surface_state.
 330     */
 331    bool array_spacing_lod0;
 332
 333    /**
 334     * The distance in rows between array slices in an uncompressed surface.
 335     *
 336     * For compressed surfaces, slices are stored closer together physically;
 337     * the real distance is (qpitch / block height).
 338     */
 339    uint32_t qpitch;
 340
 341    /**
 342     * MSAA layout used by this buffer.
 343     */
 344    enum intel_msaa_layout msaa_layout;
 345
 346    /* Derived from the above:
 347     */
 348    GLuint total_width;
 349    GLuint total_height;
 350
 351    /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to
 352     * this depth mipmap tree, if any.
 353     */
 354    uint32_t depth_clear_value;
 355
 356    /* Includes image offset tables:
 357     */
 358    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 359
 360    /* Offset into bo where miptree starts:
 361     */
 362    uint32_t offset;
 363
 364    /**
 365     * \brief HiZ miptree
 366     *
 367     * The hiz miptree contains the miptree's hiz buffer. To allocate the hiz
 368     * miptree, use intel_miptree_alloc_hiz().
 369     *
 370     * To determine if hiz is enabled, do not check this pointer. Instead, use
 371     * intel_miptree_slice_has_hiz().
 372     */
 373    struct intel_mipmap_tree *hiz_mt;
 374
 375    /**
 376     * \brief Map of miptree slices to needed resolves.
 377     *
 378     * This is used only when the miptree has a child HiZ miptree.
 379     *
 380     * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
 381     * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
 382     * mt->hiz_mt->hiz_map, is unused.
 383     */
 384    struct exec_list hiz_map; /* List of intel_resolve_map. */
 385
 386    /**
 387     * \brief Stencil miptree for depthstencil textures.
 388     *
 389     * This miptree is used for depthstencil textures and renderbuffers that
 390     * require separate stencil.  It always has the true copy of the stencil
 391     * bits, regardless of mt->format.
 392     *
 393     * \see intel_miptree_map_depthstencil()
 394     * \see intel_miptree_unmap_depthstencil()
 395     */
 396    struct intel_mipmap_tree *stencil_mt;
 397
 398    /**
 399     * \brief MCS miptree.
 400     *
 401     * This miptree contains the "multisample control surface", which stores
 402     * the necessary information to implement compressed MSAA
 403     * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
 404     *
 405     * NULL if no MCS miptree is in use for this surface.
 406     */
 407    struct intel_mipmap_tree *mcs_mt;
 408
 409    /**
 410     * Fast clear state for this buffer.
 411     */
 412    enum intel_fast_clear_state fast_clear_state;
 413
 414    /**
 415     * The SURFACE_STATE bits associated with the last fast color clear to this
 416     * color mipmap tree, if any.
 417     *
 418     * This value will only ever contain ones in bits 28-31, so it is safe to
 419     * OR into dword 7 of SURFACE_STATE.
 420     */
 421    uint32_t fast_clear_color_value;
 422
 423    /* These are also refcounted:
 424     */
 425    GLuint refcount;
 426 };
 427
 428 enum intel_miptree_tiling_mode {
 429    INTEL_MIPTREE_TILING_ANY,
 430    INTEL_MIPTREE_TILING_Y,
 431    INTEL_MIPTREE_TILING_NONE,
 432 };
 433
 434 bool
 435 intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
 436                                        struct intel_mipmap_tree *mt);
 437
 438 void
 439 intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
 440                                  struct intel_mipmap_tree *mt,
 441                                  unsigned *width_px, unsigned *height);
 442
 443 bool
 444 intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
 445                                  struct intel_mipmap_tree *mt);
 446
 447 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
 448                                                GLenum target,
 449                                                mesa_format format,
 450                                                GLuint first_level,
 451                                                GLuint last_level,
 452                                                GLuint width0,
 453                                                GLuint height0,
 454                                                GLuint depth0,
 455                                                bool expect_accelerated_upload,
 456                                                GLuint num_samples,
 457                                                enum intel_miptree_tiling_mode);
 458
 459 struct intel_mipmap_tree *
 460 intel_miptree_create_layout(struct brw_context *brw,
 461                             GLenum target,
 462                             mesa_format format,
 463                             GLuint first_level,
 464                             GLuint last_level,
 465                             GLuint width0,
 466                             GLuint height0,
 467                             GLuint depth0,
 468                             bool for_bo,
 469                             GLuint num_samples);
 470
 471 struct intel_mipmap_tree *
 472 intel_miptree_create_for_bo(struct brw_context *brw,
 473                             drm_intel_bo *bo,
 474                             mesa_format format,
 475                             uint32_t offset,
 476                             uint32_t width,
 477                             uint32_t height,
 478                             int pitch);
 479
 480 void
 481 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
 482                                          struct intel_renderbuffer *irb,
 483                                          drm_intel_bo *bo,
 484                                          uint32_t width, uint32_t height,
 485                                          uint32_t pitch);
 486
 487 /**
 488  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 489  * The miptree has the following properties:
 490  *     - The target is GL_TEXTURE_2D.
 491  *     - There are no levels other than the base level 0.
 492  *     - Depth is 1.
 493  */
 494 struct intel_mipmap_tree*
 495 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
 496                                       mesa_format format,
 497                                       uint32_t width,
 498                                       uint32_t height,
 499                                       uint32_t num_samples);
 500
 501 mesa_format
 502 intel_depth_format_for_depthstencil_format(mesa_format format);
 503
 504 mesa_format
 505 intel_lower_compressed_format(struct brw_context *brw, mesa_format format);
 506
 507 /** \brief Assert that the level and layer are valid for the miptree. */
 508 static inline void
 509 intel_miptree_check_level_layer(struct intel_mipmap_tree *mt,
 510                                 uint32_t level,
 511                                 uint32_t layer)
 512 {
 513    assert(level >= mt->first_level);
 514    assert(level <= mt->last_level);
 515    assert(layer < mt->level[level].depth);
 516 }
 517
 518 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 519                              struct intel_mipmap_tree *src);
 520
 521 void intel_miptree_release(struct intel_mipmap_tree **mt);
 522
 523 /* Check if an image fits an existing mipmap tree layout
 524  */
 525 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 526                                     struct gl_texture_image *image);
 527
 528 void
 529 intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt,
 530                                GLuint level, GLuint slice,
 531                                GLuint *x, GLuint *y);
 532
 533 void
 534 intel_miptree_get_dimensions_for_image(struct gl_texture_image *image,
 535                                        int *width, int *height, int *depth);
 536
 537 void
 538 intel_miptree_get_tile_masks(const struct intel_mipmap_tree *mt,
 539                              uint32_t *mask_x, uint32_t *mask_y,
 540                              bool map_stencil_as_y_tiled);
 541
 542 uint32_t
 543 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
 544                                GLuint level, GLuint slice,
 545                                uint32_t *tile_x,
 546                                uint32_t *tile_y);
 547 uint32_t
 548 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
 549                                  uint32_t x, uint32_t y,
 550                                  bool map_stencil_as_y_tiled);
 551
 552 void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
 553                                   GLuint level,
 554                                   GLuint x, GLuint y, GLuint d);
 555
 556 void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
 557                                     GLuint level,
 558                                     GLuint img, GLuint x, GLuint y);
 559
 560 void
 561 intel_miptree_copy_teximage(struct brw_context *brw,
 562                             struct intel_texture_image *intelImage,
 563                             struct intel_mipmap_tree *dst_mt, bool invalidate);
 564
 565 bool
 566 intel_miptree_alloc_mcs(struct brw_context *brw,
 567                         struct intel_mipmap_tree *mt,
 568                         GLuint num_samples);
 569
 570 /**
 571  * \name Miptree HiZ functions
 572  * \{
 573  *
 574  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 575  * functions on a miptree without HiZ. In that case, each function is a no-op.
 576  */
 577
 578 /**
 579  * \brief Allocate the miptree's embedded HiZ miptree.
 580  * \see intel_mipmap_tree:hiz_mt
 581  * \return false if allocation failed
 582  */
 583
 584 bool
 585 intel_miptree_alloc_hiz(struct brw_context *brw,
 586                         struct intel_mipmap_tree *mt);
 587
 588 bool
 589 intel_miptree_level_has_hiz(struct intel_mipmap_tree *mt, uint32_t level);
 590
 591 void
 592 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt,
 593                                           uint32_t level,
 594                                           uint32_t depth);
 595 void
 596 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt,
 597                                             uint32_t level,
 598                                             uint32_t depth);
 599
 600 void
 601 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree *mt,
 602                                                 uint32_t level);
 603
 604 /**
 605  * \return false if no resolve was needed
 606  */
 607 bool
 608 intel_miptree_slice_resolve_hiz(struct brw_context *brw,
 609                                 struct intel_mipmap_tree *mt,
 610                                 unsigned int level,
 611                                 unsigned int depth);
 612
 613 /**
 614  * \return false if no resolve was needed
 615  */
 616 bool
 617 intel_miptree_slice_resolve_depth(struct brw_context *brw,
 618                                   struct intel_mipmap_tree *mt,
 619                                   unsigned int level,
 620                                   unsigned int depth);
 621
 622 /**
 623  * \return false if no resolve was needed
 624  */
 625 bool
 626 intel_miptree_all_slices_resolve_hiz(struct brw_context *brw,
 627                                      struct intel_mipmap_tree *mt);
 628
 629 /**
 630  * \return false if no resolve was needed
 631  */
 632 bool
 633 intel_miptree_all_slices_resolve_depth(struct brw_context *brw,
 634                                        struct intel_mipmap_tree *mt);
 635
 636 /**\}*/
 637
 638 /**
 639  * Update the fast clear state for a miptree to indicate that it has been used
 640  * for rendering.
 641  */
 642 static inline void
 643 intel_miptree_used_for_rendering(struct intel_mipmap_tree *mt)
 644 {
 645    /* If the buffer was previously in fast clear state, change it to
 646     * unresolved state, since it won't be guaranteed to be clear after
 647     * rendering occurs.
 648     */
 649    if (mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR)
 650       mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
 651 }
 652
 653 void
 654 intel_miptree_resolve_color(struct brw_context *brw,
 655                             struct intel_mipmap_tree *mt);
 656
 657 void
 658 intel_miptree_make_shareable(struct brw_context *brw,
 659                              struct intel_mipmap_tree *mt);
 660
 661 void
 662 intel_miptree_updownsample(struct brw_context *brw,
 663                            struct intel_mipmap_tree *src,
 664                            struct intel_mipmap_tree *dst);
 665
 666 void brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt);
 667
 668 void *intel_miptree_map_raw(struct brw_context *brw,
 669                             struct intel_mipmap_tree *mt);
 670
 671 void intel_miptree_unmap_raw(struct brw_context *brw,
 672                              struct intel_mipmap_tree *mt);
 673
 674 void
 675 intel_miptree_map(struct brw_context *brw,
 676                   struct intel_mipmap_tree *mt,
 677                   unsigned int level,
 678                   unsigned int slice,
 679                   unsigned int x,
 680                   unsigned int y,
 681                   unsigned int w,
 682                   unsigned int h,
 683                   GLbitfield mode,
 684                   void **out_ptr,
 685                   int *out_stride);
 686
 687 void
 688 intel_miptree_unmap(struct brw_context *brw,
 689                     struct intel_mipmap_tree *mt,
 690                     unsigned int level,
 691                     unsigned int slice);
 692
 693 void
 694 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 695                unsigned int level, unsigned int layer, enum gen6_hiz_op op);
 696
 697 #ifdef __cplusplus
 698 }
 699 #endif
 700
 701 #endif