src/mesa/drivers/dri/i965/intel_mipmap_tree.h

   1 /*
   2  * Copyright 2006 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 /** @file intel_mipmap_tree.h
  27  *
  28  * This file defines the structure that wraps a BO and describes how the
  29  * mipmap levels and slices of a texture are laid out.
  30  *
  31  * The hardware has a fixed layout of a texture depending on parameters such
  32  * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
  33  * mipmap levels.  The individual level/layer slices are each 2D rectangles of
  34  * pixels at some x/y offset from the start of the drm_intel_bo.
  35  *
  36  * Original OpenGL allowed texture miplevels to be specified in arbitrary
  37  * order, and a texture may change size over time.  Thus, each
  38  * intel_texture_image has a reference to a miptree that contains the pixel
  39  * data sized appropriately for it, which will later be referenced by/copied
  40  * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
  41  * that there's a single miptree for the complete texture.
  42  */
  43
  44 #ifndef INTEL_MIPMAP_TREE_H
  45 #define INTEL_MIPMAP_TREE_H
  46
  47 #include <assert.h>
  48
  49 #include "main/mtypes.h"
  50 #include "isl/isl.h"
  51 #include "intel_bufmgr.h"
  52 #include "intel_resolve_map.h"
  53 #include <GL/internal/dri_interface.h>
  54
  55 #ifdef __cplusplus
  56 extern "C" {
  57 #endif
  58
  59 struct brw_context;
  60 struct intel_renderbuffer;
  61
  62 struct intel_resolve_map;
  63 struct intel_texture_image;
  64
  65 /**
  66  * This bit extends the set of GL_MAP_*_BIT enums.
  67  *
  68  * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
  69  * depthstencil-split-to-separate-stencil miptree, we'll normally make a
  70  * temporary and recreate the kind of data requested by Mesa core, since we're
  71  * satisfying some glGetTexImage() request or something.
  72  *
  73  * However, occasionally you want to actually map the miptree's current data
  74  * without transcoding back.  This flag to intel_miptree_map() gets you that.
  75  */
  76 #define BRW_MAP_DIRECT_BIT      0x80000000
  77
  78 struct intel_miptree_map {
  79    /** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */
  80    GLbitfield mode;
  81    /** Region of interest for the map. */
  82    int x, y, w, h;
  83    /** Possibly malloced temporary buffer for the mapping. */
  84    void *buffer;
  85    /** Possible pointer to a temporary linear miptree for the mapping. */
  86    struct intel_mipmap_tree *linear_mt;
  87    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  88    void *ptr;
  89    /** Stride of the mapping. */
  90    int stride;
  91 };
  92
  93 /**
  94  * Describes the location of each texture image within a miptree.
  95  */
  96 struct intel_mipmap_level
  97 {
  98    /** Offset to this miptree level, used in computing x_offset. */
  99    GLuint level_x;
 100    /** Offset to this miptree level, used in computing y_offset. */
 101    GLuint level_y;
 102
 103    /**
 104     * \brief Number of 2D slices in this miplevel.
 105     *
 106     * The exact semantics of depth varies according to the texture target:
 107     *    - For GL_TEXTURE_CUBE_MAP, depth is 6.
 108     *    - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
 109     *      identical for all miplevels in the texture.
 110     *    - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
 111     *      value, like width and height, varies with miplevel.
 112     *    - For other texture types, depth is 1.
 113     *    - Additionally, for UMS and CMS miptrees, depth is multiplied by
 114     *      sample count.
 115     */
 116    GLuint depth;
 117
 118    /**
 119     * \brief Is HiZ enabled for this level?
 120     *
 121     * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
 122     * allocated and (2) the HiZ memory for the slices in this level reside at
 123     * \c mt->hiz_mt->level[l].
 124     */
 125    bool has_hiz;
 126
 127    /**
 128     * \brief List of 2D images in this mipmap level.
 129     *
 130     * This may be a list of cube faces, array slices in 2D array texture, or
 131     * layers in a 3D texture. The list's length is \c depth.
 132     */
 133    struct intel_mipmap_slice {
 134       /**
 135        * \name Offset to slice
 136        * \{
 137        *
 138        * Hardware formats are so diverse that that there is no unified way to
 139        * compute the slice offsets, so we store them in this table.
 140        *
 141        * The (x, y) offset to slice \c s at level \c l relative the miptrees
 142        * base address is
 143        * \code
 144        *     x = mt->level[l].slice[s].x_offset
 145        *     y = mt->level[l].slice[s].y_offset
 146        *
 147        * On some hardware generations, we program these offsets into
 148        * RENDER_SURFACE_STATE.XOffset and RENDER_SURFACE_STATE.YOffset.
 149        */
 150       GLuint x_offset;
 151       GLuint y_offset;
 152       /** \} */
 153
 154       /**
 155        * Mapping information. Persistent for the duration of
 156        * intel_miptree_map/unmap on this slice.
 157        */
 158       struct intel_miptree_map *map;
 159    } *slice;
 160 };
 161
 162 /**
 163  * Enum for keeping track of the different MSAA layouts supported by Gen7.
 164  */
 165 enum intel_msaa_layout
 166 {
 167    /**
 168     * Ordinary surface with no MSAA.
 169     */
 170    INTEL_MSAA_LAYOUT_NONE,
 171
 172    /**
 173     * Interleaved Multisample Surface.  The additional samples are
 174     * accommodated by scaling up the width and the height of the surface so
 175     * that all the samples corresponding to a pixel are located at nearby
 176     * memory locations.
 177     *
 178     * @see PRM section "Interleaved Multisampled Surfaces"
 179     */
 180    INTEL_MSAA_LAYOUT_IMS,
 181
 182    /**
 183     * Uncompressed Multisample Surface.  The surface is stored as a 2D array,
 184     * with array slice n containing all pixel data for sample n.
 185     *
 186     * @see PRM section "Uncompressed Multisampled Surfaces"
 187     */
 188    INTEL_MSAA_LAYOUT_UMS,
 189
 190    /**
 191     * Compressed Multisample Surface.  The surface is stored as in
 192     * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
 193     * (Multisample Control Surface) buffer.  Each pixel in the MCS buffer
 194     * indicates the mapping from sample number to array slice.  This allows
 195     * the common case (where all samples constituting a pixel have the same
 196     * color value) to be stored efficiently by just using a single array
 197     * slice.
 198     *
 199     * @see PRM section "Compressed Multisampled Surfaces"
 200     */
 201    INTEL_MSAA_LAYOUT_CMS,
 202 };
 203
 204
 205 /**
 206  * Enum for keeping track of the fast clear state of a buffer associated with
 207  * a miptree.
 208  *
 209  * Fast clear works by deferring the memory writes that would be used to clear
 210  * the buffer, so that instead of performing them at the time of the clear
 211  * operation, the hardware automatically performs them at the time that the
 212  * buffer is later accessed for rendering.  The MCS buffer keeps track of
 213  * which regions of the buffer still have pending clear writes.
 214  *
 215  * This enum keeps track of the driver's knowledge of pending fast clears in
 216  * the MCS buffer.
 217  *
 218  * MCS buffers only exist on Gen7+.
 219  */
 220 enum intel_fast_clear_state
 221 {
 222    /**
 223     * There is no MCS buffer for this miptree, and one should never be
 224     * allocated.
 225     */
 226    INTEL_FAST_CLEAR_STATE_NO_MCS,
 227
 228    /**
 229     * No deferred clears are pending for this miptree, and the contents of the
 230     * color buffer are entirely correct.  An MCS buffer may or may not exist
 231     * for this miptree.  If it does exist, it is entirely in the "no deferred
 232     * clears pending" state.  If it does not exist, it will be created the
 233     * first time a fast color clear is executed.
 234     *
 235     * In this state, the color buffer can be used for purposes other than
 236     * rendering without needing a render target resolve.
 237     *
 238     * Since there is no such thing as a "fast color clear resolve" for MSAA
 239     * buffers, an MSAA buffer will never be in this state.
 240     */
 241    INTEL_FAST_CLEAR_STATE_RESOLVED,
 242
 243    /**
 244     * An MCS buffer exists for this miptree, and deferred clears are pending
 245     * for some regions of the color buffer, as indicated by the MCS buffer.
 246     * The contents of the color buffer are only correct for the regions where
 247     * the MCS buffer doesn't indicate a deferred clear.
 248     *
 249     * If a single-sample buffer is in this state, a render target resolve must
 250     * be performed before it can be used for purposes other than rendering.
 251     */
 252    INTEL_FAST_CLEAR_STATE_UNRESOLVED,
 253
 254    /**
 255     * An MCS buffer exists for this miptree, and deferred clears are pending
 256     * for the entire color buffer, and the contents of the MCS buffer reflect
 257     * this.  The contents of the color buffer are undefined.
 258     *
 259     * If a single-sample buffer is in this state, a render target resolve must
 260     * be performed before it can be used for purposes other than rendering.
 261     *
 262     * If the client attempts to clear a buffer which is already in this state,
 263     * the clear can be safely skipped, since the buffer is already clear.
 264     */
 265    INTEL_FAST_CLEAR_STATE_CLEAR,
 266 };
 267
 268 enum miptree_array_layout {
 269    /* Each array slice contains all miplevels packed together.
 270     *
 271     * Gen hardware usually wants multilevel miptrees configured this way.
 272     *
 273     * A 2D Array texture with 2 slices and multiple LODs using
 274     * ALL_LOD_IN_EACH_SLICE would look somewhat like this:
 275     *
 276     *   +----------+
 277     *   |          |
 278     *   |          |
 279     *   +----------+
 280     *   +---+ +-+
 281     *   |   | +-+
 282     *   +---+ *
 283     *   +----------+
 284     *   |          |
 285     *   |          |
 286     *   +----------+
 287     *   +---+ +-+
 288     *   |   | +-+
 289     *   +---+ *
 290     */
 291    ALL_LOD_IN_EACH_SLICE,
 292
 293    /* Each LOD contains all slices of that LOD packed together.
 294     *
 295     * In some situations, Gen7+ hardware can use the array_spacing_lod0
 296     * feature to save space when the surface only contains LOD 0.
 297     *
 298     * Gen6 uses this for separate stencil and hiz since gen6 does not support
 299     * multiple LODs for separate stencil and hiz.
 300     *
 301     * A 2D Array texture with 2 slices and multiple LODs using
 302     * ALL_SLICES_AT_EACH_LOD would look somewhat like this:
 303     *
 304     *   +----------+
 305     *   |          |
 306     *   |          |
 307     *   +----------+
 308     *   |          |
 309     *   |          |
 310     *   +----------+
 311     *   +---+ +-+
 312     *   |   | +-+
 313     *   +---+ +-+
 314     *   |   | :
 315     *   +---+
 316     */
 317    ALL_SLICES_AT_EACH_LOD,
 318 };
 319
 320 /**
 321  * Miptree aux buffer. These buffers are associated with a miptree, but the
 322  * format is managed by the hardware.
 323  *
 324  * For Gen7+, we always give the hardware the start of the buffer, and let it
 325  * handle all accesses to the buffer. Therefore we don't need the full miptree
 326  * layout structure for this buffer.
 327  *
 328  * For Gen6, we need a hiz miptree structure for this buffer so we can program
 329  * offsets to slices & miplevels.
 330  */
 331 struct intel_miptree_aux_buffer
 332 {
 333    /**
 334     * Buffer object containing the pixel data.
 335     *
 336     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 337     * @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
 338     */
 339    drm_intel_bo *bo;
 340
 341    /**
 342     * Pitch in bytes.
 343     *
 344     * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
 345     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
 346     */
 347    uint32_t pitch;
 348
 349    /**
 350     * The distance in rows between array slices.
 351     *
 352     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch
 353     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
 354     */
 355    uint32_t qpitch;
 356
 357    /**
 358     * Hiz miptree. Used only by Gen6.
 359     */
 360    struct intel_mipmap_tree *mt;
 361 };
 362
 363 /* Tile resource modes */
 364 enum intel_miptree_tr_mode {
 365    INTEL_MIPTREE_TRMODE_NONE,
 366    INTEL_MIPTREE_TRMODE_YF,
 367    INTEL_MIPTREE_TRMODE_YS
 368 };
 369
 370 struct intel_mipmap_tree
 371 {
 372    /**
 373     * Buffer object containing the surface.
 374     *
 375     * @see intel_mipmap_tree::offset
 376     * @see RENDER_SURFACE_STATE.SurfaceBaseAddress
 377     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 378     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 379     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 380     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 381     */
 382    drm_intel_bo *bo;
 383
 384    /**
 385     * Pitch in bytes.
 386     *
 387     * @see RENDER_SURFACE_STATE.SurfacePitch
 388     * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
 389     * @see 3DSTATE_DEPTH_BUFFER.SurfacePitch
 390     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
 391     * @see 3DSTATE_STENCIL_BUFFER.SurfacePitch
 392     */
 393    uint32_t pitch;
 394
 395    /**
 396     * One of the I915_TILING_* flags.
 397     *
 398     * @see RENDER_SURFACE_STATE.TileMode
 399     * @see 3DSTATE_DEPTH_BUFFER.TileMode
 400     */
 401    uint32_t tiling;
 402
 403    /**
 404     * @see RENDER_SURFACE_STATE.TiledResourceMode
 405     * @see 3DSTATE_DEPTH_BUFFER.TiledResourceMode
 406     */
 407    enum intel_miptree_tr_mode tr_mode;
 408
 409    /**
 410     * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
 411     *
 412     * @see RENDER_SURFACE_STATE.SurfaceType
 413     * @see RENDER_SURFACE_STATE.SurfaceArray
 414     * @see 3DSTATE_DEPTH_BUFFER.SurfaceType
 415     */
 416    GLenum target;
 417
 418    /**
 419     * Generally, this is just the same as the gl_texture_image->TexFormat or
 420     * gl_renderbuffer->Format.
 421     *
 422     * However, for textures and renderbuffers with packed depth/stencil formats
 423     * on hardware where we want or need to use separate stencil, there will be
 424     * two miptrees for storing the data.  If the depthstencil texture or rb is
 425     * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
 426     * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
 427     * MESA_FORMAT_Z24_UNORM_X8_UINT.
 428     *
 429     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
 430     * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
 431     *
 432     * @see RENDER_SURFACE_STATE.SurfaceFormat
 433     * @see 3DSTATE_DEPTH_BUFFER.SurfaceFormat
 434     */
 435    mesa_format format;
 436
 437    /**
 438     * This variable stores the value of ETC compressed texture format
 439     *
 440     * @see RENDER_SURFACE_STATE.SurfaceFormat
 441     */
 442    mesa_format etc_format;
 443
 444    /**
 445     * @name Surface Alignment
 446     * @{
 447     *
 448     * This defines the alignment of the upperleft pixel of each "slice" in the
 449     * surface. The alignment is in pixel coordinates relative to the surface's
 450     * most upperleft pixel, which is the pixel at (x=0, y=0, layer=0,
 451     * level=0).
 452     *
 453     * The hardware docs do not use the term "slice".  We use "slice" to mean
 454     * the pixels at a given miplevel and layer. For 2D surfaces, the layer is
 455     * the array slice; for 3D surfaces, the layer is the z offset.
 456     *
 457     * In the surface layout equations found in the hardware docs, the
 458     * horizontal and vertical surface alignments often appear as variables 'i'
 459     * and 'j'.
 460     */
 461
 462    /** @see RENDER_SURFACE_STATE.SurfaceHorizontalAlignment */
 463    uint32_t halign;
 464
 465    /** @see RENDER_SURFACE_STATE.SurfaceVerticalAlignment */
 466    uint32_t valign;
 467    /** @} */
 468
 469    GLuint first_level;
 470    GLuint last_level;
 471
 472    /**
 473     * Level zero image dimensions.  These dimensions correspond to the
 474     * physical layout of data in memory.  Accordingly, they account for the
 475     * extra width, height, and or depth that must be allocated in order to
 476     * accommodate multisample formats, and they account for the extra factor
 477     * of 6 in depth that must be allocated in order to accommodate cubemap
 478     * textures.
 479     */
 480    GLuint physical_width0, physical_height0, physical_depth0;
 481
 482    /** Bytes per pixel (or bytes per block if compressed) */
 483    GLuint cpp;
 484
 485    /**
 486     * @see RENDER_SURFACE_STATE.NumberOfMultisamples
 487     * @see 3DSTATE_MULTISAMPLE.NumberOfMultisamples
 488     */
 489    GLuint num_samples;
 490
 491    bool compressed;
 492
 493    /**
 494     * @name Level zero image dimensions
 495     * @{
 496     *
 497     * These dimensions correspond to the
 498     * logical width, height, and depth of the texture as seen by client code.
 499     * Accordingly, they do not account for the extra width, height, and/or
 500     * depth that must be allocated in order to accommodate multisample
 501     * formats, nor do they account for the extra factor of 6 in depth that
 502     * must be allocated in order to accommodate cubemap textures.
 503     */
 504
 505    /**
 506     * @see RENDER_SURFACE_STATE.Width
 507     * @see 3DSTATE_DEPTH_BUFFER.Width
 508     */
 509    uint32_t logical_width0;
 510
 511    /**
 512     * @see RENDER_SURFACE_STATE.Height
 513     * @see 3DSTATE_DEPTH_BUFFER.Height
 514     */
 515    uint32_t logical_height0;
 516
 517    /**
 518     * @see RENDER_SURFACE_STATE.Depth
 519     * @see 3DSTATE_DEPTH_BUFFER.Depth
 520     */
 521    uint32_t logical_depth0;
 522    /** @} */
 523
 524    /**
 525     * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
 526     * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
 527     */
 528    enum miptree_array_layout array_layout;
 529
 530    /**
 531     * The distance in between array slices.
 532     *
 533     * The value is the one that is sent in the surface state. The actual
 534     * meaning depends on certain criteria. Usually it is simply the number of
 535     * uncompressed rows between each slice. However on Gen9+ for compressed
 536     * surfaces it is the number of blocks. For 1D array surfaces that have the
 537     * mipmap tree stored horizontally it is the number of pixels between each
 538     * slice.
 539     *
 540     * @see RENDER_SURFACE_STATE.SurfaceQPitch
 541     * @see 3DSTATE_DEPTH_BUFFER.SurfaceQPitch
 542     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
 543     * @see 3DSTATE_STENCIL_BUFFER.SurfaceQPitch
 544     */
 545    uint32_t qpitch;
 546
 547    /**
 548     * MSAA layout used by this buffer.
 549     *
 550     * @see RENDER_SURFACE_STATE.MultisampledSurfaceStorageFormat
 551     */
 552    enum intel_msaa_layout msaa_layout;
 553
 554    /* Derived from the above:
 555     */
 556    GLuint total_width;
 557    GLuint total_height;
 558
 559    /**
 560     * The depth value used during the most recent fast depth clear performed
 561     * on the surface. This field is invalid only if surface has never
 562     * underwent a fast depth clear.
 563     *
 564     * @see 3DSTATE_CLEAR_PARAMS.DepthClearValue
 565     */
 566    uint32_t depth_clear_value;
 567
 568    /* Includes image offset tables: */
 569    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 570
 571    /**
 572     * Offset into bo where the surface starts.
 573     *
 574     * @see intel_mipmap_tree::bo
 575     *
 576     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 577     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 578     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 579     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 580     */
 581    uint32_t offset;
 582
 583    /**
 584     * \brief HiZ aux buffer
 585     *
 586     * To allocate the hiz buffer, use intel_miptree_alloc_hiz().
 587     *
 588     * To determine if hiz is enabled, do not check this pointer. Instead, use
 589     * intel_miptree_slice_has_hiz().
 590     */
 591    struct intel_miptree_aux_buffer *hiz_buf;
 592
 593    /**
 594     * \brief Map of miptree slices to needed resolves.
 595     *
 596     * This is used only when the miptree has a child HiZ miptree.
 597     *
 598     * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
 599     * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
 600     * mt->hiz_mt->hiz_map, is unused.
 601     */
 602    struct exec_list hiz_map; /* List of intel_resolve_map. */
 603
 604    /**
 605     * \brief Stencil miptree for depthstencil textures.
 606     *
 607     * This miptree is used for depthstencil textures and renderbuffers that
 608     * require separate stencil.  It always has the true copy of the stencil
 609     * bits, regardless of mt->format.
 610     *
 611     * \see 3DSTATE_STENCIL_BUFFER
 612     * \see intel_miptree_map_depthstencil()
 613     * \see intel_miptree_unmap_depthstencil()
 614     */
 615    struct intel_mipmap_tree *stencil_mt;
 616
 617    /**
 618     * \brief MCS miptree.
 619     *
 620     * This miptree contains the "multisample control surface", which stores
 621     * the necessary information to implement compressed MSAA
 622     * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
 623     *
 624     * NULL if no MCS miptree is in use for this surface.
 625     */
 626    struct intel_mipmap_tree *mcs_mt;
 627
 628    /**
 629     * Planes 1 and 2 in case this is a planar surface.
 630     */
 631    struct intel_mipmap_tree *plane[2];
 632
 633    /**
 634     * Fast clear state for this buffer.
 635     */
 636    enum intel_fast_clear_state fast_clear_state;
 637
 638    /**
 639     * The SURFACE_STATE bits associated with the last fast color clear to this
 640     * color mipmap tree, if any.
 641     *
 642     * Prior to GEN9 there is a single bit for RGBA clear values which gives you
 643     * the option of 2^4 clear colors. Each bit determines if the color channel
 644     * is fully saturated or unsaturated (Cherryview does add a 32b value per
 645     * channel, but it is globally applied instead of being part of the render
 646     * surface state). Starting with GEN9, the surface state accepts a 32b value
 647     * for each color channel.
 648     *
 649     * @see RENDER_SURFACE_STATE.RedClearColor
 650     * @see RENDER_SURFACE_STATE.GreenClearColor
 651     * @see RENDER_SURFACE_STATE.BlueClearColor
 652     * @see RENDER_SURFACE_STATE.AlphaClearColor
 653     */
 654    union {
 655       uint32_t fast_clear_color_value;
 656       union gl_color_union gen9_fast_clear_color;
 657    };
 658
 659    /**
 660     * Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS
 661     * buffer. This is useful for sharing the miptree bo with an external client
 662     * that doesn't understand auxiliary buffers.
 663     */
 664    bool disable_aux_buffers;
 665
 666    /**
 667     * Tells if the underlying buffer is to be also consumed by entities other
 668     * than the driver. This allows logic to turn off features such as lossless
 669     * compression which is not currently understood by client applications.
 670     */
 671    bool is_scanout;
 672
 673    /* These are also refcounted:
 674     */
 675    GLuint refcount;
 676 };
 677
 678 void
 679 intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree *mt,
 680                                  unsigned *width_px, unsigned *height);
 681
 682 bool
 683 intel_miptree_is_lossless_compressed(const struct brw_context *brw,
 684                                      const struct intel_mipmap_tree *mt);
 685
 686 bool
 687 intel_tiling_supports_non_msrt_mcs(const struct brw_context *brw,
 688                                    unsigned tiling);
 689
 690 bool
 691 intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw,
 692                                            const struct intel_mipmap_tree *mt);
 693
 694 bool
 695 intel_miptree_supports_lossless_compressed(struct brw_context *brw,
 696                                            const struct intel_mipmap_tree *mt);
 697
 698 bool
 699 intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
 700                                  struct intel_mipmap_tree *mt);
 701
 702 void
 703 intel_miptree_prepare_mcs(struct brw_context *brw,
 704                           struct intel_mipmap_tree *mt);
 705
 706 enum {
 707    MIPTREE_LAYOUT_ACCELERATED_UPLOAD       = 1 << 0,
 708    MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD   = 1 << 1,
 709    MIPTREE_LAYOUT_FOR_BO                   = 1 << 2,
 710    MIPTREE_LAYOUT_DISABLE_AUX              = 1 << 3,
 711    MIPTREE_LAYOUT_FORCE_HALIGN16           = 1 << 4,
 712
 713    MIPTREE_LAYOUT_TILING_Y                 = 1 << 5,
 714    MIPTREE_LAYOUT_TILING_NONE              = 1 << 6,
 715    MIPTREE_LAYOUT_TILING_ANY               = MIPTREE_LAYOUT_TILING_Y |
 716                                              MIPTREE_LAYOUT_TILING_NONE,
 717
 718    MIPTREE_LAYOUT_FOR_SCANOUT              = 1 << 7,
 719 };
 720
 721 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
 722                                                GLenum target,
 723                                                mesa_format format,
 724                                                GLuint first_level,
 725                                                GLuint last_level,
 726                                                GLuint width0,
 727                                                GLuint height0,
 728                                                GLuint depth0,
 729                                                GLuint num_samples,
 730                                                uint32_t flags);
 731
 732 struct intel_mipmap_tree *
 733 intel_miptree_create_for_bo(struct brw_context *brw,
 734                             drm_intel_bo *bo,
 735                             mesa_format format,
 736                             uint32_t offset,
 737                             uint32_t width,
 738                             uint32_t height,
 739                             uint32_t depth,
 740                             int pitch,
 741                             uint32_t layout_flags);
 742
 743 void
 744 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
 745                                          struct intel_renderbuffer *irb,
 746                                          drm_intel_bo *bo,
 747                                          uint32_t width, uint32_t height,
 748                                          uint32_t pitch);
 749
 750 /**
 751  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 752  * The miptree has the following properties:
 753  *     - The target is GL_TEXTURE_2D.
 754  *     - There are no levels other than the base level 0.
 755  *     - Depth is 1.
 756  */
 757 struct intel_mipmap_tree*
 758 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
 759                                       mesa_format format,
 760                                       uint32_t width,
 761                                       uint32_t height,
 762                                       uint32_t num_samples);
 763
 764 mesa_format
 765 intel_depth_format_for_depthstencil_format(mesa_format format);
 766
 767 mesa_format
 768 intel_lower_compressed_format(struct brw_context *brw, mesa_format format);
 769
 770 /** \brief Assert that the level and layer are valid for the miptree. */
 771 static inline void
 772 intel_miptree_check_level_layer(struct intel_mipmap_tree *mt,
 773                                 uint32_t level,
 774                                 uint32_t layer)
 775 {
 776    (void) mt;
 777    (void) level;
 778    (void) layer;
 779
 780    assert(level >= mt->first_level);
 781    assert(level <= mt->last_level);
 782    assert(layer < mt->level[level].depth);
 783 }
 784
 785 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 786                              struct intel_mipmap_tree *src);
 787
 788 void intel_miptree_release(struct intel_mipmap_tree **mt);
 789
 790 /* Check if an image fits an existing mipmap tree layout
 791  */
 792 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 793                                     struct gl_texture_image *image);
 794
 795 void
 796 intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt,
 797                                GLuint level, GLuint slice,
 798                                GLuint *x, GLuint *y);
 799
 800 void
 801 intel_miptree_get_isl_surf(struct brw_context *brw,
 802                            const struct intel_mipmap_tree *mt,
 803                            struct isl_surf *surf);
 804
 805 void
 806 intel_get_image_dims(struct gl_texture_image *image,
 807                      int *width, int *height, int *depth);
 808
 809 void
 810 intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
 811                      bool map_stencil_as_y_tiled,
 812                      uint32_t *mask_x, uint32_t *mask_y);
 813
 814 void
 815 intel_get_tile_dims(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
 816                     uint32_t *tile_w, uint32_t *tile_h);
 817
 818 uint32_t
 819 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
 820                                GLuint level, GLuint slice,
 821                                uint32_t *tile_x,
 822                                uint32_t *tile_y);
 823 uint32_t
 824 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
 825                                  uint32_t x, uint32_t y,
 826                                  bool map_stencil_as_y_tiled);
 827
 828 void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
 829                                   GLuint level,
 830                                   GLuint x, GLuint y, GLuint d);
 831
 832 void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
 833                                     GLuint level,
 834                                     GLuint img, GLuint x, GLuint y);
 835
 836 void
 837 intel_miptree_copy_teximage(struct brw_context *brw,
 838                             struct intel_texture_image *intelImage,
 839                             struct intel_mipmap_tree *dst_mt, bool invalidate);
 840
 841 /**
 842  * \name Miptree HiZ functions
 843  * \{
 844  *
 845  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 846  * functions on a miptree without HiZ. In that case, each function is a no-op.
 847  */
 848
 849 bool
 850 intel_miptree_wants_hiz_buffer(struct brw_context *brw,
 851                                struct intel_mipmap_tree *mt);
 852
 853 /**
 854  * \brief Allocate the miptree's embedded HiZ miptree.
 855  * \see intel_mipmap_tree:hiz_mt
 856  * \return false if allocation failed
 857  */
 858 bool
 859 intel_miptree_alloc_hiz(struct brw_context *brw,
 860                         struct intel_mipmap_tree *mt);
 861
 862 bool
 863 intel_miptree_level_has_hiz(struct intel_mipmap_tree *mt, uint32_t level);
 864
 865 void
 866 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt,
 867                                           uint32_t level,
 868                                           uint32_t depth);
 869 void
 870 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt,
 871                                             uint32_t level,
 872                                             uint32_t depth);
 873
 874 void
 875 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree *mt,
 876                                                 uint32_t level);
 877
 878 /**
 879  * \return false if no resolve was needed
 880  */
 881 bool
 882 intel_miptree_slice_resolve_hiz(struct brw_context *brw,
 883                                 struct intel_mipmap_tree *mt,
 884                                 unsigned int level,
 885                                 unsigned int depth);
 886
 887 /**
 888  * \return false if no resolve was needed
 889  */
 890 bool
 891 intel_miptree_slice_resolve_depth(struct brw_context *brw,
 892                                   struct intel_mipmap_tree *mt,
 893                                   unsigned int level,
 894                                   unsigned int depth);
 895
 896 /**
 897  * \return false if no resolve was needed
 898  */
 899 bool
 900 intel_miptree_all_slices_resolve_hiz(struct brw_context *brw,
 901                                      struct intel_mipmap_tree *mt);
 902
 903 /**
 904  * \return false if no resolve was needed
 905  */
 906 bool
 907 intel_miptree_all_slices_resolve_depth(struct brw_context *brw,
 908                                        struct intel_mipmap_tree *mt);
 909
 910 /**\}*/
 911
 912 /**
 913  * Update the fast clear state for a miptree to indicate that it has been used
 914  * for rendering.
 915  */
 916 static inline void
 917 intel_miptree_used_for_rendering(struct intel_mipmap_tree *mt)
 918 {
 919    /* If the buffer was previously in fast clear state, change it to
 920     * unresolved state, since it won't be guaranteed to be clear after
 921     * rendering occurs.
 922     */
 923    if (mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR)
 924       mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
 925 }
 926
 927 /**
 928  * Flag values telling color resolve pass which special types of buffers
 929  * can be ignored.
 930  *
 931  * INTEL_MIPTREE_IGNORE_CCS_E:   Lossless compressed (single-sample
 932  *                               compression scheme since gen9)
 933  */
 934 #define INTEL_MIPTREE_IGNORE_CCS_E (1 << 0)
 935
 936 void
 937 intel_miptree_resolve_color(struct brw_context *brw,
 938                             struct intel_mipmap_tree *mt,
 939                             int flags);
 940
 941 void
 942 intel_miptree_make_shareable(struct brw_context *brw,
 943                              struct intel_mipmap_tree *mt);
 944
 945 void
 946 intel_miptree_updownsample(struct brw_context *brw,
 947                            struct intel_mipmap_tree *src,
 948                            struct intel_mipmap_tree *dst);
 949
 950 /**
 951  * Horizontal distance from one slice to the next in the two-dimensional
 952  * miptree layout.
 953  */
 954 unsigned
 955 brw_miptree_get_horizontal_slice_pitch(const struct brw_context *brw,
 956                                        const struct intel_mipmap_tree *mt,
 957                                        unsigned level);
 958
 959 /**
 960  * Vertical distance from one slice to the next in the two-dimensional miptree
 961  * layout.
 962  */
 963 unsigned
 964 brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw,
 965                                      const struct intel_mipmap_tree *mt,
 966                                      unsigned level);
 967
 968 void
 969 brw_miptree_layout(struct brw_context *brw,
 970                    struct intel_mipmap_tree *mt,
 971                    uint32_t layout_flags);
 972
 973 void
 974 intel_miptree_map(struct brw_context *brw,
 975                   struct intel_mipmap_tree *mt,
 976                   unsigned int level,
 977                   unsigned int slice,
 978                   unsigned int x,
 979                   unsigned int y,
 980                   unsigned int w,
 981                   unsigned int h,
 982                   GLbitfield mode,
 983                   void **out_ptr,
 984                   ptrdiff_t *out_stride);
 985
 986 void
 987 intel_miptree_unmap(struct brw_context *brw,
 988                     struct intel_mipmap_tree *mt,
 989                     unsigned int level,
 990                     unsigned int slice);
 991
 992 void
 993 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 994                unsigned int level, unsigned int layer, enum gen6_hiz_op op);
 995
 996 #ifdef __cplusplus
 997 }
 998 #endif
 999
1000 #endif