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28 #ifndef INTEL_MIPMAP_TREE_H
29 #define INTEL_MIPMAP_TREE_H
33 #include "intel_regions.h"
34 #include "intel_resolve_map.h"
35 #include <GL/internal/dri_interface.h>
41 struct intel_renderbuffer
;
43 /* A layer on top of the intel_regions code which adds:
45 * - Code to size and layout a region to hold a set of mipmaps.
46 * - Query to determine if a new image fits in an existing tree.
48 * - maybe able to remove refcounting from intel_region?
51 * The fixed mipmap layout of intel hardware where one offset
52 * specifies the position of all images in a mipmap hierachy
53 * complicates the implementation of GL texture image commands,
54 * compared to hardware where each image is specified with an
57 * In an ideal world, each texture object would be associated with a
58 * single bufmgr buffer or 2d intel_region, and all the images within
59 * the texture object would slot into the tree as they arrive. The
60 * reality can be a little messier, as images can arrive from the user
61 * with sizes that don't fit in the existing tree, or in an order
62 * where the tree layout cannot be guessed immediately.
64 * This structure encodes an idealized mipmap tree. The GL image
65 * commands build these where possible, otherwise store the images in
66 * temporary system buffers.
69 struct intel_resolve_map
;
70 struct intel_texture_image
;
73 * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
74 * depthstencil-split-to-separate-stencil miptree, we'll normally make a
75 * tmeporary and recreate the kind of data requested by Mesa core, since we're
76 * satisfying some glGetTexImage() request or something.
78 * However, occasionally you want to actually map the miptree's current data
79 * without transcoding back. This flag to intel_miptree_map() gets you that.
81 #define BRW_MAP_DIRECT_BIT 0x80000000
83 struct intel_miptree_map
{
84 /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
86 /** Region of interest for the map. */
88 /** Possibly malloced temporary buffer for the mapping. */
90 /** Possible pointer to a temporary linear miptree for the mapping. */
91 struct intel_mipmap_tree
*mt
;
92 /** Pointer to the start of (map_x, map_y) returned by the mapping. */
94 /** Stride of the mapping. */
99 * Describes the location of each texture image within a texture region.
101 struct intel_mipmap_level
103 /** Offset to this miptree level, used in computing x_offset. */
105 /** Offset to this miptree level, used in computing y_offset. */
109 * \brief Number of 2D slices in this miplevel.
111 * The exact semantics of depth varies according to the texture target:
112 * - For GL_TEXTURE_CUBE_MAP, depth is 6.
113 * - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
114 * identical for all miplevels in the texture.
115 * - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
116 * value, like width and height, varies with miplevel.
117 * - For other texture types, depth is 1.
118 * - Additionally, for UMS and CMS miptrees, depth is multiplied by
124 * \brief List of 2D images in this mipmap level.
126 * This may be a list of cube faces, array slices in 2D array texture, or
127 * layers in a 3D texture. The list's length is \c depth.
129 struct intel_mipmap_slice
{
131 * \name Offset to slice
134 * Hardware formats are so diverse that that there is no unified way to
135 * compute the slice offsets, so we store them in this table.
137 * The (x, y) offset to slice \c s at level \c l relative the miptrees
140 * x = mt->level[l].slice[s].x_offset
141 * y = mt->level[l].slice[s].y_offset
148 * Mapping information. Persistent for the duration of
149 * intel_miptree_map/unmap on this slice.
151 struct intel_miptree_map
*map
;
154 * \brief Is HiZ enabled for this slice?
156 * If \c mt->level[l].slice[s].has_hiz is set, then (1) \c mt->hiz_mt
157 * has been allocated and (2) the HiZ memory corresponding to this slice
158 * resides at \c mt->hiz_mt->level[l].slice[s].
165 * Enum for keeping track of the different MSAA layouts supported by Gen7.
167 enum intel_msaa_layout
170 * Ordinary surface with no MSAA.
172 INTEL_MSAA_LAYOUT_NONE
,
175 * Interleaved Multisample Surface. The additional samples are
176 * accommodated by scaling up the width and the height of the surface so
177 * that all the samples corresponding to a pixel are located at nearby
180 INTEL_MSAA_LAYOUT_IMS
,
183 * Uncompressed Multisample Surface. The surface is stored as a 2D array,
184 * with array slice n containing all pixel data for sample n.
186 INTEL_MSAA_LAYOUT_UMS
,
189 * Compressed Multisample Surface. The surface is stored as in
190 * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
191 * (Multisample Control Surface) buffer. Each pixel in the MCS buffer
192 * indicates the mapping from sample number to array slice. This allows
193 * the common case (where all samples constituting a pixel have the same
194 * color value) to be stored efficiently by just using a single array
197 INTEL_MSAA_LAYOUT_CMS
,
202 * Enum for keeping track of the fast clear state of a buffer associated with
205 * Fast clear works by deferring the memory writes that would be used to clear
206 * the buffer, so that instead of performing them at the time of the clear
207 * operation, the hardware automatically performs them at the time that the
208 * buffer is later accessed for rendering. The MCS buffer keeps track of
209 * which regions of the buffer still have pending clear writes.
211 * This enum keeps track of the driver's knowledge of pending fast clears in
214 * MCS buffers only exist on Gen7+.
216 enum intel_fast_clear_state
219 * There is no MCS buffer for this miptree, and one should never be
222 INTEL_FAST_CLEAR_STATE_NO_MCS
,
225 * No deferred clears are pending for this miptree, and the contents of the
226 * color buffer are entirely correct. An MCS buffer may or may not exist
227 * for this miptree. If it does exist, it is entirely in the "no deferred
228 * clears pending" state. If it does not exist, it will be created the
229 * first time a fast color clear is executed.
231 * In this state, the color buffer can be used for purposes other than
232 * rendering without needing a render target resolve.
234 * Since there is no such thing as a "fast color clear resolve" for MSAA
235 * buffers, an MSAA buffer will never be in this state.
237 INTEL_FAST_CLEAR_STATE_RESOLVED
,
240 * An MCS buffer exists for this miptree, and deferred clears are pending
241 * for some regions of the color buffer, as indicated by the MCS buffer.
242 * The contents of the color buffer are only correct for the regions where
243 * the MCS buffer doesn't indicate a deferred clear.
245 * If a single-sample buffer is in this state, a render target resolve must
246 * be performed before it can be used for purposes other than rendering.
248 INTEL_FAST_CLEAR_STATE_UNRESOLVED
,
251 * An MCS buffer exists for this miptree, and deferred clears are pending
252 * for the entire color buffer, and the contents of the MCS buffer reflect
253 * this. The contents of the color buffer are undefined.
255 * If a single-sample buffer is in this state, a render target resolve must
256 * be performed before it can be used for purposes other than rendering.
258 * If the client attempts to clear a buffer which is already in this state,
259 * the clear can be safely skipped, since the buffer is already clear.
261 INTEL_FAST_CLEAR_STATE_CLEAR
,
264 struct intel_mipmap_tree
266 /* Effectively the key:
271 * Generally, this is just the same as the gl_texture_image->TexFormat or
272 * gl_renderbuffer->Format.
274 * However, for textures and renderbuffers with packed depth/stencil formats
275 * on hardware where we want or need to use separate stencil, there will be
276 * two miptrees for storing the data. If the depthstencil texture or rb is
277 * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
278 * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
279 * MESA_FORMAT_Z24_UNORM_X8_UINT.
281 * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
282 * formats if the hardware lacks support for ETC1/ETC2. See @ref wraps_etc.
286 /** This variable stores the value of ETC compressed texture format */
287 mesa_format etc_format
;
290 * The X offset of each image in the miptree must be aligned to this.
291 * See the comments in brw_tex_layout.c.
293 unsigned int align_w
;
294 unsigned int align_h
; /**< \see align_w */
300 * Level zero image dimensions. These dimensions correspond to the
301 * physical layout of data in memory. Accordingly, they account for the
302 * extra width, height, and or depth that must be allocated in order to
303 * accommodate multisample formats, and they account for the extra factor
304 * of 6 in depth that must be allocated in order to accommodate cubemap
307 GLuint physical_width0
, physical_height0
, physical_depth0
;
314 * Level zero image dimensions. These dimensions correspond to the
315 * logical width, height, and depth of the region as seen by client code.
316 * Accordingly, they do not account for the extra width, height, and/or
317 * depth that must be allocated in order to accommodate multisample
318 * formats, nor do they account for the extra factor of 6 in depth that
319 * must be allocated in order to accommodate cubemap textures.
321 uint32_t logical_width0
, logical_height0
, logical_depth0
;
324 * For 1D array, 2D array, cube, and 2D multisampled surfaces on Gen7: true
325 * if the surface only contains LOD 0, and hence no space is for LOD's
326 * other than 0 in between array slices.
328 * Corresponds to the surface_array_spacing bit in gen7_surface_state.
330 bool array_spacing_lod0
;
333 * The distance in rows between array slices in an uncompressed surface.
335 * For compressed surfaces, slices are stored closer together physically;
336 * the real distance is (qpitch / block height).
341 * MSAA layout used by this buffer.
343 enum intel_msaa_layout msaa_layout
;
345 /* Derived from the above:
350 /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to
351 * this depth mipmap tree, if any.
353 uint32_t depth_clear_value
;
355 /* Includes image offset tables:
357 struct intel_mipmap_level level
[MAX_TEXTURE_LEVELS
];
359 /* The data is held here:
361 struct intel_region
*region
;
363 /* Offset into region bo where miptree starts:
370 * The hiz miptree contains the miptree's hiz buffer. To allocate the hiz
371 * miptree, use intel_miptree_alloc_hiz().
373 * To determine if hiz is enabled, do not check this pointer. Instead, use
374 * intel_miptree_slice_has_hiz().
376 struct intel_mipmap_tree
*hiz_mt
;
379 * \brief Map of miptree slices to needed resolves.
381 * This is used only when the miptree has a child HiZ miptree.
383 * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
384 * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
385 * mt->hiz_mt->hiz_map, is unused.
387 struct intel_resolve_map hiz_map
;
390 * \brief Stencil miptree for depthstencil textures.
392 * This miptree is used for depthstencil textures and renderbuffers that
393 * require separate stencil. It always has the true copy of the stencil
394 * bits, regardless of mt->format.
396 * \see intel_miptree_map_depthstencil()
397 * \see intel_miptree_unmap_depthstencil()
399 struct intel_mipmap_tree
*stencil_mt
;
402 * \brief MCS miptree.
404 * This miptree contains the "multisample control surface", which stores
405 * the necessary information to implement compressed MSAA
406 * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
408 * NULL if no MCS miptree is in use for this surface.
410 struct intel_mipmap_tree
*mcs_mt
;
413 * Fast clear state for this buffer.
415 enum intel_fast_clear_state fast_clear_state
;
418 * The SURFACE_STATE bits associated with the last fast color clear to this
419 * color mipmap tree, if any.
421 * This value will only ever contain ones in bits 28-31, so it is safe to
422 * OR into dword 7 of SURFACE_STATE.
424 uint32_t fast_clear_color_value
;
426 /* These are also refcounted:
431 enum intel_miptree_tiling_mode
{
432 INTEL_MIPTREE_TILING_ANY
,
433 INTEL_MIPTREE_TILING_Y
,
434 INTEL_MIPTREE_TILING_NONE
,
438 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
439 struct intel_mipmap_tree
*mt
);
442 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
443 struct intel_mipmap_tree
*mt
,
444 unsigned *width_px
, unsigned *height
);
447 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
448 struct intel_mipmap_tree
*mt
);
450 struct intel_mipmap_tree
*intel_miptree_create(struct brw_context
*brw
,
458 bool expect_accelerated_upload
,
460 enum intel_miptree_tiling_mode
);
462 struct intel_mipmap_tree
*
463 intel_miptree_create_layout(struct brw_context
*brw
,
474 struct intel_mipmap_tree
*
475 intel_miptree_create_for_bo(struct brw_context
*brw
,
485 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
486 struct intel_renderbuffer
*irb
,
487 struct intel_region
*region
);
490 * Create a miptree appropriate as the storage for a non-texture renderbuffer.
491 * The miptree has the following properties:
492 * - The target is GL_TEXTURE_2D.
493 * - There are no levels other than the base level 0.
496 struct intel_mipmap_tree
*
497 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
501 uint32_t num_samples
);
504 intel_depth_format_for_depthstencil_format(mesa_format format
);
507 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
);
509 /** \brief Assert that the level and layer are valid for the miptree. */
511 intel_miptree_check_level_layer(struct intel_mipmap_tree
*mt
,
515 assert(level
>= mt
->first_level
);
516 assert(level
<= mt
->last_level
);
517 assert(layer
< mt
->level
[level
].depth
);
520 void intel_miptree_reference(struct intel_mipmap_tree
**dst
,
521 struct intel_mipmap_tree
*src
);
523 void intel_miptree_release(struct intel_mipmap_tree
**mt
);
525 /* Check if an image fits an existing mipmap tree layout
527 bool intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
528 struct gl_texture_image
*image
);
531 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
532 GLuint level
, GLuint slice
,
533 GLuint
*x
, GLuint
*y
);
536 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
537 int *width
, int *height
, int *depth
);
540 intel_miptree_get_tile_masks(const struct intel_mipmap_tree
*mt
,
541 uint32_t *mask_x
, uint32_t *mask_y
,
542 bool map_stencil_as_y_tiled
);
545 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
546 GLuint level
, GLuint slice
,
550 void intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
552 GLuint x
, GLuint y
, GLuint d
);
554 void intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
556 GLuint img
, GLuint x
, GLuint y
);
559 intel_miptree_copy_teximage(struct brw_context
*brw
,
560 struct intel_texture_image
*intelImage
,
561 struct intel_mipmap_tree
*dst_mt
, bool invalidate
);
564 intel_miptree_alloc_mcs(struct brw_context
*brw
,
565 struct intel_mipmap_tree
*mt
,
569 * \name Miptree HiZ functions
572 * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
573 * functions on a miptree without HiZ. In that case, each function is a no-op.
577 * \brief Allocate the miptree's embedded HiZ miptree.
578 * \see intel_mipmap_tree:hiz_mt
579 * \return false if allocation failed
583 intel_miptree_alloc_hiz(struct brw_context
*brw
,
584 struct intel_mipmap_tree
*mt
);
587 intel_miptree_slice_has_hiz(struct intel_mipmap_tree
*mt
,
592 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
596 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
601 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
605 * \return false if no resolve was needed
608 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
609 struct intel_mipmap_tree
*mt
,
614 * \return false if no resolve was needed
617 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
618 struct intel_mipmap_tree
*mt
,
623 * \return false if no resolve was needed
626 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
627 struct intel_mipmap_tree
*mt
);
630 * \return false if no resolve was needed
633 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
634 struct intel_mipmap_tree
*mt
);
639 * Update the fast clear state for a miptree to indicate that it has been used
643 intel_miptree_used_for_rendering(struct intel_mipmap_tree
*mt
)
645 /* If the buffer was previously in fast clear state, change it to
646 * unresolved state, since it won't be guaranteed to be clear after
649 if (mt
->fast_clear_state
== INTEL_FAST_CLEAR_STATE_CLEAR
)
650 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_UNRESOLVED
;
654 intel_miptree_resolve_color(struct brw_context
*brw
,
655 struct intel_mipmap_tree
*mt
);
658 intel_miptree_make_shareable(struct brw_context
*brw
,
659 struct intel_mipmap_tree
*mt
);
662 intel_miptree_updownsample(struct brw_context
*brw
,
663 struct intel_mipmap_tree
*src
,
664 struct intel_mipmap_tree
*dst
);
666 void brw_miptree_layout(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
);
668 void *intel_miptree_map_raw(struct brw_context
*brw
,
669 struct intel_mipmap_tree
*mt
);
671 void intel_miptree_unmap_raw(struct brw_context
*brw
,
672 struct intel_mipmap_tree
*mt
);
675 intel_miptree_map(struct brw_context
*brw
,
676 struct intel_mipmap_tree
*mt
,
688 intel_miptree_unmap(struct brw_context
*brw
,
689 struct intel_mipmap_tree
*mt
,
694 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
695 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);