1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #ifndef INTEL_MIPMAP_TREE_H
29 #define INTEL_MIPMAP_TREE_H
33 #include "intel_regions.h"
34 #include "intel_resolve_map.h"
40 /* A layer on top of the intel_regions code which adds:
42 * - Code to size and layout a region to hold a set of mipmaps.
43 * - Query to determine if a new image fits in an existing tree.
45 * - maybe able to remove refcounting from intel_region?
48 * The fixed mipmap layout of intel hardware where one offset
49 * specifies the position of all images in a mipmap hierachy
50 * complicates the implementation of GL texture image commands,
51 * compared to hardware where each image is specified with an
54 * In an ideal world, each texture object would be associated with a
55 * single bufmgr buffer or 2d intel_region, and all the images within
56 * the texture object would slot into the tree as they arrive. The
57 * reality can be a little messier, as images can arrive from the user
58 * with sizes that don't fit in the existing tree, or in an order
59 * where the tree layout cannot be guessed immediately.
61 * This structure encodes an idealized mipmap tree. The GL image
62 * commands build these where possible, otherwise store the images in
63 * temporary system buffers.
66 struct intel_resolve_map
;
67 struct intel_texture_image
;
70 * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
71 * depthstencil-split-to-separate-stencil miptree, we'll normally make a
72 * tmeporary and recreate the kind of data requested by Mesa core, since we're
73 * satisfying some glGetTexImage() request or something.
75 * However, occasionally you want to actually map the miptree's current data
76 * without transcoding back. This flag to intel_miptree_map() gets you that.
78 #define BRW_MAP_DIRECT_BIT 0x80000000
80 struct intel_miptree_map
{
81 /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
83 /** Region of interest for the map. */
85 /** Possibly malloced temporary buffer for the mapping. */
87 /** Possible pointer to a temporary linear miptree for the mapping. */
88 struct intel_mipmap_tree
*mt
;
89 /** Pointer to the start of (map_x, map_y) returned by the mapping. */
91 /** Stride of the mapping. */
95 * intel_mipmap_tree::singlesample_mt is temporary storage that persists
96 * only for the duration of the map.
98 bool singlesample_mt_is_tmp
;
102 * Describes the location of each texture image within a texture region.
104 struct intel_mipmap_level
106 /** Offset to this miptree level, used in computing x_offset. */
108 /** Offset to this miptree level, used in computing y_offset. */
114 * \brief Number of 2D slices in this miplevel.
116 * The exact semantics of depth varies according to the texture target:
117 * - For GL_TEXTURE_CUBE_MAP, depth is 6.
118 * - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
119 * identical for all miplevels in the texture.
120 * - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
121 * value, like width and height, varies with miplevel.
122 * - For other texture types, depth is 1.
127 * \brief List of 2D images in this mipmap level.
129 * This may be a list of cube faces, array slices in 2D array texture, or
130 * layers in a 3D texture. The list's length is \c depth.
132 struct intel_mipmap_slice
{
134 * \name Offset to slice
137 * Hardware formats are so diverse that that there is no unified way to
138 * compute the slice offsets, so we store them in this table.
140 * The (x, y) offset to slice \c s at level \c l relative the miptrees
143 * x = mt->level[l].slice[s].x_offset
144 * y = mt->level[l].slice[s].y_offset
151 * Mapping information. Persistent for the duration of
152 * intel_miptree_map/unmap on this slice.
154 struct intel_miptree_map
*map
;
157 * \brief Is HiZ enabled for this slice?
159 * If \c mt->level[l].slice[s].has_hiz is set, then (1) \c mt->hiz_mt
160 * has been allocated and (2) the HiZ memory corresponding to this slice
161 * resides at \c mt->hiz_mt->level[l].slice[s].
168 * Enum for keeping track of the different MSAA layouts supported by Gen7.
170 enum intel_msaa_layout
173 * Ordinary surface with no MSAA.
175 INTEL_MSAA_LAYOUT_NONE
,
178 * Interleaved Multisample Surface. The additional samples are
179 * accommodated by scaling up the width and the height of the surface so
180 * that all the samples corresponding to a pixel are located at nearby
183 INTEL_MSAA_LAYOUT_IMS
,
186 * Uncompressed Multisample Surface. The surface is stored as a 2D array,
187 * with array slice n containing all pixel data for sample n.
189 INTEL_MSAA_LAYOUT_UMS
,
192 * Compressed Multisample Surface. The surface is stored as in
193 * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
194 * (Multisample Control Surface) buffer. Each pixel in the MCS buffer
195 * indicates the mapping from sample number to array slice. This allows
196 * the common case (where all samples constituting a pixel have the same
197 * color value) to be stored efficiently by just using a single array
200 INTEL_MSAA_LAYOUT_CMS
,
205 * Enum for keeping track of the state of an MCS buffer associated with a
206 * miptree. This determines when fast clear related operations are needed.
208 * Fast clear works by deferring the memory writes that would be used to clear
209 * the buffer, so that instead of performing them at the time of the clear
210 * operation, the hardware automatically performs them at the time that the
211 * buffer is later accessed for rendering. The MCS buffer keeps track of
212 * which regions of the buffer still have pending clear writes.
214 * This enum keeps track of the driver's knowledge of the state of the MCS
217 * MCS buffers only exist on Gen7+.
222 * There is no MCS buffer for this miptree, and one should never be
225 INTEL_MCS_STATE_NONE
,
228 * An MCS buffer exists for this miptree, and it is used for MSAA purposes.
230 INTEL_MCS_STATE_MSAA
,
233 * No deferred clears are pending for this miptree, and the contents of the
234 * color buffer are entirely correct. An MCS buffer may or may not exist
235 * for this miptree. If it does exist, it is entirely in the "no deferred
236 * clears pending" state. If it does not exist, it will be created the
237 * first time a fast color clear is executed.
239 * In this state, the color buffer can be used for purposes other than
240 * rendering without needing a render target resolve.
242 INTEL_MCS_STATE_RESOLVED
,
245 * An MCS buffer exists for this miptree, and deferred clears are pending
246 * for some regions of the color buffer, as indicated by the MCS buffer.
247 * The contents of the color buffer are only correct for the regions where
248 * the MCS buffer doesn't indicate a deferred clear.
250 * In this state, a render target resolve must be performed before the
251 * color buffer can be used for purposes other than rendering.
253 INTEL_MCS_STATE_UNRESOLVED
,
256 * An MCS buffer exists for this miptree, and deferred clears are pending
257 * for the entire color buffer, and the contents of the MCS buffer reflect
258 * this. The contents of the color buffer are undefined.
260 * In this state, a render target resolve must be performed before the
261 * color buffer can be used for purposes other than rendering.
263 * If the client attempts to clear a buffer which is already in this state,
264 * the clear can be safely skipped, since the buffer is already clear.
266 INTEL_MCS_STATE_CLEAR
,
269 struct intel_mipmap_tree
271 /* Effectively the key:
276 * Generally, this is just the same as the gl_texture_image->TexFormat or
277 * gl_renderbuffer->Format.
279 * However, for textures and renderbuffers with packed depth/stencil formats
280 * on hardware where we want or need to use separate stencil, there will be
281 * two miptrees for storing the data. If the depthstencil texture or rb is
282 * MESA_FORMAT_Z32_FLOAT_X24S8, then mt->format will be
283 * MESA_FORMAT_Z32_FLOAT, otherwise for MESA_FORMAT_S8_Z24 objects it will be
284 * MESA_FORMAT_X8_Z24.
286 * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
287 * formats if the hardware lacks support for ETC1/ETC2. See @ref wraps_etc.
291 /** This variable stores the value of ETC compressed texture format */
292 gl_format etc_format
;
295 * The X offset of each image in the miptree must be aligned to this.
296 * See the comments in brw_tex_layout.c.
298 unsigned int align_w
;
299 unsigned int align_h
; /**< \see align_w */
305 * Level zero image dimensions. These dimensions correspond to the
306 * physical layout of data in memory. Accordingly, they account for the
307 * extra width, height, and or depth that must be allocated in order to
308 * accommodate multisample formats, and they account for the extra factor
309 * of 6 in depth that must be allocated in order to accommodate cubemap
312 GLuint physical_width0
, physical_height0
, physical_depth0
;
319 * Level zero image dimensions. These dimensions correspond to the
320 * logical width, height, and depth of the region as seen by client code.
321 * Accordingly, they do not account for the extra width, height, and/or
322 * depth that must be allocated in order to accommodate multisample
323 * formats, nor do they account for the extra factor of 6 in depth that
324 * must be allocated in order to accommodate cubemap textures.
326 uint32_t logical_width0
, logical_height0
, logical_depth0
;
329 * For 1D array, 2D array, cube, and 2D multisampled surfaces on Gen7: true
330 * if the surface only contains LOD 0, and hence no space is for LOD's
331 * other than 0 in between array slices.
333 * Corresponds to the surface_array_spacing bit in gen7_surface_state.
335 bool array_spacing_lod0
;
338 * MSAA layout used by this buffer.
340 enum intel_msaa_layout msaa_layout
;
342 /* Derived from the above:
347 /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to
348 * this depth mipmap tree, if any.
350 uint32_t depth_clear_value
;
352 /* Includes image offset tables:
354 struct intel_mipmap_level level
[MAX_TEXTURE_LEVELS
];
356 /* The data is held here:
358 struct intel_region
*region
;
360 /* Offset into region bo where miptree starts:
365 * \brief Singlesample miptree.
367 * This is used under two cases.
369 * --- Case 1: As persistent singlesample storage for multisample window
370 * system front and back buffers ---
372 * Suppose that the window system FBO was created with a multisample
373 * config. Let `back_irb` be the `intel_renderbuffer` for the FBO's back
374 * buffer. Then `back_irb` contains two miptrees: a parent multisample
375 * miptree (back_irb->mt) and a child singlesample miptree
376 * (back_irb->mt->singlesample_mt). The DRM buffer shared with DRI2
377 * belongs to `back_irb->mt->singlesample_mt` and contains singlesample
378 * data. The singlesample miptree is created at the same time as and
379 * persists for the lifetime of its parent multisample miptree.
381 * When access to the singlesample data is needed, such as at
382 * eglSwapBuffers and glReadPixels, an automatic downsample occurs from
383 * `back_rb->mt` to `back_rb->mt->singlesample_mt` when necessary.
385 * This description of the back buffer applies analogously to the front
389 * --- Case 2: As temporary singlesample storage for mapping multisample
392 * Suppose the intel_miptree_map is called on a multisample miptree, `mt`,
393 * for which case 1 does not apply (that is, `mt` does not belong to
394 * a front or back buffer). Then `mt->singlesample_mt` is null at the
395 * start of the call. intel_miptree_map will create a temporary
396 * singlesample miptree, store it at `mt->singlesample_mt`, downsample from
397 * `mt` to `mt->singlesample_mt` if necessary, then map
398 * `mt->singlesample_mt`. The temporary miptree is later deleted during
399 * intel_miptree_unmap.
401 struct intel_mipmap_tree
*singlesample_mt
;
404 * \brief A downsample is needed from this miptree to singlesample_mt.
406 bool need_downsample
;
411 * The hiz miptree contains the miptree's hiz buffer. To allocate the hiz
412 * miptree, use intel_miptree_alloc_hiz().
414 * To determine if hiz is enabled, do not check this pointer. Instead, use
415 * intel_miptree_slice_has_hiz().
417 struct intel_mipmap_tree
*hiz_mt
;
420 * \brief Map of miptree slices to needed resolves.
422 * This is used only when the miptree has a child HiZ miptree.
424 * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
425 * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
426 * mt->hiz_mt->hiz_map, is unused.
428 struct intel_resolve_map hiz_map
;
431 * \brief Stencil miptree for depthstencil textures.
433 * This miptree is used for depthstencil textures and renderbuffers that
434 * require separate stencil. It always has the true copy of the stencil
435 * bits, regardless of mt->format.
437 * \see intel_miptree_map_depthstencil()
438 * \see intel_miptree_unmap_depthstencil()
440 struct intel_mipmap_tree
*stencil_mt
;
443 * \brief MCS miptree.
445 * This miptree contains the "multisample control surface", which stores
446 * the necessary information to implement compressed MSAA
447 * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
449 * NULL if no MCS miptree is in use for this surface.
451 struct intel_mipmap_tree
*mcs_mt
;
454 * MCS state for this buffer.
456 enum intel_mcs_state mcs_state
;
459 * The SURFACE_STATE bits associated with the last fast color clear to this
460 * color mipmap tree, if any.
462 * This value will only ever contain ones in bits 28-31, so it is safe to
463 * OR into dword 7 of SURFACE_STATE.
465 uint32_t fast_clear_color_value
;
467 /* These are also refcounted:
472 enum intel_miptree_tiling_mode
{
473 INTEL_MIPTREE_TILING_ANY
,
474 INTEL_MIPTREE_TILING_Y
,
475 INTEL_MIPTREE_TILING_NONE
,
479 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
480 struct intel_mipmap_tree
*mt
);
483 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
484 struct intel_mipmap_tree
*mt
,
485 unsigned *width_px
, unsigned *height
);
488 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
489 struct intel_mipmap_tree
*mt
);
491 struct intel_mipmap_tree
*intel_miptree_create(struct brw_context
*brw
,
499 bool expect_accelerated_upload
,
501 enum intel_miptree_tiling_mode
);
503 struct intel_mipmap_tree
*
504 intel_miptree_create_layout(struct brw_context
*brw
,
515 struct intel_mipmap_tree
*
516 intel_miptree_create_for_bo(struct brw_context
*brw
,
525 struct intel_mipmap_tree
*
526 intel_miptree_create_for_dri2_buffer(struct brw_context
*brw
,
527 unsigned dri_attachment
,
529 uint32_t num_samples
,
530 struct intel_region
*region
);
533 * Create a miptree appropriate as the storage for a non-texture renderbuffer.
534 * The miptree has the following properties:
535 * - The target is GL_TEXTURE_2D.
536 * - There are no levels other than the base level 0.
539 struct intel_mipmap_tree
*
540 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
544 uint32_t num_samples
);
546 /** \brief Assert that the level and layer are valid for the miptree. */
548 intel_miptree_check_level_layer(struct intel_mipmap_tree
*mt
,
552 assert(level
>= mt
->first_level
);
553 assert(level
<= mt
->last_level
);
554 assert(layer
< mt
->level
[level
].depth
);
557 void intel_miptree_reference(struct intel_mipmap_tree
**dst
,
558 struct intel_mipmap_tree
*src
);
560 void intel_miptree_release(struct intel_mipmap_tree
**mt
);
562 /* Check if an image fits an existing mipmap tree layout
564 bool intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
565 struct gl_texture_image
*image
);
568 intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt
,
569 GLuint level
, GLuint slice
,
570 GLuint
*x
, GLuint
*y
);
573 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
574 int *width
, int *height
, int *depth
);
577 intel_miptree_get_tile_offsets(struct intel_mipmap_tree
*mt
,
578 GLuint level
, GLuint slice
,
582 void intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
585 GLuint w
, GLuint h
, GLuint d
);
587 void intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
589 GLuint img
, GLuint x
, GLuint y
);
592 intel_miptree_copy_teximage(struct brw_context
*brw
,
593 struct intel_texture_image
*intelImage
,
594 struct intel_mipmap_tree
*dst_mt
, bool invalidate
);
597 intel_miptree_alloc_mcs(struct brw_context
*brw
,
598 struct intel_mipmap_tree
*mt
,
602 * \name Miptree HiZ functions
605 * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
606 * functions on a miptree without HiZ. In that case, each function is a no-op.
610 * \brief Allocate the miptree's embedded HiZ miptree.
611 * \see intel_mipmap_tree:hiz_mt
612 * \return false if allocation failed
616 intel_miptree_alloc_hiz(struct brw_context
*brw
,
617 struct intel_mipmap_tree
*mt
);
620 intel_miptree_slice_has_hiz(struct intel_mipmap_tree
*mt
,
625 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
629 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
634 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
638 * \return false if no resolve was needed
641 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
642 struct intel_mipmap_tree
*mt
,
647 * \return false if no resolve was needed
650 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
651 struct intel_mipmap_tree
*mt
,
656 * \return false if no resolve was needed
659 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
660 struct intel_mipmap_tree
*mt
);
663 * \return false if no resolve was needed
666 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
667 struct intel_mipmap_tree
*mt
);
672 * Update the fast clear state for a miptree to indicate that it has been used
676 intel_miptree_used_for_rendering(struct intel_mipmap_tree
*mt
)
678 /* If the buffer was previously in fast clear state, change it to
679 * unresolved state, since it won't be guaranteed to be clear after
682 if (mt
->mcs_state
== INTEL_MCS_STATE_CLEAR
)
683 mt
->mcs_state
= INTEL_MCS_STATE_UNRESOLVED
;
687 intel_miptree_resolve_color(struct brw_context
*brw
,
688 struct intel_mipmap_tree
*mt
);
691 intel_miptree_make_shareable(struct brw_context
*brw
,
692 struct intel_mipmap_tree
*mt
);
695 intel_miptree_downsample(struct brw_context
*brw
,
696 struct intel_mipmap_tree
*mt
);
699 intel_miptree_upsample(struct brw_context
*brw
,
700 struct intel_mipmap_tree
*mt
);
702 void brw_miptree_layout(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
);
704 void *intel_miptree_map_raw(struct brw_context
*brw
,
705 struct intel_mipmap_tree
*mt
);
707 void intel_miptree_unmap_raw(struct brw_context
*brw
,
708 struct intel_mipmap_tree
*mt
);
711 intel_miptree_map(struct brw_context
*brw
,
712 struct intel_mipmap_tree
*mt
,
724 intel_miptree_unmap(struct brw_context
*brw
,
725 struct intel_mipmap_tree
*mt
,
730 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
731 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);