1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
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28 /** @file intel_mipmap_tree.h
30 * This file defines the structure that wraps a BO and describes how the
31 * mipmap levels and slices of a texture are laid out.
33 * The hardware has a fixed layout of a texture depending on parameters such
34 * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
35 * mipmap levels. The individual level/layer slices are each 2D rectangles of
36 * pixels at some x/y offset from the start of the drm_intel_bo.
38 * Original OpenGL allowed texture miplevels to be specified in arbitrary
39 * order, and a texture may change size over time. Thus, each
40 * intel_texture_image has a reference to a miptree that contains the pixel
41 * data sized appropriately for it, which will later be referenced by/copied
42 * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
43 * that there's a single miptree for the complete texture.
46 #ifndef INTEL_MIPMAP_TREE_H
47 #define INTEL_MIPMAP_TREE_H
51 #include "main/mtypes.h"
52 #include "intel_bufmgr.h"
53 #include "intel_resolve_map.h"
54 #include <GL/internal/dri_interface.h>
61 struct intel_renderbuffer
;
63 struct intel_resolve_map
;
64 struct intel_texture_image
;
67 * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
68 * depthstencil-split-to-separate-stencil miptree, we'll normally make a
69 * tmeporary and recreate the kind of data requested by Mesa core, since we're
70 * satisfying some glGetTexImage() request or something.
72 * However, occasionally you want to actually map the miptree's current data
73 * without transcoding back. This flag to intel_miptree_map() gets you that.
75 #define BRW_MAP_DIRECT_BIT 0x80000000
77 struct intel_miptree_map
{
78 /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
80 /** Region of interest for the map. */
82 /** Possibly malloced temporary buffer for the mapping. */
84 /** Possible pointer to a temporary linear miptree for the mapping. */
85 struct intel_mipmap_tree
*mt
;
86 /** Pointer to the start of (map_x, map_y) returned by the mapping. */
88 /** Stride of the mapping. */
93 * Describes the location of each texture image within a miptree.
95 struct intel_mipmap_level
97 /** Offset to this miptree level, used in computing x_offset. */
99 /** Offset to this miptree level, used in computing y_offset. */
103 * \brief Number of 2D slices in this miplevel.
105 * The exact semantics of depth varies according to the texture target:
106 * - For GL_TEXTURE_CUBE_MAP, depth is 6.
107 * - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
108 * identical for all miplevels in the texture.
109 * - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
110 * value, like width and height, varies with miplevel.
111 * - For other texture types, depth is 1.
112 * - Additionally, for UMS and CMS miptrees, depth is multiplied by
118 * \brief Is HiZ enabled for this level?
120 * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
121 * allocated and (2) the HiZ memory for the slices in this level reside at
122 * \c mt->hiz_mt->level[l].
127 * \brief List of 2D images in this mipmap level.
129 * This may be a list of cube faces, array slices in 2D array texture, or
130 * layers in a 3D texture. The list's length is \c depth.
132 struct intel_mipmap_slice
{
134 * \name Offset to slice
137 * Hardware formats are so diverse that that there is no unified way to
138 * compute the slice offsets, so we store them in this table.
140 * The (x, y) offset to slice \c s at level \c l relative the miptrees
143 * x = mt->level[l].slice[s].x_offset
144 * y = mt->level[l].slice[s].y_offset
151 * Mapping information. Persistent for the duration of
152 * intel_miptree_map/unmap on this slice.
154 struct intel_miptree_map
*map
;
159 * Enum for keeping track of the different MSAA layouts supported by Gen7.
161 enum intel_msaa_layout
164 * Ordinary surface with no MSAA.
166 INTEL_MSAA_LAYOUT_NONE
,
169 * Interleaved Multisample Surface. The additional samples are
170 * accommodated by scaling up the width and the height of the surface so
171 * that all the samples corresponding to a pixel are located at nearby
174 INTEL_MSAA_LAYOUT_IMS
,
177 * Uncompressed Multisample Surface. The surface is stored as a 2D array,
178 * with array slice n containing all pixel data for sample n.
180 INTEL_MSAA_LAYOUT_UMS
,
183 * Compressed Multisample Surface. The surface is stored as in
184 * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
185 * (Multisample Control Surface) buffer. Each pixel in the MCS buffer
186 * indicates the mapping from sample number to array slice. This allows
187 * the common case (where all samples constituting a pixel have the same
188 * color value) to be stored efficiently by just using a single array
191 INTEL_MSAA_LAYOUT_CMS
,
196 * Enum for keeping track of the fast clear state of a buffer associated with
199 * Fast clear works by deferring the memory writes that would be used to clear
200 * the buffer, so that instead of performing them at the time of the clear
201 * operation, the hardware automatically performs them at the time that the
202 * buffer is later accessed for rendering. The MCS buffer keeps track of
203 * which regions of the buffer still have pending clear writes.
205 * This enum keeps track of the driver's knowledge of pending fast clears in
208 * MCS buffers only exist on Gen7+.
210 enum intel_fast_clear_state
213 * There is no MCS buffer for this miptree, and one should never be
216 INTEL_FAST_CLEAR_STATE_NO_MCS
,
219 * No deferred clears are pending for this miptree, and the contents of the
220 * color buffer are entirely correct. An MCS buffer may or may not exist
221 * for this miptree. If it does exist, it is entirely in the "no deferred
222 * clears pending" state. If it does not exist, it will be created the
223 * first time a fast color clear is executed.
225 * In this state, the color buffer can be used for purposes other than
226 * rendering without needing a render target resolve.
228 * Since there is no such thing as a "fast color clear resolve" for MSAA
229 * buffers, an MSAA buffer will never be in this state.
231 INTEL_FAST_CLEAR_STATE_RESOLVED
,
234 * An MCS buffer exists for this miptree, and deferred clears are pending
235 * for some regions of the color buffer, as indicated by the MCS buffer.
236 * The contents of the color buffer are only correct for the regions where
237 * the MCS buffer doesn't indicate a deferred clear.
239 * If a single-sample buffer is in this state, a render target resolve must
240 * be performed before it can be used for purposes other than rendering.
242 INTEL_FAST_CLEAR_STATE_UNRESOLVED
,
245 * An MCS buffer exists for this miptree, and deferred clears are pending
246 * for the entire color buffer, and the contents of the MCS buffer reflect
247 * this. The contents of the color buffer are undefined.
249 * If a single-sample buffer is in this state, a render target resolve must
250 * be performed before it can be used for purposes other than rendering.
252 * If the client attempts to clear a buffer which is already in this state,
253 * the clear can be safely skipped, since the buffer is already clear.
255 INTEL_FAST_CLEAR_STATE_CLEAR
,
258 enum miptree_array_layout
{
259 /* Each array slice contains all miplevels packed together.
261 * Gen hardware usually wants multilevel miptrees configured this way.
263 * A 2D Array texture with 2 slices and multiple LODs using
264 * ALL_LOD_IN_EACH_SLICE would look somewhat like this:
281 ALL_LOD_IN_EACH_SLICE
,
283 /* Each LOD contains all slices of that LOD packed together.
285 * In some situations, Gen7+ hardware can use the array_spacing_lod0
286 * feature to save space when the surface only contains LOD 0.
288 * Gen6 uses this for separate stencil and hiz since gen6 does not support
289 * multiple LODs for separate stencil and hiz.
291 * A 2D Array texture with 2 slices and multiple LODs using
292 * ALL_SLICES_AT_EACH_LOD would look somewhat like this:
307 ALL_SLICES_AT_EACH_LOD
,
311 * Miptree aux buffer. These buffers are associated with a miptree, but the
312 * format is managed by the hardware.
314 * For Gen7+, we always give the hardware the start of the buffer, and let it
315 * handle all accesses to the buffer. Therefore we don't need the full miptree
316 * layout structure for this buffer.
318 * For Gen6, we need a hiz miptree structure for this buffer so we can program
319 * offsets to slices & miplevels.
321 struct intel_miptree_aux_buffer
323 /** Buffer object containing the pixel data. */
326 uint32_t pitch
; /**< pitch in bytes. */
328 uint32_t qpitch
; /**< The distance in rows between array slices. */
330 struct intel_mipmap_tree
*mt
; /**< hiz miptree used with Gen6 */
333 /* Tile resource modes */
334 enum intel_miptree_tr_mode
{
335 INTEL_MIPTREE_TRMODE_NONE
,
336 INTEL_MIPTREE_TRMODE_YF
,
337 INTEL_MIPTREE_TRMODE_YS
340 struct intel_mipmap_tree
342 /** Buffer object containing the pixel data. */
345 uint32_t pitch
; /**< pitch in bytes. */
347 uint32_t tiling
; /**< One of the I915_TILING_* flags */
348 enum intel_miptree_tr_mode tr_mode
;
350 /* Effectively the key:
355 * Generally, this is just the same as the gl_texture_image->TexFormat or
356 * gl_renderbuffer->Format.
358 * However, for textures and renderbuffers with packed depth/stencil formats
359 * on hardware where we want or need to use separate stencil, there will be
360 * two miptrees for storing the data. If the depthstencil texture or rb is
361 * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
362 * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
363 * MESA_FORMAT_Z24_UNORM_X8_UINT.
365 * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
366 * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
370 /** This variable stores the value of ETC compressed texture format */
371 mesa_format etc_format
;
374 * The X offset of each image in the miptree must be aligned to this.
375 * See the comments in brw_tex_layout.c.
377 unsigned int align_w
;
378 unsigned int align_h
; /**< \see align_w */
384 * Level zero image dimensions. These dimensions correspond to the
385 * physical layout of data in memory. Accordingly, they account for the
386 * extra width, height, and or depth that must be allocated in order to
387 * accommodate multisample formats, and they account for the extra factor
388 * of 6 in depth that must be allocated in order to accommodate cubemap
391 GLuint physical_width0
, physical_height0
, physical_depth0
;
393 GLuint cpp
; /**< bytes per pixel */
398 * Level zero image dimensions. These dimensions correspond to the
399 * logical width, height, and depth of the texture as seen by client code.
400 * Accordingly, they do not account for the extra width, height, and/or
401 * depth that must be allocated in order to accommodate multisample
402 * formats, nor do they account for the extra factor of 6 in depth that
403 * must be allocated in order to accommodate cubemap textures.
405 uint32_t logical_width0
, logical_height0
, logical_depth0
;
408 * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
409 * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
411 enum miptree_array_layout array_layout
;
414 * The distance in between array slices.
416 * The value is the one that is sent in the surface state. The actual
417 * meaning depends on certain criteria. Usually it is simply the number of
418 * uncompressed rows between each slice. However on Gen9+ for compressed
419 * surfaces it is the number of blocks. For 1D array surfaces that have the
420 * mipmap tree stored horizontally it is the number of pixels between each
426 * MSAA layout used by this buffer.
428 enum intel_msaa_layout msaa_layout
;
430 /* Derived from the above:
435 /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to
436 * this depth mipmap tree, if any.
438 uint32_t depth_clear_value
;
440 /* Includes image offset tables:
442 struct intel_mipmap_level level
[MAX_TEXTURE_LEVELS
];
444 /* Offset into bo where miptree starts:
449 * \brief HiZ aux buffer
451 * The hiz miptree contains the miptree's hiz buffer. To allocate the hiz
452 * buffer, use intel_miptree_alloc_hiz().
454 * To determine if hiz is enabled, do not check this pointer. Instead, use
455 * intel_miptree_slice_has_hiz().
457 struct intel_miptree_aux_buffer
*hiz_buf
;
460 * \brief Map of miptree slices to needed resolves.
462 * This is used only when the miptree has a child HiZ miptree.
464 * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
465 * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
466 * mt->hiz_mt->hiz_map, is unused.
468 struct exec_list hiz_map
; /* List of intel_resolve_map. */
471 * \brief Stencil miptree for depthstencil textures.
473 * This miptree is used for depthstencil textures and renderbuffers that
474 * require separate stencil. It always has the true copy of the stencil
475 * bits, regardless of mt->format.
477 * \see intel_miptree_map_depthstencil()
478 * \see intel_miptree_unmap_depthstencil()
480 struct intel_mipmap_tree
*stencil_mt
;
483 * \brief MCS miptree.
485 * This miptree contains the "multisample control surface", which stores
486 * the necessary information to implement compressed MSAA
487 * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
489 * NULL if no MCS miptree is in use for this surface.
491 struct intel_mipmap_tree
*mcs_mt
;
494 * Fast clear state for this buffer.
496 enum intel_fast_clear_state fast_clear_state
;
499 * The SURFACE_STATE bits associated with the last fast color clear to this
500 * color mipmap tree, if any.
502 * This value will only ever contain ones in bits 28-31, so it is safe to
503 * OR into dword 7 of SURFACE_STATE.
505 uint32_t fast_clear_color_value
;
508 * Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS
509 * buffer. This is useful for sharing the miptree bo with an external client
510 * that doesn't understand auxiliary buffers.
512 bool disable_aux_buffers
;
514 /* These are also refcounted:
520 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
521 struct intel_mipmap_tree
*mt
,
522 unsigned *width_px
, unsigned *height
);
524 intel_tiling_supports_non_msrt_mcs(struct brw_context
*brw
, unsigned tiling
);
526 intel_miptree_is_fast_clear_capable(struct brw_context
*brw
,
527 struct intel_mipmap_tree
*mt
);
529 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
530 struct intel_mipmap_tree
*mt
);
533 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
= 1 << 0,
534 MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
= 1 << 1,
535 MIPTREE_LAYOUT_FOR_BO
= 1 << 2,
536 MIPTREE_LAYOUT_DISABLE_AUX
= 1 << 3,
537 MIPTREE_LAYOUT_FORCE_HALIGN16
= 1 << 4,
539 MIPTREE_LAYOUT_ALLOC_YTILED
= 1 << 5,
540 MIPTREE_LAYOUT_ALLOC_LINEAR
= 1 << 6,
541 MIPTREE_LAYOUT_ALLOC_ANY_TILED
= MIPTREE_LAYOUT_ALLOC_YTILED
|
542 MIPTREE_LAYOUT_ALLOC_LINEAR
,
545 struct intel_mipmap_tree
*intel_miptree_create(struct brw_context
*brw
,
556 struct intel_mipmap_tree
*
557 intel_miptree_create_for_bo(struct brw_context
*brw
,
565 uint32_t layout_flags
);
568 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
569 struct intel_renderbuffer
*irb
,
571 uint32_t width
, uint32_t height
,
575 * Create a miptree appropriate as the storage for a non-texture renderbuffer.
576 * The miptree has the following properties:
577 * - The target is GL_TEXTURE_2D.
578 * - There are no levels other than the base level 0.
581 struct intel_mipmap_tree
*
582 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
586 uint32_t num_samples
);
589 intel_depth_format_for_depthstencil_format(mesa_format format
);
592 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
);
594 /** \brief Assert that the level and layer are valid for the miptree. */
596 intel_miptree_check_level_layer(struct intel_mipmap_tree
*mt
,
600 assert(level
>= mt
->first_level
);
601 assert(level
<= mt
->last_level
);
602 assert(layer
< mt
->level
[level
].depth
);
605 void intel_miptree_reference(struct intel_mipmap_tree
**dst
,
606 struct intel_mipmap_tree
*src
);
608 void intel_miptree_release(struct intel_mipmap_tree
**mt
);
610 /* Check if an image fits an existing mipmap tree layout
612 bool intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
613 struct gl_texture_image
*image
);
616 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
617 GLuint level
, GLuint slice
,
618 GLuint
*x
, GLuint
*y
);
621 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
622 int *width
, int *height
, int *depth
);
625 intel_miptree_get_tile_masks(const struct intel_mipmap_tree
*mt
,
626 uint32_t *mask_x
, uint32_t *mask_y
,
627 bool map_stencil_as_y_tiled
);
630 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
631 GLuint level
, GLuint slice
,
635 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
636 uint32_t x
, uint32_t y
,
637 bool map_stencil_as_y_tiled
);
639 void intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
641 GLuint x
, GLuint y
, GLuint d
);
643 void intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
645 GLuint img
, GLuint x
, GLuint y
);
648 intel_miptree_copy_teximage(struct brw_context
*brw
,
649 struct intel_texture_image
*intelImage
,
650 struct intel_mipmap_tree
*dst_mt
, bool invalidate
);
653 * \name Miptree HiZ functions
656 * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
657 * functions on a miptree without HiZ. In that case, each function is a no-op.
661 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
662 struct intel_mipmap_tree
*mt
);
665 * \brief Allocate the miptree's embedded HiZ miptree.
666 * \see intel_mipmap_tree:hiz_mt
667 * \return false if allocation failed
670 intel_miptree_alloc_hiz(struct brw_context
*brw
,
671 struct intel_mipmap_tree
*mt
);
674 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
);
677 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
681 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
686 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
690 * \return false if no resolve was needed
693 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
694 struct intel_mipmap_tree
*mt
,
699 * \return false if no resolve was needed
702 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
703 struct intel_mipmap_tree
*mt
,
708 * \return false if no resolve was needed
711 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
712 struct intel_mipmap_tree
*mt
);
715 * \return false if no resolve was needed
718 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
719 struct intel_mipmap_tree
*mt
);
724 * Update the fast clear state for a miptree to indicate that it has been used
728 intel_miptree_used_for_rendering(struct intel_mipmap_tree
*mt
)
730 /* If the buffer was previously in fast clear state, change it to
731 * unresolved state, since it won't be guaranteed to be clear after
734 if (mt
->fast_clear_state
== INTEL_FAST_CLEAR_STATE_CLEAR
)
735 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_UNRESOLVED
;
739 intel_miptree_resolve_color(struct brw_context
*brw
,
740 struct intel_mipmap_tree
*mt
);
743 intel_miptree_make_shareable(struct brw_context
*brw
,
744 struct intel_mipmap_tree
*mt
);
747 intel_miptree_updownsample(struct brw_context
*brw
,
748 struct intel_mipmap_tree
*src
,
749 struct intel_mipmap_tree
*dst
);
752 * Horizontal distance from one slice to the next in the two-dimensional
756 brw_miptree_get_horizontal_slice_pitch(const struct brw_context
*brw
,
757 const struct intel_mipmap_tree
*mt
,
761 * Vertical distance from one slice to the next in the two-dimensional miptree
765 brw_miptree_get_vertical_slice_pitch(const struct brw_context
*brw
,
766 const struct intel_mipmap_tree
*mt
,
770 brw_miptree_layout(struct brw_context
*brw
,
771 struct intel_mipmap_tree
*mt
,
772 uint32_t layout_flags
);
774 void *intel_miptree_map_raw(struct brw_context
*brw
,
775 struct intel_mipmap_tree
*mt
);
777 void intel_miptree_unmap_raw(struct brw_context
*brw
,
778 struct intel_mipmap_tree
*mt
);
781 intel_miptree_map(struct brw_context
*brw
,
782 struct intel_mipmap_tree
*mt
,
791 ptrdiff_t *out_stride
);
794 intel_miptree_unmap(struct brw_context
*brw
,
795 struct intel_mipmap_tree
*mt
,
800 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
801 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);