src/mesa/drivers/dri/i965/intel_mipmap_tree.h

   1 /*
   2  * Copyright 2006 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 /** @file intel_mipmap_tree.h
  27  *
  28  * This file defines the structure that wraps a BO and describes how the
  29  * mipmap levels and slices of a texture are laid out.
  30  *
  31  * The hardware has a fixed layout of a texture depending on parameters such
  32  * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
  33  * mipmap levels.  The individual level/layer slices are each 2D rectangles of
  34  * pixels at some x/y offset from the start of the brw_bo.
  35  *
  36  * Original OpenGL allowed texture miplevels to be specified in arbitrary
  37  * order, and a texture may change size over time.  Thus, each
  38  * intel_texture_image has a reference to a miptree that contains the pixel
  39  * data sized appropriately for it, which will later be referenced by/copied
  40  * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
  41  * that there's a single miptree for the complete texture.
  42  */
  43
  44 #ifndef INTEL_MIPMAP_TREE_H
  45 #define INTEL_MIPMAP_TREE_H
  46
  47 #include <assert.h>
  48
  49 #include "main/mtypes.h"
  50 #include "isl/isl.h"
  51 #include "blorp/blorp.h"
  52 #include "brw_bufmgr.h"
  53 #include <GL/internal/dri_interface.h>
  54
  55 #ifdef __cplusplus
  56 extern "C" {
  57 #endif
  58
  59 struct brw_context;
  60 struct intel_renderbuffer;
  61
  62 struct intel_texture_image;
  63
  64 /**
  65  * This bit extends the set of GL_MAP_*_BIT enums.
  66  *
  67  * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
  68  * depthstencil-split-to-separate-stencil miptree, we'll normally make a
  69  * temporary and recreate the kind of data requested by Mesa core, since we're
  70  * satisfying some glGetTexImage() request or something.
  71  *
  72  * However, occasionally you want to actually map the miptree's current data
  73  * without transcoding back.  This flag to intel_miptree_map() gets you that.
  74  */
  75 #define BRW_MAP_DIRECT_BIT      0x80000000
  76
  77 struct intel_miptree_map {
  78    /** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */
  79    GLbitfield mode;
  80    /** Region of interest for the map. */
  81    int x, y, w, h;
  82    /** Possibly malloced temporary buffer for the mapping. */
  83    void *buffer;
  84    /** Possible pointer to a temporary linear miptree for the mapping. */
  85    struct intel_mipmap_tree *linear_mt;
  86    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  87    void *ptr;
  88    /** Stride of the mapping. */
  89    int stride;
  90 };
  91
  92 /**
  93  * Describes the location of each texture image within a miptree.
  94  */
  95 struct intel_mipmap_level
  96 {
  97    /** Offset to this miptree level, used in computing x_offset. */
  98    GLuint level_x;
  99    /** Offset to this miptree level, used in computing y_offset. */
 100    GLuint level_y;
 101
 102    /**
 103     * \brief Number of 2D slices in this miplevel.
 104     *
 105     * The exact semantics of depth varies according to the texture target:
 106     *    - For GL_TEXTURE_CUBE_MAP, depth is 6.
 107     *    - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
 108     *      identical for all miplevels in the texture.
 109     *    - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
 110     *      value, like width and height, varies with miplevel.
 111     *    - For other texture types, depth is 1.
 112     *    - Additionally, for UMS and CMS miptrees, depth is multiplied by
 113     *      sample count.
 114     */
 115    GLuint depth;
 116
 117    /**
 118     * \brief Is HiZ enabled for this level?
 119     *
 120     * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
 121     * allocated and (2) the HiZ memory for the slices in this level reside at
 122     * \c mt->hiz_mt->level[l].
 123     */
 124    bool has_hiz;
 125
 126    /**
 127     * \brief List of 2D images in this mipmap level.
 128     *
 129     * This may be a list of cube faces, array slices in 2D array texture, or
 130     * layers in a 3D texture. The list's length is \c depth.
 131     */
 132    struct intel_mipmap_slice {
 133       /**
 134        * \name Offset to slice
 135        * \{
 136        *
 137        * Hardware formats are so diverse that that there is no unified way to
 138        * compute the slice offsets, so we store them in this table.
 139        *
 140        * The (x, y) offset to slice \c s at level \c l relative the miptrees
 141        * base address is
 142        * \code
 143        *     x = mt->level[l].slice[s].x_offset
 144        *     y = mt->level[l].slice[s].y_offset
 145        *
 146        * On some hardware generations, we program these offsets into
 147        * RENDER_SURFACE_STATE.XOffset and RENDER_SURFACE_STATE.YOffset.
 148        */
 149       GLuint x_offset;
 150       GLuint y_offset;
 151       /** \} */
 152
 153       /**
 154        * Mapping information. Persistent for the duration of
 155        * intel_miptree_map/unmap on this slice.
 156        */
 157       struct intel_miptree_map *map;
 158    } *slice;
 159 };
 160
 161 enum miptree_array_layout {
 162    /* Each array slice contains all miplevels packed together.
 163     *
 164     * Gen hardware usually wants multilevel miptrees configured this way.
 165     *
 166     * A 2D Array texture with 2 slices and multiple LODs using
 167     * ALL_LOD_IN_EACH_SLICE would look somewhat like this:
 168     *
 169     *   +----------+
 170     *   |          |
 171     *   |          |
 172     *   +----------+
 173     *   +---+ +-+
 174     *   |   | +-+
 175     *   +---+ *
 176     *   +----------+
 177     *   |          |
 178     *   |          |
 179     *   +----------+
 180     *   +---+ +-+
 181     *   |   | +-+
 182     *   +---+ *
 183     */
 184    ALL_LOD_IN_EACH_SLICE,
 185
 186    /* Each LOD contains all slices of that LOD packed together.
 187     *
 188     * In some situations, Gen7+ hardware can use the array_spacing_lod0
 189     * feature to save space when the surface only contains LOD 0.
 190     *
 191     * Gen6 uses this for separate stencil and hiz since gen6 does not support
 192     * multiple LODs for separate stencil and hiz.
 193     *
 194     * A 2D Array texture with 2 slices and multiple LODs using
 195     * ALL_SLICES_AT_EACH_LOD would look somewhat like this:
 196     *
 197     *   +----------+
 198     *   |          |
 199     *   |          |
 200     *   +----------+
 201     *   |          |
 202     *   |          |
 203     *   +----------+
 204     *   +---+ +-+
 205     *   |   | +-+
 206     *   +---+ +-+
 207     *   |   | :
 208     *   +---+
 209     */
 210    ALL_SLICES_AT_EACH_LOD,
 211
 212    /* On Sandy Bridge, HiZ and stencil buffers work the same as on Ivy Bridge
 213     * except that they don't technically support mipmapping.  That does not,
 214     * however, stop us from doing it.  As far as Sandy Bridge hardware is
 215     * concerned, HiZ and stencil always operates on a single miplevel 2D
 216     * (possibly array) image.  The dimensions of that image are NOT minified.
 217     *
 218     * In order to implement HiZ and stencil on Sandy Bridge, we create one
 219     * full-sized 2D (possibly array) image for every LOD with every image
 220     * aligned to a page boundary.  In order to save memory, we pretend that
 221     * the width of each miplevel is minified and we place LOD1 and above below
 222     * LOD0 but horizontally adjacent to each other.  When considered as
 223     * full-sized images, LOD1 and above technically overlap.  However, since
 224     * we only write to part of that image, the hardware will never notice the
 225     * overlap.
 226     *
 227     * This layout looks something like this:
 228     *
 229     *   +---------+
 230     *   |         |
 231     *   |         |
 232     *   +---------+
 233     *   |         |
 234     *   |         |
 235     *   +---------+
 236     *
 237     *   +----+ +-+ .
 238     *   |    | +-+
 239     *   +----+
 240     *
 241     *   +----+ +-+ .
 242     *   |    | +-+
 243     *   +----+
 244     */
 245    GEN6_HIZ_STENCIL,
 246 };
 247
 248 /**
 249  * Miptree aux buffer. These buffers are associated with a miptree, but the
 250  * format is managed by the hardware.
 251  *
 252  * For Gen7+, we always give the hardware the start of the buffer, and let it
 253  * handle all accesses to the buffer. Therefore we don't need the full miptree
 254  * layout structure for this buffer.
 255  */
 256 struct intel_miptree_aux_buffer
 257 {
 258    struct isl_surf surf;
 259
 260    /**
 261     * Buffer object containing the pixel data.
 262     *
 263     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 264     * @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
 265     */
 266    struct brw_bo *bo;
 267
 268    /**
 269     * Offset into bo where the surface starts.
 270     *
 271     * @see intel_mipmap_aux_buffer::bo
 272     *
 273     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 274     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 275     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 276     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 277     */
 278    uint32_t offset;
 279
 280    /*
 281     * Size of the MCS surface.
 282     *
 283     * This is needed when doing any gtt mapped operations on the buffer (which
 284     * will be Y-tiled). It is possible that it will not be the same as bo->size
 285     * when the drm allocator rounds up the requested size.
 286     */
 287    size_t size;
 288
 289    /**
 290     * Pitch in bytes.
 291     *
 292     * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
 293     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
 294     */
 295    uint32_t pitch;
 296
 297    /**
 298     * The distance in rows between array slices.
 299     *
 300     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch
 301     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
 302     */
 303    uint32_t qpitch;
 304 };
 305
 306 struct intel_mipmap_tree
 307 {
 308    struct isl_surf surf;
 309
 310    /**
 311     * Buffer object containing the surface.
 312     *
 313     * @see intel_mipmap_tree::offset
 314     * @see RENDER_SURFACE_STATE.SurfaceBaseAddress
 315     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 316     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 317     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 318     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 319     */
 320    struct brw_bo *bo;
 321
 322    /**
 323     * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
 324     *
 325     * @see RENDER_SURFACE_STATE.SurfaceType
 326     * @see RENDER_SURFACE_STATE.SurfaceArray
 327     * @see 3DSTATE_DEPTH_BUFFER.SurfaceType
 328     */
 329    GLenum target;
 330
 331    /**
 332     * Generally, this is just the same as the gl_texture_image->TexFormat or
 333     * gl_renderbuffer->Format.
 334     *
 335     * However, for textures and renderbuffers with packed depth/stencil formats
 336     * on hardware where we want or need to use separate stencil, there will be
 337     * two miptrees for storing the data.  If the depthstencil texture or rb is
 338     * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
 339     * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
 340     * MESA_FORMAT_Z24_UNORM_X8_UINT.
 341     *
 342     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
 343     * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
 344     *
 345     * @see RENDER_SURFACE_STATE.SurfaceFormat
 346     * @see 3DSTATE_DEPTH_BUFFER.SurfaceFormat
 347     */
 348    mesa_format format;
 349
 350    /**
 351     * This variable stores the value of ETC compressed texture format
 352     *
 353     * @see RENDER_SURFACE_STATE.SurfaceFormat
 354     */
 355    mesa_format etc_format;
 356
 357    /**
 358     * @name Surface Alignment
 359     * @{
 360     *
 361     * This defines the alignment of the upperleft pixel of each "slice" in the
 362     * surface. The alignment is in pixel coordinates relative to the surface's
 363     * most upperleft pixel, which is the pixel at (x=0, y=0, layer=0,
 364     * level=0).
 365     *
 366     * The hardware docs do not use the term "slice".  We use "slice" to mean
 367     * the pixels at a given miplevel and layer. For 2D surfaces, the layer is
 368     * the array slice; for 3D surfaces, the layer is the z offset.
 369     *
 370     * In the surface layout equations found in the hardware docs, the
 371     * horizontal and vertical surface alignments often appear as variables 'i'
 372     * and 'j'.
 373     */
 374
 375    /** @see RENDER_SURFACE_STATE.SurfaceHorizontalAlignment */
 376    uint32_t halign;
 377
 378    /** @see RENDER_SURFACE_STATE.SurfaceVerticalAlignment */
 379    uint32_t valign;
 380    /** @} */
 381
 382    GLuint first_level;
 383    GLuint last_level;
 384
 385    /**
 386     * Level zero image dimensions.  These dimensions correspond to the
 387     * physical layout of data in memory.  Accordingly, they account for the
 388     * extra width, height, and or depth that must be allocated in order to
 389     * accommodate multisample formats, and they account for the extra factor
 390     * of 6 in depth that must be allocated in order to accommodate cubemap
 391     * textures.
 392     */
 393    GLuint physical_width0, physical_height0, physical_depth0;
 394
 395    /** Bytes per pixel (or bytes per block if compressed) */
 396    GLuint cpp;
 397
 398    bool compressed;
 399
 400    /**
 401     * @name Level zero image dimensions
 402     * @{
 403     *
 404     * These dimensions correspond to the
 405     * logical width, height, and depth of the texture as seen by client code.
 406     * Accordingly, they do not account for the extra width, height, and/or
 407     * depth that must be allocated in order to accommodate multisample
 408     * formats, nor do they account for the extra factor of 6 in depth that
 409     * must be allocated in order to accommodate cubemap textures.
 410     */
 411
 412    /**
 413     * @see RENDER_SURFACE_STATE.Width
 414     * @see 3DSTATE_DEPTH_BUFFER.Width
 415     */
 416    uint32_t logical_width0;
 417
 418    /**
 419     * @see RENDER_SURFACE_STATE.Height
 420     * @see 3DSTATE_DEPTH_BUFFER.Height
 421     */
 422    uint32_t logical_height0;
 423
 424    /**
 425     * @see RENDER_SURFACE_STATE.Depth
 426     * @see 3DSTATE_DEPTH_BUFFER.Depth
 427     */
 428    uint32_t logical_depth0;
 429    /** @} */
 430
 431    /**
 432     * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
 433     * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
 434     */
 435    enum miptree_array_layout array_layout;
 436
 437    /**
 438     * The distance in between array slices.
 439     *
 440     * The value is the one that is sent in the surface state. The actual
 441     * meaning depends on certain criteria. Usually it is simply the number of
 442     * uncompressed rows between each slice. However on Gen9+ for compressed
 443     * surfaces it is the number of blocks. For 1D array surfaces that have the
 444     * mipmap tree stored horizontally it is the number of pixels between each
 445     * slice.
 446     *
 447     * @see RENDER_SURFACE_STATE.SurfaceQPitch
 448     * @see 3DSTATE_DEPTH_BUFFER.SurfaceQPitch
 449     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
 450     * @see 3DSTATE_STENCIL_BUFFER.SurfaceQPitch
 451     */
 452    uint32_t qpitch;
 453
 454    /* Derived from the above:
 455     */
 456    GLuint total_width;
 457    GLuint total_height;
 458
 459    /* Includes image offset tables: */
 460    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 461
 462    /**
 463     * Offset into bo where the surface starts.
 464     *
 465     * @see intel_mipmap_tree::bo
 466     *
 467     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 468     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 469     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 470     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 471     */
 472    uint32_t offset;
 473
 474    /**
 475     * \brief HiZ aux buffer
 476     *
 477     * To allocate the hiz buffer, use intel_miptree_alloc_hiz().
 478     *
 479     * To determine if hiz is enabled, do not check this pointer. Instead, use
 480     * intel_miptree_level_has_hiz().
 481     */
 482    struct intel_miptree_aux_buffer *hiz_buf;
 483
 484    /**
 485     * \brief The type of auxiliary compression used by this miptree.
 486     *
 487     * This describes the type of auxiliary compression that is intended to be
 488     * used by this miptree.  An aux usage of ISL_AUX_USAGE_NONE means that
 489     * auxiliary compression is permanently disabled.  An aux usage other than
 490     * ISL_AUX_USAGE_NONE does not imply that the auxiliary buffer has actually
 491     * been allocated nor does it imply that auxiliary compression will always
 492     * be enabled for this surface.  For instance, with CCS_D, we may allocate
 493     * the CCS on-the-fly and it may not be used for texturing if the miptree
 494     * is fully resolved.
 495     */
 496    enum isl_aux_usage aux_usage;
 497
 498    /**
 499     * \brief Whether or not this miptree supports fast clears.
 500     */
 501    bool supports_fast_clear;
 502
 503    /**
 504     * \brief Maps miptree slices to their current aux state
 505     *
 506     * This two-dimensional array is indexed as [level][layer] and stores an
 507     * aux state for each slice.
 508     */
 509    enum isl_aux_state **aux_state;
 510
 511    /**
 512     * \brief Stencil miptree for depthstencil textures.
 513     *
 514     * This miptree is used for depthstencil textures and renderbuffers that
 515     * require separate stencil.  It always has the true copy of the stencil
 516     * bits, regardless of mt->format.
 517     *
 518     * \see 3DSTATE_STENCIL_BUFFER
 519     * \see intel_miptree_map_depthstencil()
 520     * \see intel_miptree_unmap_depthstencil()
 521     */
 522    struct intel_mipmap_tree *stencil_mt;
 523
 524    /**
 525     * \brief Stencil texturing miptree for sampling from a stencil texture
 526     *
 527     * Some hardware doesn't support sampling from the stencil texture as
 528     * required by the GL_ARB_stencil_texturing extenion. To workaround this we
 529     * blit the texture into a new texture that can be sampled.
 530     *
 531     * \see intel_update_r8stencil()
 532     */
 533    struct intel_mipmap_tree *r8stencil_mt;
 534    bool r8stencil_needs_update;
 535
 536    /**
 537     * \brief MCS auxiliary buffer.
 538     *
 539     * This buffer contains the "multisample control surface", which stores
 540     * the necessary information to implement compressed MSAA
 541     * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
 542     *
 543     * NULL if no MCS buffer is in use for this surface.
 544     */
 545    struct intel_miptree_aux_buffer *mcs_buf;
 546
 547    /**
 548     * Planes 1 and 2 in case this is a planar surface.
 549     */
 550    struct intel_mipmap_tree *plane[2];
 551
 552    /**
 553     * Fast clear color for this surface.  For depth surfaces, the clear value
 554     * is stored as a float32 in the red component.
 555     */
 556    union isl_color_value fast_clear_color;
 557
 558    /**
 559     * Tells if the underlying buffer is to be also consumed by entities other
 560     * than the driver. This allows logic to turn off features such as lossless
 561     * compression which is not currently understood by client applications.
 562     */
 563    bool is_scanout;
 564
 565    /* These are also refcounted:
 566     */
 567    GLuint refcount;
 568 };
 569
 570 bool
 571 intel_miptree_alloc_ccs(struct brw_context *brw,
 572                         struct intel_mipmap_tree *mt);
 573
 574 enum {
 575    MIPTREE_LAYOUT_ACCELERATED_UPLOAD       = 1 << 0,
 576    MIPTREE_LAYOUT_GEN6_HIZ_STENCIL         = 1 << 1,
 577    MIPTREE_LAYOUT_FOR_BO                   = 1 << 2,
 578    MIPTREE_LAYOUT_DISABLE_AUX              = 1 << 3,
 579    MIPTREE_LAYOUT_FORCE_HALIGN16           = 1 << 4,
 580
 581    MIPTREE_LAYOUT_TILING_Y                 = 1 << 5,
 582    MIPTREE_LAYOUT_TILING_NONE              = 1 << 6,
 583    MIPTREE_LAYOUT_TILING_ANY               = MIPTREE_LAYOUT_TILING_Y |
 584                                              MIPTREE_LAYOUT_TILING_NONE,
 585
 586    MIPTREE_LAYOUT_FOR_SCANOUT              = 1 << 7,
 587 };
 588
 589 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
 590                                                GLenum target,
 591                                                mesa_format format,
 592                                                GLuint first_level,
 593                                                GLuint last_level,
 594                                                GLuint width0,
 595                                                GLuint height0,
 596                                                GLuint depth0,
 597                                                GLuint num_samples,
 598                                                uint32_t flags);
 599
 600 struct intel_mipmap_tree *
 601 intel_miptree_create_for_bo(struct brw_context *brw,
 602                             struct brw_bo *bo,
 603                             mesa_format format,
 604                             uint32_t offset,
 605                             uint32_t width,
 606                             uint32_t height,
 607                             uint32_t depth,
 608                             int pitch,
 609                             uint32_t layout_flags);
 610
 611 struct intel_mipmap_tree *
 612 intel_miptree_create_for_dri_image(struct brw_context *brw,
 613                                    __DRIimage *image,
 614                                    GLenum target,
 615                                    enum isl_colorspace colorspace,
 616                                    bool is_winsys_image);
 617
 618 bool
 619 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
 620                                          struct intel_renderbuffer *irb,
 621                                          struct intel_mipmap_tree *singlesample_mt,
 622                                          uint32_t width, uint32_t height,
 623                                          uint32_t pitch);
 624
 625 /**
 626  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 627  * The miptree has the following properties:
 628  *     - The target is GL_TEXTURE_2D.
 629  *     - There are no levels other than the base level 0.
 630  *     - Depth is 1.
 631  */
 632 struct intel_mipmap_tree*
 633 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
 634                                       mesa_format format,
 635                                       uint32_t width,
 636                                       uint32_t height,
 637                                       uint32_t num_samples);
 638
 639 mesa_format
 640 intel_depth_format_for_depthstencil_format(mesa_format format);
 641
 642 mesa_format
 643 intel_lower_compressed_format(struct brw_context *brw, mesa_format format);
 644
 645 /** \brief Assert that the level and layer are valid for the miptree. */
 646 void
 647 intel_miptree_check_level_layer(const struct intel_mipmap_tree *mt,
 648                                 uint32_t level,
 649                                 uint32_t layer);
 650
 651 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 652                              struct intel_mipmap_tree *src);
 653
 654 void intel_miptree_release(struct intel_mipmap_tree **mt);
 655
 656 /* Check if an image fits an existing mipmap tree layout
 657  */
 658 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 659                                     struct gl_texture_image *image);
 660
 661 void
 662 intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt,
 663                                GLuint level, GLuint slice,
 664                                GLuint *x, GLuint *y);
 665
 666 enum isl_surf_dim
 667 get_isl_surf_dim(GLenum target);
 668
 669 enum isl_dim_layout
 670 get_isl_dim_layout(const struct gen_device_info *devinfo,
 671                    enum isl_tiling tiling, GLenum target);
 672
 673 enum isl_tiling
 674 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree *mt);
 675
 676 void
 677 intel_miptree_get_isl_surf(struct brw_context *brw,
 678                            const struct intel_mipmap_tree *mt,
 679                            struct isl_surf *surf);
 680
 681 enum isl_aux_usage
 682 intel_miptree_get_aux_isl_usage(const struct brw_context *brw,
 683                                 const struct intel_mipmap_tree *mt);
 684
 685 void
 686 intel_get_image_dims(struct gl_texture_image *image,
 687                      int *width, int *height, int *depth);
 688
 689 void
 690 intel_get_tile_masks(enum isl_tiling tiling, uint32_t cpp,
 691                      uint32_t *mask_x, uint32_t *mask_y);
 692
 693 void
 694 intel_get_tile_dims(enum isl_tiling tiling, uint32_t cpp,
 695                     uint32_t *tile_w, uint32_t *tile_h);
 696
 697 uint32_t
 698 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
 699                                GLuint level, GLuint slice,
 700                                uint32_t *tile_x,
 701                                uint32_t *tile_y);
 702 uint32_t
 703 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
 704                                  uint32_t x, uint32_t y);
 705
 706 void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
 707                                   GLuint level,
 708                                   GLuint x, GLuint y, GLuint d);
 709
 710 void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
 711                                     GLuint level,
 712                                     GLuint img, GLuint x, GLuint y);
 713
 714 void
 715 intel_miptree_copy_slice(struct brw_context *brw,
 716                          struct intel_mipmap_tree *src_mt,
 717                          unsigned src_level, unsigned src_layer,
 718                          struct intel_mipmap_tree *dst_mt,
 719                          unsigned dst_level, unsigned dst_layer);
 720
 721 void
 722 intel_miptree_copy_teximage(struct brw_context *brw,
 723                             struct intel_texture_image *intelImage,
 724                             struct intel_mipmap_tree *dst_mt, bool invalidate);
 725
 726 /**
 727  * \name Miptree HiZ functions
 728  * \{
 729  *
 730  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 731  * functions on a miptree without HiZ. In that case, each function is a no-op.
 732  */
 733
 734 /**
 735  * \brief Allocate the miptree's embedded HiZ miptree.
 736  * \see intel_mipmap_tree:hiz_mt
 737  * \return false if allocation failed
 738  */
 739 bool
 740 intel_miptree_alloc_hiz(struct brw_context *brw,
 741                         struct intel_mipmap_tree *mt);
 742
 743 bool
 744 intel_miptree_level_has_hiz(const struct intel_mipmap_tree *mt, uint32_t level);
 745
 746 /**\}*/
 747
 748 bool
 749 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree *mt,
 750                                    unsigned start_level, unsigned num_levels,
 751                                    unsigned start_layer, unsigned num_layers);
 752
 753
 754 #define INTEL_REMAINING_LAYERS UINT32_MAX
 755 #define INTEL_REMAINING_LEVELS UINT32_MAX
 756
 757 /** Prepare a miptree for access
 758  *
 759  * This function should be called prior to any access to miptree in order to
 760  * perform any needed resolves.
 761  *
 762  * \param[in]  start_level    The first mip level to be accessed
 763  *
 764  * \param[in]  num_levels     The number of miplevels to be accessed or
 765  *                            INTEL_REMAINING_LEVELS to indicate every level
 766  *                            above start_level will be accessed
 767  *
 768  * \param[in]  start_layer    The first array slice or 3D layer to be accessed
 769  *
 770  * \param[in]  num_layers     The number of array slices or 3D layers be
 771  *                            accessed or INTEL_REMAINING_LAYERS to indicate
 772  *                            every layer above start_layer will be accessed
 773  *
 774  * \param[in]  aux_supported  Whether or not the access will support the
 775  *                            miptree's auxiliary compression format;  this
 776  *                            must be false for uncompressed miptrees
 777  *
 778  * \param[in]  fast_clear_supported Whether or not the access will support
 779  *                                  fast clears in the miptree's auxiliary
 780  *                                  compression format
 781  */
 782 void
 783 intel_miptree_prepare_access(struct brw_context *brw,
 784                              struct intel_mipmap_tree *mt,
 785                              uint32_t start_level, uint32_t num_levels,
 786                              uint32_t start_layer, uint32_t num_layers,
 787                              bool aux_supported, bool fast_clear_supported);
 788
 789 /** Complete a write operation
 790  *
 791  * This function should be called after any operation writes to a miptree.
 792  * This will update the miptree's compression state so that future resolves
 793  * happen correctly.  Technically, this function can be called before the
 794  * write occurs but the caller must ensure that they don't interlace
 795  * intel_miptree_prepare_access and intel_miptree_finish_write calls to
 796  * overlapping layer/level ranges.
 797  *
 798  * \param[in]  level             The mip level that was written
 799  *
 800  * \param[in]  start_layer       The first array slice or 3D layer written
 801  *
 802  * \param[in]  num_layers        The number of array slices or 3D layers
 803  *                               written or INTEL_REMAINING_LAYERS to indicate
 804  *                               every layer above start_layer was written
 805  *
 806  * \param[in]  written_with_aux  Whether or not the write was done with
 807  *                               auxiliary compression enabled
 808  */
 809 void
 810 intel_miptree_finish_write(struct brw_context *brw,
 811                            struct intel_mipmap_tree *mt, uint32_t level,
 812                            uint32_t start_layer, uint32_t num_layers,
 813                            bool written_with_aux);
 814
 815 /** Get the auxiliary compression state of a miptree slice */
 816 enum isl_aux_state
 817 intel_miptree_get_aux_state(const struct intel_mipmap_tree *mt,
 818                             uint32_t level, uint32_t layer);
 819
 820 /** Set the auxiliary compression state of a miptree slice range
 821  *
 822  * This function directly sets the auxiliary compression state of a slice
 823  * range of a miptree.  It only modifies data structures and does not do any
 824  * resolves.  This should only be called by code which directly performs
 825  * compression operations such as fast clears and resolves.  Most code should
 826  * use intel_miptree_prepare_access or intel_miptree_finish_write.
 827  */
 828 void
 829 intel_miptree_set_aux_state(struct brw_context *brw,
 830                             struct intel_mipmap_tree *mt, uint32_t level,
 831                             uint32_t start_layer, uint32_t num_layers,
 832                             enum isl_aux_state aux_state);
 833
 834 /**
 835  * Prepare a miptree for raw access
 836  *
 837  * This helper prepares the miptree for access that knows nothing about any
 838  * sort of compression whatsoever.  This is useful when mapping the surface or
 839  * using it with the blitter.
 840  */
 841 static inline void
 842 intel_miptree_access_raw(struct brw_context *brw,
 843                          struct intel_mipmap_tree *mt,
 844                          uint32_t level, uint32_t layer,
 845                          bool write)
 846 {
 847    intel_miptree_prepare_access(brw, mt, level, 1, layer, 1, false, false);
 848    if (write)
 849       intel_miptree_finish_write(brw, mt, level, layer, 1, false);
 850 }
 851
 852 void
 853 intel_miptree_prepare_texture(struct brw_context *brw,
 854                               struct intel_mipmap_tree *mt,
 855                               mesa_format view_format,
 856                               bool *aux_supported_out);
 857 void
 858 intel_miptree_prepare_image(struct brw_context *brw,
 859                             struct intel_mipmap_tree *mt);
 860 void
 861 intel_miptree_prepare_fb_fetch(struct brw_context *brw,
 862                                struct intel_mipmap_tree *mt, uint32_t level,
 863                                uint32_t start_layer, uint32_t num_layers);
 864 void
 865 intel_miptree_prepare_render(struct brw_context *brw,
 866                              struct intel_mipmap_tree *mt, uint32_t level,
 867                              uint32_t start_layer, uint32_t layer_count,
 868                              bool srgb_enabled);
 869 void
 870 intel_miptree_finish_render(struct brw_context *brw,
 871                             struct intel_mipmap_tree *mt, uint32_t level,
 872                             uint32_t start_layer, uint32_t layer_count);
 873 void
 874 intel_miptree_prepare_depth(struct brw_context *brw,
 875                             struct intel_mipmap_tree *mt, uint32_t level,
 876                             uint32_t start_layer, uint32_t layer_count);
 877 void
 878 intel_miptree_finish_depth(struct brw_context *brw,
 879                            struct intel_mipmap_tree *mt, uint32_t level,
 880                            uint32_t start_layer, uint32_t layer_count,
 881                            bool depth_written);
 882
 883 void
 884 intel_miptree_make_shareable(struct brw_context *brw,
 885                              struct intel_mipmap_tree *mt);
 886
 887 void
 888 intel_miptree_updownsample(struct brw_context *brw,
 889                            struct intel_mipmap_tree *src,
 890                            struct intel_mipmap_tree *dst);
 891
 892 void
 893 intel_update_r8stencil(struct brw_context *brw,
 894                        struct intel_mipmap_tree *mt);
 895
 896 /**
 897  * Horizontal distance from one slice to the next in the two-dimensional
 898  * miptree layout.
 899  */
 900 unsigned
 901 brw_miptree_get_horizontal_slice_pitch(const struct brw_context *brw,
 902                                        const struct intel_mipmap_tree *mt,
 903                                        unsigned level);
 904
 905 bool
 906 brw_miptree_layout(struct brw_context *brw,
 907                    struct intel_mipmap_tree *mt,
 908                    uint32_t layout_flags);
 909
 910 void
 911 intel_miptree_map(struct brw_context *brw,
 912                   struct intel_mipmap_tree *mt,
 913                   unsigned int level,
 914                   unsigned int slice,
 915                   unsigned int x,
 916                   unsigned int y,
 917                   unsigned int w,
 918                   unsigned int h,
 919                   GLbitfield mode,
 920                   void **out_ptr,
 921                   ptrdiff_t *out_stride);
 922
 923 void
 924 intel_miptree_unmap(struct brw_context *brw,
 925                     struct intel_mipmap_tree *mt,
 926                     unsigned int level,
 927                     unsigned int slice);
 928
 929 bool
 930 intel_miptree_sample_with_hiz(struct brw_context *brw,
 931                               struct intel_mipmap_tree *mt);
 932
 933 #ifdef __cplusplus
 934 }
 935 #endif
 936
 937 #endif