src/mesa/drivers/dri/i965/intel_mipmap_tree.h

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   3  * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
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  27
  28 #ifndef INTEL_MIPMAP_TREE_H
  29 #define INTEL_MIPMAP_TREE_H
  30
  31 #include <assert.h>
  32
  33 #include "intel_regions.h"
  34 #include "intel_resolve_map.h"
  35 #include <GL/internal/dri_interface.h>
  36
  37 #ifdef __cplusplus
  38 extern "C" {
  39 #endif
  40
  41 /* A layer on top of the intel_regions code which adds:
  42  *
  43  * - Code to size and layout a region to hold a set of mipmaps.
  44  * - Query to determine if a new image fits in an existing tree.
  45  * - More refcounting
  46  *     - maybe able to remove refcounting from intel_region?
  47  * - ?
  48  *
  49  * The fixed mipmap layout of intel hardware where one offset
  50  * specifies the position of all images in a mipmap hierachy
  51  * complicates the implementation of GL texture image commands,
  52  * compared to hardware where each image is specified with an
  53  * independent offset.
  54  *
  55  * In an ideal world, each texture object would be associated with a
  56  * single bufmgr buffer or 2d intel_region, and all the images within
  57  * the texture object would slot into the tree as they arrive.  The
  58  * reality can be a little messier, as images can arrive from the user
  59  * with sizes that don't fit in the existing tree, or in an order
  60  * where the tree layout cannot be guessed immediately.
  61  *
  62  * This structure encodes an idealized mipmap tree.  The GL image
  63  * commands build these where possible, otherwise store the images in
  64  * temporary system buffers.
  65  */
  66
  67 struct intel_resolve_map;
  68 struct intel_texture_image;
  69
  70 /**
  71  * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
  72  * depthstencil-split-to-separate-stencil miptree, we'll normally make a
  73  * tmeporary and recreate the kind of data requested by Mesa core, since we're
  74  * satisfying some glGetTexImage() request or something.
  75  *
  76  * However, occasionally you want to actually map the miptree's current data
  77  * without transcoding back.  This flag to intel_miptree_map() gets you that.
  78  */
  79 #define BRW_MAP_DIRECT_BIT      0x80000000
  80
  81 struct intel_miptree_map {
  82    /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
  83    GLbitfield mode;
  84    /** Region of interest for the map. */
  85    int x, y, w, h;
  86    /** Possibly malloced temporary buffer for the mapping. */
  87    void *buffer;
  88    /** Possible pointer to a temporary linear miptree for the mapping. */
  89    struct intel_mipmap_tree *mt;
  90    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  91    void *ptr;
  92    /** Stride of the mapping. */
  93    int stride;
  94
  95    /**
  96     * intel_mipmap_tree::singlesample_mt is temporary storage that persists
  97     * only for the duration of the map.
  98     */
  99    bool singlesample_mt_is_tmp;
 100 };
 101
 102 /**
 103  * Describes the location of each texture image within a texture region.
 104  */
 105 struct intel_mipmap_level
 106 {
 107    /** Offset to this miptree level, used in computing x_offset. */
 108    GLuint level_x;
 109    /** Offset to this miptree level, used in computing y_offset. */
 110    GLuint level_y;
 111    GLuint width;
 112    GLuint height;
 113
 114    /**
 115     * \brief Number of 2D slices in this miplevel.
 116     *
 117     * The exact semantics of depth varies according to the texture target:
 118     *    - For GL_TEXTURE_CUBE_MAP, depth is 6.
 119     *    - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
 120     *      identical for all miplevels in the texture.
 121     *    - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
 122     *      value, like width and height, varies with miplevel.
 123     *    - For other texture types, depth is 1.
 124     */
 125    GLuint depth;
 126
 127    /**
 128     * \brief List of 2D images in this mipmap level.
 129     *
 130     * This may be a list of cube faces, array slices in 2D array texture, or
 131     * layers in a 3D texture. The list's length is \c depth.
 132     */
 133    struct intel_mipmap_slice {
 134       /**
 135        * \name Offset to slice
 136        * \{
 137        *
 138        * Hardware formats are so diverse that that there is no unified way to
 139        * compute the slice offsets, so we store them in this table.
 140        *
 141        * The (x, y) offset to slice \c s at level \c l relative the miptrees
 142        * base address is
 143        * \code
 144        *     x = mt->level[l].slice[s].x_offset
 145        *     y = mt->level[l].slice[s].y_offset
 146        */
 147       GLuint x_offset;
 148       GLuint y_offset;
 149       /** \} */
 150
 151       /**
 152        * Mapping information. Persistent for the duration of
 153        * intel_miptree_map/unmap on this slice.
 154        */
 155       struct intel_miptree_map *map;
 156
 157       /**
 158        * \brief Is HiZ enabled for this slice?
 159        *
 160        * If \c mt->level[l].slice[s].has_hiz is set, then (1) \c mt->hiz_mt
 161        * has been allocated and (2) the HiZ memory corresponding to this slice
 162        * resides at \c mt->hiz_mt->level[l].slice[s].
 163        */
 164       bool has_hiz;
 165    } *slice;
 166 };
 167
 168 /**
 169  * Enum for keeping track of the different MSAA layouts supported by Gen7.
 170  */
 171 enum intel_msaa_layout
 172 {
 173    /**
 174     * Ordinary surface with no MSAA.
 175     */
 176    INTEL_MSAA_LAYOUT_NONE,
 177
 178    /**
 179     * Interleaved Multisample Surface.  The additional samples are
 180     * accommodated by scaling up the width and the height of the surface so
 181     * that all the samples corresponding to a pixel are located at nearby
 182     * memory locations.
 183     */
 184    INTEL_MSAA_LAYOUT_IMS,
 185
 186    /**
 187     * Uncompressed Multisample Surface.  The surface is stored as a 2D array,
 188     * with array slice n containing all pixel data for sample n.
 189     */
 190    INTEL_MSAA_LAYOUT_UMS,
 191
 192    /**
 193     * Compressed Multisample Surface.  The surface is stored as in
 194     * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
 195     * (Multisample Control Surface) buffer.  Each pixel in the MCS buffer
 196     * indicates the mapping from sample number to array slice.  This allows
 197     * the common case (where all samples constituting a pixel have the same
 198     * color value) to be stored efficiently by just using a single array
 199     * slice.
 200     */
 201    INTEL_MSAA_LAYOUT_CMS,
 202 };
 203
 204
 205 /**
 206  * Enum for keeping track of the state of an MCS buffer associated with a
 207  * miptree.  This determines when fast clear related operations are needed.
 208  *
 209  * Fast clear works by deferring the memory writes that would be used to clear
 210  * the buffer, so that instead of performing them at the time of the clear
 211  * operation, the hardware automatically performs them at the time that the
 212  * buffer is later accessed for rendering.  The MCS buffer keeps track of
 213  * which regions of the buffer still have pending clear writes.
 214  *
 215  * This enum keeps track of the driver's knowledge of the state of the MCS
 216  * buffer.
 217  *
 218  * MCS buffers only exist on Gen7+.
 219  */
 220 enum intel_mcs_state
 221 {
 222    /**
 223     * There is no MCS buffer for this miptree, and one should never be
 224     * allocated.
 225     */
 226    INTEL_MCS_STATE_NONE,
 227
 228    /**
 229     * An MCS buffer exists for this miptree, and it is used for MSAA purposes.
 230     */
 231    INTEL_MCS_STATE_MSAA,
 232
 233    /**
 234     * No deferred clears are pending for this miptree, and the contents of the
 235     * color buffer are entirely correct.  An MCS buffer may or may not exist
 236     * for this miptree.  If it does exist, it is entirely in the "no deferred
 237     * clears pending" state.  If it does not exist, it will be created the
 238     * first time a fast color clear is executed.
 239     *
 240     * In this state, the color buffer can be used for purposes other than
 241     * rendering without needing a render target resolve.
 242     */
 243    INTEL_MCS_STATE_RESOLVED,
 244
 245    /**
 246     * An MCS buffer exists for this miptree, and deferred clears are pending
 247     * for some regions of the color buffer, as indicated by the MCS buffer.
 248     * The contents of the color buffer are only correct for the regions where
 249     * the MCS buffer doesn't indicate a deferred clear.
 250     *
 251     * In this state, a render target resolve must be performed before the
 252     * color buffer can be used for purposes other than rendering.
 253     */
 254    INTEL_MCS_STATE_UNRESOLVED,
 255
 256    /**
 257     * An MCS buffer exists for this miptree, and deferred clears are pending
 258     * for the entire color buffer, and the contents of the MCS buffer reflect
 259     * this.  The contents of the color buffer are undefined.
 260     *
 261     * In this state, a render target resolve must be performed before the
 262     * color buffer can be used for purposes other than rendering.
 263     *
 264     * If the client attempts to clear a buffer which is already in this state,
 265     * the clear can be safely skipped, since the buffer is already clear.
 266     */
 267    INTEL_MCS_STATE_CLEAR,
 268 };
 269
 270 struct intel_mipmap_tree
 271 {
 272    /* Effectively the key:
 273     */
 274    GLenum target;
 275
 276    /**
 277     * Generally, this is just the same as the gl_texture_image->TexFormat or
 278     * gl_renderbuffer->Format.
 279     *
 280     * However, for textures and renderbuffers with packed depth/stencil formats
 281     * on hardware where we want or need to use separate stencil, there will be
 282     * two miptrees for storing the data.  If the depthstencil texture or rb is
 283     * MESA_FORMAT_Z32_FLOAT_X24S8, then mt->format will be
 284     * MESA_FORMAT_Z32_FLOAT, otherwise for MESA_FORMAT_S8_Z24 objects it will be
 285     * MESA_FORMAT_X8_Z24.
 286     *
 287     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
 288     * formats if the hardware lacks support for ETC1/ETC2. See @ref wraps_etc.
 289     */
 290    gl_format format;
 291
 292    /** This variable stores the value of ETC compressed texture format */
 293    gl_format etc_format;
 294
 295    /**
 296     * The X offset of each image in the miptree must be aligned to this.
 297     * See the comments in brw_tex_layout.c.
 298     */
 299    unsigned int align_w;
 300    unsigned int align_h; /**< \see align_w */
 301
 302    GLuint first_level;
 303    GLuint last_level;
 304
 305    /**
 306     * Level zero image dimensions.  These dimensions correspond to the
 307     * physical layout of data in memory.  Accordingly, they account for the
 308     * extra width, height, and or depth that must be allocated in order to
 309     * accommodate multisample formats, and they account for the extra factor
 310     * of 6 in depth that must be allocated in order to accommodate cubemap
 311     * textures.
 312     */
 313    GLuint physical_width0, physical_height0, physical_depth0;
 314
 315    GLuint cpp;
 316    GLuint num_samples;
 317    bool compressed;
 318
 319    /**
 320     * Level zero image dimensions.  These dimensions correspond to the
 321     * logical width, height, and depth of the region as seen by client code.
 322     * Accordingly, they do not account for the extra width, height, and/or
 323     * depth that must be allocated in order to accommodate multisample
 324     * formats, nor do they account for the extra factor of 6 in depth that
 325     * must be allocated in order to accommodate cubemap textures.
 326     */
 327    uint32_t logical_width0, logical_height0, logical_depth0;
 328
 329    /**
 330     * For 1D array, 2D array, cube, and 2D multisampled surfaces on Gen7: true
 331     * if the surface only contains LOD 0, and hence no space is for LOD's
 332     * other than 0 in between array slices.
 333     *
 334     * Corresponds to the surface_array_spacing bit in gen7_surface_state.
 335     */
 336    bool array_spacing_lod0;
 337
 338    /**
 339     * MSAA layout used by this buffer.
 340     */
 341    enum intel_msaa_layout msaa_layout;
 342
 343    /* Derived from the above:
 344     */
 345    GLuint total_width;
 346    GLuint total_height;
 347
 348    /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to
 349     * this depth mipmap tree, if any.
 350     */
 351    uint32_t depth_clear_value;
 352
 353    /* Includes image offset tables:
 354     */
 355    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 356
 357    /* The data is held here:
 358     */
 359    struct intel_region *region;
 360
 361    /* Offset into region bo where miptree starts:
 362     */
 363    uint32_t offset;
 364
 365    /**
 366     * \brief Singlesample miptree.
 367     *
 368     * This is used under two cases.
 369     *
 370     * --- Case 1: As persistent singlesample storage for multisample window
 371     *  system front and back buffers ---
 372     *
 373     * Suppose that the window system FBO was created with a multisample
 374     * config.  Let `back_irb` be the `intel_renderbuffer` for the FBO's back
 375     * buffer. Then `back_irb` contains two miptrees: a parent multisample
 376     * miptree (back_irb->mt) and a child singlesample miptree
 377     * (back_irb->mt->singlesample_mt).  The DRM buffer shared with DRI2
 378     * belongs to `back_irb->mt->singlesample_mt` and contains singlesample
 379     * data.  The singlesample miptree is created at the same time as and
 380     * persists for the lifetime of its parent multisample miptree.
 381     *
 382     * When access to the singlesample data is needed, such as at
 383     * eglSwapBuffers and glReadPixels, an automatic downsample occurs from
 384     * `back_rb->mt` to `back_rb->mt->singlesample_mt` when necessary.
 385     *
 386     * This description of the back buffer applies analogously to the front
 387     * buffer.
 388     *
 389     *
 390     * --- Case 2: As temporary singlesample storage for mapping multisample
 391     *  miptrees ---
 392     *
 393     * Suppose the intel_miptree_map is called on a multisample miptree, `mt`,
 394     * for which case 1 does not apply (that is, `mt` does not belong to
 395     * a front or back buffer).  Then `mt->singlesample_mt` is null at the
 396     * start of the call. intel_miptree_map will create a temporary
 397     * singlesample miptree, store it at `mt->singlesample_mt`, downsample from
 398     * `mt` to `mt->singlesample_mt` if necessary, then map
 399     * `mt->singlesample_mt`. The temporary miptree is later deleted during
 400     * intel_miptree_unmap.
 401     */
 402    struct intel_mipmap_tree *singlesample_mt;
 403
 404    /**
 405     * \brief A downsample is needed from this miptree to singlesample_mt.
 406     */
 407    bool need_downsample;
 408
 409    /**
 410     * \brief HiZ miptree
 411     *
 412     * The hiz miptree contains the miptree's hiz buffer. To allocate the hiz
 413     * miptree, use intel_miptree_alloc_hiz().
 414     *
 415     * To determine if hiz is enabled, do not check this pointer. Instead, use
 416     * intel_miptree_slice_has_hiz().
 417     */
 418    struct intel_mipmap_tree *hiz_mt;
 419
 420    /**
 421     * \brief Map of miptree slices to needed resolves.
 422     *
 423     * This is used only when the miptree has a child HiZ miptree.
 424     *
 425     * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
 426     * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
 427     * mt->hiz_mt->hiz_map, is unused.
 428     */
 429    struct intel_resolve_map hiz_map;
 430
 431    /**
 432     * \brief Stencil miptree for depthstencil textures.
 433     *
 434     * This miptree is used for depthstencil textures and renderbuffers that
 435     * require separate stencil.  It always has the true copy of the stencil
 436     * bits, regardless of mt->format.
 437     *
 438     * \see intel_miptree_map_depthstencil()
 439     * \see intel_miptree_unmap_depthstencil()
 440     */
 441    struct intel_mipmap_tree *stencil_mt;
 442
 443    /**
 444     * \brief MCS miptree.
 445     *
 446     * This miptree contains the "multisample control surface", which stores
 447     * the necessary information to implement compressed MSAA
 448     * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
 449     *
 450     * NULL if no MCS miptree is in use for this surface.
 451     */
 452    struct intel_mipmap_tree *mcs_mt;
 453
 454    /**
 455     * MCS state for this buffer.
 456     */
 457    enum intel_mcs_state mcs_state;
 458
 459    /**
 460     * The SURFACE_STATE bits associated with the last fast color clear to this
 461     * color mipmap tree, if any.
 462     *
 463     * This value will only ever contain ones in bits 28-31, so it is safe to
 464     * OR into dword 7 of SURFACE_STATE.
 465     */
 466    uint32_t fast_clear_color_value;
 467
 468    /* These are also refcounted:
 469     */
 470    GLuint refcount;
 471 };
 472
 473 enum intel_miptree_tiling_mode {
 474    INTEL_MIPTREE_TILING_ANY,
 475    INTEL_MIPTREE_TILING_Y,
 476    INTEL_MIPTREE_TILING_NONE,
 477 };
 478
 479 bool
 480 intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
 481                                        struct intel_mipmap_tree *mt);
 482
 483 void
 484 intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
 485                                  struct intel_mipmap_tree *mt,
 486                                  unsigned *width_px, unsigned *height);
 487
 488 bool
 489 intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
 490                                  struct intel_mipmap_tree *mt);
 491
 492 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
 493                                                GLenum target,
 494                                                gl_format format,
 495                                                GLuint first_level,
 496                                                GLuint last_level,
 497                                                GLuint width0,
 498                                                GLuint height0,
 499                                                GLuint depth0,
 500                                                bool expect_accelerated_upload,
 501                                                GLuint num_samples,
 502                                                enum intel_miptree_tiling_mode);
 503
 504 struct intel_mipmap_tree *
 505 intel_miptree_create_layout(struct brw_context *brw,
 506                             GLenum target,
 507                             gl_format format,
 508                             GLuint first_level,
 509                             GLuint last_level,
 510                             GLuint width0,
 511                             GLuint height0,
 512                             GLuint depth0,
 513                             bool for_bo,
 514                             GLuint num_samples);
 515
 516 struct intel_mipmap_tree *
 517 intel_miptree_create_for_bo(struct brw_context *brw,
 518                             drm_intel_bo *bo,
 519                             gl_format format,
 520                             uint32_t offset,
 521                             uint32_t width,
 522                             uint32_t height,
 523                             int pitch,
 524                             uint32_t tiling);
 525
 526 struct intel_mipmap_tree*
 527 intel_miptree_create_for_dri2_buffer(struct brw_context *brw,
 528                                      unsigned dri_attachment,
 529                                      gl_format format,
 530                                      uint32_t num_samples,
 531                                      struct intel_region *region);
 532
 533 struct intel_mipmap_tree*
 534 intel_miptree_create_for_image_buffer(struct brw_context *intel,
 535                                      enum __DRIimageBufferMask buffer_type,
 536                                      gl_format format,
 537                                      uint32_t num_samples,
 538                                      struct intel_region *region);
 539
 540 /**
 541  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 542  * The miptree has the following properties:
 543  *     - The target is GL_TEXTURE_2D.
 544  *     - There are no levels other than the base level 0.
 545  *     - Depth is 1.
 546  */
 547 struct intel_mipmap_tree*
 548 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
 549                                       gl_format format,
 550                                       uint32_t width,
 551                                       uint32_t height,
 552                                       uint32_t num_samples);
 553
 554 /** \brief Assert that the level and layer are valid for the miptree. */
 555 static inline void
 556 intel_miptree_check_level_layer(struct intel_mipmap_tree *mt,
 557                                 uint32_t level,
 558                                 uint32_t layer)
 559 {
 560    assert(level >= mt->first_level);
 561    assert(level <= mt->last_level);
 562    assert(layer < mt->level[level].depth);
 563 }
 564
 565 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 566                              struct intel_mipmap_tree *src);
 567
 568 void intel_miptree_release(struct intel_mipmap_tree **mt);
 569
 570 /* Check if an image fits an existing mipmap tree layout
 571  */
 572 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 573                                     struct gl_texture_image *image);
 574
 575 void
 576 intel_miptree_get_image_offset(struct intel_mipmap_tree *mt,
 577                                GLuint level, GLuint slice,
 578                                GLuint *x, GLuint *y);
 579
 580 void
 581 intel_miptree_get_dimensions_for_image(struct gl_texture_image *image,
 582                                        int *width, int *height, int *depth);
 583
 584 uint32_t
 585 intel_miptree_get_tile_offsets(struct intel_mipmap_tree *mt,
 586                                GLuint level, GLuint slice,
 587                                uint32_t *tile_x,
 588                                uint32_t *tile_y);
 589
 590 void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
 591                                   GLuint level,
 592                                   GLuint x, GLuint y,
 593                                   GLuint w, GLuint h, GLuint d);
 594
 595 void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
 596                                     GLuint level,
 597                                     GLuint img, GLuint x, GLuint y);
 598
 599 void
 600 intel_miptree_copy_teximage(struct brw_context *brw,
 601                             struct intel_texture_image *intelImage,
 602                             struct intel_mipmap_tree *dst_mt, bool invalidate);
 603
 604 bool
 605 intel_miptree_alloc_mcs(struct brw_context *brw,
 606                         struct intel_mipmap_tree *mt,
 607                         GLuint num_samples);
 608
 609 /**
 610  * \name Miptree HiZ functions
 611  * \{
 612  *
 613  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 614  * functions on a miptree without HiZ. In that case, each function is a no-op.
 615  */
 616
 617 /**
 618  * \brief Allocate the miptree's embedded HiZ miptree.
 619  * \see intel_mipmap_tree:hiz_mt
 620  * \return false if allocation failed
 621  */
 622
 623 bool
 624 intel_miptree_alloc_hiz(struct brw_context *brw,
 625                         struct intel_mipmap_tree *mt);
 626
 627 bool
 628 intel_miptree_slice_has_hiz(struct intel_mipmap_tree *mt,
 629                             uint32_t level,
 630                             uint32_t layer);
 631
 632 void
 633 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt,
 634                                           uint32_t level,
 635                                           uint32_t depth);
 636 void
 637 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt,
 638                                             uint32_t level,
 639                                             uint32_t depth);
 640
 641 void
 642 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree *mt,
 643                                                 uint32_t level);
 644
 645 /**
 646  * \return false if no resolve was needed
 647  */
 648 bool
 649 intel_miptree_slice_resolve_hiz(struct brw_context *brw,
 650                                 struct intel_mipmap_tree *mt,
 651                                 unsigned int level,
 652                                 unsigned int depth);
 653
 654 /**
 655  * \return false if no resolve was needed
 656  */
 657 bool
 658 intel_miptree_slice_resolve_depth(struct brw_context *brw,
 659                                   struct intel_mipmap_tree *mt,
 660                                   unsigned int level,
 661                                   unsigned int depth);
 662
 663 /**
 664  * \return false if no resolve was needed
 665  */
 666 bool
 667 intel_miptree_all_slices_resolve_hiz(struct brw_context *brw,
 668                                      struct intel_mipmap_tree *mt);
 669
 670 /**
 671  * \return false if no resolve was needed
 672  */
 673 bool
 674 intel_miptree_all_slices_resolve_depth(struct brw_context *brw,
 675                                        struct intel_mipmap_tree *mt);
 676
 677 /**\}*/
 678
 679 /**
 680  * Update the fast clear state for a miptree to indicate that it has been used
 681  * for rendering.
 682  */
 683 static inline void
 684 intel_miptree_used_for_rendering(struct intel_mipmap_tree *mt)
 685 {
 686    /* If the buffer was previously in fast clear state, change it to
 687     * unresolved state, since it won't be guaranteed to be clear after
 688     * rendering occurs.
 689     */
 690    if (mt->mcs_state == INTEL_MCS_STATE_CLEAR)
 691       mt->mcs_state = INTEL_MCS_STATE_UNRESOLVED;
 692 }
 693
 694 void
 695 intel_miptree_resolve_color(struct brw_context *brw,
 696                             struct intel_mipmap_tree *mt);
 697
 698 void
 699 intel_miptree_make_shareable(struct brw_context *brw,
 700                              struct intel_mipmap_tree *mt);
 701
 702 void
 703 intel_miptree_downsample(struct brw_context *brw,
 704                          struct intel_mipmap_tree *mt);
 705
 706 void
 707 intel_miptree_upsample(struct brw_context *brw,
 708                        struct intel_mipmap_tree *mt);
 709
 710 void brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt);
 711
 712 void *intel_miptree_map_raw(struct brw_context *brw,
 713                             struct intel_mipmap_tree *mt);
 714
 715 void intel_miptree_unmap_raw(struct brw_context *brw,
 716                              struct intel_mipmap_tree *mt);
 717
 718 void
 719 intel_miptree_map(struct brw_context *brw,
 720                   struct intel_mipmap_tree *mt,
 721                   unsigned int level,
 722                   unsigned int slice,
 723                   unsigned int x,
 724                   unsigned int y,
 725                   unsigned int w,
 726                   unsigned int h,
 727                   GLbitfield mode,
 728                   void **out_ptr,
 729                   int *out_stride);
 730
 731 void
 732 intel_miptree_unmap(struct brw_context *brw,
 733                     struct intel_mipmap_tree *mt,
 734                     unsigned int level,
 735                     unsigned int slice);
 736
 737 void
 738 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 739                unsigned int level, unsigned int layer, enum gen6_hiz_op op);
 740
 741 #ifdef __cplusplus
 742 }
 743 #endif
 744
 745 #endif