src/mesa/drivers/dri/i965/intel_mipmap_tree.h

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  27
  28 #ifndef INTEL_MIPMAP_TREE_H
  29 #define INTEL_MIPMAP_TREE_H
  30
  31 #include <assert.h>
  32
  33 #include "intel_regions.h"
  34 #include "intel_resolve_map.h"
  35 #include <GL/internal/dri_interface.h>
  36
  37 #ifdef __cplusplus
  38 extern "C" {
  39 #endif
  40
  41 struct intel_renderbuffer;
  42
  43 /* A layer on top of the intel_regions code which adds:
  44  *
  45  * - Code to size and layout a region to hold a set of mipmaps.
  46  * - Query to determine if a new image fits in an existing tree.
  47  * - More refcounting
  48  *     - maybe able to remove refcounting from intel_region?
  49  * - ?
  50  *
  51  * The fixed mipmap layout of intel hardware where one offset
  52  * specifies the position of all images in a mipmap hierachy
  53  * complicates the implementation of GL texture image commands,
  54  * compared to hardware where each image is specified with an
  55  * independent offset.
  56  *
  57  * In an ideal world, each texture object would be associated with a
  58  * single bufmgr buffer or 2d intel_region, and all the images within
  59  * the texture object would slot into the tree as they arrive.  The
  60  * reality can be a little messier, as images can arrive from the user
  61  * with sizes that don't fit in the existing tree, or in an order
  62  * where the tree layout cannot be guessed immediately.
  63  *
  64  * This structure encodes an idealized mipmap tree.  The GL image
  65  * commands build these where possible, otherwise store the images in
  66  * temporary system buffers.
  67  */
  68
  69 struct intel_resolve_map;
  70 struct intel_texture_image;
  71
  72 /**
  73  * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
  74  * depthstencil-split-to-separate-stencil miptree, we'll normally make a
  75  * tmeporary and recreate the kind of data requested by Mesa core, since we're
  76  * satisfying some glGetTexImage() request or something.
  77  *
  78  * However, occasionally you want to actually map the miptree's current data
  79  * without transcoding back.  This flag to intel_miptree_map() gets you that.
  80  */
  81 #define BRW_MAP_DIRECT_BIT      0x80000000
  82
  83 struct intel_miptree_map {
  84    /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
  85    GLbitfield mode;
  86    /** Region of interest for the map. */
  87    int x, y, w, h;
  88    /** Possibly malloced temporary buffer for the mapping. */
  89    void *buffer;
  90    /** Possible pointer to a temporary linear miptree for the mapping. */
  91    struct intel_mipmap_tree *mt;
  92    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  93    void *ptr;
  94    /** Stride of the mapping. */
  95    int stride;
  96 };
  97
  98 /**
  99  * Describes the location of each texture image within a texture region.
 100  */
 101 struct intel_mipmap_level
 102 {
 103    /** Offset to this miptree level, used in computing x_offset. */
 104    GLuint level_x;
 105    /** Offset to this miptree level, used in computing y_offset. */
 106    GLuint level_y;
 107    GLuint width;
 108    GLuint height;
 109
 110    /**
 111     * \brief Number of 2D slices in this miplevel.
 112     *
 113     * The exact semantics of depth varies according to the texture target:
 114     *    - For GL_TEXTURE_CUBE_MAP, depth is 6.
 115     *    - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
 116     *      identical for all miplevels in the texture.
 117     *    - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
 118     *      value, like width and height, varies with miplevel.
 119     *    - For other texture types, depth is 1.
 120     */
 121    GLuint depth;
 122
 123    /**
 124     * \brief List of 2D images in this mipmap level.
 125     *
 126     * This may be a list of cube faces, array slices in 2D array texture, or
 127     * layers in a 3D texture. The list's length is \c depth.
 128     */
 129    struct intel_mipmap_slice {
 130       /**
 131        * \name Offset to slice
 132        * \{
 133        *
 134        * Hardware formats are so diverse that that there is no unified way to
 135        * compute the slice offsets, so we store them in this table.
 136        *
 137        * The (x, y) offset to slice \c s at level \c l relative the miptrees
 138        * base address is
 139        * \code
 140        *     x = mt->level[l].slice[s].x_offset
 141        *     y = mt->level[l].slice[s].y_offset
 142        */
 143       GLuint x_offset;
 144       GLuint y_offset;
 145       /** \} */
 146
 147       /**
 148        * Mapping information. Persistent for the duration of
 149        * intel_miptree_map/unmap on this slice.
 150        */
 151       struct intel_miptree_map *map;
 152
 153       /**
 154        * \brief Is HiZ enabled for this slice?
 155        *
 156        * If \c mt->level[l].slice[s].has_hiz is set, then (1) \c mt->hiz_mt
 157        * has been allocated and (2) the HiZ memory corresponding to this slice
 158        * resides at \c mt->hiz_mt->level[l].slice[s].
 159        */
 160       bool has_hiz;
 161    } *slice;
 162 };
 163
 164 /**
 165  * Enum for keeping track of the different MSAA layouts supported by Gen7.
 166  */
 167 enum intel_msaa_layout
 168 {
 169    /**
 170     * Ordinary surface with no MSAA.
 171     */
 172    INTEL_MSAA_LAYOUT_NONE,
 173
 174    /**
 175     * Interleaved Multisample Surface.  The additional samples are
 176     * accommodated by scaling up the width and the height of the surface so
 177     * that all the samples corresponding to a pixel are located at nearby
 178     * memory locations.
 179     */
 180    INTEL_MSAA_LAYOUT_IMS,
 181
 182    /**
 183     * Uncompressed Multisample Surface.  The surface is stored as a 2D array,
 184     * with array slice n containing all pixel data for sample n.
 185     */
 186    INTEL_MSAA_LAYOUT_UMS,
 187
 188    /**
 189     * Compressed Multisample Surface.  The surface is stored as in
 190     * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
 191     * (Multisample Control Surface) buffer.  Each pixel in the MCS buffer
 192     * indicates the mapping from sample number to array slice.  This allows
 193     * the common case (where all samples constituting a pixel have the same
 194     * color value) to be stored efficiently by just using a single array
 195     * slice.
 196     */
 197    INTEL_MSAA_LAYOUT_CMS,
 198 };
 199
 200
 201 /**
 202  * Enum for keeping track of the fast clear state of a buffer associated with
 203  * a miptree.
 204  *
 205  * Fast clear works by deferring the memory writes that would be used to clear
 206  * the buffer, so that instead of performing them at the time of the clear
 207  * operation, the hardware automatically performs them at the time that the
 208  * buffer is later accessed for rendering.  The MCS buffer keeps track of
 209  * which regions of the buffer still have pending clear writes.
 210  *
 211  * This enum keeps track of the driver's knowledge of pending fast clears in
 212  * the MCS buffer.
 213  *
 214  * MCS buffers only exist on Gen7+.
 215  */
 216 enum intel_fast_clear_state
 217 {
 218    /**
 219     * There is no MCS buffer for this miptree, and one should never be
 220     * allocated.
 221     */
 222    INTEL_FAST_CLEAR_STATE_NO_MCS,
 223
 224    /**
 225     * No deferred clears are pending for this miptree, and the contents of the
 226     * color buffer are entirely correct.  An MCS buffer may or may not exist
 227     * for this miptree.  If it does exist, it is entirely in the "no deferred
 228     * clears pending" state.  If it does not exist, it will be created the
 229     * first time a fast color clear is executed.
 230     *
 231     * In this state, the color buffer can be used for purposes other than
 232     * rendering without needing a render target resolve.
 233     *
 234     * Since there is no such thing as a "fast color clear resolve" for MSAA
 235     * buffers, an MSAA buffer will never be in this state.
 236     */
 237    INTEL_FAST_CLEAR_STATE_RESOLVED,
 238
 239    /**
 240     * An MCS buffer exists for this miptree, and deferred clears are pending
 241     * for some regions of the color buffer, as indicated by the MCS buffer.
 242     * The contents of the color buffer are only correct for the regions where
 243     * the MCS buffer doesn't indicate a deferred clear.
 244     *
 245     * If a single-sample buffer is in this state, a render target resolve must
 246     * be performed before it can be used for purposes other than rendering.
 247     */
 248    INTEL_FAST_CLEAR_STATE_UNRESOLVED,
 249
 250    /**
 251     * An MCS buffer exists for this miptree, and deferred clears are pending
 252     * for the entire color buffer, and the contents of the MCS buffer reflect
 253     * this.  The contents of the color buffer are undefined.
 254     *
 255     * If a single-sample buffer is in this state, a render target resolve must
 256     * be performed before it can be used for purposes other than rendering.
 257     *
 258     * If the client attempts to clear a buffer which is already in this state,
 259     * the clear can be safely skipped, since the buffer is already clear.
 260     */
 261    INTEL_FAST_CLEAR_STATE_CLEAR,
 262 };
 263
 264 struct intel_mipmap_tree
 265 {
 266    /* Effectively the key:
 267     */
 268    GLenum target;
 269
 270    /**
 271     * Generally, this is just the same as the gl_texture_image->TexFormat or
 272     * gl_renderbuffer->Format.
 273     *
 274     * However, for textures and renderbuffers with packed depth/stencil formats
 275     * on hardware where we want or need to use separate stencil, there will be
 276     * two miptrees for storing the data.  If the depthstencil texture or rb is
 277     * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
 278     * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
 279     * MESA_FORMAT_Z24_UNORM_X8_UINT.
 280     *
 281     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
 282     * formats if the hardware lacks support for ETC1/ETC2. See @ref wraps_etc.
 283     */
 284    mesa_format format;
 285
 286    /** This variable stores the value of ETC compressed texture format */
 287    mesa_format etc_format;
 288
 289    /**
 290     * The X offset of each image in the miptree must be aligned to this.
 291     * See the comments in brw_tex_layout.c.
 292     */
 293    unsigned int align_w;
 294    unsigned int align_h; /**< \see align_w */
 295
 296    GLuint first_level;
 297    GLuint last_level;
 298
 299    /**
 300     * Level zero image dimensions.  These dimensions correspond to the
 301     * physical layout of data in memory.  Accordingly, they account for the
 302     * extra width, height, and or depth that must be allocated in order to
 303     * accommodate multisample formats, and they account for the extra factor
 304     * of 6 in depth that must be allocated in order to accommodate cubemap
 305     * textures.
 306     */
 307    GLuint physical_width0, physical_height0, physical_depth0;
 308
 309    GLuint cpp;
 310    GLuint num_samples;
 311    bool compressed;
 312
 313    /**
 314     * Level zero image dimensions.  These dimensions correspond to the
 315     * logical width, height, and depth of the region as seen by client code.
 316     * Accordingly, they do not account for the extra width, height, and/or
 317     * depth that must be allocated in order to accommodate multisample
 318     * formats, nor do they account for the extra factor of 6 in depth that
 319     * must be allocated in order to accommodate cubemap textures.
 320     */
 321    uint32_t logical_width0, logical_height0, logical_depth0;
 322
 323    /**
 324     * For 1D array, 2D array, cube, and 2D multisampled surfaces on Gen7: true
 325     * if the surface only contains LOD 0, and hence no space is for LOD's
 326     * other than 0 in between array slices.
 327     *
 328     * Corresponds to the surface_array_spacing bit in gen7_surface_state.
 329     */
 330    bool array_spacing_lod0;
 331
 332    /**
 333     * The distance in rows between array slices in an uncompressed surface.
 334     *
 335     * For compressed surfaces, slices are stored closer together physically;
 336     * the real distance is (qpitch / block height).
 337     */
 338    uint32_t qpitch;
 339
 340    /**
 341     * MSAA layout used by this buffer.
 342     */
 343    enum intel_msaa_layout msaa_layout;
 344
 345    /* Derived from the above:
 346     */
 347    GLuint total_width;
 348    GLuint total_height;
 349
 350    /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to
 351     * this depth mipmap tree, if any.
 352     */
 353    uint32_t depth_clear_value;
 354
 355    /* Includes image offset tables:
 356     */
 357    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 358
 359    /* The data is held here:
 360     */
 361    struct intel_region *region;
 362
 363    /* Offset into region bo where miptree starts:
 364     */
 365    uint32_t offset;
 366
 367    /**
 368     * \brief HiZ miptree
 369     *
 370     * The hiz miptree contains the miptree's hiz buffer. To allocate the hiz
 371     * miptree, use intel_miptree_alloc_hiz().
 372     *
 373     * To determine if hiz is enabled, do not check this pointer. Instead, use
 374     * intel_miptree_slice_has_hiz().
 375     */
 376    struct intel_mipmap_tree *hiz_mt;
 377
 378    /**
 379     * \brief Map of miptree slices to needed resolves.
 380     *
 381     * This is used only when the miptree has a child HiZ miptree.
 382     *
 383     * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
 384     * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
 385     * mt->hiz_mt->hiz_map, is unused.
 386     */
 387    struct intel_resolve_map hiz_map;
 388
 389    /**
 390     * \brief Stencil miptree for depthstencil textures.
 391     *
 392     * This miptree is used for depthstencil textures and renderbuffers that
 393     * require separate stencil.  It always has the true copy of the stencil
 394     * bits, regardless of mt->format.
 395     *
 396     * \see intel_miptree_map_depthstencil()
 397     * \see intel_miptree_unmap_depthstencil()
 398     */
 399    struct intel_mipmap_tree *stencil_mt;
 400
 401    /**
 402     * \brief MCS miptree.
 403     *
 404     * This miptree contains the "multisample control surface", which stores
 405     * the necessary information to implement compressed MSAA
 406     * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
 407     *
 408     * NULL if no MCS miptree is in use for this surface.
 409     */
 410    struct intel_mipmap_tree *mcs_mt;
 411
 412    /**
 413     * Fast clear state for this buffer.
 414     */
 415    enum intel_fast_clear_state fast_clear_state;
 416
 417    /**
 418     * The SURFACE_STATE bits associated with the last fast color clear to this
 419     * color mipmap tree, if any.
 420     *
 421     * This value will only ever contain ones in bits 28-31, so it is safe to
 422     * OR into dword 7 of SURFACE_STATE.
 423     */
 424    uint32_t fast_clear_color_value;
 425
 426    /* These are also refcounted:
 427     */
 428    GLuint refcount;
 429 };
 430
 431 enum intel_miptree_tiling_mode {
 432    INTEL_MIPTREE_TILING_ANY,
 433    INTEL_MIPTREE_TILING_Y,
 434    INTEL_MIPTREE_TILING_NONE,
 435 };
 436
 437 bool
 438 intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
 439                                        struct intel_mipmap_tree *mt);
 440
 441 void
 442 intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
 443                                  struct intel_mipmap_tree *mt,
 444                                  unsigned *width_px, unsigned *height);
 445
 446 bool
 447 intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
 448                                  struct intel_mipmap_tree *mt);
 449
 450 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
 451                                                GLenum target,
 452                                                mesa_format format,
 453                                                GLuint first_level,
 454                                                GLuint last_level,
 455                                                GLuint width0,
 456                                                GLuint height0,
 457                                                GLuint depth0,
 458                                                bool expect_accelerated_upload,
 459                                                GLuint num_samples,
 460                                                enum intel_miptree_tiling_mode);
 461
 462 struct intel_mipmap_tree *
 463 intel_miptree_create_layout(struct brw_context *brw,
 464                             GLenum target,
 465                             mesa_format format,
 466                             GLuint first_level,
 467                             GLuint last_level,
 468                             GLuint width0,
 469                             GLuint height0,
 470                             GLuint depth0,
 471                             bool for_bo,
 472                             GLuint num_samples);
 473
 474 struct intel_mipmap_tree *
 475 intel_miptree_create_for_bo(struct brw_context *brw,
 476                             drm_intel_bo *bo,
 477                             mesa_format format,
 478                             uint32_t offset,
 479                             uint32_t width,
 480                             uint32_t height,
 481                             int pitch,
 482                             uint32_t tiling);
 483
 484 void
 485 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
 486                                          struct intel_renderbuffer *irb,
 487                                          struct intel_region *region);
 488
 489 /**
 490  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 491  * The miptree has the following properties:
 492  *     - The target is GL_TEXTURE_2D.
 493  *     - There are no levels other than the base level 0.
 494  *     - Depth is 1.
 495  */
 496 struct intel_mipmap_tree*
 497 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
 498                                       mesa_format format,
 499                                       uint32_t width,
 500                                       uint32_t height,
 501                                       uint32_t num_samples);
 502
 503 /** \brief Assert that the level and layer are valid for the miptree. */
 504 static inline void
 505 intel_miptree_check_level_layer(struct intel_mipmap_tree *mt,
 506                                 uint32_t level,
 507                                 uint32_t layer)
 508 {
 509    assert(level >= mt->first_level);
 510    assert(level <= mt->last_level);
 511    assert(layer < mt->level[level].depth);
 512 }
 513
 514 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 515                              struct intel_mipmap_tree *src);
 516
 517 void intel_miptree_release(struct intel_mipmap_tree **mt);
 518
 519 /* Check if an image fits an existing mipmap tree layout
 520  */
 521 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 522                                     struct gl_texture_image *image);
 523
 524 void
 525 intel_miptree_get_image_offset(struct intel_mipmap_tree *mt,
 526                                GLuint level, GLuint slice,
 527                                GLuint *x, GLuint *y);
 528
 529 void
 530 intel_miptree_get_dimensions_for_image(struct gl_texture_image *image,
 531                                        int *width, int *height, int *depth);
 532
 533 uint32_t
 534 intel_miptree_get_tile_offsets(struct intel_mipmap_tree *mt,
 535                                GLuint level, GLuint slice,
 536                                uint32_t *tile_x,
 537                                uint32_t *tile_y);
 538
 539 void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
 540                                   GLuint level,
 541                                   GLuint x, GLuint y,
 542                                   GLuint w, GLuint h, GLuint d);
 543
 544 void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
 545                                     GLuint level,
 546                                     GLuint img, GLuint x, GLuint y);
 547
 548 void
 549 intel_miptree_copy_teximage(struct brw_context *brw,
 550                             struct intel_texture_image *intelImage,
 551                             struct intel_mipmap_tree *dst_mt, bool invalidate);
 552
 553 bool
 554 intel_miptree_alloc_mcs(struct brw_context *brw,
 555                         struct intel_mipmap_tree *mt,
 556                         GLuint num_samples);
 557
 558 /**
 559  * \name Miptree HiZ functions
 560  * \{
 561  *
 562  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 563  * functions on a miptree without HiZ. In that case, each function is a no-op.
 564  */
 565
 566 /**
 567  * \brief Allocate the miptree's embedded HiZ miptree.
 568  * \see intel_mipmap_tree:hiz_mt
 569  * \return false if allocation failed
 570  */
 571
 572 bool
 573 intel_miptree_alloc_hiz(struct brw_context *brw,
 574                         struct intel_mipmap_tree *mt);
 575
 576 bool
 577 intel_miptree_slice_has_hiz(struct intel_mipmap_tree *mt,
 578                             uint32_t level,
 579                             uint32_t layer);
 580
 581 void
 582 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt,
 583                                           uint32_t level,
 584                                           uint32_t depth);
 585 void
 586 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt,
 587                                             uint32_t level,
 588                                             uint32_t depth);
 589
 590 void
 591 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree *mt,
 592                                                 uint32_t level);
 593
 594 /**
 595  * \return false if no resolve was needed
 596  */
 597 bool
 598 intel_miptree_slice_resolve_hiz(struct brw_context *brw,
 599                                 struct intel_mipmap_tree *mt,
 600                                 unsigned int level,
 601                                 unsigned int depth);
 602
 603 /**
 604  * \return false if no resolve was needed
 605  */
 606 bool
 607 intel_miptree_slice_resolve_depth(struct brw_context *brw,
 608                                   struct intel_mipmap_tree *mt,
 609                                   unsigned int level,
 610                                   unsigned int depth);
 611
 612 /**
 613  * \return false if no resolve was needed
 614  */
 615 bool
 616 intel_miptree_all_slices_resolve_hiz(struct brw_context *brw,
 617                                      struct intel_mipmap_tree *mt);
 618
 619 /**
 620  * \return false if no resolve was needed
 621  */
 622 bool
 623 intel_miptree_all_slices_resolve_depth(struct brw_context *brw,
 624                                        struct intel_mipmap_tree *mt);
 625
 626 /**\}*/
 627
 628 /**
 629  * Update the fast clear state for a miptree to indicate that it has been used
 630  * for rendering.
 631  */
 632 static inline void
 633 intel_miptree_used_for_rendering(struct intel_mipmap_tree *mt)
 634 {
 635    /* If the buffer was previously in fast clear state, change it to
 636     * unresolved state, since it won't be guaranteed to be clear after
 637     * rendering occurs.
 638     */
 639    if (mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR)
 640       mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
 641 }
 642
 643 void
 644 intel_miptree_resolve_color(struct brw_context *brw,
 645                             struct intel_mipmap_tree *mt);
 646
 647 void
 648 intel_miptree_make_shareable(struct brw_context *brw,
 649                              struct intel_mipmap_tree *mt);
 650
 651 void
 652 intel_miptree_updownsample(struct brw_context *brw,
 653                            struct intel_mipmap_tree *src,
 654                            struct intel_mipmap_tree *dst);
 655
 656 void brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt);
 657
 658 void *intel_miptree_map_raw(struct brw_context *brw,
 659                             struct intel_mipmap_tree *mt);
 660
 661 void intel_miptree_unmap_raw(struct brw_context *brw,
 662                              struct intel_mipmap_tree *mt);
 663
 664 void
 665 intel_miptree_map(struct brw_context *brw,
 666                   struct intel_mipmap_tree *mt,
 667                   unsigned int level,
 668                   unsigned int slice,
 669                   unsigned int x,
 670                   unsigned int y,
 671                   unsigned int w,
 672                   unsigned int h,
 673                   GLbitfield mode,
 674                   void **out_ptr,
 675                   int *out_stride);
 676
 677 void
 678 intel_miptree_unmap(struct brw_context *brw,
 679                     struct intel_mipmap_tree *mt,
 680                     unsigned int level,
 681                     unsigned int slice);
 682
 683 void
 684 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 685                unsigned int level, unsigned int layer, enum gen6_hiz_op op);
 686
 687 #ifdef __cplusplus
 688 }
 689 #endif
 690
 691 #endif