src/mesa/drivers/dri/i965/intel_mipmap_tree.h

   1 /*
   2  * Copyright 2006 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 /** @file intel_mipmap_tree.h
  27  *
  28  * This file defines the structure that wraps a BO and describes how the
  29  * mipmap levels and slices of a texture are laid out.
  30  *
  31  * The hardware has a fixed layout of a texture depending on parameters such
  32  * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
  33  * mipmap levels.  The individual level/layer slices are each 2D rectangles of
  34  * pixels at some x/y offset from the start of the drm_intel_bo.
  35  *
  36  * Original OpenGL allowed texture miplevels to be specified in arbitrary
  37  * order, and a texture may change size over time.  Thus, each
  38  * intel_texture_image has a reference to a miptree that contains the pixel
  39  * data sized appropriately for it, which will later be referenced by/copied
  40  * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
  41  * that there's a single miptree for the complete texture.
  42  */
  43
  44 #ifndef INTEL_MIPMAP_TREE_H
  45 #define INTEL_MIPMAP_TREE_H
  46
  47 #include <assert.h>
  48
  49 #include "main/mtypes.h"
  50 #include "isl/isl.h"
  51 #include "intel_bufmgr.h"
  52 #include "intel_resolve_map.h"
  53 #include <GL/internal/dri_interface.h>
  54
  55 #ifdef __cplusplus
  56 extern "C" {
  57 #endif
  58
  59 struct brw_context;
  60 struct intel_renderbuffer;
  61
  62 struct intel_resolve_map;
  63 struct intel_texture_image;
  64
  65 /**
  66  * This bit extends the set of GL_MAP_*_BIT enums.
  67  *
  68  * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
  69  * depthstencil-split-to-separate-stencil miptree, we'll normally make a
  70  * temporary and recreate the kind of data requested by Mesa core, since we're
  71  * satisfying some glGetTexImage() request or something.
  72  *
  73  * However, occasionally you want to actually map the miptree's current data
  74  * without transcoding back.  This flag to intel_miptree_map() gets you that.
  75  */
  76 #define BRW_MAP_DIRECT_BIT      0x80000000
  77
  78 struct intel_miptree_map {
  79    /** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */
  80    GLbitfield mode;
  81    /** Region of interest for the map. */
  82    int x, y, w, h;
  83    /** Possibly malloced temporary buffer for the mapping. */
  84    void *buffer;
  85    /** Possible pointer to a temporary linear miptree for the mapping. */
  86    struct intel_mipmap_tree *linear_mt;
  87    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  88    void *ptr;
  89    /** Stride of the mapping. */
  90    int stride;
  91 };
  92
  93 /**
  94  * Describes the location of each texture image within a miptree.
  95  */
  96 struct intel_mipmap_level
  97 {
  98    /** Offset to this miptree level, used in computing x_offset. */
  99    GLuint level_x;
 100    /** Offset to this miptree level, used in computing y_offset. */
 101    GLuint level_y;
 102
 103    /**
 104     * \brief Number of 2D slices in this miplevel.
 105     *
 106     * The exact semantics of depth varies according to the texture target:
 107     *    - For GL_TEXTURE_CUBE_MAP, depth is 6.
 108     *    - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
 109     *      identical for all miplevels in the texture.
 110     *    - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
 111     *      value, like width and height, varies with miplevel.
 112     *    - For other texture types, depth is 1.
 113     *    - Additionally, for UMS and CMS miptrees, depth is multiplied by
 114     *      sample count.
 115     */
 116    GLuint depth;
 117
 118    /**
 119     * \brief Is HiZ enabled for this level?
 120     *
 121     * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
 122     * allocated and (2) the HiZ memory for the slices in this level reside at
 123     * \c mt->hiz_mt->level[l].
 124     */
 125    bool has_hiz;
 126
 127    /**
 128     * \brief List of 2D images in this mipmap level.
 129     *
 130     * This may be a list of cube faces, array slices in 2D array texture, or
 131     * layers in a 3D texture. The list's length is \c depth.
 132     */
 133    struct intel_mipmap_slice {
 134       /**
 135        * \name Offset to slice
 136        * \{
 137        *
 138        * Hardware formats are so diverse that that there is no unified way to
 139        * compute the slice offsets, so we store them in this table.
 140        *
 141        * The (x, y) offset to slice \c s at level \c l relative the miptrees
 142        * base address is
 143        * \code
 144        *     x = mt->level[l].slice[s].x_offset
 145        *     y = mt->level[l].slice[s].y_offset
 146        *
 147        * On some hardware generations, we program these offsets into
 148        * RENDER_SURFACE_STATE.XOffset and RENDER_SURFACE_STATE.YOffset.
 149        */
 150       GLuint x_offset;
 151       GLuint y_offset;
 152       /** \} */
 153
 154       /**
 155        * Mapping information. Persistent for the duration of
 156        * intel_miptree_map/unmap on this slice.
 157        */
 158       struct intel_miptree_map *map;
 159    } *slice;
 160 };
 161
 162 /**
 163  * Enum for keeping track of the different MSAA layouts supported by Gen7.
 164  */
 165 enum intel_msaa_layout
 166 {
 167    /**
 168     * Ordinary surface with no MSAA.
 169     */
 170    INTEL_MSAA_LAYOUT_NONE,
 171
 172    /**
 173     * Interleaved Multisample Surface.  The additional samples are
 174     * accommodated by scaling up the width and the height of the surface so
 175     * that all the samples corresponding to a pixel are located at nearby
 176     * memory locations.
 177     *
 178     * @see PRM section "Interleaved Multisampled Surfaces"
 179     */
 180    INTEL_MSAA_LAYOUT_IMS,
 181
 182    /**
 183     * Uncompressed Multisample Surface.  The surface is stored as a 2D array,
 184     * with array slice n containing all pixel data for sample n.
 185     *
 186     * @see PRM section "Uncompressed Multisampled Surfaces"
 187     */
 188    INTEL_MSAA_LAYOUT_UMS,
 189
 190    /**
 191     * Compressed Multisample Surface.  The surface is stored as in
 192     * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
 193     * (Multisample Control Surface) buffer.  Each pixel in the MCS buffer
 194     * indicates the mapping from sample number to array slice.  This allows
 195     * the common case (where all samples constituting a pixel have the same
 196     * color value) to be stored efficiently by just using a single array
 197     * slice.
 198     *
 199     * @see PRM section "Compressed Multisampled Surfaces"
 200     */
 201    INTEL_MSAA_LAYOUT_CMS,
 202 };
 203
 204 enum miptree_array_layout {
 205    /* Each array slice contains all miplevels packed together.
 206     *
 207     * Gen hardware usually wants multilevel miptrees configured this way.
 208     *
 209     * A 2D Array texture with 2 slices and multiple LODs using
 210     * ALL_LOD_IN_EACH_SLICE would look somewhat like this:
 211     *
 212     *   +----------+
 213     *   |          |
 214     *   |          |
 215     *   +----------+
 216     *   +---+ +-+
 217     *   |   | +-+
 218     *   +---+ *
 219     *   +----------+
 220     *   |          |
 221     *   |          |
 222     *   +----------+
 223     *   +---+ +-+
 224     *   |   | +-+
 225     *   +---+ *
 226     */
 227    ALL_LOD_IN_EACH_SLICE,
 228
 229    /* Each LOD contains all slices of that LOD packed together.
 230     *
 231     * In some situations, Gen7+ hardware can use the array_spacing_lod0
 232     * feature to save space when the surface only contains LOD 0.
 233     *
 234     * Gen6 uses this for separate stencil and hiz since gen6 does not support
 235     * multiple LODs for separate stencil and hiz.
 236     *
 237     * A 2D Array texture with 2 slices and multiple LODs using
 238     * ALL_SLICES_AT_EACH_LOD would look somewhat like this:
 239     *
 240     *   +----------+
 241     *   |          |
 242     *   |          |
 243     *   +----------+
 244     *   |          |
 245     *   |          |
 246     *   +----------+
 247     *   +---+ +-+
 248     *   |   | +-+
 249     *   +---+ +-+
 250     *   |   | :
 251     *   +---+
 252     */
 253    ALL_SLICES_AT_EACH_LOD,
 254 };
 255
 256 /**
 257  * Miptree aux buffer. These buffers are associated with a miptree, but the
 258  * format is managed by the hardware.
 259  *
 260  * For Gen7+, we always give the hardware the start of the buffer, and let it
 261  * handle all accesses to the buffer. Therefore we don't need the full miptree
 262  * layout structure for this buffer.
 263  */
 264 struct intel_miptree_aux_buffer
 265 {
 266    /**
 267     * Buffer object containing the pixel data.
 268     *
 269     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 270     * @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
 271     */
 272    drm_intel_bo *bo;
 273
 274    /**
 275     * Offset into bo where the surface starts.
 276     *
 277     * @see intel_mipmap_aux_buffer::bo
 278     *
 279     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 280     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 281     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 282     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 283     */
 284    uint32_t offset;
 285
 286    /*
 287     * Size of the MCS surface.
 288     *
 289     * This is needed when doing any gtt mapped operations on the buffer (which
 290     * will be Y-tiled). It is possible that it will not be the same as bo->size
 291     * when the drm allocator rounds up the requested size.
 292     */
 293    size_t size;
 294
 295    /**
 296     * Pitch in bytes.
 297     *
 298     * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
 299     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
 300     */
 301    uint32_t pitch;
 302
 303    /**
 304     * The distance in rows between array slices.
 305     *
 306     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch
 307     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
 308     */
 309    uint32_t qpitch;
 310 };
 311 /**
 312  * The HiZ buffer requires extra attributes on earlier GENs. This is easily
 313  * contained within an intel_mipmap_tree. To make sure we do not abuse this, we
 314  * keep the hiz datastructure separate.
 315  */
 316 struct intel_miptree_hiz_buffer
 317 {
 318    struct intel_miptree_aux_buffer aux_base;
 319
 320    /**
 321     * Hiz miptree. Used only by Gen6.
 322     */
 323    struct intel_mipmap_tree *mt;
 324 };
 325
 326 /* Tile resource modes */
 327 enum intel_miptree_tr_mode {
 328    INTEL_MIPTREE_TRMODE_NONE,
 329    INTEL_MIPTREE_TRMODE_YF,
 330    INTEL_MIPTREE_TRMODE_YS
 331 };
 332
 333 struct intel_mipmap_tree
 334 {
 335    /**
 336     * Buffer object containing the surface.
 337     *
 338     * @see intel_mipmap_tree::offset
 339     * @see RENDER_SURFACE_STATE.SurfaceBaseAddress
 340     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 341     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 342     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 343     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 344     */
 345    drm_intel_bo *bo;
 346
 347    /**
 348     * Pitch in bytes.
 349     *
 350     * @see RENDER_SURFACE_STATE.SurfacePitch
 351     * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
 352     * @see 3DSTATE_DEPTH_BUFFER.SurfacePitch
 353     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
 354     * @see 3DSTATE_STENCIL_BUFFER.SurfacePitch
 355     */
 356    uint32_t pitch;
 357
 358    /**
 359     * One of the I915_TILING_* flags.
 360     *
 361     * @see RENDER_SURFACE_STATE.TileMode
 362     * @see 3DSTATE_DEPTH_BUFFER.TileMode
 363     */
 364    uint32_t tiling;
 365
 366    /**
 367     * @see RENDER_SURFACE_STATE.TiledResourceMode
 368     * @see 3DSTATE_DEPTH_BUFFER.TiledResourceMode
 369     */
 370    enum intel_miptree_tr_mode tr_mode;
 371
 372    /**
 373     * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
 374     *
 375     * @see RENDER_SURFACE_STATE.SurfaceType
 376     * @see RENDER_SURFACE_STATE.SurfaceArray
 377     * @see 3DSTATE_DEPTH_BUFFER.SurfaceType
 378     */
 379    GLenum target;
 380
 381    /**
 382     * Generally, this is just the same as the gl_texture_image->TexFormat or
 383     * gl_renderbuffer->Format.
 384     *
 385     * However, for textures and renderbuffers with packed depth/stencil formats
 386     * on hardware where we want or need to use separate stencil, there will be
 387     * two miptrees for storing the data.  If the depthstencil texture or rb is
 388     * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
 389     * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
 390     * MESA_FORMAT_Z24_UNORM_X8_UINT.
 391     *
 392     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
 393     * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
 394     *
 395     * @see RENDER_SURFACE_STATE.SurfaceFormat
 396     * @see 3DSTATE_DEPTH_BUFFER.SurfaceFormat
 397     */
 398    mesa_format format;
 399
 400    /**
 401     * This variable stores the value of ETC compressed texture format
 402     *
 403     * @see RENDER_SURFACE_STATE.SurfaceFormat
 404     */
 405    mesa_format etc_format;
 406
 407    /**
 408     * @name Surface Alignment
 409     * @{
 410     *
 411     * This defines the alignment of the upperleft pixel of each "slice" in the
 412     * surface. The alignment is in pixel coordinates relative to the surface's
 413     * most upperleft pixel, which is the pixel at (x=0, y=0, layer=0,
 414     * level=0).
 415     *
 416     * The hardware docs do not use the term "slice".  We use "slice" to mean
 417     * the pixels at a given miplevel and layer. For 2D surfaces, the layer is
 418     * the array slice; for 3D surfaces, the layer is the z offset.
 419     *
 420     * In the surface layout equations found in the hardware docs, the
 421     * horizontal and vertical surface alignments often appear as variables 'i'
 422     * and 'j'.
 423     */
 424
 425    /** @see RENDER_SURFACE_STATE.SurfaceHorizontalAlignment */
 426    uint32_t halign;
 427
 428    /** @see RENDER_SURFACE_STATE.SurfaceVerticalAlignment */
 429    uint32_t valign;
 430    /** @} */
 431
 432    GLuint first_level;
 433    GLuint last_level;
 434
 435    /**
 436     * Level zero image dimensions.  These dimensions correspond to the
 437     * physical layout of data in memory.  Accordingly, they account for the
 438     * extra width, height, and or depth that must be allocated in order to
 439     * accommodate multisample formats, and they account for the extra factor
 440     * of 6 in depth that must be allocated in order to accommodate cubemap
 441     * textures.
 442     */
 443    GLuint physical_width0, physical_height0, physical_depth0;
 444
 445    /** Bytes per pixel (or bytes per block if compressed) */
 446    GLuint cpp;
 447
 448    /**
 449     * @see RENDER_SURFACE_STATE.NumberOfMultisamples
 450     * @see 3DSTATE_MULTISAMPLE.NumberOfMultisamples
 451     */
 452    GLuint num_samples;
 453
 454    bool compressed;
 455
 456    /**
 457     * @name Level zero image dimensions
 458     * @{
 459     *
 460     * These dimensions correspond to the
 461     * logical width, height, and depth of the texture as seen by client code.
 462     * Accordingly, they do not account for the extra width, height, and/or
 463     * depth that must be allocated in order to accommodate multisample
 464     * formats, nor do they account for the extra factor of 6 in depth that
 465     * must be allocated in order to accommodate cubemap textures.
 466     */
 467
 468    /**
 469     * @see RENDER_SURFACE_STATE.Width
 470     * @see 3DSTATE_DEPTH_BUFFER.Width
 471     */
 472    uint32_t logical_width0;
 473
 474    /**
 475     * @see RENDER_SURFACE_STATE.Height
 476     * @see 3DSTATE_DEPTH_BUFFER.Height
 477     */
 478    uint32_t logical_height0;
 479
 480    /**
 481     * @see RENDER_SURFACE_STATE.Depth
 482     * @see 3DSTATE_DEPTH_BUFFER.Depth
 483     */
 484    uint32_t logical_depth0;
 485    /** @} */
 486
 487    /**
 488     * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
 489     * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
 490     */
 491    enum miptree_array_layout array_layout;
 492
 493    /**
 494     * The distance in between array slices.
 495     *
 496     * The value is the one that is sent in the surface state. The actual
 497     * meaning depends on certain criteria. Usually it is simply the number of
 498     * uncompressed rows between each slice. However on Gen9+ for compressed
 499     * surfaces it is the number of blocks. For 1D array surfaces that have the
 500     * mipmap tree stored horizontally it is the number of pixels between each
 501     * slice.
 502     *
 503     * @see RENDER_SURFACE_STATE.SurfaceQPitch
 504     * @see 3DSTATE_DEPTH_BUFFER.SurfaceQPitch
 505     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
 506     * @see 3DSTATE_STENCIL_BUFFER.SurfaceQPitch
 507     */
 508    uint32_t qpitch;
 509
 510    /**
 511     * MSAA layout used by this buffer.
 512     *
 513     * @see RENDER_SURFACE_STATE.MultisampledSurfaceStorageFormat
 514     */
 515    enum intel_msaa_layout msaa_layout;
 516
 517    /* Derived from the above:
 518     */
 519    GLuint total_width;
 520    GLuint total_height;
 521
 522    /**
 523     * The depth value used during the most recent fast depth clear performed
 524     * on the surface. This field is invalid only if surface has never
 525     * underwent a fast depth clear.
 526     *
 527     * @see 3DSTATE_CLEAR_PARAMS.DepthClearValue
 528     */
 529    uint32_t depth_clear_value;
 530
 531    /* Includes image offset tables: */
 532    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 533
 534    /**
 535     * Offset into bo where the surface starts.
 536     *
 537     * @see intel_mipmap_tree::bo
 538     *
 539     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 540     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 541     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 542     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 543     */
 544    uint32_t offset;
 545
 546    /**
 547     * \brief HiZ aux buffer
 548     *
 549     * To allocate the hiz buffer, use intel_miptree_alloc_hiz().
 550     *
 551     * To determine if hiz is enabled, do not check this pointer. Instead, use
 552     * intel_miptree_slice_has_hiz().
 553     */
 554    struct intel_miptree_hiz_buffer *hiz_buf;
 555
 556    /**
 557     * \brief Maps of miptree slices to needed resolves.
 558     *
 559     * hiz_map is used only when the miptree has a child HiZ miptree.
 560     *
 561     * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
 562     * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
 563     * mt->hiz_mt->hiz_map, is unused.
 564     *
 565     *
 566     * color_resolve_map is used only when the miptree uses fast clear (Gen7+)
 567     * lossless compression (Gen9+). It should be noted that absence in the
 568     * map means implicitly RESOLVED state. If item is found it always
 569     * indicates state other than RESOLVED.
 570     */
 571    struct exec_list hiz_map; /* List of intel_resolve_map. */
 572    struct exec_list color_resolve_map; /* List of intel_resolve_map. */
 573
 574    /**
 575     * \brief Stencil miptree for depthstencil textures.
 576     *
 577     * This miptree is used for depthstencil textures and renderbuffers that
 578     * require separate stencil.  It always has the true copy of the stencil
 579     * bits, regardless of mt->format.
 580     *
 581     * \see 3DSTATE_STENCIL_BUFFER
 582     * \see intel_miptree_map_depthstencil()
 583     * \see intel_miptree_unmap_depthstencil()
 584     */
 585    struct intel_mipmap_tree *stencil_mt;
 586
 587    /**
 588     * \brief Stencil texturing miptree for sampling from a stencil texture
 589     *
 590     * Some hardware doesn't support sampling from the stencil texture as
 591     * required by the GL_ARB_stencil_texturing extenion. To workaround this we
 592     * blit the texture into a new texture that can be sampled.
 593     *
 594     * \see intel_update_r8stencil()
 595     */
 596    struct intel_mipmap_tree *r8stencil_mt;
 597    bool r8stencil_needs_update;
 598
 599    /**
 600     * \brief MCS auxiliary buffer.
 601     *
 602     * This buffer contains the "multisample control surface", which stores
 603     * the necessary information to implement compressed MSAA
 604     * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
 605     *
 606     * NULL if no MCS buffer is in use for this surface.
 607     */
 608    struct intel_miptree_aux_buffer *mcs_buf;
 609
 610    /**
 611     * Planes 1 and 2 in case this is a planar surface.
 612     */
 613    struct intel_mipmap_tree *plane[2];
 614
 615    /**
 616     * The SURFACE_STATE bits associated with the last fast color clear to this
 617     * color mipmap tree, if any.
 618     *
 619     * Prior to GEN9 there is a single bit for RGBA clear values which gives you
 620     * the option of 2^4 clear colors. Each bit determines if the color channel
 621     * is fully saturated or unsaturated (Cherryview does add a 32b value per
 622     * channel, but it is globally applied instead of being part of the render
 623     * surface state). Starting with GEN9, the surface state accepts a 32b value
 624     * for each color channel.
 625     *
 626     * @see RENDER_SURFACE_STATE.RedClearColor
 627     * @see RENDER_SURFACE_STATE.GreenClearColor
 628     * @see RENDER_SURFACE_STATE.BlueClearColor
 629     * @see RENDER_SURFACE_STATE.AlphaClearColor
 630     */
 631    union {
 632       uint32_t fast_clear_color_value;
 633       union gl_color_union gen9_fast_clear_color;
 634    };
 635
 636    /**
 637     * Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS
 638     * buffer. This is useful for sharing the miptree bo with an external client
 639     * that doesn't understand auxiliary buffers.
 640     */
 641    bool disable_aux_buffers;
 642
 643    /**
 644     * Fast clear and lossless compression are always disabled for this
 645     * miptree.
 646     */
 647    bool no_ccs;
 648
 649    /**
 650     * Tells if the underlying buffer is to be also consumed by entities other
 651     * than the driver. This allows logic to turn off features such as lossless
 652     * compression which is not currently understood by client applications.
 653     */
 654    bool is_scanout;
 655
 656    /* These are also refcounted:
 657     */
 658    GLuint refcount;
 659 };
 660
 661 bool
 662 intel_miptree_is_lossless_compressed(const struct brw_context *brw,
 663                                      const struct intel_mipmap_tree *mt);
 664
 665 bool
 666 intel_tiling_supports_non_msrt_mcs(const struct brw_context *brw,
 667                                    unsigned tiling);
 668
 669 bool
 670 intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw,
 671                                            const struct intel_mipmap_tree *mt);
 672
 673 bool
 674 intel_miptree_supports_lossless_compressed(struct brw_context *brw,
 675                                            const struct intel_mipmap_tree *mt);
 676
 677 bool
 678 intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
 679                                  struct intel_mipmap_tree *mt,
 680                                  bool is_lossless_compressed);
 681
 682 enum {
 683    MIPTREE_LAYOUT_ACCELERATED_UPLOAD       = 1 << 0,
 684    MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD   = 1 << 1,
 685    MIPTREE_LAYOUT_FOR_BO                   = 1 << 2,
 686    MIPTREE_LAYOUT_DISABLE_AUX              = 1 << 3,
 687    MIPTREE_LAYOUT_FORCE_HALIGN16           = 1 << 4,
 688
 689    MIPTREE_LAYOUT_TILING_Y                 = 1 << 5,
 690    MIPTREE_LAYOUT_TILING_NONE              = 1 << 6,
 691    MIPTREE_LAYOUT_TILING_ANY               = MIPTREE_LAYOUT_TILING_Y |
 692                                              MIPTREE_LAYOUT_TILING_NONE,
 693
 694    MIPTREE_LAYOUT_FOR_SCANOUT              = 1 << 7,
 695 };
 696
 697 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
 698                                                GLenum target,
 699                                                mesa_format format,
 700                                                GLuint first_level,
 701                                                GLuint last_level,
 702                                                GLuint width0,
 703                                                GLuint height0,
 704                                                GLuint depth0,
 705                                                GLuint num_samples,
 706                                                uint32_t flags);
 707
 708 struct intel_mipmap_tree *
 709 intel_miptree_create_for_bo(struct brw_context *brw,
 710                             drm_intel_bo *bo,
 711                             mesa_format format,
 712                             uint32_t offset,
 713                             uint32_t width,
 714                             uint32_t height,
 715                             uint32_t depth,
 716                             int pitch,
 717                             uint32_t layout_flags);
 718
 719 void
 720 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
 721                                          struct intel_renderbuffer *irb,
 722                                          drm_intel_bo *bo,
 723                                          uint32_t width, uint32_t height,
 724                                          uint32_t pitch);
 725
 726 /**
 727  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 728  * The miptree has the following properties:
 729  *     - The target is GL_TEXTURE_2D.
 730  *     - There are no levels other than the base level 0.
 731  *     - Depth is 1.
 732  */
 733 struct intel_mipmap_tree*
 734 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
 735                                       mesa_format format,
 736                                       uint32_t width,
 737                                       uint32_t height,
 738                                       uint32_t num_samples);
 739
 740 mesa_format
 741 intel_depth_format_for_depthstencil_format(mesa_format format);
 742
 743 mesa_format
 744 intel_lower_compressed_format(struct brw_context *brw, mesa_format format);
 745
 746 /** \brief Assert that the level and layer are valid for the miptree. */
 747 static inline void
 748 intel_miptree_check_level_layer(const struct intel_mipmap_tree *mt,
 749                                 uint32_t level,
 750                                 uint32_t layer)
 751 {
 752    (void) mt;
 753    (void) level;
 754    (void) layer;
 755
 756    assert(level >= mt->first_level);
 757    assert(level <= mt->last_level);
 758    assert(layer < mt->level[level].depth);
 759 }
 760
 761 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 762                              struct intel_mipmap_tree *src);
 763
 764 void intel_miptree_release(struct intel_mipmap_tree **mt);
 765
 766 /* Check if an image fits an existing mipmap tree layout
 767  */
 768 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 769                                     struct gl_texture_image *image);
 770
 771 void
 772 intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt,
 773                                GLuint level, GLuint slice,
 774                                GLuint *x, GLuint *y);
 775
 776 enum isl_surf_dim
 777 get_isl_surf_dim(GLenum target);
 778
 779 enum isl_dim_layout
 780 get_isl_dim_layout(const struct gen_device_info *devinfo, uint32_t tiling,
 781                    GLenum target);
 782
 783 enum isl_tiling
 784 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree *mt);
 785
 786 void
 787 intel_miptree_get_isl_surf(struct brw_context *brw,
 788                            const struct intel_mipmap_tree *mt,
 789                            struct isl_surf *surf);
 790 void
 791 intel_miptree_get_aux_isl_surf(struct brw_context *brw,
 792                                const struct intel_mipmap_tree *mt,
 793                                struct isl_surf *surf,
 794                                enum isl_aux_usage *usage);
 795
 796 union isl_color_value
 797 intel_miptree_get_isl_clear_color(struct brw_context *brw,
 798                                   const struct intel_mipmap_tree *mt);
 799
 800 void
 801 intel_get_image_dims(struct gl_texture_image *image,
 802                      int *width, int *height, int *depth);
 803
 804 void
 805 intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
 806                      uint32_t *mask_x, uint32_t *mask_y);
 807
 808 void
 809 intel_get_tile_dims(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
 810                     uint32_t *tile_w, uint32_t *tile_h);
 811
 812 uint32_t
 813 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
 814                                GLuint level, GLuint slice,
 815                                uint32_t *tile_x,
 816                                uint32_t *tile_y);
 817 uint32_t
 818 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
 819                                  uint32_t x, uint32_t y);
 820
 821 void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
 822                                   GLuint level,
 823                                   GLuint x, GLuint y, GLuint d);
 824
 825 void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
 826                                     GLuint level,
 827                                     GLuint img, GLuint x, GLuint y);
 828
 829 void
 830 intel_miptree_copy_teximage(struct brw_context *brw,
 831                             struct intel_texture_image *intelImage,
 832                             struct intel_mipmap_tree *dst_mt, bool invalidate);
 833
 834 /**
 835  * \name Miptree HiZ functions
 836  * \{
 837  *
 838  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 839  * functions on a miptree without HiZ. In that case, each function is a no-op.
 840  */
 841
 842 bool
 843 intel_miptree_wants_hiz_buffer(struct brw_context *brw,
 844                                struct intel_mipmap_tree *mt);
 845
 846 /**
 847  * \brief Allocate the miptree's embedded HiZ miptree.
 848  * \see intel_mipmap_tree:hiz_mt
 849  * \return false if allocation failed
 850  */
 851 bool
 852 intel_miptree_alloc_hiz(struct brw_context *brw,
 853                         struct intel_mipmap_tree *mt);
 854
 855 bool
 856 intel_miptree_level_has_hiz(struct intel_mipmap_tree *mt, uint32_t level);
 857
 858 void
 859 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt,
 860                                           uint32_t level,
 861                                           uint32_t depth);
 862 void
 863 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt,
 864                                             uint32_t level,
 865                                             uint32_t depth);
 866
 867 void
 868 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree *mt,
 869                                                 uint32_t level);
 870
 871 /**
 872  * \return false if no resolve was needed
 873  */
 874 bool
 875 intel_miptree_slice_resolve_hiz(struct brw_context *brw,
 876                                 struct intel_mipmap_tree *mt,
 877                                 unsigned int level,
 878                                 unsigned int depth);
 879
 880 /**
 881  * \return false if no resolve was needed
 882  */
 883 bool
 884 intel_miptree_slice_resolve_depth(struct brw_context *brw,
 885                                   struct intel_mipmap_tree *mt,
 886                                   unsigned int level,
 887                                   unsigned int depth);
 888
 889 /**
 890  * \return false if no resolve was needed
 891  */
 892 bool
 893 intel_miptree_all_slices_resolve_hiz(struct brw_context *brw,
 894                                      struct intel_mipmap_tree *mt);
 895
 896 /**
 897  * \return false if no resolve was needed
 898  */
 899 bool
 900 intel_miptree_all_slices_resolve_depth(struct brw_context *brw,
 901                                        struct intel_mipmap_tree *mt);
 902
 903 /**\}*/
 904
 905 enum intel_fast_clear_state
 906 intel_miptree_get_fast_clear_state(const struct intel_mipmap_tree *mt,
 907                                    unsigned level, unsigned layer);
 908
 909 void
 910 intel_miptree_set_fast_clear_state(struct intel_mipmap_tree *mt,
 911                                    unsigned level,
 912                                    unsigned first_layer,
 913                                    unsigned num_layers,
 914                                    enum intel_fast_clear_state new_state);
 915
 916 bool
 917 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree *mt,
 918                                    unsigned start_level, unsigned num_levels,
 919                                    unsigned start_layer, unsigned num_layers);
 920
 921 /**
 922  * Update the fast clear state for a miptree to indicate that it has been used
 923  * for rendering.
 924  */
 925 void
 926 intel_miptree_used_for_rendering(const struct brw_context *brw,
 927                                  struct intel_mipmap_tree *mt, unsigned level,
 928                                  unsigned start_layer, unsigned num_layers);
 929
 930 /**
 931  * Flag values telling color resolve pass which special types of buffers
 932  * can be ignored.
 933  *
 934  * INTEL_MIPTREE_IGNORE_CCS_E:   Lossless compressed (single-sample
 935  *                               compression scheme since gen9)
 936  */
 937 #define INTEL_MIPTREE_IGNORE_CCS_E (1 << 0)
 938
 939 bool
 940 intel_miptree_resolve_color(struct brw_context *brw,
 941                             struct intel_mipmap_tree *mt, unsigned level,
 942                             unsigned start_layer, unsigned num_layers,
 943                             int flags);
 944
 945 void
 946 intel_miptree_all_slices_resolve_color(struct brw_context *brw,
 947                                        struct intel_mipmap_tree *mt,
 948                                        int flags);
 949
 950 void
 951 intel_miptree_make_shareable(struct brw_context *brw,
 952                              struct intel_mipmap_tree *mt);
 953
 954 void
 955 intel_miptree_updownsample(struct brw_context *brw,
 956                            struct intel_mipmap_tree *src,
 957                            struct intel_mipmap_tree *dst);
 958
 959 void
 960 intel_update_r8stencil(struct brw_context *brw,
 961                        struct intel_mipmap_tree *mt);
 962
 963 /**
 964  * Horizontal distance from one slice to the next in the two-dimensional
 965  * miptree layout.
 966  */
 967 unsigned
 968 brw_miptree_get_horizontal_slice_pitch(const struct brw_context *brw,
 969                                        const struct intel_mipmap_tree *mt,
 970                                        unsigned level);
 971
 972 /**
 973  * Vertical distance from one slice to the next in the two-dimensional miptree
 974  * layout.
 975  */
 976 unsigned
 977 brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw,
 978                                      const struct intel_mipmap_tree *mt,
 979                                      unsigned level);
 980
 981 void
 982 brw_miptree_layout(struct brw_context *brw,
 983                    struct intel_mipmap_tree *mt,
 984                    uint32_t layout_flags);
 985
 986 void
 987 intel_miptree_map(struct brw_context *brw,
 988                   struct intel_mipmap_tree *mt,
 989                   unsigned int level,
 990                   unsigned int slice,
 991                   unsigned int x,
 992                   unsigned int y,
 993                   unsigned int w,
 994                   unsigned int h,
 995                   GLbitfield mode,
 996                   void **out_ptr,
 997                   ptrdiff_t *out_stride);
 998
 999 void
1000 intel_miptree_unmap(struct brw_context *brw,
1001                     struct intel_mipmap_tree *mt,
1002                     unsigned int level,
1003                     unsigned int slice);
1004
1005 void
1006 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
1007                unsigned int level, unsigned int layer, enum blorp_hiz_op op);
1008
1009 bool
1010 intel_miptree_sample_with_hiz(struct brw_context *brw,
1011                               struct intel_mipmap_tree *mt);
1012
1013 #ifdef __cplusplus
1014 }
1015 #endif
1016
1017 #endif