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26 /** @file intel_mipmap_tree.h
28 * This file defines the structure that wraps a BO and describes how the
29 * mipmap levels and slices of a texture are laid out.
31 * The hardware has a fixed layout of a texture depending on parameters such
32 * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
33 * mipmap levels. The individual level/layer slices are each 2D rectangles of
34 * pixels at some x/y offset from the start of the drm_intel_bo.
36 * Original OpenGL allowed texture miplevels to be specified in arbitrary
37 * order, and a texture may change size over time. Thus, each
38 * intel_texture_image has a reference to a miptree that contains the pixel
39 * data sized appropriately for it, which will later be referenced by/copied
40 * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
41 * that there's a single miptree for the complete texture.
44 #ifndef INTEL_MIPMAP_TREE_H
45 #define INTEL_MIPMAP_TREE_H
49 #include "main/mtypes.h"
51 #include "intel_bufmgr.h"
52 #include "intel_resolve_map.h"
53 #include <GL/internal/dri_interface.h>
60 struct intel_renderbuffer
;
62 struct intel_resolve_map
;
63 struct intel_texture_image
;
66 * This bit extends the set of GL_MAP_*_BIT enums.
68 * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
69 * depthstencil-split-to-separate-stencil miptree, we'll normally make a
70 * temporary and recreate the kind of data requested by Mesa core, since we're
71 * satisfying some glGetTexImage() request or something.
73 * However, occasionally you want to actually map the miptree's current data
74 * without transcoding back. This flag to intel_miptree_map() gets you that.
76 #define BRW_MAP_DIRECT_BIT 0x80000000
78 struct intel_miptree_map
{
79 /** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */
81 /** Region of interest for the map. */
83 /** Possibly malloced temporary buffer for the mapping. */
85 /** Possible pointer to a temporary linear miptree for the mapping. */
86 struct intel_mipmap_tree
*linear_mt
;
87 /** Pointer to the start of (map_x, map_y) returned by the mapping. */
89 /** Stride of the mapping. */
94 * Describes the location of each texture image within a miptree.
96 struct intel_mipmap_level
98 /** Offset to this miptree level, used in computing x_offset. */
100 /** Offset to this miptree level, used in computing y_offset. */
104 * \brief Number of 2D slices in this miplevel.
106 * The exact semantics of depth varies according to the texture target:
107 * - For GL_TEXTURE_CUBE_MAP, depth is 6.
108 * - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
109 * identical for all miplevels in the texture.
110 * - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
111 * value, like width and height, varies with miplevel.
112 * - For other texture types, depth is 1.
113 * - Additionally, for UMS and CMS miptrees, depth is multiplied by
119 * \brief Is HiZ enabled for this level?
121 * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
122 * allocated and (2) the HiZ memory for the slices in this level reside at
123 * \c mt->hiz_mt->level[l].
128 * \brief List of 2D images in this mipmap level.
130 * This may be a list of cube faces, array slices in 2D array texture, or
131 * layers in a 3D texture. The list's length is \c depth.
133 struct intel_mipmap_slice
{
135 * \name Offset to slice
138 * Hardware formats are so diverse that that there is no unified way to
139 * compute the slice offsets, so we store them in this table.
141 * The (x, y) offset to slice \c s at level \c l relative the miptrees
144 * x = mt->level[l].slice[s].x_offset
145 * y = mt->level[l].slice[s].y_offset
147 * On some hardware generations, we program these offsets into
148 * RENDER_SURFACE_STATE.XOffset and RENDER_SURFACE_STATE.YOffset.
155 * Mapping information. Persistent for the duration of
156 * intel_miptree_map/unmap on this slice.
158 struct intel_miptree_map
*map
;
163 * Enum for keeping track of the different MSAA layouts supported by Gen7.
165 enum intel_msaa_layout
168 * Ordinary surface with no MSAA.
170 INTEL_MSAA_LAYOUT_NONE
,
173 * Interleaved Multisample Surface. The additional samples are
174 * accommodated by scaling up the width and the height of the surface so
175 * that all the samples corresponding to a pixel are located at nearby
178 * @see PRM section "Interleaved Multisampled Surfaces"
180 INTEL_MSAA_LAYOUT_IMS
,
183 * Uncompressed Multisample Surface. The surface is stored as a 2D array,
184 * with array slice n containing all pixel data for sample n.
186 * @see PRM section "Uncompressed Multisampled Surfaces"
188 INTEL_MSAA_LAYOUT_UMS
,
191 * Compressed Multisample Surface. The surface is stored as in
192 * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
193 * (Multisample Control Surface) buffer. Each pixel in the MCS buffer
194 * indicates the mapping from sample number to array slice. This allows
195 * the common case (where all samples constituting a pixel have the same
196 * color value) to be stored efficiently by just using a single array
199 * @see PRM section "Compressed Multisampled Surfaces"
201 INTEL_MSAA_LAYOUT_CMS
,
206 * Enum for keeping track of the fast clear state of a buffer associated with
209 * Fast clear works by deferring the memory writes that would be used to clear
210 * the buffer, so that instead of performing them at the time of the clear
211 * operation, the hardware automatically performs them at the time that the
212 * buffer is later accessed for rendering. The MCS buffer keeps track of
213 * which regions of the buffer still have pending clear writes.
215 * This enum keeps track of the driver's knowledge of pending fast clears in
218 * MCS buffers only exist on Gen7+.
220 enum intel_fast_clear_state
223 * There is no MCS buffer for this miptree, and one should never be
226 INTEL_FAST_CLEAR_STATE_NO_MCS
,
229 * No deferred clears are pending for this miptree, and the contents of the
230 * color buffer are entirely correct. An MCS buffer may or may not exist
231 * for this miptree. If it does exist, it is entirely in the "no deferred
232 * clears pending" state. If it does not exist, it will be created the
233 * first time a fast color clear is executed.
235 * In this state, the color buffer can be used for purposes other than
236 * rendering without needing a render target resolve.
238 * Since there is no such thing as a "fast color clear resolve" for MSAA
239 * buffers, an MSAA buffer will never be in this state.
241 INTEL_FAST_CLEAR_STATE_RESOLVED
,
244 * An MCS buffer exists for this miptree, and deferred clears are pending
245 * for some regions of the color buffer, as indicated by the MCS buffer.
246 * The contents of the color buffer are only correct for the regions where
247 * the MCS buffer doesn't indicate a deferred clear.
249 * If a single-sample buffer is in this state, a render target resolve must
250 * be performed before it can be used for purposes other than rendering.
252 INTEL_FAST_CLEAR_STATE_UNRESOLVED
,
255 * An MCS buffer exists for this miptree, and deferred clears are pending
256 * for the entire color buffer, and the contents of the MCS buffer reflect
257 * this. The contents of the color buffer are undefined.
259 * If a single-sample buffer is in this state, a render target resolve must
260 * be performed before it can be used for purposes other than rendering.
262 * If the client attempts to clear a buffer which is already in this state,
263 * the clear can be safely skipped, since the buffer is already clear.
265 INTEL_FAST_CLEAR_STATE_CLEAR
,
268 enum miptree_array_layout
{
269 /* Each array slice contains all miplevels packed together.
271 * Gen hardware usually wants multilevel miptrees configured this way.
273 * A 2D Array texture with 2 slices and multiple LODs using
274 * ALL_LOD_IN_EACH_SLICE would look somewhat like this:
291 ALL_LOD_IN_EACH_SLICE
,
293 /* Each LOD contains all slices of that LOD packed together.
295 * In some situations, Gen7+ hardware can use the array_spacing_lod0
296 * feature to save space when the surface only contains LOD 0.
298 * Gen6 uses this for separate stencil and hiz since gen6 does not support
299 * multiple LODs for separate stencil and hiz.
301 * A 2D Array texture with 2 slices and multiple LODs using
302 * ALL_SLICES_AT_EACH_LOD would look somewhat like this:
317 ALL_SLICES_AT_EACH_LOD
,
321 * Miptree aux buffer. These buffers are associated with a miptree, but the
322 * format is managed by the hardware.
324 * For Gen7+, we always give the hardware the start of the buffer, and let it
325 * handle all accesses to the buffer. Therefore we don't need the full miptree
326 * layout structure for this buffer.
328 struct intel_miptree_aux_buffer
331 * Buffer object containing the pixel data.
333 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
334 * @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
339 * Offset into bo where the surface starts.
341 * @see intel_mipmap_aux_buffer::bo
343 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
344 * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
345 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
346 * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
351 * Size of the MCS surface.
353 * This is needed when doing any gtt mapped operations on the buffer (which
354 * will be Y-tiled). It is possible that it will not be the same as bo->size
355 * when the drm allocator rounds up the requested size.
362 * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
363 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
368 * The distance in rows between array slices.
370 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch
371 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
376 * The HiZ buffer requires extra attributes on earlier GENs. This is easily
377 * contained within an intel_mipmap_tree. To make sure we do not abuse this, we
378 * keep the hiz datastructure separate.
380 struct intel_miptree_hiz_buffer
382 struct intel_miptree_aux_buffer aux_base
;
385 * Hiz miptree. Used only by Gen6.
387 struct intel_mipmap_tree
*mt
;
390 /* Tile resource modes */
391 enum intel_miptree_tr_mode
{
392 INTEL_MIPTREE_TRMODE_NONE
,
393 INTEL_MIPTREE_TRMODE_YF
,
394 INTEL_MIPTREE_TRMODE_YS
397 struct intel_mipmap_tree
400 * Buffer object containing the surface.
402 * @see intel_mipmap_tree::offset
403 * @see RENDER_SURFACE_STATE.SurfaceBaseAddress
404 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
405 * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
406 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
407 * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
414 * @see RENDER_SURFACE_STATE.SurfacePitch
415 * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
416 * @see 3DSTATE_DEPTH_BUFFER.SurfacePitch
417 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
418 * @see 3DSTATE_STENCIL_BUFFER.SurfacePitch
423 * One of the I915_TILING_* flags.
425 * @see RENDER_SURFACE_STATE.TileMode
426 * @see 3DSTATE_DEPTH_BUFFER.TileMode
431 * @see RENDER_SURFACE_STATE.TiledResourceMode
432 * @see 3DSTATE_DEPTH_BUFFER.TiledResourceMode
434 enum intel_miptree_tr_mode tr_mode
;
437 * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
439 * @see RENDER_SURFACE_STATE.SurfaceType
440 * @see RENDER_SURFACE_STATE.SurfaceArray
441 * @see 3DSTATE_DEPTH_BUFFER.SurfaceType
446 * Generally, this is just the same as the gl_texture_image->TexFormat or
447 * gl_renderbuffer->Format.
449 * However, for textures and renderbuffers with packed depth/stencil formats
450 * on hardware where we want or need to use separate stencil, there will be
451 * two miptrees for storing the data. If the depthstencil texture or rb is
452 * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
453 * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
454 * MESA_FORMAT_Z24_UNORM_X8_UINT.
456 * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
457 * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
459 * @see RENDER_SURFACE_STATE.SurfaceFormat
460 * @see 3DSTATE_DEPTH_BUFFER.SurfaceFormat
465 * This variable stores the value of ETC compressed texture format
467 * @see RENDER_SURFACE_STATE.SurfaceFormat
469 mesa_format etc_format
;
472 * @name Surface Alignment
475 * This defines the alignment of the upperleft pixel of each "slice" in the
476 * surface. The alignment is in pixel coordinates relative to the surface's
477 * most upperleft pixel, which is the pixel at (x=0, y=0, layer=0,
480 * The hardware docs do not use the term "slice". We use "slice" to mean
481 * the pixels at a given miplevel and layer. For 2D surfaces, the layer is
482 * the array slice; for 3D surfaces, the layer is the z offset.
484 * In the surface layout equations found in the hardware docs, the
485 * horizontal and vertical surface alignments often appear as variables 'i'
489 /** @see RENDER_SURFACE_STATE.SurfaceHorizontalAlignment */
492 /** @see RENDER_SURFACE_STATE.SurfaceVerticalAlignment */
500 * Level zero image dimensions. These dimensions correspond to the
501 * physical layout of data in memory. Accordingly, they account for the
502 * extra width, height, and or depth that must be allocated in order to
503 * accommodate multisample formats, and they account for the extra factor
504 * of 6 in depth that must be allocated in order to accommodate cubemap
507 GLuint physical_width0
, physical_height0
, physical_depth0
;
509 /** Bytes per pixel (or bytes per block if compressed) */
513 * @see RENDER_SURFACE_STATE.NumberOfMultisamples
514 * @see 3DSTATE_MULTISAMPLE.NumberOfMultisamples
521 * @name Level zero image dimensions
524 * These dimensions correspond to the
525 * logical width, height, and depth of the texture as seen by client code.
526 * Accordingly, they do not account for the extra width, height, and/or
527 * depth that must be allocated in order to accommodate multisample
528 * formats, nor do they account for the extra factor of 6 in depth that
529 * must be allocated in order to accommodate cubemap textures.
533 * @see RENDER_SURFACE_STATE.Width
534 * @see 3DSTATE_DEPTH_BUFFER.Width
536 uint32_t logical_width0
;
539 * @see RENDER_SURFACE_STATE.Height
540 * @see 3DSTATE_DEPTH_BUFFER.Height
542 uint32_t logical_height0
;
545 * @see RENDER_SURFACE_STATE.Depth
546 * @see 3DSTATE_DEPTH_BUFFER.Depth
548 uint32_t logical_depth0
;
552 * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
553 * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
555 enum miptree_array_layout array_layout
;
558 * The distance in between array slices.
560 * The value is the one that is sent in the surface state. The actual
561 * meaning depends on certain criteria. Usually it is simply the number of
562 * uncompressed rows between each slice. However on Gen9+ for compressed
563 * surfaces it is the number of blocks. For 1D array surfaces that have the
564 * mipmap tree stored horizontally it is the number of pixels between each
567 * @see RENDER_SURFACE_STATE.SurfaceQPitch
568 * @see 3DSTATE_DEPTH_BUFFER.SurfaceQPitch
569 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
570 * @see 3DSTATE_STENCIL_BUFFER.SurfaceQPitch
575 * MSAA layout used by this buffer.
577 * @see RENDER_SURFACE_STATE.MultisampledSurfaceStorageFormat
579 enum intel_msaa_layout msaa_layout
;
581 /* Derived from the above:
587 * The depth value used during the most recent fast depth clear performed
588 * on the surface. This field is invalid only if surface has never
589 * underwent a fast depth clear.
591 * @see 3DSTATE_CLEAR_PARAMS.DepthClearValue
593 uint32_t depth_clear_value
;
595 /* Includes image offset tables: */
596 struct intel_mipmap_level level
[MAX_TEXTURE_LEVELS
];
599 * Offset into bo where the surface starts.
601 * @see intel_mipmap_tree::bo
603 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
604 * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
605 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
606 * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
611 * \brief HiZ aux buffer
613 * To allocate the hiz buffer, use intel_miptree_alloc_hiz().
615 * To determine if hiz is enabled, do not check this pointer. Instead, use
616 * intel_miptree_slice_has_hiz().
618 struct intel_miptree_hiz_buffer
*hiz_buf
;
621 * \brief Map of miptree slices to needed resolves.
623 * This is used only when the miptree has a child HiZ miptree.
625 * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
626 * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
627 * mt->hiz_mt->hiz_map, is unused.
629 struct exec_list hiz_map
; /* List of intel_resolve_map. */
632 * \brief Stencil miptree for depthstencil textures.
634 * This miptree is used for depthstencil textures and renderbuffers that
635 * require separate stencil. It always has the true copy of the stencil
636 * bits, regardless of mt->format.
638 * \see 3DSTATE_STENCIL_BUFFER
639 * \see intel_miptree_map_depthstencil()
640 * \see intel_miptree_unmap_depthstencil()
642 struct intel_mipmap_tree
*stencil_mt
;
645 * \brief Stencil texturing miptree for sampling from a stencil texture
647 * Some hardware doesn't support sampling from the stencil texture as
648 * required by the GL_ARB_stencil_texturing extenion. To workaround this we
649 * blit the texture into a new texture that can be sampled.
651 * \see intel_update_r8stencil()
653 struct intel_mipmap_tree
*r8stencil_mt
;
654 bool r8stencil_needs_update
;
657 * \brief MCS auxiliary buffer.
659 * This buffer contains the "multisample control surface", which stores
660 * the necessary information to implement compressed MSAA
661 * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
663 * NULL if no MCS buffer is in use for this surface.
665 struct intel_miptree_aux_buffer
*mcs_buf
;
668 * Planes 1 and 2 in case this is a planar surface.
670 struct intel_mipmap_tree
*plane
[2];
673 * Fast clear state for this buffer.
675 enum intel_fast_clear_state fast_clear_state
;
678 * The SURFACE_STATE bits associated with the last fast color clear to this
679 * color mipmap tree, if any.
681 * Prior to GEN9 there is a single bit for RGBA clear values which gives you
682 * the option of 2^4 clear colors. Each bit determines if the color channel
683 * is fully saturated or unsaturated (Cherryview does add a 32b value per
684 * channel, but it is globally applied instead of being part of the render
685 * surface state). Starting with GEN9, the surface state accepts a 32b value
686 * for each color channel.
688 * @see RENDER_SURFACE_STATE.RedClearColor
689 * @see RENDER_SURFACE_STATE.GreenClearColor
690 * @see RENDER_SURFACE_STATE.BlueClearColor
691 * @see RENDER_SURFACE_STATE.AlphaClearColor
694 uint32_t fast_clear_color_value
;
695 union gl_color_union gen9_fast_clear_color
;
699 * Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS
700 * buffer. This is useful for sharing the miptree bo with an external client
701 * that doesn't understand auxiliary buffers.
703 bool disable_aux_buffers
;
706 * Tells if the underlying buffer is to be also consumed by entities other
707 * than the driver. This allows logic to turn off features such as lossless
708 * compression which is not currently understood by client applications.
712 /* These are also refcounted:
718 intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree
*mt
,
719 unsigned *width_px
, unsigned *height
);
722 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
723 const struct intel_mipmap_tree
*mt
);
726 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
730 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
731 const struct intel_mipmap_tree
*mt
);
734 intel_miptree_supports_lossless_compressed(struct brw_context
*brw
,
735 const struct intel_mipmap_tree
*mt
);
738 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
739 struct intel_mipmap_tree
*mt
,
740 bool is_lossless_compressed
);
743 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
= 1 << 0,
744 MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
= 1 << 1,
745 MIPTREE_LAYOUT_FOR_BO
= 1 << 2,
746 MIPTREE_LAYOUT_DISABLE_AUX
= 1 << 3,
747 MIPTREE_LAYOUT_FORCE_HALIGN16
= 1 << 4,
749 MIPTREE_LAYOUT_TILING_Y
= 1 << 5,
750 MIPTREE_LAYOUT_TILING_NONE
= 1 << 6,
751 MIPTREE_LAYOUT_TILING_ANY
= MIPTREE_LAYOUT_TILING_Y
|
752 MIPTREE_LAYOUT_TILING_NONE
,
754 MIPTREE_LAYOUT_FOR_SCANOUT
= 1 << 7,
757 struct intel_mipmap_tree
*intel_miptree_create(struct brw_context
*brw
,
768 struct intel_mipmap_tree
*
769 intel_miptree_create_for_bo(struct brw_context
*brw
,
777 uint32_t layout_flags
);
780 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
781 struct intel_renderbuffer
*irb
,
783 uint32_t width
, uint32_t height
,
787 * Create a miptree appropriate as the storage for a non-texture renderbuffer.
788 * The miptree has the following properties:
789 * - The target is GL_TEXTURE_2D.
790 * - There are no levels other than the base level 0.
793 struct intel_mipmap_tree
*
794 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
798 uint32_t num_samples
);
801 intel_depth_format_for_depthstencil_format(mesa_format format
);
804 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
);
806 /** \brief Assert that the level and layer are valid for the miptree. */
808 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
816 assert(level
>= mt
->first_level
);
817 assert(level
<= mt
->last_level
);
818 assert(layer
< mt
->level
[level
].depth
);
821 void intel_miptree_reference(struct intel_mipmap_tree
**dst
,
822 struct intel_mipmap_tree
*src
);
824 void intel_miptree_release(struct intel_mipmap_tree
**mt
);
826 /* Check if an image fits an existing mipmap tree layout
828 bool intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
829 struct gl_texture_image
*image
);
832 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
833 GLuint level
, GLuint slice
,
834 GLuint
*x
, GLuint
*y
);
837 get_isl_surf_dim(GLenum target
);
840 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
844 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
);
847 intel_miptree_get_isl_surf(struct brw_context
*brw
,
848 const struct intel_mipmap_tree
*mt
,
849 struct isl_surf
*surf
);
851 intel_miptree_get_aux_isl_surf(struct brw_context
*brw
,
852 const struct intel_mipmap_tree
*mt
,
853 struct isl_surf
*surf
,
854 enum isl_aux_usage
*usage
);
856 union isl_color_value
857 intel_miptree_get_isl_clear_color(struct brw_context
*brw
,
858 const struct intel_mipmap_tree
*mt
);
861 intel_get_image_dims(struct gl_texture_image
*image
,
862 int *width
, int *height
, int *depth
);
865 intel_get_tile_masks(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
866 uint32_t *mask_x
, uint32_t *mask_y
);
869 intel_get_tile_dims(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
870 uint32_t *tile_w
, uint32_t *tile_h
);
873 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
874 GLuint level
, GLuint slice
,
878 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
879 uint32_t x
, uint32_t y
);
881 void intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
883 GLuint x
, GLuint y
, GLuint d
);
885 void intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
887 GLuint img
, GLuint x
, GLuint y
);
890 intel_miptree_copy_teximage(struct brw_context
*brw
,
891 struct intel_texture_image
*intelImage
,
892 struct intel_mipmap_tree
*dst_mt
, bool invalidate
);
895 * \name Miptree HiZ functions
898 * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
899 * functions on a miptree without HiZ. In that case, each function is a no-op.
903 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
904 struct intel_mipmap_tree
*mt
);
907 * \brief Allocate the miptree's embedded HiZ miptree.
908 * \see intel_mipmap_tree:hiz_mt
909 * \return false if allocation failed
912 intel_miptree_alloc_hiz(struct brw_context
*brw
,
913 struct intel_mipmap_tree
*mt
);
916 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
);
919 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
923 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
928 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
932 * \return false if no resolve was needed
935 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
936 struct intel_mipmap_tree
*mt
,
941 * \return false if no resolve was needed
944 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
945 struct intel_mipmap_tree
*mt
,
950 * \return false if no resolve was needed
953 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
954 struct intel_mipmap_tree
*mt
);
957 * \return false if no resolve was needed
960 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
961 struct intel_mipmap_tree
*mt
);
966 * Update the fast clear state for a miptree to indicate that it has been used
970 intel_miptree_used_for_rendering(const struct brw_context
*brw
,
971 struct intel_mipmap_tree
*mt
)
973 /* If the buffer was previously in fast clear state, change it to
974 * unresolved state, since it won't be guaranteed to be clear after
977 if (mt
->fast_clear_state
== INTEL_FAST_CLEAR_STATE_CLEAR
||
978 intel_miptree_is_lossless_compressed(brw
, mt
))
979 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_UNRESOLVED
;
983 * Flag values telling color resolve pass which special types of buffers
986 * INTEL_MIPTREE_IGNORE_CCS_E: Lossless compressed (single-sample
987 * compression scheme since gen9)
989 #define INTEL_MIPTREE_IGNORE_CCS_E (1 << 0)
992 intel_miptree_resolve_color(struct brw_context
*brw
,
993 struct intel_mipmap_tree
*mt
,
997 intel_miptree_make_shareable(struct brw_context
*brw
,
998 struct intel_mipmap_tree
*mt
);
1001 intel_miptree_updownsample(struct brw_context
*brw
,
1002 struct intel_mipmap_tree
*src
,
1003 struct intel_mipmap_tree
*dst
);
1006 intel_update_r8stencil(struct brw_context
*brw
,
1007 struct intel_mipmap_tree
*mt
);
1010 * Horizontal distance from one slice to the next in the two-dimensional
1014 brw_miptree_get_horizontal_slice_pitch(const struct brw_context
*brw
,
1015 const struct intel_mipmap_tree
*mt
,
1019 * Vertical distance from one slice to the next in the two-dimensional miptree
1023 brw_miptree_get_vertical_slice_pitch(const struct brw_context
*brw
,
1024 const struct intel_mipmap_tree
*mt
,
1028 brw_miptree_layout(struct brw_context
*brw
,
1029 struct intel_mipmap_tree
*mt
,
1030 uint32_t layout_flags
);
1033 intel_miptree_map(struct brw_context
*brw
,
1034 struct intel_mipmap_tree
*mt
,
1043 ptrdiff_t *out_stride
);
1046 intel_miptree_unmap(struct brw_context
*brw
,
1047 struct intel_mipmap_tree
*mt
,
1049 unsigned int slice
);
1052 intel_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1053 unsigned int level
, unsigned int layer
, enum blorp_hiz_op op
);
1056 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1057 struct intel_mipmap_tree
*mt
);