src/mesa/drivers/dri/i965/intel_mipmap_tree.h

   1 /*
   2  * Copyright 2006 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 /** @file intel_mipmap_tree.h
  27  *
  28  * This file defines the structure that wraps a BO and describes how the
  29  * mipmap levels and slices of a texture are laid out.
  30  *
  31  * The hardware has a fixed layout of a texture depending on parameters such
  32  * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
  33  * mipmap levels.  The individual level/layer slices are each 2D rectangles of
  34  * pixels at some x/y offset from the start of the brw_bo.
  35  *
  36  * Original OpenGL allowed texture miplevels to be specified in arbitrary
  37  * order, and a texture may change size over time.  Thus, each
  38  * intel_texture_image has a reference to a miptree that contains the pixel
  39  * data sized appropriately for it, which will later be referenced by/copied
  40  * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
  41  * that there's a single miptree for the complete texture.
  42  */
  43
  44 #ifndef INTEL_MIPMAP_TREE_H
  45 #define INTEL_MIPMAP_TREE_H
  46
  47 #include <assert.h>
  48
  49 #include "main/mtypes.h"
  50 #include "isl/isl.h"
  51 #include "blorp/blorp.h"
  52 #include "brw_bufmgr.h"
  53 #include "brw_context.h"
  54 #include <GL/internal/dri_interface.h>
  55
  56 #ifdef __cplusplus
  57 extern "C" {
  58 #endif
  59
  60 struct brw_context;
  61 struct intel_renderbuffer;
  62
  63 struct intel_texture_image;
  64
  65 /**
  66  * This bit extends the set of GL_MAP_*_BIT enums.
  67  *
  68  * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
  69  * depthstencil-split-to-separate-stencil miptree, we'll normally make a
  70  * temporary and recreate the kind of data requested by Mesa core, since we're
  71  * satisfying some glGetTexImage() request or something.
  72  *
  73  * However, occasionally you want to actually map the miptree's current data
  74  * without transcoding back.  This flag to intel_miptree_map() gets you that.
  75  */
  76 #define BRW_MAP_DIRECT_BIT      0x80000000
  77
  78 struct intel_miptree_map {
  79    /** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */
  80    GLbitfield mode;
  81    /** Region of interest for the map. */
  82    int x, y, w, h;
  83    /** Possibly malloced temporary buffer for the mapping. */
  84    void *buffer;
  85    /** Possible pointer to a temporary linear miptree for the mapping. */
  86    struct intel_mipmap_tree *linear_mt;
  87    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  88    void *ptr;
  89    /** Stride of the mapping. */
  90    int stride;
  91 };
  92
  93 /**
  94  * Describes the location of each texture image within a miptree.
  95  */
  96 struct intel_mipmap_level
  97 {
  98    /** Offset to this miptree level, used in computing x_offset. */
  99    GLuint level_x;
 100    /** Offset to this miptree level, used in computing y_offset. */
 101    GLuint level_y;
 102
 103    /**
 104     * \brief Is HiZ enabled for this level?
 105     *
 106     * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
 107     * allocated and (2) the HiZ memory for the slices in this level reside at
 108     * \c mt->hiz_mt->level[l].
 109     */
 110    bool has_hiz;
 111
 112    /**
 113     * \brief List of 2D images in this mipmap level.
 114     *
 115     * This may be a list of cube faces, array slices in 2D array texture, or
 116     * layers in a 3D texture. The list's length is \c depth.
 117     */
 118    struct intel_mipmap_slice {
 119       /**
 120        * Mapping information. Persistent for the duration of
 121        * intel_miptree_map/unmap on this slice.
 122        */
 123       struct intel_miptree_map *map;
 124    } *slice;
 125 };
 126
 127 /**
 128  * Miptree aux buffer. These buffers are associated with a miptree, but the
 129  * format is managed by the hardware.
 130  *
 131  * For Gen7+, we always give the hardware the start of the buffer, and let it
 132  * handle all accesses to the buffer. Therefore we don't need the full miptree
 133  * layout structure for this buffer.
 134  */
 135 struct intel_miptree_aux_buffer
 136 {
 137    struct isl_surf surf;
 138
 139    /**
 140     * Buffer object containing the pixel data.
 141     *
 142     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 143     * @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
 144     */
 145    struct brw_bo *bo;
 146
 147    /**
 148     * Offset into bo where the surface starts.
 149     *
 150     * @see intel_mipmap_aux_buffer::bo
 151     *
 152     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 153     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 154     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 155     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 156     */
 157    uint32_t offset;
 158
 159    /*
 160     * Size of the MCS surface.
 161     *
 162     * This is needed when doing any gtt mapped operations on the buffer (which
 163     * will be Y-tiled). It is possible that it will not be the same as bo->size
 164     * when the drm allocator rounds up the requested size.
 165     */
 166    size_t size;
 167
 168    /**
 169     * Pitch in bytes.
 170     *
 171     * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
 172     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
 173     */
 174    uint32_t pitch;
 175
 176    /**
 177     * The distance in rows between array slices.
 178     *
 179     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch
 180     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
 181     */
 182    uint32_t qpitch;
 183
 184    /**
 185     * Buffer object containing the indirect clear color.
 186     *
 187     * @see create_ccs_buf_for_image
 188     * @see RENDER_SURFACE_STATE.ClearValueAddress
 189     */
 190    struct brw_bo *clear_color_bo;
 191
 192    /**
 193     * Offset into bo where the clear color can be found.
 194     *
 195     * @see create_ccs_buf_for_image
 196     * @see RENDER_SURFACE_STATE.ClearValueAddress
 197     */
 198    uint32_t clear_color_offset;
 199 };
 200
 201 struct intel_mipmap_tree
 202 {
 203    struct isl_surf surf;
 204
 205    /**
 206     * Buffer object containing the surface.
 207     *
 208     * @see intel_mipmap_tree::offset
 209     * @see RENDER_SURFACE_STATE.SurfaceBaseAddress
 210     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 211     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 212     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 213     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 214     */
 215    struct brw_bo *bo;
 216
 217    /**
 218     * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
 219     *
 220     * @see RENDER_SURFACE_STATE.SurfaceType
 221     * @see RENDER_SURFACE_STATE.SurfaceArray
 222     * @see 3DSTATE_DEPTH_BUFFER.SurfaceType
 223     */
 224    GLenum target;
 225
 226    /**
 227     * Generally, this is just the same as the gl_texture_image->TexFormat or
 228     * gl_renderbuffer->Format.
 229     *
 230     * However, for textures and renderbuffers with packed depth/stencil formats
 231     * on hardware where we want or need to use separate stencil, there will be
 232     * two miptrees for storing the data.  If the depthstencil texture or rb is
 233     * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
 234     * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
 235     * MESA_FORMAT_Z24_UNORM_X8_UINT.
 236     *
 237     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
 238     * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
 239     *
 240     * @see RENDER_SURFACE_STATE.SurfaceFormat
 241     * @see 3DSTATE_DEPTH_BUFFER.SurfaceFormat
 242     */
 243    mesa_format format;
 244
 245    /**
 246     * This variable stores the value of ETC compressed texture format
 247     *
 248     * @see RENDER_SURFACE_STATE.SurfaceFormat
 249     */
 250    mesa_format etc_format;
 251
 252    GLuint first_level;
 253    GLuint last_level;
 254
 255    /** Bytes per pixel (or bytes per block if compressed) */
 256    GLuint cpp;
 257
 258    bool compressed;
 259
 260    /* Includes image offset tables: */
 261    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 262
 263    /**
 264     * Offset into bo where the surface starts.
 265     *
 266     * @see intel_mipmap_tree::bo
 267     *
 268     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 269     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 270     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 271     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 272     */
 273    uint32_t offset;
 274
 275    /**
 276     * \brief HiZ aux buffer
 277     *
 278     * To allocate the hiz buffer, use intel_miptree_alloc_hiz().
 279     *
 280     * To determine if hiz is enabled, do not check this pointer. Instead, use
 281     * intel_miptree_level_has_hiz().
 282     */
 283    struct intel_miptree_aux_buffer *hiz_buf;
 284
 285    /**
 286     * \brief The type of auxiliary compression used by this miptree.
 287     *
 288     * This describes the type of auxiliary compression that is intended to be
 289     * used by this miptree.  An aux usage of ISL_AUX_USAGE_NONE means that
 290     * auxiliary compression is permanently disabled.  An aux usage other than
 291     * ISL_AUX_USAGE_NONE does not imply that the auxiliary buffer has actually
 292     * been allocated nor does it imply that auxiliary compression will always
 293     * be enabled for this surface.  For instance, with CCS_D, we may allocate
 294     * the CCS on-the-fly and it may not be used for texturing if the miptree
 295     * is fully resolved.
 296     */
 297    enum isl_aux_usage aux_usage;
 298
 299    /**
 300     * \brief Whether or not this miptree supports fast clears.
 301     */
 302    bool supports_fast_clear;
 303
 304    /**
 305     * \brief Maps miptree slices to their current aux state
 306     *
 307     * This two-dimensional array is indexed as [level][layer] and stores an
 308     * aux state for each slice.
 309     */
 310    enum isl_aux_state **aux_state;
 311
 312    /**
 313     * \brief Stencil miptree for depthstencil textures.
 314     *
 315     * This miptree is used for depthstencil textures and renderbuffers that
 316     * require separate stencil.  It always has the true copy of the stencil
 317     * bits, regardless of mt->format.
 318     *
 319     * \see 3DSTATE_STENCIL_BUFFER
 320     * \see intel_miptree_map_depthstencil()
 321     * \see intel_miptree_unmap_depthstencil()
 322     */
 323    struct intel_mipmap_tree *stencil_mt;
 324
 325    /**
 326     * \brief Stencil texturing miptree for sampling from a stencil texture
 327     *
 328     * Some hardware doesn't support sampling from the stencil texture as
 329     * required by the GL_ARB_stencil_texturing extenion. To workaround this we
 330     * blit the texture into a new texture that can be sampled.
 331     *
 332     * \see intel_update_r8stencil()
 333     */
 334    struct intel_mipmap_tree *r8stencil_mt;
 335    bool r8stencil_needs_update;
 336
 337    /**
 338     * \brief MCS auxiliary buffer.
 339     *
 340     * This buffer contains the "multisample control surface", which stores
 341     * the necessary information to implement compressed MSAA
 342     * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
 343     *
 344     * NULL if no MCS buffer is in use for this surface.
 345     */
 346    struct intel_miptree_aux_buffer *mcs_buf;
 347
 348    /**
 349     * Planes 1 and 2 in case this is a planar surface.
 350     */
 351    struct intel_mipmap_tree *plane[2];
 352
 353    /**
 354     * Fast clear color for this surface.  For depth surfaces, the clear value
 355     * is stored as a float32 in the red component.
 356     */
 357    union isl_color_value fast_clear_color;
 358
 359    /**
 360     * For external surfaces, this is DRM format modifier that was used to
 361     * create or import the surface.  For internal surfaces, this will always
 362     * be DRM_FORMAT_MOD_INVALID.
 363     */
 364    uint64_t drm_modifier;
 365
 366    /* These are also refcounted:
 367     */
 368    GLuint refcount;
 369 };
 370
 371 bool
 372 intel_miptree_alloc_ccs(struct brw_context *brw,
 373                         struct intel_mipmap_tree *mt);
 374
 375 enum intel_miptree_create_flags {
 376    /** No miptree create flags */
 377    MIPTREE_CREATE_DEFAULT  = 0,
 378
 379    /** Miptree creation should try to allocate a currently busy BO
 380     *
 381     * This may be advantageous if we know the next thing to touch the BO will
 382     * be the GPU because the BO will likely already be in the GTT and maybe
 383     * even in some caches.  If there is a chance that the next thing to touch
 384     * the miptree BO will be the CPU, this flag should not be set.
 385     */
 386    MIPTREE_CREATE_BUSY     = 1 << 0,
 387
 388    /** Create a linear (not tiled) miptree */
 389    MIPTREE_CREATE_LINEAR   = 1 << 1,
 390
 391    /** Create the miptree with auxiliary compression disabled
 392     *
 393     * This does not prevent the caller of intel_miptree_create from coming
 394     * along later and turning auxiliary compression back on but it does mean
 395     * that the miptree will be created with mt->aux_usage == NONE.
 396     */
 397    MIPTREE_CREATE_NO_AUX   = 1 << 2,
 398 };
 399
 400 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
 401                                                GLenum target,
 402                                                mesa_format format,
 403                                                GLuint first_level,
 404                                                GLuint last_level,
 405                                                GLuint width0,
 406                                                GLuint height0,
 407                                                GLuint depth0,
 408                                                GLuint num_samples,
 409                                                enum intel_miptree_create_flags flags);
 410
 411 struct intel_mipmap_tree *
 412 intel_miptree_create_for_bo(struct brw_context *brw,
 413                             struct brw_bo *bo,
 414                             mesa_format format,
 415                             uint32_t offset,
 416                             uint32_t width,
 417                             uint32_t height,
 418                             uint32_t depth,
 419                             int pitch,
 420                             enum isl_tiling tiling,
 421                             enum intel_miptree_create_flags flags);
 422
 423 struct intel_mipmap_tree *
 424 intel_miptree_create_for_dri_image(struct brw_context *brw,
 425                                    __DRIimage *image,
 426                                    GLenum target,
 427                                    mesa_format format,
 428                                    bool is_winsys_image);
 429
 430 bool
 431 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
 432                                          struct intel_renderbuffer *irb,
 433                                          struct intel_mipmap_tree *singlesample_mt,
 434                                          uint32_t width, uint32_t height,
 435                                          uint32_t pitch);
 436
 437 /**
 438  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 439  * The miptree has the following properties:
 440  *     - The target is GL_TEXTURE_2D.
 441  *     - There are no levels other than the base level 0.
 442  *     - Depth is 1.
 443  */
 444 struct intel_mipmap_tree*
 445 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
 446                                       mesa_format format,
 447                                       uint32_t width,
 448                                       uint32_t height,
 449                                       uint32_t num_samples);
 450
 451 mesa_format
 452 intel_depth_format_for_depthstencil_format(mesa_format format);
 453
 454 mesa_format
 455 intel_lower_compressed_format(struct brw_context *brw, mesa_format format);
 456
 457 unsigned
 458 brw_get_num_logical_layers(const struct intel_mipmap_tree *mt, unsigned level);
 459
 460 /** \brief Assert that the level and layer are valid for the miptree. */
 461 void
 462 intel_miptree_check_level_layer(const struct intel_mipmap_tree *mt,
 463                                 uint32_t level,
 464                                 uint32_t layer);
 465
 466 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 467                              struct intel_mipmap_tree *src);
 468
 469 void intel_miptree_release(struct intel_mipmap_tree **mt);
 470
 471 /* Check if an image fits an existing mipmap tree layout
 472  */
 473 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 474                                     struct gl_texture_image *image);
 475
 476 void
 477 intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt,
 478                                GLuint level, GLuint slice,
 479                                GLuint *x, GLuint *y);
 480
 481 enum isl_surf_dim
 482 get_isl_surf_dim(GLenum target);
 483
 484 enum isl_dim_layout
 485 get_isl_dim_layout(const struct gen_device_info *devinfo,
 486                    enum isl_tiling tiling, GLenum target);
 487
 488 void
 489 intel_get_image_dims(struct gl_texture_image *image,
 490                      int *width, int *height, int *depth);
 491
 492 void
 493 intel_get_tile_masks(enum isl_tiling tiling, uint32_t cpp,
 494                      uint32_t *mask_x, uint32_t *mask_y);
 495
 496 void
 497 intel_get_tile_dims(enum isl_tiling tiling, uint32_t cpp,
 498                     uint32_t *tile_w, uint32_t *tile_h);
 499
 500 uint32_t
 501 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
 502                                GLuint level, GLuint slice,
 503                                uint32_t *tile_x,
 504                                uint32_t *tile_y);
 505 uint32_t
 506 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
 507                                  uint32_t x, uint32_t y);
 508
 509 void
 510 intel_miptree_copy_slice(struct brw_context *brw,
 511                          struct intel_mipmap_tree *src_mt,
 512                          unsigned src_level, unsigned src_layer,
 513                          struct intel_mipmap_tree *dst_mt,
 514                          unsigned dst_level, unsigned dst_layer);
 515
 516 void
 517 intel_miptree_copy_teximage(struct brw_context *brw,
 518                             struct intel_texture_image *intelImage,
 519                             struct intel_mipmap_tree *dst_mt);
 520
 521 /**
 522  * \name Miptree HiZ functions
 523  * \{
 524  *
 525  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 526  * functions on a miptree without HiZ. In that case, each function is a no-op.
 527  */
 528
 529 /**
 530  * \brief Allocate the miptree's embedded HiZ miptree.
 531  * \see intel_mipmap_tree:hiz_mt
 532  * \return false if allocation failed
 533  */
 534 bool
 535 intel_miptree_alloc_hiz(struct brw_context *brw,
 536                         struct intel_mipmap_tree *mt);
 537
 538 bool
 539 intel_miptree_level_has_hiz(const struct intel_mipmap_tree *mt, uint32_t level);
 540
 541 /**\}*/
 542
 543 bool
 544 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree *mt,
 545                                    unsigned start_level, unsigned num_levels,
 546                                    unsigned start_layer, unsigned num_layers);
 547
 548
 549 #define INTEL_REMAINING_LAYERS UINT32_MAX
 550 #define INTEL_REMAINING_LEVELS UINT32_MAX
 551
 552 /** Prepare a miptree for access
 553  *
 554  * This function should be called prior to any access to miptree in order to
 555  * perform any needed resolves.
 556  *
 557  * \param[in]  start_level    The first mip level to be accessed
 558  *
 559  * \param[in]  num_levels     The number of miplevels to be accessed or
 560  *                            INTEL_REMAINING_LEVELS to indicate every level
 561  *                            above start_level will be accessed
 562  *
 563  * \param[in]  start_layer    The first array slice or 3D layer to be accessed
 564  *
 565  * \param[in]  num_layers     The number of array slices or 3D layers be
 566  *                            accessed or INTEL_REMAINING_LAYERS to indicate
 567  *                            every layer above start_layer will be accessed
 568  *
 569  * \param[in]  aux_supported  Whether or not the access will support the
 570  *                            miptree's auxiliary compression format;  this
 571  *                            must be false for uncompressed miptrees
 572  *
 573  * \param[in]  fast_clear_supported Whether or not the access will support
 574  *                                  fast clears in the miptree's auxiliary
 575  *                                  compression format
 576  */
 577 void
 578 intel_miptree_prepare_access(struct brw_context *brw,
 579                              struct intel_mipmap_tree *mt,
 580                              uint32_t start_level, uint32_t num_levels,
 581                              uint32_t start_layer, uint32_t num_layers,
 582                              enum isl_aux_usage aux_usage,
 583                              bool fast_clear_supported);
 584
 585 /** Complete a write operation
 586  *
 587  * This function should be called after any operation writes to a miptree.
 588  * This will update the miptree's compression state so that future resolves
 589  * happen correctly.  Technically, this function can be called before the
 590  * write occurs but the caller must ensure that they don't interlace
 591  * intel_miptree_prepare_access and intel_miptree_finish_write calls to
 592  * overlapping layer/level ranges.
 593  *
 594  * \param[in]  level             The mip level that was written
 595  *
 596  * \param[in]  start_layer       The first array slice or 3D layer written
 597  *
 598  * \param[in]  num_layers        The number of array slices or 3D layers
 599  *                               written or INTEL_REMAINING_LAYERS to indicate
 600  *                               every layer above start_layer was written
 601  *
 602  * \param[in]  written_with_aux  Whether or not the write was done with
 603  *                               auxiliary compression enabled
 604  */
 605 void
 606 intel_miptree_finish_write(struct brw_context *brw,
 607                            struct intel_mipmap_tree *mt, uint32_t level,
 608                            uint32_t start_layer, uint32_t num_layers,
 609                            enum isl_aux_usage aux_usage);
 610
 611 /** Get the auxiliary compression state of a miptree slice */
 612 enum isl_aux_state
 613 intel_miptree_get_aux_state(const struct intel_mipmap_tree *mt,
 614                             uint32_t level, uint32_t layer);
 615
 616 /** Set the auxiliary compression state of a miptree slice range
 617  *
 618  * This function directly sets the auxiliary compression state of a slice
 619  * range of a miptree.  It only modifies data structures and does not do any
 620  * resolves.  This should only be called by code which directly performs
 621  * compression operations such as fast clears and resolves.  Most code should
 622  * use intel_miptree_prepare_access or intel_miptree_finish_write.
 623  */
 624 void
 625 intel_miptree_set_aux_state(struct brw_context *brw,
 626                             struct intel_mipmap_tree *mt, uint32_t level,
 627                             uint32_t start_layer, uint32_t num_layers,
 628                             enum isl_aux_state aux_state);
 629
 630 /**
 631  * Prepare a miptree for raw access
 632  *
 633  * This helper prepares the miptree for access that knows nothing about any
 634  * sort of compression whatsoever.  This is useful when mapping the surface or
 635  * using it with the blitter.
 636  */
 637 static inline void
 638 intel_miptree_access_raw(struct brw_context *brw,
 639                          struct intel_mipmap_tree *mt,
 640                          uint32_t level, uint32_t layer,
 641                          bool write)
 642 {
 643    intel_miptree_prepare_access(brw, mt, level, 1, layer, 1, false, false);
 644    if (write)
 645       intel_miptree_finish_write(brw, mt, level, layer, 1, false);
 646 }
 647
 648 enum isl_aux_usage
 649 intel_miptree_texture_aux_usage(struct brw_context *brw,
 650                                 struct intel_mipmap_tree *mt,
 651                                 enum isl_format view_format);
 652 void
 653 intel_miptree_prepare_texture(struct brw_context *brw,
 654                               struct intel_mipmap_tree *mt,
 655                               enum isl_format view_format,
 656                               uint32_t start_level, uint32_t num_levels,
 657                               uint32_t start_layer, uint32_t num_layers);
 658 void
 659 intel_miptree_prepare_image(struct brw_context *brw,
 660                             struct intel_mipmap_tree *mt);
 661
 662 enum isl_aux_usage
 663 intel_miptree_render_aux_usage(struct brw_context *brw,
 664                                struct intel_mipmap_tree *mt,
 665                                enum isl_format render_format,
 666                                bool blend_enabled,
 667                                bool draw_aux_disabled);
 668 void
 669 intel_miptree_prepare_render(struct brw_context *brw,
 670                              struct intel_mipmap_tree *mt, uint32_t level,
 671                              uint32_t start_layer, uint32_t layer_count,
 672                              enum isl_aux_usage aux_usage);
 673 void
 674 intel_miptree_finish_render(struct brw_context *brw,
 675                             struct intel_mipmap_tree *mt, uint32_t level,
 676                             uint32_t start_layer, uint32_t layer_count,
 677                             enum isl_aux_usage aux_usage);
 678 void
 679 intel_miptree_prepare_depth(struct brw_context *brw,
 680                             struct intel_mipmap_tree *mt, uint32_t level,
 681                             uint32_t start_layer, uint32_t layer_count);
 682 void
 683 intel_miptree_finish_depth(struct brw_context *brw,
 684                            struct intel_mipmap_tree *mt, uint32_t level,
 685                            uint32_t start_layer, uint32_t layer_count,
 686                            bool depth_written);
 687 void
 688 intel_miptree_prepare_external(struct brw_context *brw,
 689                                struct intel_mipmap_tree *mt);
 690 void
 691 intel_miptree_finish_external(struct brw_context *brw,
 692                               struct intel_mipmap_tree *mt);
 693
 694 void
 695 intel_miptree_make_shareable(struct brw_context *brw,
 696                              struct intel_mipmap_tree *mt);
 697
 698 void
 699 intel_miptree_updownsample(struct brw_context *brw,
 700                            struct intel_mipmap_tree *src,
 701                            struct intel_mipmap_tree *dst);
 702
 703 void
 704 intel_update_r8stencil(struct brw_context *brw,
 705                        struct intel_mipmap_tree *mt);
 706
 707 void
 708 intel_miptree_map(struct brw_context *brw,
 709                   struct intel_mipmap_tree *mt,
 710                   unsigned int level,
 711                   unsigned int slice,
 712                   unsigned int x,
 713                   unsigned int y,
 714                   unsigned int w,
 715                   unsigned int h,
 716                   GLbitfield mode,
 717                   void **out_ptr,
 718                   ptrdiff_t *out_stride);
 719
 720 void
 721 intel_miptree_unmap(struct brw_context *brw,
 722                     struct intel_mipmap_tree *mt,
 723                     unsigned int level,
 724                     unsigned int slice);
 725
 726 bool
 727 intel_miptree_sample_with_hiz(struct brw_context *brw,
 728                               struct intel_mipmap_tree *mt);
 729
 730 bool
 731 intel_miptree_set_clear_color(struct brw_context *brw,
 732                               struct intel_mipmap_tree *mt,
 733                               const union gl_color_union *color);
 734
 735 bool
 736 intel_miptree_set_depth_clear_value(struct brw_context *brw,
 737                                     struct intel_mipmap_tree *mt,
 738                                     float clear_value);
 739
 740 #ifdef __cplusplus
 741 }
 742 #endif
 743
 744 #endif