src/mesa/drivers/dri/i965/intel_mipmap_tree.h

   1 /*
   2  * Copyright 2006 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 /** @file intel_mipmap_tree.h
  27  *
  28  * This file defines the structure that wraps a BO and describes how the
  29  * mipmap levels and slices of a texture are laid out.
  30  *
  31  * The hardware has a fixed layout of a texture depending on parameters such
  32  * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
  33  * mipmap levels.  The individual level/layer slices are each 2D rectangles of
  34  * pixels at some x/y offset from the start of the brw_bo.
  35  *
  36  * Original OpenGL allowed texture miplevels to be specified in arbitrary
  37  * order, and a texture may change size over time.  Thus, each
  38  * intel_texture_image has a reference to a miptree that contains the pixel
  39  * data sized appropriately for it, which will later be referenced by/copied
  40  * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
  41  * that there's a single miptree for the complete texture.
  42  */
  43
  44 #ifndef INTEL_MIPMAP_TREE_H
  45 #define INTEL_MIPMAP_TREE_H
  46
  47 #include <assert.h>
  48
  49 #include "main/mtypes.h"
  50 #include "isl/isl.h"
  51 #include "blorp/blorp.h"
  52 #include "brw_bufmgr.h"
  53 #include "brw_context.h"
  54 #include <GL/internal/dri_interface.h>
  55
  56 #ifdef __cplusplus
  57 extern "C" {
  58 #endif
  59
  60 struct brw_context;
  61 struct intel_renderbuffer;
  62
  63 struct intel_texture_image;
  64
  65 /**
  66  * This bit extends the set of GL_MAP_*_BIT enums.
  67  *
  68  * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
  69  * depthstencil-split-to-separate-stencil miptree, we'll normally make a
  70  * temporary and recreate the kind of data requested by Mesa core, since we're
  71  * satisfying some glGetTexImage() request or something.
  72  *
  73  * However, occasionally you want to actually map the miptree's current data
  74  * without transcoding back.  This flag to intel_miptree_map() gets you that.
  75  */
  76 #define BRW_MAP_DIRECT_BIT      0x80000000
  77
  78 struct intel_miptree_map {
  79    /** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */
  80    GLbitfield mode;
  81    /** Region of interest for the map. */
  82    int x, y, w, h;
  83    /** Possibly malloced temporary buffer for the mapping. */
  84    void *buffer;
  85    /** Possible pointer to a temporary linear miptree for the mapping. */
  86    struct intel_mipmap_tree *linear_mt;
  87    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  88    void *ptr;
  89    /** Stride of the mapping. */
  90    int stride;
  91 };
  92
  93 /**
  94  * Describes the location of each texture image within a miptree.
  95  */
  96 struct intel_mipmap_level
  97 {
  98    /** Offset to this miptree level, used in computing x_offset. */
  99    GLuint level_x;
 100    /** Offset to this miptree level, used in computing y_offset. */
 101    GLuint level_y;
 102
 103    /**
 104     * \brief Is HiZ enabled for this level?
 105     *
 106     * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
 107     * allocated and (2) the HiZ memory for the slices in this level reside at
 108     * \c mt->hiz_mt->level[l].
 109     */
 110    bool has_hiz;
 111
 112    /**
 113     * \brief List of 2D images in this mipmap level.
 114     *
 115     * This may be a list of cube faces, array slices in 2D array texture, or
 116     * layers in a 3D texture. The list's length is \c depth.
 117     */
 118    struct intel_mipmap_slice {
 119       /**
 120        * Mapping information. Persistent for the duration of
 121        * intel_miptree_map/unmap on this slice.
 122        */
 123       struct intel_miptree_map *map;
 124    } *slice;
 125 };
 126
 127 /**
 128  * Miptree aux buffer. These buffers are associated with a miptree, but the
 129  * format is managed by the hardware.
 130  *
 131  * For Gen7+, we always give the hardware the start of the buffer, and let it
 132  * handle all accesses to the buffer. Therefore we don't need the full miptree
 133  * layout structure for this buffer.
 134  */
 135 struct intel_miptree_aux_buffer
 136 {
 137    struct isl_surf surf;
 138
 139    /**
 140     * Buffer object containing the pixel data.
 141     *
 142     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 143     * @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
 144     */
 145    struct brw_bo *bo;
 146
 147    /**
 148     * Offset into bo where the surface starts.
 149     *
 150     * @see intel_mipmap_aux_buffer::bo
 151     *
 152     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 153     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 154     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 155     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 156     */
 157    uint32_t offset;
 158
 159    /*
 160     * Size of the MCS surface.
 161     *
 162     * This is needed when doing any gtt mapped operations on the buffer (which
 163     * will be Y-tiled). It is possible that it will not be the same as bo->size
 164     * when the drm allocator rounds up the requested size.
 165     */
 166    size_t size;
 167
 168    /**
 169     * Pitch in bytes.
 170     *
 171     * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
 172     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
 173     */
 174    uint32_t pitch;
 175
 176    /**
 177     * The distance in rows between array slices.
 178     *
 179     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch
 180     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
 181     */
 182    uint32_t qpitch;
 183
 184    /**
 185     * Buffer object containing the indirect clear color.
 186     *
 187     * @see create_ccs_buf_for_image
 188     * @see RENDER_SURFACE_STATE.ClearValueAddress
 189     */
 190    struct brw_bo *clear_color_bo;
 191
 192    /**
 193     * Offset into bo where the clear color can be found.
 194     *
 195     * @see create_ccs_buf_for_image
 196     * @see RENDER_SURFACE_STATE.ClearValueAddress
 197     */
 198    uint32_t clear_color_offset;
 199 };
 200
 201 struct intel_mipmap_tree
 202 {
 203    struct isl_surf surf;
 204
 205    /**
 206     * Buffer object containing the surface.
 207     *
 208     * @see intel_mipmap_tree::offset
 209     * @see RENDER_SURFACE_STATE.SurfaceBaseAddress
 210     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 211     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 212     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 213     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 214     */
 215    struct brw_bo *bo;
 216
 217    /**
 218     * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
 219     *
 220     * @see RENDER_SURFACE_STATE.SurfaceType
 221     * @see RENDER_SURFACE_STATE.SurfaceArray
 222     * @see 3DSTATE_DEPTH_BUFFER.SurfaceType
 223     */
 224    GLenum target;
 225
 226    /**
 227     * Generally, this is just the same as the gl_texture_image->TexFormat or
 228     * gl_renderbuffer->Format.
 229     *
 230     * However, for textures and renderbuffers with packed depth/stencil formats
 231     * on hardware where we want or need to use separate stencil, there will be
 232     * two miptrees for storing the data.  If the depthstencil texture or rb is
 233     * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
 234     * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
 235     * MESA_FORMAT_Z24_UNORM_X8_UINT.
 236     *
 237     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
 238     * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
 239     *
 240     * @see RENDER_SURFACE_STATE.SurfaceFormat
 241     * @see 3DSTATE_DEPTH_BUFFER.SurfaceFormat
 242     */
 243    mesa_format format;
 244
 245    /**
 246     * This variable stores the value of ETC compressed texture format
 247     *
 248     * @see RENDER_SURFACE_STATE.SurfaceFormat
 249     */
 250    mesa_format etc_format;
 251
 252    GLuint first_level;
 253    GLuint last_level;
 254
 255    /** Bytes per pixel (or bytes per block if compressed) */
 256    GLuint cpp;
 257
 258    bool compressed;
 259
 260    /* Includes image offset tables: */
 261    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 262
 263    /**
 264     * Offset into bo where the surface starts.
 265     *
 266     * @see intel_mipmap_tree::bo
 267     *
 268     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 269     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 270     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 271     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 272     */
 273    uint32_t offset;
 274
 275    /**
 276     * \brief The type of auxiliary compression used by this miptree.
 277     *
 278     * This describes the type of auxiliary compression that is intended to be
 279     * used by this miptree.  An aux usage of ISL_AUX_USAGE_NONE means that
 280     * auxiliary compression is permanently disabled.  An aux usage other than
 281     * ISL_AUX_USAGE_NONE does not imply that the auxiliary buffer has actually
 282     * been allocated nor does it imply that auxiliary compression will always
 283     * be enabled for this surface.  For instance, with CCS_D, we may allocate
 284     * the CCS on-the-fly and it may not be used for texturing if the miptree
 285     * is fully resolved.
 286     */
 287    enum isl_aux_usage aux_usage;
 288
 289    /**
 290     * \brief Whether or not this miptree supports fast clears.
 291     */
 292    bool supports_fast_clear;
 293
 294    /**
 295     * \brief Maps miptree slices to their current aux state
 296     *
 297     * This two-dimensional array is indexed as [level][layer] and stores an
 298     * aux state for each slice.
 299     */
 300    enum isl_aux_state **aux_state;
 301
 302    /**
 303     * \brief Stencil miptree for depthstencil textures.
 304     *
 305     * This miptree is used for depthstencil textures and renderbuffers that
 306     * require separate stencil.  It always has the true copy of the stencil
 307     * bits, regardless of mt->format.
 308     *
 309     * \see 3DSTATE_STENCIL_BUFFER
 310     * \see intel_miptree_map_depthstencil()
 311     * \see intel_miptree_unmap_depthstencil()
 312     */
 313    struct intel_mipmap_tree *stencil_mt;
 314
 315    /**
 316     * \brief Stencil texturing miptree for sampling from a stencil texture
 317     *
 318     * Some hardware doesn't support sampling from the stencil texture as
 319     * required by the GL_ARB_stencil_texturing extenion. To workaround this we
 320     * blit the texture into a new texture that can be sampled.
 321     *
 322     * \see intel_update_r8stencil()
 323     */
 324    struct intel_mipmap_tree *r8stencil_mt;
 325    bool r8stencil_needs_update;
 326
 327    /**
 328     * \brief CCS, MCS, or HiZ auxiliary buffer.
 329     *
 330     * NULL if no auxiliary buffer is in use for this surface.
 331     *
 332     * For single-sampled color miptrees:
 333     *    This buffer contains the Color Control Surface, which stores the
 334     *    necessary information to implement lossless color compression (CCS_E)
 335     *    and "fast color clear" (CCS_D) behaviour.
 336     *
 337     * For multi-sampled color miptrees:
 338     *    This buffer contains the Multisample Control Surface, which stores the
 339     *    necessary information to implement compressed MSAA
 340     *    (INTEL_MSAA_FORMAT_CMS).
 341     *
 342     * For depth miptrees:
 343     *    This buffer contains the Hierarchical Depth Buffer, which stores the
 344     *    necessary information to implement lossless depth compression and fast
 345     *    depth clear behavior.
 346     *
 347     *    To determine if HiZ is enabled, do not check this pointer. Instead,
 348     *    use intel_miptree_level_has_hiz().
 349     */
 350    struct intel_miptree_aux_buffer *aux_buf;
 351
 352    /**
 353     * Planes 1 and 2 in case this is a planar surface.
 354     */
 355    struct intel_mipmap_tree *plane[2];
 356
 357    /**
 358     * Fast clear color for this surface.  For depth surfaces, the clear value
 359     * is stored as a float32 in the red component.
 360     */
 361    union isl_color_value fast_clear_color;
 362
 363    /**
 364     * For external surfaces, this is DRM format modifier that was used to
 365     * create or import the surface.  For internal surfaces, this will always
 366     * be DRM_FORMAT_MOD_INVALID.
 367     */
 368    uint64_t drm_modifier;
 369
 370    /* These are also refcounted:
 371     */
 372    GLuint refcount;
 373 };
 374
 375 bool
 376 intel_miptree_alloc_ccs(struct brw_context *brw,
 377                         struct intel_mipmap_tree *mt);
 378
 379 enum intel_miptree_create_flags {
 380    /** No miptree create flags */
 381    MIPTREE_CREATE_DEFAULT  = 0,
 382
 383    /** Miptree creation should try to allocate a currently busy BO
 384     *
 385     * This may be advantageous if we know the next thing to touch the BO will
 386     * be the GPU because the BO will likely already be in the GTT and maybe
 387     * even in some caches.  If there is a chance that the next thing to touch
 388     * the miptree BO will be the CPU, this flag should not be set.
 389     */
 390    MIPTREE_CREATE_BUSY     = 1 << 0,
 391
 392    /** Create a linear (not tiled) miptree */
 393    MIPTREE_CREATE_LINEAR   = 1 << 1,
 394
 395    /** Create the miptree with auxiliary compression disabled
 396     *
 397     * This does not prevent the caller of intel_miptree_create from coming
 398     * along later and turning auxiliary compression back on but it does mean
 399     * that the miptree will be created with mt->aux_usage == NONE.
 400     */
 401    MIPTREE_CREATE_NO_AUX   = 1 << 2,
 402 };
 403
 404 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
 405                                                GLenum target,
 406                                                mesa_format format,
 407                                                GLuint first_level,
 408                                                GLuint last_level,
 409                                                GLuint width0,
 410                                                GLuint height0,
 411                                                GLuint depth0,
 412                                                GLuint num_samples,
 413                                                enum intel_miptree_create_flags flags);
 414
 415 struct intel_mipmap_tree *
 416 intel_miptree_create_for_bo(struct brw_context *brw,
 417                             struct brw_bo *bo,
 418                             mesa_format format,
 419                             uint32_t offset,
 420                             uint32_t width,
 421                             uint32_t height,
 422                             uint32_t depth,
 423                             int pitch,
 424                             enum isl_tiling tiling,
 425                             enum intel_miptree_create_flags flags);
 426
 427 struct intel_mipmap_tree *
 428 intel_miptree_create_for_dri_image(struct brw_context *brw,
 429                                    __DRIimage *image,
 430                                    GLenum target,
 431                                    mesa_format format,
 432                                    bool is_winsys_image);
 433
 434 bool
 435 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
 436                                          struct intel_renderbuffer *irb,
 437                                          struct intel_mipmap_tree *singlesample_mt,
 438                                          uint32_t width, uint32_t height,
 439                                          uint32_t pitch);
 440
 441 /**
 442  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 443  * The miptree has the following properties:
 444  *     - The target is GL_TEXTURE_2D.
 445  *     - There are no levels other than the base level 0.
 446  *     - Depth is 1.
 447  */
 448 struct intel_mipmap_tree*
 449 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
 450                                       mesa_format format,
 451                                       uint32_t width,
 452                                       uint32_t height,
 453                                       uint32_t num_samples);
 454
 455 mesa_format
 456 intel_depth_format_for_depthstencil_format(mesa_format format);
 457
 458 mesa_format
 459 intel_lower_compressed_format(struct brw_context *brw, mesa_format format);
 460
 461 unsigned
 462 brw_get_num_logical_layers(const struct intel_mipmap_tree *mt, unsigned level);
 463
 464 /** \brief Assert that the level and layer are valid for the miptree. */
 465 void
 466 intel_miptree_check_level_layer(const struct intel_mipmap_tree *mt,
 467                                 uint32_t level,
 468                                 uint32_t layer);
 469
 470 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 471                              struct intel_mipmap_tree *src);
 472
 473 void intel_miptree_release(struct intel_mipmap_tree **mt);
 474
 475 /* Check if an image fits an existing mipmap tree layout
 476  */
 477 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 478                                     struct gl_texture_image *image);
 479
 480 void
 481 intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt,
 482                                GLuint level, GLuint slice,
 483                                GLuint *x, GLuint *y);
 484
 485 enum isl_surf_dim
 486 get_isl_surf_dim(GLenum target);
 487
 488 enum isl_dim_layout
 489 get_isl_dim_layout(const struct gen_device_info *devinfo,
 490                    enum isl_tiling tiling, GLenum target);
 491
 492 void
 493 intel_get_image_dims(struct gl_texture_image *image,
 494                      int *width, int *height, int *depth);
 495
 496 void
 497 intel_get_tile_masks(enum isl_tiling tiling, uint32_t cpp,
 498                      uint32_t *mask_x, uint32_t *mask_y);
 499
 500 void
 501 intel_get_tile_dims(enum isl_tiling tiling, uint32_t cpp,
 502                     uint32_t *tile_w, uint32_t *tile_h);
 503
 504 uint32_t
 505 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
 506                                GLuint level, GLuint slice,
 507                                uint32_t *tile_x,
 508                                uint32_t *tile_y);
 509 uint32_t
 510 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
 511                                  uint32_t x, uint32_t y);
 512
 513 void
 514 intel_miptree_copy_slice(struct brw_context *brw,
 515                          struct intel_mipmap_tree *src_mt,
 516                          unsigned src_level, unsigned src_layer,
 517                          struct intel_mipmap_tree *dst_mt,
 518                          unsigned dst_level, unsigned dst_layer);
 519
 520 void
 521 intel_miptree_copy_teximage(struct brw_context *brw,
 522                             struct intel_texture_image *intelImage,
 523                             struct intel_mipmap_tree *dst_mt);
 524
 525 /**
 526  * \name Miptree HiZ functions
 527  * \{
 528  *
 529  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 530  * functions on a miptree without HiZ. In that case, each function is a no-op.
 531  */
 532
 533 /**
 534  * \brief Allocate the miptree's embedded HiZ miptree.
 535  * \see intel_mipmap_tree:hiz_mt
 536  * \return false if allocation failed
 537  */
 538 bool
 539 intel_miptree_alloc_hiz(struct brw_context *brw,
 540                         struct intel_mipmap_tree *mt);
 541
 542 bool
 543 intel_miptree_level_has_hiz(const struct intel_mipmap_tree *mt, uint32_t level);
 544
 545 /**\}*/
 546
 547 bool
 548 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree *mt,
 549                                    unsigned start_level, unsigned num_levels,
 550                                    unsigned start_layer, unsigned num_layers);
 551
 552
 553 #define INTEL_REMAINING_LAYERS UINT32_MAX
 554 #define INTEL_REMAINING_LEVELS UINT32_MAX
 555
 556 /** Prepare a miptree for access
 557  *
 558  * This function should be called prior to any access to miptree in order to
 559  * perform any needed resolves.
 560  *
 561  * \param[in]  start_level    The first mip level to be accessed
 562  *
 563  * \param[in]  num_levels     The number of miplevels to be accessed or
 564  *                            INTEL_REMAINING_LEVELS to indicate every level
 565  *                            above start_level will be accessed
 566  *
 567  * \param[in]  start_layer    The first array slice or 3D layer to be accessed
 568  *
 569  * \param[in]  num_layers     The number of array slices or 3D layers be
 570  *                            accessed or INTEL_REMAINING_LAYERS to indicate
 571  *                            every layer above start_layer will be accessed
 572  *
 573  * \param[in]  aux_supported  Whether or not the access will support the
 574  *                            miptree's auxiliary compression format;  this
 575  *                            must be false for uncompressed miptrees
 576  *
 577  * \param[in]  fast_clear_supported Whether or not the access will support
 578  *                                  fast clears in the miptree's auxiliary
 579  *                                  compression format
 580  */
 581 void
 582 intel_miptree_prepare_access(struct brw_context *brw,
 583                              struct intel_mipmap_tree *mt,
 584                              uint32_t start_level, uint32_t num_levels,
 585                              uint32_t start_layer, uint32_t num_layers,
 586                              enum isl_aux_usage aux_usage,
 587                              bool fast_clear_supported);
 588
 589 /** Complete a write operation
 590  *
 591  * This function should be called after any operation writes to a miptree.
 592  * This will update the miptree's compression state so that future resolves
 593  * happen correctly.  Technically, this function can be called before the
 594  * write occurs but the caller must ensure that they don't interlace
 595  * intel_miptree_prepare_access and intel_miptree_finish_write calls to
 596  * overlapping layer/level ranges.
 597  *
 598  * \param[in]  level             The mip level that was written
 599  *
 600  * \param[in]  start_layer       The first array slice or 3D layer written
 601  *
 602  * \param[in]  num_layers        The number of array slices or 3D layers
 603  *                               written or INTEL_REMAINING_LAYERS to indicate
 604  *                               every layer above start_layer was written
 605  *
 606  * \param[in]  written_with_aux  Whether or not the write was done with
 607  *                               auxiliary compression enabled
 608  */
 609 void
 610 intel_miptree_finish_write(struct brw_context *brw,
 611                            struct intel_mipmap_tree *mt, uint32_t level,
 612                            uint32_t start_layer, uint32_t num_layers,
 613                            enum isl_aux_usage aux_usage);
 614
 615 /** Get the auxiliary compression state of a miptree slice */
 616 enum isl_aux_state
 617 intel_miptree_get_aux_state(const struct intel_mipmap_tree *mt,
 618                             uint32_t level, uint32_t layer);
 619
 620 /** Set the auxiliary compression state of a miptree slice range
 621  *
 622  * This function directly sets the auxiliary compression state of a slice
 623  * range of a miptree.  It only modifies data structures and does not do any
 624  * resolves.  This should only be called by code which directly performs
 625  * compression operations such as fast clears and resolves.  Most code should
 626  * use intel_miptree_prepare_access or intel_miptree_finish_write.
 627  */
 628 void
 629 intel_miptree_set_aux_state(struct brw_context *brw,
 630                             struct intel_mipmap_tree *mt, uint32_t level,
 631                             uint32_t start_layer, uint32_t num_layers,
 632                             enum isl_aux_state aux_state);
 633
 634 /**
 635  * Prepare a miptree for raw access
 636  *
 637  * This helper prepares the miptree for access that knows nothing about any
 638  * sort of compression whatsoever.  This is useful when mapping the surface or
 639  * using it with the blitter.
 640  */
 641 static inline void
 642 intel_miptree_access_raw(struct brw_context *brw,
 643                          struct intel_mipmap_tree *mt,
 644                          uint32_t level, uint32_t layer,
 645                          bool write)
 646 {
 647    intel_miptree_prepare_access(brw, mt, level, 1, layer, 1, false, false);
 648    if (write)
 649       intel_miptree_finish_write(brw, mt, level, layer, 1, false);
 650 }
 651
 652 enum isl_aux_usage
 653 intel_miptree_texture_aux_usage(struct brw_context *brw,
 654                                 struct intel_mipmap_tree *mt,
 655                                 enum isl_format view_format);
 656 void
 657 intel_miptree_prepare_texture(struct brw_context *brw,
 658                               struct intel_mipmap_tree *mt,
 659                               enum isl_format view_format,
 660                               uint32_t start_level, uint32_t num_levels,
 661                               uint32_t start_layer, uint32_t num_layers);
 662 void
 663 intel_miptree_prepare_image(struct brw_context *brw,
 664                             struct intel_mipmap_tree *mt);
 665
 666 enum isl_aux_usage
 667 intel_miptree_render_aux_usage(struct brw_context *brw,
 668                                struct intel_mipmap_tree *mt,
 669                                enum isl_format render_format,
 670                                bool blend_enabled,
 671                                bool draw_aux_disabled);
 672 void
 673 intel_miptree_prepare_render(struct brw_context *brw,
 674                              struct intel_mipmap_tree *mt, uint32_t level,
 675                              uint32_t start_layer, uint32_t layer_count,
 676                              enum isl_aux_usage aux_usage);
 677 void
 678 intel_miptree_finish_render(struct brw_context *brw,
 679                             struct intel_mipmap_tree *mt, uint32_t level,
 680                             uint32_t start_layer, uint32_t layer_count,
 681                             enum isl_aux_usage aux_usage);
 682 void
 683 intel_miptree_prepare_depth(struct brw_context *brw,
 684                             struct intel_mipmap_tree *mt, uint32_t level,
 685                             uint32_t start_layer, uint32_t layer_count);
 686 void
 687 intel_miptree_finish_depth(struct brw_context *brw,
 688                            struct intel_mipmap_tree *mt, uint32_t level,
 689                            uint32_t start_layer, uint32_t layer_count,
 690                            bool depth_written);
 691 void
 692 intel_miptree_prepare_external(struct brw_context *brw,
 693                                struct intel_mipmap_tree *mt);
 694 void
 695 intel_miptree_finish_external(struct brw_context *brw,
 696                               struct intel_mipmap_tree *mt);
 697
 698 void
 699 intel_miptree_make_shareable(struct brw_context *brw,
 700                              struct intel_mipmap_tree *mt);
 701
 702 void
 703 intel_miptree_updownsample(struct brw_context *brw,
 704                            struct intel_mipmap_tree *src,
 705                            struct intel_mipmap_tree *dst);
 706
 707 void
 708 intel_update_r8stencil(struct brw_context *brw,
 709                        struct intel_mipmap_tree *mt);
 710
 711 void
 712 intel_miptree_map(struct brw_context *brw,
 713                   struct intel_mipmap_tree *mt,
 714                   unsigned int level,
 715                   unsigned int slice,
 716                   unsigned int x,
 717                   unsigned int y,
 718                   unsigned int w,
 719                   unsigned int h,
 720                   GLbitfield mode,
 721                   void **out_ptr,
 722                   ptrdiff_t *out_stride);
 723
 724 void
 725 intel_miptree_unmap(struct brw_context *brw,
 726                     struct intel_mipmap_tree *mt,
 727                     unsigned int level,
 728                     unsigned int slice);
 729
 730 bool
 731 intel_miptree_sample_with_hiz(struct brw_context *brw,
 732                               struct intel_mipmap_tree *mt);
 733
 734 bool
 735 intel_miptree_set_clear_color(struct brw_context *brw,
 736                               struct intel_mipmap_tree *mt,
 737                               const union gl_color_union *color);
 738
 739 /* Get a clear color suitable for filling out an ISL surface state. */
 740 union isl_color_value
 741 intel_miptree_get_clear_color(const struct gen_device_info *devinfo,
 742                               const struct intel_mipmap_tree *mt,
 743                               enum isl_format view_format, bool sampling,
 744                               struct brw_bo **clear_color_bo,
 745                               uint32_t *clear_color_offset);
 746
 747 bool
 748 intel_miptree_set_depth_clear_value(struct brw_context *brw,
 749                                     struct intel_mipmap_tree *mt,
 750                                     float clear_value);
 751
 752 #ifdef __cplusplus
 753 }
 754 #endif
 755
 756 #endif