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26 /** @file intel_mipmap_tree.h
28 * This file defines the structure that wraps a BO and describes how the
29 * mipmap levels and slices of a texture are laid out.
31 * The hardware has a fixed layout of a texture depending on parameters such
32 * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
33 * mipmap levels. The individual level/layer slices are each 2D rectangles of
34 * pixels at some x/y offset from the start of the brw_bo.
36 * Original OpenGL allowed texture miplevels to be specified in arbitrary
37 * order, and a texture may change size over time. Thus, each
38 * intel_texture_image has a reference to a miptree that contains the pixel
39 * data sized appropriately for it, which will later be referenced by/copied
40 * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
41 * that there's a single miptree for the complete texture.
44 #ifndef INTEL_MIPMAP_TREE_H
45 #define INTEL_MIPMAP_TREE_H
49 #include "main/mtypes.h"
51 #include "blorp/blorp.h"
52 #include "brw_bufmgr.h"
53 #include "brw_context.h"
54 #include <GL/internal/dri_interface.h>
61 struct intel_renderbuffer
;
63 struct intel_texture_image
;
66 * This bit extends the set of GL_MAP_*_BIT enums.
68 * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
69 * depthstencil-split-to-separate-stencil miptree, we'll normally make a
70 * temporary and recreate the kind of data requested by Mesa core, since we're
71 * satisfying some glGetTexImage() request or something.
73 * However, occasionally you want to actually map the miptree's current data
74 * without transcoding back. This flag to intel_miptree_map() gets you that.
76 #define BRW_MAP_DIRECT_BIT 0x80000000
78 struct intel_miptree_map
{
79 /** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */
81 /** Region of interest for the map. */
83 /** Possibly malloced temporary buffer for the mapping. */
85 /** Possible pointer to a temporary linear miptree for the mapping. */
86 struct intel_mipmap_tree
*linear_mt
;
87 /** Pointer to the start of (map_x, map_y) returned by the mapping. */
89 /** Stride of the mapping. */
94 * Describes the location of each texture image within a miptree.
96 struct intel_mipmap_level
98 /** Offset to this miptree level, used in computing x_offset. */
100 /** Offset to this miptree level, used in computing y_offset. */
104 * \brief Is HiZ enabled for this level?
106 * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
107 * allocated and (2) the HiZ memory for the slices in this level reside at
108 * \c mt->hiz_mt->level[l].
113 * \brief List of 2D images in this mipmap level.
115 * This may be a list of cube faces, array slices in 2D array texture, or
116 * layers in a 3D texture. The list's length is \c depth.
118 struct intel_mipmap_slice
{
120 * Mapping information. Persistent for the duration of
121 * intel_miptree_map/unmap on this slice.
123 struct intel_miptree_map
*map
;
128 * Miptree aux buffer. These buffers are associated with a miptree, but the
129 * format is managed by the hardware.
131 * For Gen7+, we always give the hardware the start of the buffer, and let it
132 * handle all accesses to the buffer. Therefore we don't need the full miptree
133 * layout structure for this buffer.
135 struct intel_miptree_aux_buffer
137 struct isl_surf surf
;
140 * Buffer object containing the pixel data.
142 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
143 * @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
148 * Offset into bo where the surface starts.
150 * @see intel_mipmap_aux_buffer::bo
152 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
153 * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
154 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
155 * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
160 * Size of the MCS surface.
162 * This is needed when doing any gtt mapped operations on the buffer (which
163 * will be Y-tiled). It is possible that it will not be the same as bo->size
164 * when the drm allocator rounds up the requested size.
171 * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
172 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
177 * The distance in rows between array slices.
179 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch
180 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
185 struct intel_mipmap_tree
187 struct isl_surf surf
;
190 * Buffer object containing the surface.
192 * @see intel_mipmap_tree::offset
193 * @see RENDER_SURFACE_STATE.SurfaceBaseAddress
194 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
195 * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
196 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
197 * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
202 * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
204 * @see RENDER_SURFACE_STATE.SurfaceType
205 * @see RENDER_SURFACE_STATE.SurfaceArray
206 * @see 3DSTATE_DEPTH_BUFFER.SurfaceType
211 * Generally, this is just the same as the gl_texture_image->TexFormat or
212 * gl_renderbuffer->Format.
214 * However, for textures and renderbuffers with packed depth/stencil formats
215 * on hardware where we want or need to use separate stencil, there will be
216 * two miptrees for storing the data. If the depthstencil texture or rb is
217 * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
218 * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
219 * MESA_FORMAT_Z24_UNORM_X8_UINT.
221 * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
222 * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
224 * @see RENDER_SURFACE_STATE.SurfaceFormat
225 * @see 3DSTATE_DEPTH_BUFFER.SurfaceFormat
230 * This variable stores the value of ETC compressed texture format
232 * @see RENDER_SURFACE_STATE.SurfaceFormat
234 mesa_format etc_format
;
239 /** Bytes per pixel (or bytes per block if compressed) */
244 /* Includes image offset tables: */
245 struct intel_mipmap_level level
[MAX_TEXTURE_LEVELS
];
248 * Offset into bo where the surface starts.
250 * @see intel_mipmap_tree::bo
252 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
253 * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
254 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
255 * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
260 * \brief HiZ aux buffer
262 * To allocate the hiz buffer, use intel_miptree_alloc_hiz().
264 * To determine if hiz is enabled, do not check this pointer. Instead, use
265 * intel_miptree_level_has_hiz().
267 struct intel_miptree_aux_buffer
*hiz_buf
;
270 * \brief The type of auxiliary compression used by this miptree.
272 * This describes the type of auxiliary compression that is intended to be
273 * used by this miptree. An aux usage of ISL_AUX_USAGE_NONE means that
274 * auxiliary compression is permanently disabled. An aux usage other than
275 * ISL_AUX_USAGE_NONE does not imply that the auxiliary buffer has actually
276 * been allocated nor does it imply that auxiliary compression will always
277 * be enabled for this surface. For instance, with CCS_D, we may allocate
278 * the CCS on-the-fly and it may not be used for texturing if the miptree
281 enum isl_aux_usage aux_usage
;
284 * \brief Whether or not this miptree supports fast clears.
286 bool supports_fast_clear
;
289 * \brief Maps miptree slices to their current aux state
291 * This two-dimensional array is indexed as [level][layer] and stores an
292 * aux state for each slice.
294 enum isl_aux_state
**aux_state
;
297 * \brief Stencil miptree for depthstencil textures.
299 * This miptree is used for depthstencil textures and renderbuffers that
300 * require separate stencil. It always has the true copy of the stencil
301 * bits, regardless of mt->format.
303 * \see 3DSTATE_STENCIL_BUFFER
304 * \see intel_miptree_map_depthstencil()
305 * \see intel_miptree_unmap_depthstencil()
307 struct intel_mipmap_tree
*stencil_mt
;
310 * \brief Stencil texturing miptree for sampling from a stencil texture
312 * Some hardware doesn't support sampling from the stencil texture as
313 * required by the GL_ARB_stencil_texturing extenion. To workaround this we
314 * blit the texture into a new texture that can be sampled.
316 * \see intel_update_r8stencil()
318 struct intel_mipmap_tree
*r8stencil_mt
;
319 bool r8stencil_needs_update
;
322 * \brief MCS auxiliary buffer.
324 * This buffer contains the "multisample control surface", which stores
325 * the necessary information to implement compressed MSAA
326 * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
328 * NULL if no MCS buffer is in use for this surface.
330 struct intel_miptree_aux_buffer
*mcs_buf
;
333 * Planes 1 and 2 in case this is a planar surface.
335 struct intel_mipmap_tree
*plane
[2];
338 * Fast clear color for this surface. For depth surfaces, the clear value
339 * is stored as a float32 in the red component.
341 union isl_color_value fast_clear_color
;
344 * For external surfaces, this is DRM format modifier that was used to
345 * create or import the surface. For internal surfaces, this will always
346 * be DRM_FORMAT_MOD_INVALID.
348 uint64_t drm_modifier
;
350 /* These are also refcounted:
356 intel_miptree_alloc_ccs(struct brw_context
*brw
,
357 struct intel_mipmap_tree
*mt
);
359 enum intel_miptree_create_flags
{
360 /** No miptree create flags */
361 MIPTREE_CREATE_DEFAULT
= 0,
363 /** Miptree creation should try to allocate a currently busy BO
365 * This may be advantageous if we know the next thing to touch the BO will
366 * be the GPU because the BO will likely already be in the GTT and maybe
367 * even in some caches. If there is a chance that the next thing to touch
368 * the miptree BO will be the CPU, this flag should not be set.
370 MIPTREE_CREATE_BUSY
= 1 << 0,
372 /** Create a linear (not tiled) miptree */
373 MIPTREE_CREATE_LINEAR
= 1 << 1,
375 /** Create the miptree with auxiliary compression disabled
377 * This does not prevent the caller of intel_miptree_create from coming
378 * along later and turning auxiliary compression back on but it does mean
379 * that the miptree will be created with mt->aux_usage == NONE.
381 MIPTREE_CREATE_NO_AUX
= 1 << 2,
384 struct intel_mipmap_tree
*intel_miptree_create(struct brw_context
*brw
,
393 enum intel_miptree_create_flags flags
);
395 struct intel_mipmap_tree
*
396 intel_miptree_create_for_bo(struct brw_context
*brw
,
404 enum intel_miptree_create_flags flags
);
406 struct intel_mipmap_tree
*
407 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
410 enum isl_colorspace colorspace
,
411 bool is_winsys_image
);
414 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
415 struct intel_renderbuffer
*irb
,
416 struct intel_mipmap_tree
*singlesample_mt
,
417 uint32_t width
, uint32_t height
,
421 * Create a miptree appropriate as the storage for a non-texture renderbuffer.
422 * The miptree has the following properties:
423 * - The target is GL_TEXTURE_2D.
424 * - There are no levels other than the base level 0.
427 struct intel_mipmap_tree
*
428 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
432 uint32_t num_samples
);
435 intel_depth_format_for_depthstencil_format(mesa_format format
);
438 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
);
441 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
);
443 /** \brief Assert that the level and layer are valid for the miptree. */
445 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
449 void intel_miptree_reference(struct intel_mipmap_tree
**dst
,
450 struct intel_mipmap_tree
*src
);
452 void intel_miptree_release(struct intel_mipmap_tree
**mt
);
454 /* Check if an image fits an existing mipmap tree layout
456 bool intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
457 struct gl_texture_image
*image
);
460 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
461 GLuint level
, GLuint slice
,
462 GLuint
*x
, GLuint
*y
);
465 get_isl_surf_dim(GLenum target
);
468 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
469 enum isl_tiling tiling
, GLenum target
);
472 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
473 const struct intel_mipmap_tree
*mt
);
476 intel_get_image_dims(struct gl_texture_image
*image
,
477 int *width
, int *height
, int *depth
);
480 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
481 uint32_t *mask_x
, uint32_t *mask_y
);
484 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
485 uint32_t *tile_w
, uint32_t *tile_h
);
488 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
489 GLuint level
, GLuint slice
,
493 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
494 uint32_t x
, uint32_t y
);
497 intel_miptree_copy_slice(struct brw_context
*brw
,
498 struct intel_mipmap_tree
*src_mt
,
499 unsigned src_level
, unsigned src_layer
,
500 struct intel_mipmap_tree
*dst_mt
,
501 unsigned dst_level
, unsigned dst_layer
);
504 intel_miptree_copy_teximage(struct brw_context
*brw
,
505 struct intel_texture_image
*intelImage
,
506 struct intel_mipmap_tree
*dst_mt
, bool invalidate
);
509 * \name Miptree HiZ functions
512 * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
513 * functions on a miptree without HiZ. In that case, each function is a no-op.
517 * \brief Allocate the miptree's embedded HiZ miptree.
518 * \see intel_mipmap_tree:hiz_mt
519 * \return false if allocation failed
522 intel_miptree_alloc_hiz(struct brw_context
*brw
,
523 struct intel_mipmap_tree
*mt
);
526 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
);
531 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
532 unsigned start_level
, unsigned num_levels
,
533 unsigned start_layer
, unsigned num_layers
);
536 #define INTEL_REMAINING_LAYERS UINT32_MAX
537 #define INTEL_REMAINING_LEVELS UINT32_MAX
539 /** Prepare a miptree for access
541 * This function should be called prior to any access to miptree in order to
542 * perform any needed resolves.
544 * \param[in] start_level The first mip level to be accessed
546 * \param[in] num_levels The number of miplevels to be accessed or
547 * INTEL_REMAINING_LEVELS to indicate every level
548 * above start_level will be accessed
550 * \param[in] start_layer The first array slice or 3D layer to be accessed
552 * \param[in] num_layers The number of array slices or 3D layers be
553 * accessed or INTEL_REMAINING_LAYERS to indicate
554 * every layer above start_layer will be accessed
556 * \param[in] aux_supported Whether or not the access will support the
557 * miptree's auxiliary compression format; this
558 * must be false for uncompressed miptrees
560 * \param[in] fast_clear_supported Whether or not the access will support
561 * fast clears in the miptree's auxiliary
565 intel_miptree_prepare_access(struct brw_context
*brw
,
566 struct intel_mipmap_tree
*mt
,
567 uint32_t start_level
, uint32_t num_levels
,
568 uint32_t start_layer
, uint32_t num_layers
,
569 enum isl_aux_usage aux_usage
,
570 bool fast_clear_supported
);
572 /** Complete a write operation
574 * This function should be called after any operation writes to a miptree.
575 * This will update the miptree's compression state so that future resolves
576 * happen correctly. Technically, this function can be called before the
577 * write occurs but the caller must ensure that they don't interlace
578 * intel_miptree_prepare_access and intel_miptree_finish_write calls to
579 * overlapping layer/level ranges.
581 * \param[in] level The mip level that was written
583 * \param[in] start_layer The first array slice or 3D layer written
585 * \param[in] num_layers The number of array slices or 3D layers
586 * written or INTEL_REMAINING_LAYERS to indicate
587 * every layer above start_layer was written
589 * \param[in] written_with_aux Whether or not the write was done with
590 * auxiliary compression enabled
593 intel_miptree_finish_write(struct brw_context
*brw
,
594 struct intel_mipmap_tree
*mt
, uint32_t level
,
595 uint32_t start_layer
, uint32_t num_layers
,
596 enum isl_aux_usage aux_usage
);
598 /** Get the auxiliary compression state of a miptree slice */
600 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
601 uint32_t level
, uint32_t layer
);
603 /** Set the auxiliary compression state of a miptree slice range
605 * This function directly sets the auxiliary compression state of a slice
606 * range of a miptree. It only modifies data structures and does not do any
607 * resolves. This should only be called by code which directly performs
608 * compression operations such as fast clears and resolves. Most code should
609 * use intel_miptree_prepare_access or intel_miptree_finish_write.
612 intel_miptree_set_aux_state(struct brw_context
*brw
,
613 struct intel_mipmap_tree
*mt
, uint32_t level
,
614 uint32_t start_layer
, uint32_t num_layers
,
615 enum isl_aux_state aux_state
);
618 * Prepare a miptree for raw access
620 * This helper prepares the miptree for access that knows nothing about any
621 * sort of compression whatsoever. This is useful when mapping the surface or
622 * using it with the blitter.
625 intel_miptree_access_raw(struct brw_context
*brw
,
626 struct intel_mipmap_tree
*mt
,
627 uint32_t level
, uint32_t layer
,
630 intel_miptree_prepare_access(brw
, mt
, level
, 1, layer
, 1, false, false);
632 intel_miptree_finish_write(brw
, mt
, level
, layer
, 1, false);
636 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
637 struct intel_mipmap_tree
*mt
,
638 enum isl_format view_format
);
640 intel_miptree_prepare_texture(struct brw_context
*brw
,
641 struct intel_mipmap_tree
*mt
,
642 enum isl_format view_format
,
643 bool *aux_supported_out
);
645 intel_miptree_prepare_image(struct brw_context
*brw
,
646 struct intel_mipmap_tree
*mt
);
648 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
649 struct intel_mipmap_tree
*mt
, uint32_t level
,
650 uint32_t start_layer
, uint32_t num_layers
);
652 intel_miptree_render_aux_usage(struct brw_context
*brw
,
653 struct intel_mipmap_tree
*mt
,
654 bool srgb_enabled
, bool blend_enabled
);
656 intel_miptree_prepare_render(struct brw_context
*brw
,
657 struct intel_mipmap_tree
*mt
, uint32_t level
,
658 uint32_t start_layer
, uint32_t layer_count
,
659 bool srgb_enabled
, bool blend_enabled
);
661 intel_miptree_finish_render(struct brw_context
*brw
,
662 struct intel_mipmap_tree
*mt
, uint32_t level
,
663 uint32_t start_layer
, uint32_t layer_count
,
664 bool srgb_enabled
, bool blend_enabled
);
666 intel_miptree_prepare_depth(struct brw_context
*brw
,
667 struct intel_mipmap_tree
*mt
, uint32_t level
,
668 uint32_t start_layer
, uint32_t layer_count
);
670 intel_miptree_finish_depth(struct brw_context
*brw
,
671 struct intel_mipmap_tree
*mt
, uint32_t level
,
672 uint32_t start_layer
, uint32_t layer_count
,
675 intel_miptree_prepare_external(struct brw_context
*brw
,
676 struct intel_mipmap_tree
*mt
);
679 intel_miptree_make_shareable(struct brw_context
*brw
,
680 struct intel_mipmap_tree
*mt
);
683 intel_miptree_updownsample(struct brw_context
*brw
,
684 struct intel_mipmap_tree
*src
,
685 struct intel_mipmap_tree
*dst
);
688 intel_update_r8stencil(struct brw_context
*brw
,
689 struct intel_mipmap_tree
*mt
);
692 intel_miptree_map(struct brw_context
*brw
,
693 struct intel_mipmap_tree
*mt
,
702 ptrdiff_t *out_stride
);
705 intel_miptree_unmap(struct brw_context
*brw
,
706 struct intel_mipmap_tree
*mt
,
711 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
712 struct intel_mipmap_tree
*mt
);
716 intel_miptree_set_clear_color(struct gl_context
*ctx
,
717 struct intel_mipmap_tree
*mt
,
718 union isl_color_value clear_color
)
720 if (memcmp(&mt
->fast_clear_color
, &clear_color
, sizeof(clear_color
)) != 0) {
721 mt
->fast_clear_color
= clear_color
;
722 ctx
->NewDriverState
|= BRW_NEW_AUX_STATE
;
729 intel_miptree_set_depth_clear_value(struct gl_context
*ctx
,
730 struct intel_mipmap_tree
*mt
,
733 if (mt
->fast_clear_color
.f32
[0] != clear_value
) {
734 mt
->fast_clear_color
.f32
[0] = clear_value
;
735 ctx
->NewDriverState
|= BRW_NEW_AUX_STATE
;