src/mesa/drivers/dri/i965/intel_mipmap_tree.h

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  27
  28 #ifndef INTEL_MIPMAP_TREE_H
  29 #define INTEL_MIPMAP_TREE_H
  30
  31 #include <assert.h>
  32
  33 #include "intel_regions.h"
  34 #include "intel_resolve_map.h"
  35 #include <GL/internal/dri_interface.h>
  36
  37 #ifdef __cplusplus
  38 extern "C" {
  39 #endif
  40
  41 /* A layer on top of the intel_regions code which adds:
  42  *
  43  * - Code to size and layout a region to hold a set of mipmaps.
  44  * - Query to determine if a new image fits in an existing tree.
  45  * - More refcounting
  46  *     - maybe able to remove refcounting from intel_region?
  47  * - ?
  48  *
  49  * The fixed mipmap layout of intel hardware where one offset
  50  * specifies the position of all images in a mipmap hierachy
  51  * complicates the implementation of GL texture image commands,
  52  * compared to hardware where each image is specified with an
  53  * independent offset.
  54  *
  55  * In an ideal world, each texture object would be associated with a
  56  * single bufmgr buffer or 2d intel_region, and all the images within
  57  * the texture object would slot into the tree as they arrive.  The
  58  * reality can be a little messier, as images can arrive from the user
  59  * with sizes that don't fit in the existing tree, or in an order
  60  * where the tree layout cannot be guessed immediately.
  61  *
  62  * This structure encodes an idealized mipmap tree.  The GL image
  63  * commands build these where possible, otherwise store the images in
  64  * temporary system buffers.
  65  */
  66
  67 struct intel_resolve_map;
  68 struct intel_texture_image;
  69
  70 /**
  71  * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
  72  * depthstencil-split-to-separate-stencil miptree, we'll normally make a
  73  * tmeporary and recreate the kind of data requested by Mesa core, since we're
  74  * satisfying some glGetTexImage() request or something.
  75  *
  76  * However, occasionally you want to actually map the miptree's current data
  77  * without transcoding back.  This flag to intel_miptree_map() gets you that.
  78  */
  79 #define BRW_MAP_DIRECT_BIT      0x80000000
  80
  81 struct intel_miptree_map {
  82    /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
  83    GLbitfield mode;
  84    /** Region of interest for the map. */
  85    int x, y, w, h;
  86    /** Possibly malloced temporary buffer for the mapping. */
  87    void *buffer;
  88    /** Possible pointer to a temporary linear miptree for the mapping. */
  89    struct intel_mipmap_tree *mt;
  90    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  91    void *ptr;
  92    /** Stride of the mapping. */
  93    int stride;
  94
  95    /**
  96     * intel_mipmap_tree::singlesample_mt is temporary storage that persists
  97     * only for the duration of the map.
  98     */
  99    bool singlesample_mt_is_tmp;
 100 };
 101
 102 /**
 103  * Describes the location of each texture image within a texture region.
 104  */
 105 struct intel_mipmap_level
 106 {
 107    /** Offset to this miptree level, used in computing x_offset. */
 108    GLuint level_x;
 109    /** Offset to this miptree level, used in computing y_offset. */
 110    GLuint level_y;
 111    GLuint width;
 112    GLuint height;
 113
 114    /**
 115     * \brief Number of 2D slices in this miplevel.
 116     *
 117     * The exact semantics of depth varies according to the texture target:
 118     *    - For GL_TEXTURE_CUBE_MAP, depth is 6.
 119     *    - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
 120     *      identical for all miplevels in the texture.
 121     *    - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
 122     *      value, like width and height, varies with miplevel.
 123     *    - For other texture types, depth is 1.
 124     */
 125    GLuint depth;
 126
 127    /**
 128     * \brief List of 2D images in this mipmap level.
 129     *
 130     * This may be a list of cube faces, array slices in 2D array texture, or
 131     * layers in a 3D texture. The list's length is \c depth.
 132     */
 133    struct intel_mipmap_slice {
 134       /**
 135        * \name Offset to slice
 136        * \{
 137        *
 138        * Hardware formats are so diverse that that there is no unified way to
 139        * compute the slice offsets, so we store them in this table.
 140        *
 141        * The (x, y) offset to slice \c s at level \c l relative the miptrees
 142        * base address is
 143        * \code
 144        *     x = mt->level[l].slice[s].x_offset
 145        *     y = mt->level[l].slice[s].y_offset
 146        */
 147       GLuint x_offset;
 148       GLuint y_offset;
 149       /** \} */
 150
 151       /**
 152        * Mapping information. Persistent for the duration of
 153        * intel_miptree_map/unmap on this slice.
 154        */
 155       struct intel_miptree_map *map;
 156
 157       /**
 158        * \brief Is HiZ enabled for this slice?
 159        *
 160        * If \c mt->level[l].slice[s].has_hiz is set, then (1) \c mt->hiz_mt
 161        * has been allocated and (2) the HiZ memory corresponding to this slice
 162        * resides at \c mt->hiz_mt->level[l].slice[s].
 163        */
 164       bool has_hiz;
 165    } *slice;
 166 };
 167
 168 /**
 169  * Enum for keeping track of the different MSAA layouts supported by Gen7.
 170  */
 171 enum intel_msaa_layout
 172 {
 173    /**
 174     * Ordinary surface with no MSAA.
 175     */
 176    INTEL_MSAA_LAYOUT_NONE,
 177
 178    /**
 179     * Interleaved Multisample Surface.  The additional samples are
 180     * accommodated by scaling up the width and the height of the surface so
 181     * that all the samples corresponding to a pixel are located at nearby
 182     * memory locations.
 183     */
 184    INTEL_MSAA_LAYOUT_IMS,
 185
 186    /**
 187     * Uncompressed Multisample Surface.  The surface is stored as a 2D array,
 188     * with array slice n containing all pixel data for sample n.
 189     */
 190    INTEL_MSAA_LAYOUT_UMS,
 191
 192    /**
 193     * Compressed Multisample Surface.  The surface is stored as in
 194     * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
 195     * (Multisample Control Surface) buffer.  Each pixel in the MCS buffer
 196     * indicates the mapping from sample number to array slice.  This allows
 197     * the common case (where all samples constituting a pixel have the same
 198     * color value) to be stored efficiently by just using a single array
 199     * slice.
 200     */
 201    INTEL_MSAA_LAYOUT_CMS,
 202 };
 203
 204
 205 /**
 206  * Enum for keeping track of the fast clear state of a buffer associated with
 207  * a miptree.
 208  *
 209  * Fast clear works by deferring the memory writes that would be used to clear
 210  * the buffer, so that instead of performing them at the time of the clear
 211  * operation, the hardware automatically performs them at the time that the
 212  * buffer is later accessed for rendering.  The MCS buffer keeps track of
 213  * which regions of the buffer still have pending clear writes.
 214  *
 215  * This enum keeps track of the driver's knowledge of pending fast clears in
 216  * the MCS buffer.
 217  *
 218  * MCS buffers only exist on Gen7+.
 219  */
 220 enum intel_fast_clear_state
 221 {
 222    /**
 223     * There is no MCS buffer for this miptree, and one should never be
 224     * allocated.
 225     */
 226    INTEL_FAST_CLEAR_STATE_NO_MCS,
 227
 228    /**
 229     * No deferred clears are pending for this miptree, and the contents of the
 230     * color buffer are entirely correct.  An MCS buffer may or may not exist
 231     * for this miptree.  If it does exist, it is entirely in the "no deferred
 232     * clears pending" state.  If it does not exist, it will be created the
 233     * first time a fast color clear is executed.
 234     *
 235     * In this state, the color buffer can be used for purposes other than
 236     * rendering without needing a render target resolve.
 237     *
 238     * Since there is no such thing as a "fast color clear resolve" for MSAA
 239     * buffers, an MSAA buffer will never be in this state.
 240     */
 241    INTEL_FAST_CLEAR_STATE_RESOLVED,
 242
 243    /**
 244     * An MCS buffer exists for this miptree, and deferred clears are pending
 245     * for some regions of the color buffer, as indicated by the MCS buffer.
 246     * The contents of the color buffer are only correct for the regions where
 247     * the MCS buffer doesn't indicate a deferred clear.
 248     *
 249     * If a single-sample buffer is in this state, a render target resolve must
 250     * be performed before it can be used for purposes other than rendering.
 251     */
 252    INTEL_FAST_CLEAR_STATE_UNRESOLVED,
 253
 254    /**
 255     * An MCS buffer exists for this miptree, and deferred clears are pending
 256     * for the entire color buffer, and the contents of the MCS buffer reflect
 257     * this.  The contents of the color buffer are undefined.
 258     *
 259     * If a single-sample buffer is in this state, a render target resolve must
 260     * be performed before it can be used for purposes other than rendering.
 261     *
 262     * If the client attempts to clear a buffer which is already in this state,
 263     * the clear can be safely skipped, since the buffer is already clear.
 264     */
 265    INTEL_FAST_CLEAR_STATE_CLEAR,
 266 };
 267
 268 struct intel_mipmap_tree
 269 {
 270    /* Effectively the key:
 271     */
 272    GLenum target;
 273
 274    /**
 275     * Generally, this is just the same as the gl_texture_image->TexFormat or
 276     * gl_renderbuffer->Format.
 277     *
 278     * However, for textures and renderbuffers with packed depth/stencil formats
 279     * on hardware where we want or need to use separate stencil, there will be
 280     * two miptrees for storing the data.  If the depthstencil texture or rb is
 281     * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
 282     * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
 283     * MESA_FORMAT_Z24_UNORM_X8_UINT.
 284     *
 285     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
 286     * formats if the hardware lacks support for ETC1/ETC2. See @ref wraps_etc.
 287     */
 288    mesa_format format;
 289
 290    /** This variable stores the value of ETC compressed texture format */
 291    mesa_format etc_format;
 292
 293    /**
 294     * The X offset of each image in the miptree must be aligned to this.
 295     * See the comments in brw_tex_layout.c.
 296     */
 297    unsigned int align_w;
 298    unsigned int align_h; /**< \see align_w */
 299
 300    GLuint first_level;
 301    GLuint last_level;
 302
 303    /**
 304     * Level zero image dimensions.  These dimensions correspond to the
 305     * physical layout of data in memory.  Accordingly, they account for the
 306     * extra width, height, and or depth that must be allocated in order to
 307     * accommodate multisample formats, and they account for the extra factor
 308     * of 6 in depth that must be allocated in order to accommodate cubemap
 309     * textures.
 310     */
 311    GLuint physical_width0, physical_height0, physical_depth0;
 312
 313    GLuint cpp;
 314    GLuint num_samples;
 315    bool compressed;
 316
 317    /**
 318     * Level zero image dimensions.  These dimensions correspond to the
 319     * logical width, height, and depth of the region as seen by client code.
 320     * Accordingly, they do not account for the extra width, height, and/or
 321     * depth that must be allocated in order to accommodate multisample
 322     * formats, nor do they account for the extra factor of 6 in depth that
 323     * must be allocated in order to accommodate cubemap textures.
 324     */
 325    uint32_t logical_width0, logical_height0, logical_depth0;
 326
 327    /**
 328     * For 1D array, 2D array, cube, and 2D multisampled surfaces on Gen7: true
 329     * if the surface only contains LOD 0, and hence no space is for LOD's
 330     * other than 0 in between array slices.
 331     *
 332     * Corresponds to the surface_array_spacing bit in gen7_surface_state.
 333     */
 334    bool array_spacing_lod0;
 335
 336    /**
 337     * The distance in rows between array slices in an uncompressed surface.
 338     *
 339     * For compressed surfaces, slices are stored closer together physically;
 340     * the real distance is (qpitch / block height).
 341     */
 342    uint32_t qpitch;
 343
 344    /**
 345     * MSAA layout used by this buffer.
 346     */
 347    enum intel_msaa_layout msaa_layout;
 348
 349    /* Derived from the above:
 350     */
 351    GLuint total_width;
 352    GLuint total_height;
 353
 354    /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to
 355     * this depth mipmap tree, if any.
 356     */
 357    uint32_t depth_clear_value;
 358
 359    /* Includes image offset tables:
 360     */
 361    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 362
 363    /* The data is held here:
 364     */
 365    struct intel_region *region;
 366
 367    /* Offset into region bo where miptree starts:
 368     */
 369    uint32_t offset;
 370
 371    /**
 372     * \brief Singlesample miptree.
 373     *
 374     * This is used under two cases.
 375     *
 376     * --- Case 1: As persistent singlesample storage for multisample window
 377     *  system front and back buffers ---
 378     *
 379     * Suppose that the window system FBO was created with a multisample
 380     * config.  Let `back_irb` be the `intel_renderbuffer` for the FBO's back
 381     * buffer. Then `back_irb` contains two miptrees: a parent multisample
 382     * miptree (back_irb->mt) and a child singlesample miptree
 383     * (back_irb->mt->singlesample_mt).  The DRM buffer shared with DRI2
 384     * belongs to `back_irb->mt->singlesample_mt` and contains singlesample
 385     * data.  The singlesample miptree is created at the same time as and
 386     * persists for the lifetime of its parent multisample miptree.
 387     *
 388     * When access to the singlesample data is needed, such as at
 389     * eglSwapBuffers and glReadPixels, an automatic downsample occurs from
 390     * `back_rb->mt` to `back_rb->mt->singlesample_mt` when necessary.
 391     *
 392     * This description of the back buffer applies analogously to the front
 393     * buffer.
 394     *
 395     *
 396     * --- Case 2: As temporary singlesample storage for mapping multisample
 397     *  miptrees ---
 398     *
 399     * Suppose the intel_miptree_map is called on a multisample miptree, `mt`,
 400     * for which case 1 does not apply (that is, `mt` does not belong to
 401     * a front or back buffer).  Then `mt->singlesample_mt` is null at the
 402     * start of the call. intel_miptree_map will create a temporary
 403     * singlesample miptree, store it at `mt->singlesample_mt`, downsample from
 404     * `mt` to `mt->singlesample_mt` if necessary, then map
 405     * `mt->singlesample_mt`. The temporary miptree is later deleted during
 406     * intel_miptree_unmap.
 407     */
 408    struct intel_mipmap_tree *singlesample_mt;
 409
 410    /**
 411     * \brief A downsample is needed from this miptree to singlesample_mt.
 412     */
 413    bool need_downsample;
 414
 415    /**
 416     * \brief HiZ miptree
 417     *
 418     * The hiz miptree contains the miptree's hiz buffer. To allocate the hiz
 419     * miptree, use intel_miptree_alloc_hiz().
 420     *
 421     * To determine if hiz is enabled, do not check this pointer. Instead, use
 422     * intel_miptree_slice_has_hiz().
 423     */
 424    struct intel_mipmap_tree *hiz_mt;
 425
 426    /**
 427     * \brief Map of miptree slices to needed resolves.
 428     *
 429     * This is used only when the miptree has a child HiZ miptree.
 430     *
 431     * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
 432     * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
 433     * mt->hiz_mt->hiz_map, is unused.
 434     */
 435    struct intel_resolve_map hiz_map;
 436
 437    /**
 438     * \brief Stencil miptree for depthstencil textures.
 439     *
 440     * This miptree is used for depthstencil textures and renderbuffers that
 441     * require separate stencil.  It always has the true copy of the stencil
 442     * bits, regardless of mt->format.
 443     *
 444     * \see intel_miptree_map_depthstencil()
 445     * \see intel_miptree_unmap_depthstencil()
 446     */
 447    struct intel_mipmap_tree *stencil_mt;
 448
 449    /**
 450     * \brief MCS miptree.
 451     *
 452     * This miptree contains the "multisample control surface", which stores
 453     * the necessary information to implement compressed MSAA
 454     * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
 455     *
 456     * NULL if no MCS miptree is in use for this surface.
 457     */
 458    struct intel_mipmap_tree *mcs_mt;
 459
 460    /**
 461     * Fast clear state for this buffer.
 462     */
 463    enum intel_fast_clear_state fast_clear_state;
 464
 465    /**
 466     * The SURFACE_STATE bits associated with the last fast color clear to this
 467     * color mipmap tree, if any.
 468     *
 469     * This value will only ever contain ones in bits 28-31, so it is safe to
 470     * OR into dword 7 of SURFACE_STATE.
 471     */
 472    uint32_t fast_clear_color_value;
 473
 474    /* These are also refcounted:
 475     */
 476    GLuint refcount;
 477 };
 478
 479 enum intel_miptree_tiling_mode {
 480    INTEL_MIPTREE_TILING_ANY,
 481    INTEL_MIPTREE_TILING_Y,
 482    INTEL_MIPTREE_TILING_NONE,
 483 };
 484
 485 bool
 486 intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
 487                                        struct intel_mipmap_tree *mt);
 488
 489 void
 490 intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
 491                                  struct intel_mipmap_tree *mt,
 492                                  unsigned *width_px, unsigned *height);
 493
 494 bool
 495 intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
 496                                  struct intel_mipmap_tree *mt);
 497
 498 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
 499                                                GLenum target,
 500                                                mesa_format format,
 501                                                GLuint first_level,
 502                                                GLuint last_level,
 503                                                GLuint width0,
 504                                                GLuint height0,
 505                                                GLuint depth0,
 506                                                bool expect_accelerated_upload,
 507                                                GLuint num_samples,
 508                                                enum intel_miptree_tiling_mode);
 509
 510 struct intel_mipmap_tree *
 511 intel_miptree_create_layout(struct brw_context *brw,
 512                             GLenum target,
 513                             mesa_format format,
 514                             GLuint first_level,
 515                             GLuint last_level,
 516                             GLuint width0,
 517                             GLuint height0,
 518                             GLuint depth0,
 519                             bool for_bo,
 520                             GLuint num_samples);
 521
 522 struct intel_mipmap_tree *
 523 intel_miptree_create_for_bo(struct brw_context *brw,
 524                             drm_intel_bo *bo,
 525                             mesa_format format,
 526                             uint32_t offset,
 527                             uint32_t width,
 528                             uint32_t height,
 529                             int pitch,
 530                             uint32_t tiling);
 531
 532 struct intel_mipmap_tree*
 533 intel_miptree_create_for_dri2_buffer(struct brw_context *brw,
 534                                      unsigned dri_attachment,
 535                                      mesa_format format,
 536                                      uint32_t num_samples,
 537                                      struct intel_region *region);
 538
 539 struct intel_mipmap_tree*
 540 intel_miptree_create_for_image_buffer(struct brw_context *intel,
 541                                      enum __DRIimageBufferMask buffer_type,
 542                                      mesa_format format,
 543                                      uint32_t num_samples,
 544                                      struct intel_region *region);
 545
 546 /**
 547  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 548  * The miptree has the following properties:
 549  *     - The target is GL_TEXTURE_2D.
 550  *     - There are no levels other than the base level 0.
 551  *     - Depth is 1.
 552  */
 553 struct intel_mipmap_tree*
 554 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
 555                                       mesa_format format,
 556                                       uint32_t width,
 557                                       uint32_t height,
 558                                       uint32_t num_samples);
 559
 560 /** \brief Assert that the level and layer are valid for the miptree. */
 561 static inline void
 562 intel_miptree_check_level_layer(struct intel_mipmap_tree *mt,
 563                                 uint32_t level,
 564                                 uint32_t layer)
 565 {
 566    assert(level >= mt->first_level);
 567    assert(level <= mt->last_level);
 568    assert(layer < mt->level[level].depth);
 569 }
 570
 571 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 572                              struct intel_mipmap_tree *src);
 573
 574 void intel_miptree_release(struct intel_mipmap_tree **mt);
 575
 576 /* Check if an image fits an existing mipmap tree layout
 577  */
 578 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 579                                     struct gl_texture_image *image);
 580
 581 void
 582 intel_miptree_get_image_offset(struct intel_mipmap_tree *mt,
 583                                GLuint level, GLuint slice,
 584                                GLuint *x, GLuint *y);
 585
 586 void
 587 intel_miptree_get_dimensions_for_image(struct gl_texture_image *image,
 588                                        int *width, int *height, int *depth);
 589
 590 uint32_t
 591 intel_miptree_get_tile_offsets(struct intel_mipmap_tree *mt,
 592                                GLuint level, GLuint slice,
 593                                uint32_t *tile_x,
 594                                uint32_t *tile_y);
 595
 596 void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
 597                                   GLuint level,
 598                                   GLuint x, GLuint y,
 599                                   GLuint w, GLuint h, GLuint d);
 600
 601 void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
 602                                     GLuint level,
 603                                     GLuint img, GLuint x, GLuint y);
 604
 605 void
 606 intel_miptree_copy_teximage(struct brw_context *brw,
 607                             struct intel_texture_image *intelImage,
 608                             struct intel_mipmap_tree *dst_mt, bool invalidate);
 609
 610 bool
 611 intel_miptree_alloc_mcs(struct brw_context *brw,
 612                         struct intel_mipmap_tree *mt,
 613                         GLuint num_samples);
 614
 615 /**
 616  * \name Miptree HiZ functions
 617  * \{
 618  *
 619  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 620  * functions on a miptree without HiZ. In that case, each function is a no-op.
 621  */
 622
 623 /**
 624  * \brief Allocate the miptree's embedded HiZ miptree.
 625  * \see intel_mipmap_tree:hiz_mt
 626  * \return false if allocation failed
 627  */
 628
 629 bool
 630 intel_miptree_alloc_hiz(struct brw_context *brw,
 631                         struct intel_mipmap_tree *mt);
 632
 633 bool
 634 intel_miptree_slice_has_hiz(struct intel_mipmap_tree *mt,
 635                             uint32_t level,
 636                             uint32_t layer);
 637
 638 void
 639 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt,
 640                                           uint32_t level,
 641                                           uint32_t depth);
 642 void
 643 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt,
 644                                             uint32_t level,
 645                                             uint32_t depth);
 646
 647 void
 648 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree *mt,
 649                                                 uint32_t level);
 650
 651 /**
 652  * \return false if no resolve was needed
 653  */
 654 bool
 655 intel_miptree_slice_resolve_hiz(struct brw_context *brw,
 656                                 struct intel_mipmap_tree *mt,
 657                                 unsigned int level,
 658                                 unsigned int depth);
 659
 660 /**
 661  * \return false if no resolve was needed
 662  */
 663 bool
 664 intel_miptree_slice_resolve_depth(struct brw_context *brw,
 665                                   struct intel_mipmap_tree *mt,
 666                                   unsigned int level,
 667                                   unsigned int depth);
 668
 669 /**
 670  * \return false if no resolve was needed
 671  */
 672 bool
 673 intel_miptree_all_slices_resolve_hiz(struct brw_context *brw,
 674                                      struct intel_mipmap_tree *mt);
 675
 676 /**
 677  * \return false if no resolve was needed
 678  */
 679 bool
 680 intel_miptree_all_slices_resolve_depth(struct brw_context *brw,
 681                                        struct intel_mipmap_tree *mt);
 682
 683 /**\}*/
 684
 685 /**
 686  * Update the fast clear state for a miptree to indicate that it has been used
 687  * for rendering.
 688  */
 689 static inline void
 690 intel_miptree_used_for_rendering(struct intel_mipmap_tree *mt)
 691 {
 692    /* If the buffer was previously in fast clear state, change it to
 693     * unresolved state, since it won't be guaranteed to be clear after
 694     * rendering occurs.
 695     */
 696    if (mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR)
 697       mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
 698 }
 699
 700 void
 701 intel_miptree_resolve_color(struct brw_context *brw,
 702                             struct intel_mipmap_tree *mt);
 703
 704 void
 705 intel_miptree_make_shareable(struct brw_context *brw,
 706                              struct intel_mipmap_tree *mt);
 707
 708 void
 709 intel_miptree_downsample(struct brw_context *brw,
 710                          struct intel_mipmap_tree *mt);
 711
 712 void
 713 intel_miptree_upsample(struct brw_context *brw,
 714                        struct intel_mipmap_tree *mt);
 715
 716 void brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt);
 717
 718 void *intel_miptree_map_raw(struct brw_context *brw,
 719                             struct intel_mipmap_tree *mt);
 720
 721 void intel_miptree_unmap_raw(struct brw_context *brw,
 722                              struct intel_mipmap_tree *mt);
 723
 724 void
 725 intel_miptree_map(struct brw_context *brw,
 726                   struct intel_mipmap_tree *mt,
 727                   unsigned int level,
 728                   unsigned int slice,
 729                   unsigned int x,
 730                   unsigned int y,
 731                   unsigned int w,
 732                   unsigned int h,
 733                   GLbitfield mode,
 734                   void **out_ptr,
 735                   int *out_stride);
 736
 737 void
 738 intel_miptree_unmap(struct brw_context *brw,
 739                     struct intel_mipmap_tree *mt,
 740                     unsigned int level,
 741                     unsigned int slice);
 742
 743 void
 744 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 745                unsigned int level, unsigned int layer, enum gen6_hiz_op op);
 746
 747 #ifdef __cplusplus
 748 }
 749 #endif
 750
 751 #endif