src/mesa/drivers/dri/i965/intel_mipmap_tree.h

   1 /*
   2  * Copyright 2006 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 /** @file intel_mipmap_tree.h
  27  *
  28  * This file defines the structure that wraps a BO and describes how the
  29  * mipmap levels and slices of a texture are laid out.
  30  *
  31  * The hardware has a fixed layout of a texture depending on parameters such
  32  * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
  33  * mipmap levels.  The individual level/layer slices are each 2D rectangles of
  34  * pixels at some x/y offset from the start of the brw_bo.
  35  *
  36  * Original OpenGL allowed texture miplevels to be specified in arbitrary
  37  * order, and a texture may change size over time.  Thus, each
  38  * intel_texture_image has a reference to a miptree that contains the pixel
  39  * data sized appropriately for it, which will later be referenced by/copied
  40  * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
  41  * that there's a single miptree for the complete texture.
  42  */
  43
  44 #ifndef INTEL_MIPMAP_TREE_H
  45 #define INTEL_MIPMAP_TREE_H
  46
  47 #include <assert.h>
  48
  49 #include "main/mtypes.h"
  50 #include "isl/isl.h"
  51 #include "blorp/blorp.h"
  52 #include "brw_bufmgr.h"
  53 #include <GL/internal/dri_interface.h>
  54
  55 #ifdef __cplusplus
  56 extern "C" {
  57 #endif
  58
  59 struct brw_context;
  60 struct intel_renderbuffer;
  61
  62 struct intel_texture_image;
  63
  64 /**
  65  * This bit extends the set of GL_MAP_*_BIT enums.
  66  *
  67  * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
  68  * depthstencil-split-to-separate-stencil miptree, we'll normally make a
  69  * temporary and recreate the kind of data requested by Mesa core, since we're
  70  * satisfying some glGetTexImage() request or something.
  71  *
  72  * However, occasionally you want to actually map the miptree's current data
  73  * without transcoding back.  This flag to intel_miptree_map() gets you that.
  74  */
  75 #define BRW_MAP_DIRECT_BIT      0x80000000
  76
  77 struct intel_miptree_map {
  78    /** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */
  79    GLbitfield mode;
  80    /** Region of interest for the map. */
  81    int x, y, w, h;
  82    /** Possibly malloced temporary buffer for the mapping. */
  83    void *buffer;
  84    /** Possible pointer to a temporary linear miptree for the mapping. */
  85    struct intel_mipmap_tree *linear_mt;
  86    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  87    void *ptr;
  88    /** Stride of the mapping. */
  89    int stride;
  90 };
  91
  92 /**
  93  * Describes the location of each texture image within a miptree.
  94  */
  95 struct intel_mipmap_level
  96 {
  97    /** Offset to this miptree level, used in computing x_offset. */
  98    GLuint level_x;
  99    /** Offset to this miptree level, used in computing y_offset. */
 100    GLuint level_y;
 101
 102    /**
 103     * \brief Is HiZ enabled for this level?
 104     *
 105     * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
 106     * allocated and (2) the HiZ memory for the slices in this level reside at
 107     * \c mt->hiz_mt->level[l].
 108     */
 109    bool has_hiz;
 110
 111    /**
 112     * \brief List of 2D images in this mipmap level.
 113     *
 114     * This may be a list of cube faces, array slices in 2D array texture, or
 115     * layers in a 3D texture. The list's length is \c depth.
 116     */
 117    struct intel_mipmap_slice {
 118       /**
 119        * Mapping information. Persistent for the duration of
 120        * intel_miptree_map/unmap on this slice.
 121        */
 122       struct intel_miptree_map *map;
 123    } *slice;
 124 };
 125
 126 /**
 127  * Miptree aux buffer. These buffers are associated with a miptree, but the
 128  * format is managed by the hardware.
 129  *
 130  * For Gen7+, we always give the hardware the start of the buffer, and let it
 131  * handle all accesses to the buffer. Therefore we don't need the full miptree
 132  * layout structure for this buffer.
 133  */
 134 struct intel_miptree_aux_buffer
 135 {
 136    struct isl_surf surf;
 137
 138    /**
 139     * Buffer object containing the pixel data.
 140     *
 141     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 142     * @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
 143     */
 144    struct brw_bo *bo;
 145
 146    /**
 147     * Offset into bo where the surface starts.
 148     *
 149     * @see intel_mipmap_aux_buffer::bo
 150     *
 151     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 152     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 153     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 154     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 155     */
 156    uint32_t offset;
 157
 158    /*
 159     * Size of the MCS surface.
 160     *
 161     * This is needed when doing any gtt mapped operations on the buffer (which
 162     * will be Y-tiled). It is possible that it will not be the same as bo->size
 163     * when the drm allocator rounds up the requested size.
 164     */
 165    size_t size;
 166
 167    /**
 168     * Pitch in bytes.
 169     *
 170     * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
 171     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
 172     */
 173    uint32_t pitch;
 174
 175    /**
 176     * The distance in rows between array slices.
 177     *
 178     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch
 179     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
 180     */
 181    uint32_t qpitch;
 182 };
 183
 184 struct intel_mipmap_tree
 185 {
 186    struct isl_surf surf;
 187
 188    /**
 189     * Buffer object containing the surface.
 190     *
 191     * @see intel_mipmap_tree::offset
 192     * @see RENDER_SURFACE_STATE.SurfaceBaseAddress
 193     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 194     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 195     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 196     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 197     */
 198    struct brw_bo *bo;
 199
 200    /**
 201     * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
 202     *
 203     * @see RENDER_SURFACE_STATE.SurfaceType
 204     * @see RENDER_SURFACE_STATE.SurfaceArray
 205     * @see 3DSTATE_DEPTH_BUFFER.SurfaceType
 206     */
 207    GLenum target;
 208
 209    /**
 210     * Generally, this is just the same as the gl_texture_image->TexFormat or
 211     * gl_renderbuffer->Format.
 212     *
 213     * However, for textures and renderbuffers with packed depth/stencil formats
 214     * on hardware where we want or need to use separate stencil, there will be
 215     * two miptrees for storing the data.  If the depthstencil texture or rb is
 216     * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
 217     * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
 218     * MESA_FORMAT_Z24_UNORM_X8_UINT.
 219     *
 220     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
 221     * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
 222     *
 223     * @see RENDER_SURFACE_STATE.SurfaceFormat
 224     * @see 3DSTATE_DEPTH_BUFFER.SurfaceFormat
 225     */
 226    mesa_format format;
 227
 228    /**
 229     * This variable stores the value of ETC compressed texture format
 230     *
 231     * @see RENDER_SURFACE_STATE.SurfaceFormat
 232     */
 233    mesa_format etc_format;
 234
 235    GLuint first_level;
 236    GLuint last_level;
 237
 238    /** Bytes per pixel (or bytes per block if compressed) */
 239    GLuint cpp;
 240
 241    bool compressed;
 242
 243    /* Includes image offset tables: */
 244    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 245
 246    /**
 247     * Offset into bo where the surface starts.
 248     *
 249     * @see intel_mipmap_tree::bo
 250     *
 251     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 252     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 253     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 254     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 255     */
 256    uint32_t offset;
 257
 258    /**
 259     * \brief HiZ aux buffer
 260     *
 261     * To allocate the hiz buffer, use intel_miptree_alloc_hiz().
 262     *
 263     * To determine if hiz is enabled, do not check this pointer. Instead, use
 264     * intel_miptree_level_has_hiz().
 265     */
 266    struct intel_miptree_aux_buffer *hiz_buf;
 267
 268    /**
 269     * \brief The type of auxiliary compression used by this miptree.
 270     *
 271     * This describes the type of auxiliary compression that is intended to be
 272     * used by this miptree.  An aux usage of ISL_AUX_USAGE_NONE means that
 273     * auxiliary compression is permanently disabled.  An aux usage other than
 274     * ISL_AUX_USAGE_NONE does not imply that the auxiliary buffer has actually
 275     * been allocated nor does it imply that auxiliary compression will always
 276     * be enabled for this surface.  For instance, with CCS_D, we may allocate
 277     * the CCS on-the-fly and it may not be used for texturing if the miptree
 278     * is fully resolved.
 279     */
 280    enum isl_aux_usage aux_usage;
 281
 282    /**
 283     * \brief Whether or not this miptree supports fast clears.
 284     */
 285    bool supports_fast_clear;
 286
 287    /**
 288     * \brief Maps miptree slices to their current aux state
 289     *
 290     * This two-dimensional array is indexed as [level][layer] and stores an
 291     * aux state for each slice.
 292     */
 293    enum isl_aux_state **aux_state;
 294
 295    /**
 296     * \brief Stencil miptree for depthstencil textures.
 297     *
 298     * This miptree is used for depthstencil textures and renderbuffers that
 299     * require separate stencil.  It always has the true copy of the stencil
 300     * bits, regardless of mt->format.
 301     *
 302     * \see 3DSTATE_STENCIL_BUFFER
 303     * \see intel_miptree_map_depthstencil()
 304     * \see intel_miptree_unmap_depthstencil()
 305     */
 306    struct intel_mipmap_tree *stencil_mt;
 307
 308    /**
 309     * \brief Stencil texturing miptree for sampling from a stencil texture
 310     *
 311     * Some hardware doesn't support sampling from the stencil texture as
 312     * required by the GL_ARB_stencil_texturing extenion. To workaround this we
 313     * blit the texture into a new texture that can be sampled.
 314     *
 315     * \see intel_update_r8stencil()
 316     */
 317    struct intel_mipmap_tree *r8stencil_mt;
 318    bool r8stencil_needs_update;
 319
 320    /**
 321     * \brief MCS auxiliary buffer.
 322     *
 323     * This buffer contains the "multisample control surface", which stores
 324     * the necessary information to implement compressed MSAA
 325     * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
 326     *
 327     * NULL if no MCS buffer is in use for this surface.
 328     */
 329    struct intel_miptree_aux_buffer *mcs_buf;
 330
 331    /**
 332     * Planes 1 and 2 in case this is a planar surface.
 333     */
 334    struct intel_mipmap_tree *plane[2];
 335
 336    /**
 337     * Fast clear color for this surface.  For depth surfaces, the clear value
 338     * is stored as a float32 in the red component.
 339     */
 340    union isl_color_value fast_clear_color;
 341
 342    /* These are also refcounted:
 343     */
 344    GLuint refcount;
 345 };
 346
 347 bool
 348 intel_miptree_alloc_ccs(struct brw_context *brw,
 349                         struct intel_mipmap_tree *mt);
 350
 351 enum {
 352    MIPTREE_LAYOUT_ACCELERATED_UPLOAD       = 1 << 0,
 353    MIPTREE_LAYOUT_GEN6_HIZ_STENCIL         = 1 << 1,
 354    MIPTREE_LAYOUT_FOR_BO                   = 1 << 2,
 355    MIPTREE_LAYOUT_DISABLE_AUX              = 1 << 3,
 356    MIPTREE_LAYOUT_FORCE_HALIGN16           = 1 << 4,
 357
 358    MIPTREE_LAYOUT_TILING_Y                 = 1 << 5,
 359    MIPTREE_LAYOUT_TILING_NONE              = 1 << 6,
 360    MIPTREE_LAYOUT_TILING_ANY               = MIPTREE_LAYOUT_TILING_Y |
 361                                              MIPTREE_LAYOUT_TILING_NONE,
 362
 363    MIPTREE_LAYOUT_FOR_SCANOUT              = 1 << 7,
 364 };
 365
 366 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
 367                                                GLenum target,
 368                                                mesa_format format,
 369                                                GLuint first_level,
 370                                                GLuint last_level,
 371                                                GLuint width0,
 372                                                GLuint height0,
 373                                                GLuint depth0,
 374                                                GLuint num_samples,
 375                                                uint32_t flags);
 376
 377 struct intel_mipmap_tree *
 378 intel_miptree_create_for_bo(struct brw_context *brw,
 379                             struct brw_bo *bo,
 380                             mesa_format format,
 381                             uint32_t offset,
 382                             uint32_t width,
 383                             uint32_t height,
 384                             uint32_t depth,
 385                             int pitch,
 386                             uint32_t layout_flags);
 387
 388 struct intel_mipmap_tree *
 389 intel_miptree_create_for_dri_image(struct brw_context *brw,
 390                                    __DRIimage *image,
 391                                    GLenum target,
 392                                    enum isl_colorspace colorspace,
 393                                    bool is_winsys_image);
 394
 395 bool
 396 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
 397                                          struct intel_renderbuffer *irb,
 398                                          struct intel_mipmap_tree *singlesample_mt,
 399                                          uint32_t width, uint32_t height,
 400                                          uint32_t pitch);
 401
 402 /**
 403  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 404  * The miptree has the following properties:
 405  *     - The target is GL_TEXTURE_2D.
 406  *     - There are no levels other than the base level 0.
 407  *     - Depth is 1.
 408  */
 409 struct intel_mipmap_tree*
 410 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
 411                                       mesa_format format,
 412                                       uint32_t width,
 413                                       uint32_t height,
 414                                       uint32_t num_samples);
 415
 416 mesa_format
 417 intel_depth_format_for_depthstencil_format(mesa_format format);
 418
 419 mesa_format
 420 intel_lower_compressed_format(struct brw_context *brw, mesa_format format);
 421
 422 /** \brief Assert that the level and layer are valid for the miptree. */
 423 void
 424 intel_miptree_check_level_layer(const struct intel_mipmap_tree *mt,
 425                                 uint32_t level,
 426                                 uint32_t layer);
 427
 428 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 429                              struct intel_mipmap_tree *src);
 430
 431 void intel_miptree_release(struct intel_mipmap_tree **mt);
 432
 433 /* Check if an image fits an existing mipmap tree layout
 434  */
 435 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 436                                     struct gl_texture_image *image);
 437
 438 void
 439 intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt,
 440                                GLuint level, GLuint slice,
 441                                GLuint *x, GLuint *y);
 442
 443 enum isl_surf_dim
 444 get_isl_surf_dim(GLenum target);
 445
 446 enum isl_dim_layout
 447 get_isl_dim_layout(const struct gen_device_info *devinfo,
 448                    enum isl_tiling tiling, GLenum target);
 449
 450 enum isl_aux_usage
 451 intel_miptree_get_aux_isl_usage(const struct brw_context *brw,
 452                                 const struct intel_mipmap_tree *mt);
 453
 454 void
 455 intel_get_image_dims(struct gl_texture_image *image,
 456                      int *width, int *height, int *depth);
 457
 458 void
 459 intel_get_tile_masks(enum isl_tiling tiling, uint32_t cpp,
 460                      uint32_t *mask_x, uint32_t *mask_y);
 461
 462 void
 463 intel_get_tile_dims(enum isl_tiling tiling, uint32_t cpp,
 464                     uint32_t *tile_w, uint32_t *tile_h);
 465
 466 uint32_t
 467 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
 468                                GLuint level, GLuint slice,
 469                                uint32_t *tile_x,
 470                                uint32_t *tile_y);
 471 uint32_t
 472 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
 473                                  uint32_t x, uint32_t y);
 474
 475 void
 476 intel_miptree_copy_slice(struct brw_context *brw,
 477                          struct intel_mipmap_tree *src_mt,
 478                          unsigned src_level, unsigned src_layer,
 479                          struct intel_mipmap_tree *dst_mt,
 480                          unsigned dst_level, unsigned dst_layer);
 481
 482 void
 483 intel_miptree_copy_teximage(struct brw_context *brw,
 484                             struct intel_texture_image *intelImage,
 485                             struct intel_mipmap_tree *dst_mt, bool invalidate);
 486
 487 /**
 488  * \name Miptree HiZ functions
 489  * \{
 490  *
 491  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 492  * functions on a miptree without HiZ. In that case, each function is a no-op.
 493  */
 494
 495 /**
 496  * \brief Allocate the miptree's embedded HiZ miptree.
 497  * \see intel_mipmap_tree:hiz_mt
 498  * \return false if allocation failed
 499  */
 500 bool
 501 intel_miptree_alloc_hiz(struct brw_context *brw,
 502                         struct intel_mipmap_tree *mt);
 503
 504 bool
 505 intel_miptree_level_has_hiz(const struct intel_mipmap_tree *mt, uint32_t level);
 506
 507 /**\}*/
 508
 509 bool
 510 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree *mt,
 511                                    unsigned start_level, unsigned num_levels,
 512                                    unsigned start_layer, unsigned num_layers);
 513
 514
 515 #define INTEL_REMAINING_LAYERS UINT32_MAX
 516 #define INTEL_REMAINING_LEVELS UINT32_MAX
 517
 518 /** Prepare a miptree for access
 519  *
 520  * This function should be called prior to any access to miptree in order to
 521  * perform any needed resolves.
 522  *
 523  * \param[in]  start_level    The first mip level to be accessed
 524  *
 525  * \param[in]  num_levels     The number of miplevels to be accessed or
 526  *                            INTEL_REMAINING_LEVELS to indicate every level
 527  *                            above start_level will be accessed
 528  *
 529  * \param[in]  start_layer    The first array slice or 3D layer to be accessed
 530  *
 531  * \param[in]  num_layers     The number of array slices or 3D layers be
 532  *                            accessed or INTEL_REMAINING_LAYERS to indicate
 533  *                            every layer above start_layer will be accessed
 534  *
 535  * \param[in]  aux_supported  Whether or not the access will support the
 536  *                            miptree's auxiliary compression format;  this
 537  *                            must be false for uncompressed miptrees
 538  *
 539  * \param[in]  fast_clear_supported Whether or not the access will support
 540  *                                  fast clears in the miptree's auxiliary
 541  *                                  compression format
 542  */
 543 void
 544 intel_miptree_prepare_access(struct brw_context *brw,
 545                              struct intel_mipmap_tree *mt,
 546                              uint32_t start_level, uint32_t num_levels,
 547                              uint32_t start_layer, uint32_t num_layers,
 548                              bool aux_supported, bool fast_clear_supported);
 549
 550 /** Complete a write operation
 551  *
 552  * This function should be called after any operation writes to a miptree.
 553  * This will update the miptree's compression state so that future resolves
 554  * happen correctly.  Technically, this function can be called before the
 555  * write occurs but the caller must ensure that they don't interlace
 556  * intel_miptree_prepare_access and intel_miptree_finish_write calls to
 557  * overlapping layer/level ranges.
 558  *
 559  * \param[in]  level             The mip level that was written
 560  *
 561  * \param[in]  start_layer       The first array slice or 3D layer written
 562  *
 563  * \param[in]  num_layers        The number of array slices or 3D layers
 564  *                               written or INTEL_REMAINING_LAYERS to indicate
 565  *                               every layer above start_layer was written
 566  *
 567  * \param[in]  written_with_aux  Whether or not the write was done with
 568  *                               auxiliary compression enabled
 569  */
 570 void
 571 intel_miptree_finish_write(struct brw_context *brw,
 572                            struct intel_mipmap_tree *mt, uint32_t level,
 573                            uint32_t start_layer, uint32_t num_layers,
 574                            bool written_with_aux);
 575
 576 /** Get the auxiliary compression state of a miptree slice */
 577 enum isl_aux_state
 578 intel_miptree_get_aux_state(const struct intel_mipmap_tree *mt,
 579                             uint32_t level, uint32_t layer);
 580
 581 /** Set the auxiliary compression state of a miptree slice range
 582  *
 583  * This function directly sets the auxiliary compression state of a slice
 584  * range of a miptree.  It only modifies data structures and does not do any
 585  * resolves.  This should only be called by code which directly performs
 586  * compression operations such as fast clears and resolves.  Most code should
 587  * use intel_miptree_prepare_access or intel_miptree_finish_write.
 588  */
 589 void
 590 intel_miptree_set_aux_state(struct brw_context *brw,
 591                             struct intel_mipmap_tree *mt, uint32_t level,
 592                             uint32_t start_layer, uint32_t num_layers,
 593                             enum isl_aux_state aux_state);
 594
 595 /**
 596  * Prepare a miptree for raw access
 597  *
 598  * This helper prepares the miptree for access that knows nothing about any
 599  * sort of compression whatsoever.  This is useful when mapping the surface or
 600  * using it with the blitter.
 601  */
 602 static inline void
 603 intel_miptree_access_raw(struct brw_context *brw,
 604                          struct intel_mipmap_tree *mt,
 605                          uint32_t level, uint32_t layer,
 606                          bool write)
 607 {
 608    intel_miptree_prepare_access(brw, mt, level, 1, layer, 1, false, false);
 609    if (write)
 610       intel_miptree_finish_write(brw, mt, level, layer, 1, false);
 611 }
 612
 613 enum isl_aux_usage
 614 intel_miptree_texture_aux_usage(struct brw_context *brw,
 615                                 struct intel_mipmap_tree *mt,
 616                                 enum isl_format view_format);
 617 void
 618 intel_miptree_prepare_texture(struct brw_context *brw,
 619                               struct intel_mipmap_tree *mt,
 620                               mesa_format view_format,
 621                               bool *aux_supported_out);
 622 void
 623 intel_miptree_prepare_image(struct brw_context *brw,
 624                             struct intel_mipmap_tree *mt);
 625 void
 626 intel_miptree_prepare_fb_fetch(struct brw_context *brw,
 627                                struct intel_mipmap_tree *mt, uint32_t level,
 628                                uint32_t start_layer, uint32_t num_layers);
 629 enum isl_aux_usage
 630 intel_miptree_render_aux_usage(struct brw_context *brw,
 631                                struct intel_mipmap_tree *mt,
 632                                bool srgb_enabled);
 633 void
 634 intel_miptree_prepare_render(struct brw_context *brw,
 635                              struct intel_mipmap_tree *mt, uint32_t level,
 636                              uint32_t start_layer, uint32_t layer_count,
 637                              bool srgb_enabled);
 638 void
 639 intel_miptree_finish_render(struct brw_context *brw,
 640                             struct intel_mipmap_tree *mt, uint32_t level,
 641                             uint32_t start_layer, uint32_t layer_count,
 642                             bool srgb_enabled);
 643 void
 644 intel_miptree_prepare_depth(struct brw_context *brw,
 645                             struct intel_mipmap_tree *mt, uint32_t level,
 646                             uint32_t start_layer, uint32_t layer_count);
 647 void
 648 intel_miptree_finish_depth(struct brw_context *brw,
 649                            struct intel_mipmap_tree *mt, uint32_t level,
 650                            uint32_t start_layer, uint32_t layer_count,
 651                            bool depth_written);
 652
 653 void
 654 intel_miptree_make_shareable(struct brw_context *brw,
 655                              struct intel_mipmap_tree *mt);
 656
 657 void
 658 intel_miptree_updownsample(struct brw_context *brw,
 659                            struct intel_mipmap_tree *src,
 660                            struct intel_mipmap_tree *dst);
 661
 662 void
 663 intel_update_r8stencil(struct brw_context *brw,
 664                        struct intel_mipmap_tree *mt);
 665
 666 bool
 667 brw_miptree_layout(struct brw_context *brw,
 668                    struct intel_mipmap_tree *mt,
 669                    uint32_t layout_flags);
 670
 671 void
 672 intel_miptree_map(struct brw_context *brw,
 673                   struct intel_mipmap_tree *mt,
 674                   unsigned int level,
 675                   unsigned int slice,
 676                   unsigned int x,
 677                   unsigned int y,
 678                   unsigned int w,
 679                   unsigned int h,
 680                   GLbitfield mode,
 681                   void **out_ptr,
 682                   ptrdiff_t *out_stride);
 683
 684 void
 685 intel_miptree_unmap(struct brw_context *brw,
 686                     struct intel_mipmap_tree *mt,
 687                     unsigned int level,
 688                     unsigned int slice);
 689
 690 bool
 691 intel_miptree_sample_with_hiz(struct brw_context *brw,
 692                               struct intel_mipmap_tree *mt);
 693
 694 #ifdef __cplusplus
 695 }
 696 #endif
 697
 698 #endif