src/mesa/drivers/dri/i965/intel_mipmap_tree.h

   1 /*
   2  * Copyright 2006 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 /** @file intel_mipmap_tree.h
  27  *
  28  * This file defines the structure that wraps a BO and describes how the
  29  * mipmap levels and slices of a texture are laid out.
  30  *
  31  * The hardware has a fixed layout of a texture depending on parameters such
  32  * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
  33  * mipmap levels.  The individual level/layer slices are each 2D rectangles of
  34  * pixels at some x/y offset from the start of the drm_intel_bo.
  35  *
  36  * Original OpenGL allowed texture miplevels to be specified in arbitrary
  37  * order, and a texture may change size over time.  Thus, each
  38  * intel_texture_image has a reference to a miptree that contains the pixel
  39  * data sized appropriately for it, which will later be referenced by/copied
  40  * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
  41  * that there's a single miptree for the complete texture.
  42  */
  43
  44 #ifndef INTEL_MIPMAP_TREE_H
  45 #define INTEL_MIPMAP_TREE_H
  46
  47 #include <assert.h>
  48
  49 #include "main/mtypes.h"
  50 #include "intel_bufmgr.h"
  51 #include "intel_resolve_map.h"
  52 #include <GL/internal/dri_interface.h>
  53
  54 #ifdef __cplusplus
  55 extern "C" {
  56 #endif
  57
  58 struct brw_context;
  59 struct intel_renderbuffer;
  60
  61 struct intel_resolve_map;
  62 struct intel_texture_image;
  63
  64 /**
  65  * This bit extends the set of GL_MAP_*_BIT enums.
  66  *
  67  * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
  68  * depthstencil-split-to-separate-stencil miptree, we'll normally make a
  69  * temporary and recreate the kind of data requested by Mesa core, since we're
  70  * satisfying some glGetTexImage() request or something.
  71  *
  72  * However, occasionally you want to actually map the miptree's current data
  73  * without transcoding back.  This flag to intel_miptree_map() gets you that.
  74  */
  75 #define BRW_MAP_DIRECT_BIT      0x80000000
  76
  77 struct intel_miptree_map {
  78    /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
  79    GLbitfield mode;
  80    /** Region of interest for the map. */
  81    int x, y, w, h;
  82    /** Possibly malloced temporary buffer for the mapping. */
  83    void *buffer;
  84    /** Possible pointer to a temporary linear miptree for the mapping. */
  85    struct intel_mipmap_tree *mt;
  86    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  87    void *ptr;
  88    /** Stride of the mapping. */
  89    int stride;
  90 };
  91
  92 /**
  93  * Describes the location of each texture image within a miptree.
  94  */
  95 struct intel_mipmap_level
  96 {
  97    /** Offset to this miptree level, used in computing x_offset. */
  98    GLuint level_x;
  99    /** Offset to this miptree level, used in computing y_offset. */
 100    GLuint level_y;
 101
 102    /**
 103     * \brief Number of 2D slices in this miplevel.
 104     *
 105     * The exact semantics of depth varies according to the texture target:
 106     *    - For GL_TEXTURE_CUBE_MAP, depth is 6.
 107     *    - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
 108     *      identical for all miplevels in the texture.
 109     *    - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
 110     *      value, like width and height, varies with miplevel.
 111     *    - For other texture types, depth is 1.
 112     *    - Additionally, for UMS and CMS miptrees, depth is multiplied by
 113     *      sample count.
 114     */
 115    GLuint depth;
 116
 117    /**
 118     * \brief Is HiZ enabled for this level?
 119     *
 120     * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
 121     * allocated and (2) the HiZ memory for the slices in this level reside at
 122     * \c mt->hiz_mt->level[l].
 123     */
 124    bool has_hiz;
 125
 126    /**
 127     * \brief List of 2D images in this mipmap level.
 128     *
 129     * This may be a list of cube faces, array slices in 2D array texture, or
 130     * layers in a 3D texture. The list's length is \c depth.
 131     */
 132    struct intel_mipmap_slice {
 133       /**
 134        * \name Offset to slice
 135        * \{
 136        *
 137        * Hardware formats are so diverse that that there is no unified way to
 138        * compute the slice offsets, so we store them in this table.
 139        *
 140        * The (x, y) offset to slice \c s at level \c l relative the miptrees
 141        * base address is
 142        * \code
 143        *     x = mt->level[l].slice[s].x_offset
 144        *     y = mt->level[l].slice[s].y_offset
 145        */
 146       GLuint x_offset;
 147       GLuint y_offset;
 148       /** \} */
 149
 150       /**
 151        * Mapping information. Persistent for the duration of
 152        * intel_miptree_map/unmap on this slice.
 153        */
 154       struct intel_miptree_map *map;
 155    } *slice;
 156 };
 157
 158 /**
 159  * Enum for keeping track of the different MSAA layouts supported by Gen7.
 160  */
 161 enum intel_msaa_layout
 162 {
 163    /**
 164     * Ordinary surface with no MSAA.
 165     */
 166    INTEL_MSAA_LAYOUT_NONE,
 167
 168    /**
 169     * Interleaved Multisample Surface.  The additional samples are
 170     * accommodated by scaling up the width and the height of the surface so
 171     * that all the samples corresponding to a pixel are located at nearby
 172     * memory locations.
 173     */
 174    INTEL_MSAA_LAYOUT_IMS,
 175
 176    /**
 177     * Uncompressed Multisample Surface.  The surface is stored as a 2D array,
 178     * with array slice n containing all pixel data for sample n.
 179     */
 180    INTEL_MSAA_LAYOUT_UMS,
 181
 182    /**
 183     * Compressed Multisample Surface.  The surface is stored as in
 184     * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
 185     * (Multisample Control Surface) buffer.  Each pixel in the MCS buffer
 186     * indicates the mapping from sample number to array slice.  This allows
 187     * the common case (where all samples constituting a pixel have the same
 188     * color value) to be stored efficiently by just using a single array
 189     * slice.
 190     */
 191    INTEL_MSAA_LAYOUT_CMS,
 192 };
 193
 194
 195 /**
 196  * Enum for keeping track of the fast clear state of a buffer associated with
 197  * a miptree.
 198  *
 199  * Fast clear works by deferring the memory writes that would be used to clear
 200  * the buffer, so that instead of performing them at the time of the clear
 201  * operation, the hardware automatically performs them at the time that the
 202  * buffer is later accessed for rendering.  The MCS buffer keeps track of
 203  * which regions of the buffer still have pending clear writes.
 204  *
 205  * This enum keeps track of the driver's knowledge of pending fast clears in
 206  * the MCS buffer.
 207  *
 208  * MCS buffers only exist on Gen7+.
 209  */
 210 enum intel_fast_clear_state
 211 {
 212    /**
 213     * There is no MCS buffer for this miptree, and one should never be
 214     * allocated.
 215     */
 216    INTEL_FAST_CLEAR_STATE_NO_MCS,
 217
 218    /**
 219     * No deferred clears are pending for this miptree, and the contents of the
 220     * color buffer are entirely correct.  An MCS buffer may or may not exist
 221     * for this miptree.  If it does exist, it is entirely in the "no deferred
 222     * clears pending" state.  If it does not exist, it will be created the
 223     * first time a fast color clear is executed.
 224     *
 225     * In this state, the color buffer can be used for purposes other than
 226     * rendering without needing a render target resolve.
 227     *
 228     * Since there is no such thing as a "fast color clear resolve" for MSAA
 229     * buffers, an MSAA buffer will never be in this state.
 230     */
 231    INTEL_FAST_CLEAR_STATE_RESOLVED,
 232
 233    /**
 234     * An MCS buffer exists for this miptree, and deferred clears are pending
 235     * for some regions of the color buffer, as indicated by the MCS buffer.
 236     * The contents of the color buffer are only correct for the regions where
 237     * the MCS buffer doesn't indicate a deferred clear.
 238     *
 239     * If a single-sample buffer is in this state, a render target resolve must
 240     * be performed before it can be used for purposes other than rendering.
 241     */
 242    INTEL_FAST_CLEAR_STATE_UNRESOLVED,
 243
 244    /**
 245     * An MCS buffer exists for this miptree, and deferred clears are pending
 246     * for the entire color buffer, and the contents of the MCS buffer reflect
 247     * this.  The contents of the color buffer are undefined.
 248     *
 249     * If a single-sample buffer is in this state, a render target resolve must
 250     * be performed before it can be used for purposes other than rendering.
 251     *
 252     * If the client attempts to clear a buffer which is already in this state,
 253     * the clear can be safely skipped, since the buffer is already clear.
 254     */
 255    INTEL_FAST_CLEAR_STATE_CLEAR,
 256 };
 257
 258 enum miptree_array_layout {
 259    /* Each array slice contains all miplevels packed together.
 260     *
 261     * Gen hardware usually wants multilevel miptrees configured this way.
 262     *
 263     * A 2D Array texture with 2 slices and multiple LODs using
 264     * ALL_LOD_IN_EACH_SLICE would look somewhat like this:
 265     *
 266     *   +----------+
 267     *   |          |
 268     *   |          |
 269     *   +----------+
 270     *   +---+ +-+
 271     *   |   | +-+
 272     *   +---+ *
 273     *   +----------+
 274     *   |          |
 275     *   |          |
 276     *   +----------+
 277     *   +---+ +-+
 278     *   |   | +-+
 279     *   +---+ *
 280     */
 281    ALL_LOD_IN_EACH_SLICE,
 282
 283    /* Each LOD contains all slices of that LOD packed together.
 284     *
 285     * In some situations, Gen7+ hardware can use the array_spacing_lod0
 286     * feature to save space when the surface only contains LOD 0.
 287     *
 288     * Gen6 uses this for separate stencil and hiz since gen6 does not support
 289     * multiple LODs for separate stencil and hiz.
 290     *
 291     * A 2D Array texture with 2 slices and multiple LODs using
 292     * ALL_SLICES_AT_EACH_LOD would look somewhat like this:
 293     *
 294     *   +----------+
 295     *   |          |
 296     *   |          |
 297     *   +----------+
 298     *   |          |
 299     *   |          |
 300     *   +----------+
 301     *   +---+ +-+
 302     *   |   | +-+
 303     *   +---+ +-+
 304     *   |   | :
 305     *   +---+
 306     */
 307    ALL_SLICES_AT_EACH_LOD,
 308 };
 309
 310 /**
 311  * Miptree aux buffer. These buffers are associated with a miptree, but the
 312  * format is managed by the hardware.
 313  *
 314  * For Gen7+, we always give the hardware the start of the buffer, and let it
 315  * handle all accesses to the buffer. Therefore we don't need the full miptree
 316  * layout structure for this buffer.
 317  *
 318  * For Gen6, we need a hiz miptree structure for this buffer so we can program
 319  * offsets to slices & miplevels.
 320  */
 321 struct intel_miptree_aux_buffer
 322 {
 323    /** Buffer object containing the pixel data. */
 324    drm_intel_bo *bo;
 325
 326    uint32_t pitch; /**< pitch in bytes. */
 327
 328    uint32_t qpitch; /**< The distance in rows between array slices. */
 329
 330    struct intel_mipmap_tree *mt; /**< hiz miptree used with Gen6 */
 331 };
 332
 333 /* Tile resource modes */
 334 enum intel_miptree_tr_mode {
 335    INTEL_MIPTREE_TRMODE_NONE,
 336    INTEL_MIPTREE_TRMODE_YF,
 337    INTEL_MIPTREE_TRMODE_YS
 338 };
 339
 340 struct intel_mipmap_tree
 341 {
 342    /** Buffer object containing the pixel data. */
 343    drm_intel_bo *bo;
 344
 345    uint32_t pitch; /**< pitch in bytes. */
 346
 347    uint32_t tiling; /**< One of the I915_TILING_* flags */
 348    enum intel_miptree_tr_mode tr_mode;
 349
 350    /* Effectively the key:
 351     */
 352    GLenum target;
 353
 354    /**
 355     * Generally, this is just the same as the gl_texture_image->TexFormat or
 356     * gl_renderbuffer->Format.
 357     *
 358     * However, for textures and renderbuffers with packed depth/stencil formats
 359     * on hardware where we want or need to use separate stencil, there will be
 360     * two miptrees for storing the data.  If the depthstencil texture or rb is
 361     * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
 362     * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
 363     * MESA_FORMAT_Z24_UNORM_X8_UINT.
 364     *
 365     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
 366     * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
 367     */
 368    mesa_format format;
 369
 370    /** This variable stores the value of ETC compressed texture format */
 371    mesa_format etc_format;
 372
 373    /**
 374     * The X offset of each image in the miptree must be aligned to this.
 375     * See the comments in brw_tex_layout.c.
 376     */
 377    unsigned int align_w;
 378    unsigned int align_h; /**< \see align_w */
 379
 380    GLuint first_level;
 381    GLuint last_level;
 382
 383    /**
 384     * Level zero image dimensions.  These dimensions correspond to the
 385     * physical layout of data in memory.  Accordingly, they account for the
 386     * extra width, height, and or depth that must be allocated in order to
 387     * accommodate multisample formats, and they account for the extra factor
 388     * of 6 in depth that must be allocated in order to accommodate cubemap
 389     * textures.
 390     */
 391    GLuint physical_width0, physical_height0, physical_depth0;
 392
 393    GLuint cpp; /**< bytes per pixel (or bytes per block if compressed) */
 394    GLuint num_samples;
 395    bool compressed;
 396
 397    /**
 398     * Level zero image dimensions.  These dimensions correspond to the
 399     * logical width, height, and depth of the texture as seen by client code.
 400     * Accordingly, they do not account for the extra width, height, and/or
 401     * depth that must be allocated in order to accommodate multisample
 402     * formats, nor do they account for the extra factor of 6 in depth that
 403     * must be allocated in order to accommodate cubemap textures.
 404     */
 405    uint32_t logical_width0, logical_height0, logical_depth0;
 406
 407    /**
 408     * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
 409     * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
 410     */
 411    enum miptree_array_layout array_layout;
 412
 413    /**
 414     * The distance in between array slices.
 415     *
 416     * The value is the one that is sent in the surface state. The actual
 417     * meaning depends on certain criteria. Usually it is simply the number of
 418     * uncompressed rows between each slice. However on Gen9+ for compressed
 419     * surfaces it is the number of blocks. For 1D array surfaces that have the
 420     * mipmap tree stored horizontally it is the number of pixels between each
 421     * slice.
 422     */
 423    uint32_t qpitch;
 424
 425    /**
 426     * MSAA layout used by this buffer.
 427     */
 428    enum intel_msaa_layout msaa_layout;
 429
 430    /* Derived from the above:
 431     */
 432    GLuint total_width;
 433    GLuint total_height;
 434
 435    /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to
 436     * this depth mipmap tree, if any.
 437     */
 438    uint32_t depth_clear_value;
 439
 440    /* Includes image offset tables:
 441     */
 442    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 443
 444    /* Offset into bo where miptree starts:
 445     */
 446    uint32_t offset;
 447
 448    /**
 449     * \brief HiZ aux buffer
 450     *
 451     * The hiz miptree contains the miptree's hiz buffer. To allocate the hiz
 452     * buffer, use intel_miptree_alloc_hiz().
 453     *
 454     * To determine if hiz is enabled, do not check this pointer. Instead, use
 455     * intel_miptree_slice_has_hiz().
 456     */
 457    struct intel_miptree_aux_buffer *hiz_buf;
 458
 459    /**
 460     * \brief Map of miptree slices to needed resolves.
 461     *
 462     * This is used only when the miptree has a child HiZ miptree.
 463     *
 464     * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
 465     * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
 466     * mt->hiz_mt->hiz_map, is unused.
 467     */
 468    struct exec_list hiz_map; /* List of intel_resolve_map. */
 469
 470    /**
 471     * \brief Stencil miptree for depthstencil textures.
 472     *
 473     * This miptree is used for depthstencil textures and renderbuffers that
 474     * require separate stencil.  It always has the true copy of the stencil
 475     * bits, regardless of mt->format.
 476     *
 477     * \see intel_miptree_map_depthstencil()
 478     * \see intel_miptree_unmap_depthstencil()
 479     */
 480    struct intel_mipmap_tree *stencil_mt;
 481
 482    /**
 483     * \brief MCS miptree.
 484     *
 485     * This miptree contains the "multisample control surface", which stores
 486     * the necessary information to implement compressed MSAA
 487     * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
 488     *
 489     * NULL if no MCS miptree is in use for this surface.
 490     */
 491    struct intel_mipmap_tree *mcs_mt;
 492
 493    /**
 494     * Fast clear state for this buffer.
 495     */
 496    enum intel_fast_clear_state fast_clear_state;
 497
 498    /**
 499     * The SURFACE_STATE bits associated with the last fast color clear to this
 500     * color mipmap tree, if any.
 501     *
 502     * This value will only ever contain ones in bits 28-31, so it is safe to
 503     * OR into dword 7 of SURFACE_STATE.
 504     */
 505    uint32_t fast_clear_color_value;
 506
 507    /**
 508     * Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS
 509     * buffer. This is useful for sharing the miptree bo with an external client
 510     * that doesn't understand auxiliary buffers.
 511     */
 512    bool disable_aux_buffers;
 513
 514    /* These are also refcounted:
 515     */
 516    GLuint refcount;
 517 };
 518
 519 void
 520 intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree *mt,
 521                                  unsigned *width_px, unsigned *height);
 522 bool
 523 intel_tiling_supports_non_msrt_mcs(struct brw_context *brw, unsigned tiling);
 524 bool
 525 intel_miptree_is_fast_clear_capable(struct brw_context *brw,
 526                                     struct intel_mipmap_tree *mt);
 527 bool
 528 intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
 529                                  struct intel_mipmap_tree *mt);
 530
 531 enum {
 532    MIPTREE_LAYOUT_ACCELERATED_UPLOAD       = 1 << 0,
 533    MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD   = 1 << 1,
 534    MIPTREE_LAYOUT_FOR_BO                   = 1 << 2,
 535    MIPTREE_LAYOUT_DISABLE_AUX              = 1 << 3,
 536    MIPTREE_LAYOUT_FORCE_HALIGN16           = 1 << 4,
 537
 538    MIPTREE_LAYOUT_TILING_Y                 = 1 << 5,
 539    MIPTREE_LAYOUT_TILING_NONE              = 1 << 6,
 540    MIPTREE_LAYOUT_TILING_ANY               = MIPTREE_LAYOUT_TILING_Y |
 541                                              MIPTREE_LAYOUT_TILING_NONE,
 542 };
 543
 544 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
 545                                                GLenum target,
 546                                                mesa_format format,
 547                                                GLuint first_level,
 548                                                GLuint last_level,
 549                                                GLuint width0,
 550                                                GLuint height0,
 551                                                GLuint depth0,
 552                                                GLuint num_samples,
 553                                                uint32_t flags);
 554
 555 struct intel_mipmap_tree *
 556 intel_miptree_create_for_bo(struct brw_context *brw,
 557                             drm_intel_bo *bo,
 558                             mesa_format format,
 559                             uint32_t offset,
 560                             uint32_t width,
 561                             uint32_t height,
 562                             uint32_t depth,
 563                             int pitch,
 564                             uint32_t layout_flags);
 565
 566 void
 567 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
 568                                          struct intel_renderbuffer *irb,
 569                                          drm_intel_bo *bo,
 570                                          uint32_t width, uint32_t height,
 571                                          uint32_t pitch);
 572
 573 /**
 574  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 575  * The miptree has the following properties:
 576  *     - The target is GL_TEXTURE_2D.
 577  *     - There are no levels other than the base level 0.
 578  *     - Depth is 1.
 579  */
 580 struct intel_mipmap_tree*
 581 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
 582                                       mesa_format format,
 583                                       uint32_t width,
 584                                       uint32_t height,
 585                                       uint32_t num_samples);
 586
 587 mesa_format
 588 intel_depth_format_for_depthstencil_format(mesa_format format);
 589
 590 mesa_format
 591 intel_lower_compressed_format(struct brw_context *brw, mesa_format format);
 592
 593 /** \brief Assert that the level and layer are valid for the miptree. */
 594 static inline void
 595 intel_miptree_check_level_layer(struct intel_mipmap_tree *mt,
 596                                 uint32_t level,
 597                                 uint32_t layer)
 598 {
 599    (void) mt;
 600    (void) level;
 601    (void) layer;
 602
 603    assert(level >= mt->first_level);
 604    assert(level <= mt->last_level);
 605    assert(layer < mt->level[level].depth);
 606 }
 607
 608 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 609                              struct intel_mipmap_tree *src);
 610
 611 void intel_miptree_release(struct intel_mipmap_tree **mt);
 612
 613 /* Check if an image fits an existing mipmap tree layout
 614  */
 615 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 616                                     struct gl_texture_image *image);
 617
 618 void
 619 intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt,
 620                                GLuint level, GLuint slice,
 621                                GLuint *x, GLuint *y);
 622
 623 void
 624 intel_get_image_dims(struct gl_texture_image *image,
 625                      int *width, int *height, int *depth);
 626
 627 void
 628 intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
 629                      bool map_stencil_as_y_tiled,
 630                      uint32_t *mask_x, uint32_t *mask_y);
 631
 632 void
 633 intel_get_tile_dims(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
 634                     uint32_t *tile_w, uint32_t *tile_h);
 635
 636 uint32_t
 637 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
 638                                GLuint level, GLuint slice,
 639                                uint32_t *tile_x,
 640                                uint32_t *tile_y);
 641 uint32_t
 642 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
 643                                  uint32_t x, uint32_t y,
 644                                  bool map_stencil_as_y_tiled);
 645
 646 void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
 647                                   GLuint level,
 648                                   GLuint x, GLuint y, GLuint d);
 649
 650 void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
 651                                     GLuint level,
 652                                     GLuint img, GLuint x, GLuint y);
 653
 654 void
 655 intel_miptree_copy_teximage(struct brw_context *brw,
 656                             struct intel_texture_image *intelImage,
 657                             struct intel_mipmap_tree *dst_mt, bool invalidate);
 658
 659 /**
 660  * \name Miptree HiZ functions
 661  * \{
 662  *
 663  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 664  * functions on a miptree without HiZ. In that case, each function is a no-op.
 665  */
 666
 667 bool
 668 intel_miptree_wants_hiz_buffer(struct brw_context *brw,
 669                                struct intel_mipmap_tree *mt);
 670
 671 /**
 672  * \brief Allocate the miptree's embedded HiZ miptree.
 673  * \see intel_mipmap_tree:hiz_mt
 674  * \return false if allocation failed
 675  */
 676 bool
 677 intel_miptree_alloc_hiz(struct brw_context *brw,
 678                         struct intel_mipmap_tree *mt);
 679
 680 bool
 681 intel_miptree_level_has_hiz(struct intel_mipmap_tree *mt, uint32_t level);
 682
 683 void
 684 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt,
 685                                           uint32_t level,
 686                                           uint32_t depth);
 687 void
 688 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt,
 689                                             uint32_t level,
 690                                             uint32_t depth);
 691
 692 void
 693 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree *mt,
 694                                                 uint32_t level);
 695
 696 /**
 697  * \return false if no resolve was needed
 698  */
 699 bool
 700 intel_miptree_slice_resolve_hiz(struct brw_context *brw,
 701                                 struct intel_mipmap_tree *mt,
 702                                 unsigned int level,
 703                                 unsigned int depth);
 704
 705 /**
 706  * \return false if no resolve was needed
 707  */
 708 bool
 709 intel_miptree_slice_resolve_depth(struct brw_context *brw,
 710                                   struct intel_mipmap_tree *mt,
 711                                   unsigned int level,
 712                                   unsigned int depth);
 713
 714 /**
 715  * \return false if no resolve was needed
 716  */
 717 bool
 718 intel_miptree_all_slices_resolve_hiz(struct brw_context *brw,
 719                                      struct intel_mipmap_tree *mt);
 720
 721 /**
 722  * \return false if no resolve was needed
 723  */
 724 bool
 725 intel_miptree_all_slices_resolve_depth(struct brw_context *brw,
 726                                        struct intel_mipmap_tree *mt);
 727
 728 /**\}*/
 729
 730 /**
 731  * Update the fast clear state for a miptree to indicate that it has been used
 732  * for rendering.
 733  */
 734 static inline void
 735 intel_miptree_used_for_rendering(struct intel_mipmap_tree *mt)
 736 {
 737    /* If the buffer was previously in fast clear state, change it to
 738     * unresolved state, since it won't be guaranteed to be clear after
 739     * rendering occurs.
 740     */
 741    if (mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR)
 742       mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
 743 }
 744
 745 void
 746 intel_miptree_resolve_color(struct brw_context *brw,
 747                             struct intel_mipmap_tree *mt);
 748
 749 void
 750 intel_miptree_make_shareable(struct brw_context *brw,
 751                              struct intel_mipmap_tree *mt);
 752
 753 void
 754 intel_miptree_updownsample(struct brw_context *brw,
 755                            struct intel_mipmap_tree *src,
 756                            struct intel_mipmap_tree *dst);
 757
 758 /**
 759  * Horizontal distance from one slice to the next in the two-dimensional
 760  * miptree layout.
 761  */
 762 unsigned
 763 brw_miptree_get_horizontal_slice_pitch(const struct brw_context *brw,
 764                                        const struct intel_mipmap_tree *mt,
 765                                        unsigned level);
 766
 767 /**
 768  * Vertical distance from one slice to the next in the two-dimensional miptree
 769  * layout.
 770  */
 771 unsigned
 772 brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw,
 773                                      const struct intel_mipmap_tree *mt,
 774                                      unsigned level);
 775
 776 void
 777 brw_miptree_layout(struct brw_context *brw,
 778                    struct intel_mipmap_tree *mt,
 779                    uint32_t layout_flags);
 780
 781 void
 782 intel_miptree_map(struct brw_context *brw,
 783                   struct intel_mipmap_tree *mt,
 784                   unsigned int level,
 785                   unsigned int slice,
 786                   unsigned int x,
 787                   unsigned int y,
 788                   unsigned int w,
 789                   unsigned int h,
 790                   GLbitfield mode,
 791                   void **out_ptr,
 792                   ptrdiff_t *out_stride);
 793
 794 void
 795 intel_miptree_unmap(struct brw_context *brw,
 796                     struct intel_mipmap_tree *mt,
 797                     unsigned int level,
 798                     unsigned int slice);
 799
 800 void
 801 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 802                unsigned int level, unsigned int layer, enum gen6_hiz_op op);
 803
 804 #ifdef __cplusplus
 805 }
 806 #endif
 807
 808 #endif