src/mesa/drivers/dri/i965/intel_mipmap_tree.h

   1 /**************************************************************************
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   3  * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
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  16  * of the Software.
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  27
  28 #ifndef INTEL_MIPMAP_TREE_H
  29 #define INTEL_MIPMAP_TREE_H
  30
  31 #include <assert.h>
  32
  33 #include "intel_regions.h"
  34 #include "intel_resolve_map.h"
  35
  36 #ifdef __cplusplus
  37 extern "C" {
  38 #endif
  39
  40 /* A layer on top of the intel_regions code which adds:
  41  *
  42  * - Code to size and layout a region to hold a set of mipmaps.
  43  * - Query to determine if a new image fits in an existing tree.
  44  * - More refcounting
  45  *     - maybe able to remove refcounting from intel_region?
  46  * - ?
  47  *
  48  * The fixed mipmap layout of intel hardware where one offset
  49  * specifies the position of all images in a mipmap hierachy
  50  * complicates the implementation of GL texture image commands,
  51  * compared to hardware where each image is specified with an
  52  * independent offset.
  53  *
  54  * In an ideal world, each texture object would be associated with a
  55  * single bufmgr buffer or 2d intel_region, and all the images within
  56  * the texture object would slot into the tree as they arrive.  The
  57  * reality can be a little messier, as images can arrive from the user
  58  * with sizes that don't fit in the existing tree, or in an order
  59  * where the tree layout cannot be guessed immediately.
  60  *
  61  * This structure encodes an idealized mipmap tree.  The GL image
  62  * commands build these where possible, otherwise store the images in
  63  * temporary system buffers.
  64  */
  65
  66 struct intel_resolve_map;
  67 struct intel_texture_image;
  68
  69 /**
  70  * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
  71  * depthstencil-split-to-separate-stencil miptree, we'll normally make a
  72  * tmeporary and recreate the kind of data requested by Mesa core, since we're
  73  * satisfying some glGetTexImage() request or something.
  74  *
  75  * However, occasionally you want to actually map the miptree's current data
  76  * without transcoding back.  This flag to intel_miptree_map() gets you that.
  77  */
  78 #define BRW_MAP_DIRECT_BIT      0x80000000
  79
  80 struct intel_miptree_map {
  81    /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
  82    GLbitfield mode;
  83    /** Region of interest for the map. */
  84    int x, y, w, h;
  85    /** Possibly malloced temporary buffer for the mapping. */
  86    void *buffer;
  87    /** Possible pointer to a temporary linear miptree for the mapping. */
  88    struct intel_mipmap_tree *mt;
  89    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  90    void *ptr;
  91    /** Stride of the mapping. */
  92    int stride;
  93
  94    /**
  95     * intel_mipmap_tree::singlesample_mt is temporary storage that persists
  96     * only for the duration of the map.
  97     */
  98    bool singlesample_mt_is_tmp;
  99 };
 100
 101 /**
 102  * Describes the location of each texture image within a texture region.
 103  */
 104 struct intel_mipmap_level
 105 {
 106    /** Offset to this miptree level, used in computing x_offset. */
 107    GLuint level_x;
 108    /** Offset to this miptree level, used in computing y_offset. */
 109    GLuint level_y;
 110    GLuint width;
 111    GLuint height;
 112
 113    /**
 114     * \brief Number of 2D slices in this miplevel.
 115     *
 116     * The exact semantics of depth varies according to the texture target:
 117     *    - For GL_TEXTURE_CUBE_MAP, depth is 6.
 118     *    - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
 119     *      identical for all miplevels in the texture.
 120     *    - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
 121     *      value, like width and height, varies with miplevel.
 122     *    - For other texture types, depth is 1.
 123     */
 124    GLuint depth;
 125
 126    /**
 127     * \brief List of 2D images in this mipmap level.
 128     *
 129     * This may be a list of cube faces, array slices in 2D array texture, or
 130     * layers in a 3D texture. The list's length is \c depth.
 131     */
 132    struct intel_mipmap_slice {
 133       /**
 134        * \name Offset to slice
 135        * \{
 136        *
 137        * Hardware formats are so diverse that that there is no unified way to
 138        * compute the slice offsets, so we store them in this table.
 139        *
 140        * The (x, y) offset to slice \c s at level \c l relative the miptrees
 141        * base address is
 142        * \code
 143        *     x = mt->level[l].slice[s].x_offset
 144        *     y = mt->level[l].slice[s].y_offset
 145        */
 146       GLuint x_offset;
 147       GLuint y_offset;
 148       /** \} */
 149
 150       /**
 151        * Mapping information. Persistent for the duration of
 152        * intel_miptree_map/unmap on this slice.
 153        */
 154       struct intel_miptree_map *map;
 155
 156       /**
 157        * \brief Is HiZ enabled for this slice?
 158        *
 159        * If \c mt->level[l].slice[s].has_hiz is set, then (1) \c mt->hiz_mt
 160        * has been allocated and (2) the HiZ memory corresponding to this slice
 161        * resides at \c mt->hiz_mt->level[l].slice[s].
 162        */
 163       bool has_hiz;
 164    } *slice;
 165 };
 166
 167 /**
 168  * Enum for keeping track of the different MSAA layouts supported by Gen7.
 169  */
 170 enum intel_msaa_layout
 171 {
 172    /**
 173     * Ordinary surface with no MSAA.
 174     */
 175    INTEL_MSAA_LAYOUT_NONE,
 176
 177    /**
 178     * Interleaved Multisample Surface.  The additional samples are
 179     * accommodated by scaling up the width and the height of the surface so
 180     * that all the samples corresponding to a pixel are located at nearby
 181     * memory locations.
 182     */
 183    INTEL_MSAA_LAYOUT_IMS,
 184
 185    /**
 186     * Uncompressed Multisample Surface.  The surface is stored as a 2D array,
 187     * with array slice n containing all pixel data for sample n.
 188     */
 189    INTEL_MSAA_LAYOUT_UMS,
 190
 191    /**
 192     * Compressed Multisample Surface.  The surface is stored as in
 193     * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
 194     * (Multisample Control Surface) buffer.  Each pixel in the MCS buffer
 195     * indicates the mapping from sample number to array slice.  This allows
 196     * the common case (where all samples constituting a pixel have the same
 197     * color value) to be stored efficiently by just using a single array
 198     * slice.
 199     */
 200    INTEL_MSAA_LAYOUT_CMS,
 201 };
 202
 203
 204 /**
 205  * Enum for keeping track of the state of an MCS buffer associated with a
 206  * miptree.  This determines when fast clear related operations are needed.
 207  *
 208  * Fast clear works by deferring the memory writes that would be used to clear
 209  * the buffer, so that instead of performing them at the time of the clear
 210  * operation, the hardware automatically performs them at the time that the
 211  * buffer is later accessed for rendering.  The MCS buffer keeps track of
 212  * which regions of the buffer still have pending clear writes.
 213  *
 214  * This enum keeps track of the driver's knowledge of the state of the MCS
 215  * buffer.
 216  *
 217  * MCS buffers only exist on Gen7+.
 218  */
 219 enum intel_mcs_state
 220 {
 221    /**
 222     * There is no MCS buffer for this miptree, and one should never be
 223     * allocated.
 224     */
 225    INTEL_MCS_STATE_NONE,
 226
 227    /**
 228     * An MCS buffer exists for this miptree, and it is used for MSAA purposes.
 229     */
 230    INTEL_MCS_STATE_MSAA,
 231
 232    /**
 233     * No deferred clears are pending for this miptree, and the contents of the
 234     * color buffer are entirely correct.  An MCS buffer may or may not exist
 235     * for this miptree.  If it does exist, it is entirely in the "no deferred
 236     * clears pending" state.  If it does not exist, it will be created the
 237     * first time a fast color clear is executed.
 238     *
 239     * In this state, the color buffer can be used for purposes other than
 240     * rendering without needing a render target resolve.
 241     */
 242    INTEL_MCS_STATE_RESOLVED,
 243
 244    /**
 245     * An MCS buffer exists for this miptree, and deferred clears are pending
 246     * for some regions of the color buffer, as indicated by the MCS buffer.
 247     * The contents of the color buffer are only correct for the regions where
 248     * the MCS buffer doesn't indicate a deferred clear.
 249     *
 250     * In this state, a render target resolve must be performed before the
 251     * color buffer can be used for purposes other than rendering.
 252     */
 253    INTEL_MCS_STATE_UNRESOLVED,
 254
 255    /**
 256     * An MCS buffer exists for this miptree, and deferred clears are pending
 257     * for the entire color buffer, and the contents of the MCS buffer reflect
 258     * this.  The contents of the color buffer are undefined.
 259     *
 260     * In this state, a render target resolve must be performed before the
 261     * color buffer can be used for purposes other than rendering.
 262     *
 263     * If the client attempts to clear a buffer which is already in this state,
 264     * the clear can be safely skipped, since the buffer is already clear.
 265     */
 266    INTEL_MCS_STATE_CLEAR,
 267 };
 268
 269 struct intel_mipmap_tree
 270 {
 271    /* Effectively the key:
 272     */
 273    GLenum target;
 274
 275    /**
 276     * Generally, this is just the same as the gl_texture_image->TexFormat or
 277     * gl_renderbuffer->Format.
 278     *
 279     * However, for textures and renderbuffers with packed depth/stencil formats
 280     * on hardware where we want or need to use separate stencil, there will be
 281     * two miptrees for storing the data.  If the depthstencil texture or rb is
 282     * MESA_FORMAT_Z32_FLOAT_X24S8, then mt->format will be
 283     * MESA_FORMAT_Z32_FLOAT, otherwise for MESA_FORMAT_S8_Z24 objects it will be
 284     * MESA_FORMAT_X8_Z24.
 285     *
 286     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
 287     * formats if the hardware lacks support for ETC1/ETC2. See @ref wraps_etc.
 288     */
 289    gl_format format;
 290
 291    /** This variable stores the value of ETC compressed texture format */
 292    gl_format etc_format;
 293
 294    /**
 295     * The X offset of each image in the miptree must be aligned to this. See
 296     * the "Alignment Unit Size" section of the BSpec.
 297     */
 298    unsigned int align_w;
 299    unsigned int align_h; /**< \see align_w */
 300
 301    GLuint first_level;
 302    GLuint last_level;
 303
 304    /**
 305     * Level zero image dimensions.  These dimensions correspond to the
 306     * physical layout of data in memory.  Accordingly, they account for the
 307     * extra width, height, and or depth that must be allocated in order to
 308     * accommodate multisample formats, and they account for the extra factor
 309     * of 6 in depth that must be allocated in order to accommodate cubemap
 310     * textures.
 311     */
 312    GLuint physical_width0, physical_height0, physical_depth0;
 313
 314    GLuint cpp;
 315    GLuint num_samples;
 316    bool compressed;
 317
 318    /**
 319     * Level zero image dimensions.  These dimensions correspond to the
 320     * logical width, height, and depth of the region as seen by client code.
 321     * Accordingly, they do not account for the extra width, height, and/or
 322     * depth that must be allocated in order to accommodate multisample
 323     * formats, nor do they account for the extra factor of 6 in depth that
 324     * must be allocated in order to accommodate cubemap textures.
 325     */
 326    uint32_t logical_width0, logical_height0, logical_depth0;
 327
 328    /**
 329     * For 1D array, 2D array, cube, and 2D multisampled surfaces on Gen7: true
 330     * if the surface only contains LOD 0, and hence no space is for LOD's
 331     * other than 0 in between array slices.
 332     *
 333     * Corresponds to the surface_array_spacing bit in gen7_surface_state.
 334     */
 335    bool array_spacing_lod0;
 336
 337    /**
 338     * MSAA layout used by this buffer.
 339     */
 340    enum intel_msaa_layout msaa_layout;
 341
 342    /* Derived from the above:
 343     */
 344    GLuint total_width;
 345    GLuint total_height;
 346
 347    /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to
 348     * this depth mipmap tree, if any.
 349     */
 350    uint32_t depth_clear_value;
 351
 352    /* Includes image offset tables:
 353     */
 354    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 355
 356    /* The data is held here:
 357     */
 358    struct intel_region *region;
 359
 360    /* Offset into region bo where miptree starts:
 361     */
 362    uint32_t offset;
 363
 364    /**
 365     * \brief Singlesample miptree.
 366     *
 367     * This is used under two cases.
 368     *
 369     * --- Case 1: As persistent singlesample storage for multisample window
 370     *  system front and back buffers ---
 371     *
 372     * Suppose that the window system FBO was created with a multisample
 373     * config.  Let `back_irb` be the `intel_renderbuffer` for the FBO's back
 374     * buffer. Then `back_irb` contains two miptrees: a parent multisample
 375     * miptree (back_irb->mt) and a child singlesample miptree
 376     * (back_irb->mt->singlesample_mt).  The DRM buffer shared with DRI2
 377     * belongs to `back_irb->mt->singlesample_mt` and contains singlesample
 378     * data.  The singlesample miptree is created at the same time as and
 379     * persists for the lifetime of its parent multisample miptree.
 380     *
 381     * When access to the singlesample data is needed, such as at
 382     * eglSwapBuffers and glReadPixels, an automatic downsample occurs from
 383     * `back_rb->mt` to `back_rb->mt->singlesample_mt` when necessary.
 384     *
 385     * This description of the back buffer applies analogously to the front
 386     * buffer.
 387     *
 388     *
 389     * --- Case 2: As temporary singlesample storage for mapping multisample
 390     *  miptrees ---
 391     *
 392     * Suppose the intel_miptree_map is called on a multisample miptree, `mt`,
 393     * for which case 1 does not apply (that is, `mt` does not belong to
 394     * a front or back buffer).  Then `mt->singlesample_mt` is null at the
 395     * start of the call. intel_miptree_map will create a temporary
 396     * singlesample miptree, store it at `mt->singlesample_mt`, downsample from
 397     * `mt` to `mt->singlesample_mt` if necessary, then map
 398     * `mt->singlesample_mt`. The temporary miptree is later deleted during
 399     * intel_miptree_unmap.
 400     */
 401    struct intel_mipmap_tree *singlesample_mt;
 402
 403    /**
 404     * \brief A downsample is needed from this miptree to singlesample_mt.
 405     */
 406    bool need_downsample;
 407
 408    /**
 409     * \brief HiZ miptree
 410     *
 411     * The hiz miptree contains the miptree's hiz buffer. To allocate the hiz
 412     * miptree, use intel_miptree_alloc_hiz().
 413     *
 414     * To determine if hiz is enabled, do not check this pointer. Instead, use
 415     * intel_miptree_slice_has_hiz().
 416     */
 417    struct intel_mipmap_tree *hiz_mt;
 418
 419    /**
 420     * \brief Map of miptree slices to needed resolves.
 421     *
 422     * This is used only when the miptree has a child HiZ miptree.
 423     *
 424     * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
 425     * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
 426     * mt->hiz_mt->hiz_map, is unused.
 427     */
 428    struct intel_resolve_map hiz_map;
 429
 430    /**
 431     * \brief Stencil miptree for depthstencil textures.
 432     *
 433     * This miptree is used for depthstencil textures and renderbuffers that
 434     * require separate stencil.  It always has the true copy of the stencil
 435     * bits, regardless of mt->format.
 436     *
 437     * \see intel_miptree_map_depthstencil()
 438     * \see intel_miptree_unmap_depthstencil()
 439     */
 440    struct intel_mipmap_tree *stencil_mt;
 441
 442    /**
 443     * \brief MCS miptree.
 444     *
 445     * This miptree contains the "multisample control surface", which stores
 446     * the necessary information to implement compressed MSAA
 447     * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
 448     *
 449     * NULL if no MCS miptree is in use for this surface.
 450     */
 451    struct intel_mipmap_tree *mcs_mt;
 452
 453    /**
 454     * MCS state for this buffer.
 455     */
 456    enum intel_mcs_state mcs_state;
 457
 458    /**
 459     * The SURFACE_STATE bits associated with the last fast color clear to this
 460     * color mipmap tree, if any.
 461     *
 462     * This value will only ever contain ones in bits 28-31, so it is safe to
 463     * OR into dword 7 of SURFACE_STATE.
 464     */
 465    uint32_t fast_clear_color_value;
 466
 467    /* These are also refcounted:
 468     */
 469    GLuint refcount;
 470 };
 471
 472 enum intel_miptree_tiling_mode {
 473    INTEL_MIPTREE_TILING_ANY,
 474    INTEL_MIPTREE_TILING_Y,
 475    INTEL_MIPTREE_TILING_NONE,
 476 };
 477
 478 bool
 479 intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
 480                                        struct intel_mipmap_tree *mt);
 481
 482 void
 483 intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
 484                                  struct intel_mipmap_tree *mt,
 485                                  unsigned *width_px, unsigned *height);
 486
 487 bool
 488 intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
 489                                  struct intel_mipmap_tree *mt);
 490
 491 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
 492                                                GLenum target,
 493                                                gl_format format,
 494                                                GLuint first_level,
 495                                                GLuint last_level,
 496                                                GLuint width0,
 497                                                GLuint height0,
 498                                                GLuint depth0,
 499                                                bool expect_accelerated_upload,
 500                                                GLuint num_samples,
 501                                                enum intel_miptree_tiling_mode);
 502
 503 struct intel_mipmap_tree *
 504 intel_miptree_create_layout(struct brw_context *brw,
 505                             GLenum target,
 506                             gl_format format,
 507                             GLuint first_level,
 508                             GLuint last_level,
 509                             GLuint width0,
 510                             GLuint height0,
 511                             GLuint depth0,
 512                             bool for_bo,
 513                             GLuint num_samples);
 514
 515 struct intel_mipmap_tree *
 516 intel_miptree_create_for_bo(struct brw_context *brw,
 517                             drm_intel_bo *bo,
 518                             gl_format format,
 519                             uint32_t offset,
 520                             uint32_t width,
 521                             uint32_t height,
 522                             int pitch,
 523                             uint32_t tiling);
 524
 525 struct intel_mipmap_tree*
 526 intel_miptree_create_for_dri2_buffer(struct brw_context *brw,
 527                                      unsigned dri_attachment,
 528                                      gl_format format,
 529                                      uint32_t num_samples,
 530                                      struct intel_region *region);
 531
 532 /**
 533  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 534  * The miptree has the following properties:
 535  *     - The target is GL_TEXTURE_2D.
 536  *     - There are no levels other than the base level 0.
 537  *     - Depth is 1.
 538  */
 539 struct intel_mipmap_tree*
 540 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
 541                                       gl_format format,
 542                                       uint32_t width,
 543                                       uint32_t height,
 544                                       uint32_t num_samples);
 545
 546 /** \brief Assert that the level and layer are valid for the miptree. */
 547 static inline void
 548 intel_miptree_check_level_layer(struct intel_mipmap_tree *mt,
 549                                 uint32_t level,
 550                                 uint32_t layer)
 551 {
 552    assert(level >= mt->first_level);
 553    assert(level <= mt->last_level);
 554    assert(layer < mt->level[level].depth);
 555 }
 556
 557 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 558                              struct intel_mipmap_tree *src);
 559
 560 void intel_miptree_release(struct intel_mipmap_tree **mt);
 561
 562 /* Check if an image fits an existing mipmap tree layout
 563  */
 564 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 565                                     struct gl_texture_image *image);
 566
 567 void
 568 intel_miptree_get_image_offset(struct intel_mipmap_tree *mt,
 569                                GLuint level, GLuint slice,
 570                                GLuint *x, GLuint *y);
 571
 572 void
 573 intel_miptree_get_dimensions_for_image(struct gl_texture_image *image,
 574                                        int *width, int *height, int *depth);
 575
 576 uint32_t
 577 intel_miptree_get_tile_offsets(struct intel_mipmap_tree *mt,
 578                                GLuint level, GLuint slice,
 579                                uint32_t *tile_x,
 580                                uint32_t *tile_y);
 581
 582 void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
 583                                   GLuint level,
 584                                   GLuint x, GLuint y,
 585                                   GLuint w, GLuint h, GLuint d);
 586
 587 void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
 588                                     GLuint level,
 589                                     GLuint img, GLuint x, GLuint y);
 590
 591 void
 592 intel_miptree_copy_teximage(struct brw_context *brw,
 593                             struct intel_texture_image *intelImage,
 594                             struct intel_mipmap_tree *dst_mt, bool invalidate);
 595
 596 bool
 597 intel_miptree_alloc_mcs(struct brw_context *brw,
 598                         struct intel_mipmap_tree *mt,
 599                         GLuint num_samples);
 600
 601 /**
 602  * \name Miptree HiZ functions
 603  * \{
 604  *
 605  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 606  * functions on a miptree without HiZ. In that case, each function is a no-op.
 607  */
 608
 609 /**
 610  * \brief Allocate the miptree's embedded HiZ miptree.
 611  * \see intel_mipmap_tree:hiz_mt
 612  * \return false if allocation failed
 613  */
 614
 615 bool
 616 intel_miptree_alloc_hiz(struct brw_context *brw,
 617                         struct intel_mipmap_tree *mt);
 618
 619 bool
 620 intel_miptree_slice_has_hiz(struct intel_mipmap_tree *mt,
 621                             uint32_t level,
 622                             uint32_t layer);
 623
 624 void
 625 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt,
 626                                           uint32_t level,
 627                                           uint32_t depth);
 628 void
 629 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt,
 630                                             uint32_t level,
 631                                             uint32_t depth);
 632
 633 /**
 634  * \return false if no resolve was needed
 635  */
 636 bool
 637 intel_miptree_slice_resolve_hiz(struct brw_context *brw,
 638                                 struct intel_mipmap_tree *mt,
 639                                 unsigned int level,
 640                                 unsigned int depth);
 641
 642 /**
 643  * \return false if no resolve was needed
 644  */
 645 bool
 646 intel_miptree_slice_resolve_depth(struct brw_context *brw,
 647                                   struct intel_mipmap_tree *mt,
 648                                   unsigned int level,
 649                                   unsigned int depth);
 650
 651 /**
 652  * \return false if no resolve was needed
 653  */
 654 bool
 655 intel_miptree_all_slices_resolve_hiz(struct brw_context *brw,
 656                                      struct intel_mipmap_tree *mt);
 657
 658 /**
 659  * \return false if no resolve was needed
 660  */
 661 bool
 662 intel_miptree_all_slices_resolve_depth(struct brw_context *brw,
 663                                        struct intel_mipmap_tree *mt);
 664
 665 /**\}*/
 666
 667 /**
 668  * Update the fast clear state for a miptree to indicate that it has been used
 669  * for rendering.
 670  */
 671 static inline void
 672 intel_miptree_used_for_rendering(struct intel_mipmap_tree *mt)
 673 {
 674    /* If the buffer was previously in fast clear state, change it to
 675     * unresolved state, since it won't be guaranteed to be clear after
 676     * rendering occurs.
 677     */
 678    if (mt->mcs_state == INTEL_MCS_STATE_CLEAR)
 679       mt->mcs_state = INTEL_MCS_STATE_UNRESOLVED;
 680 }
 681
 682 void
 683 intel_miptree_resolve_color(struct brw_context *brw,
 684                             struct intel_mipmap_tree *mt);
 685
 686 void
 687 intel_miptree_make_shareable(struct brw_context *brw,
 688                              struct intel_mipmap_tree *mt);
 689
 690 void
 691 intel_miptree_downsample(struct brw_context *brw,
 692                          struct intel_mipmap_tree *mt);
 693
 694 void
 695 intel_miptree_upsample(struct brw_context *brw,
 696                        struct intel_mipmap_tree *mt);
 697
 698 void brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt);
 699
 700 void *intel_miptree_map_raw(struct brw_context *brw,
 701                             struct intel_mipmap_tree *mt);
 702
 703 void intel_miptree_unmap_raw(struct brw_context *brw,
 704                              struct intel_mipmap_tree *mt);
 705
 706 void
 707 intel_miptree_map(struct brw_context *brw,
 708                   struct intel_mipmap_tree *mt,
 709                   unsigned int level,
 710                   unsigned int slice,
 711                   unsigned int x,
 712                   unsigned int y,
 713                   unsigned int w,
 714                   unsigned int h,
 715                   GLbitfield mode,
 716                   void **out_ptr,
 717                   int *out_stride);
 718
 719 void
 720 intel_miptree_unmap(struct brw_context *brw,
 721                     struct intel_mipmap_tree *mt,
 722                     unsigned int level,
 723                     unsigned int slice);
 724
 725 void
 726 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 727                unsigned int level, unsigned int layer, enum gen6_hiz_op op);
 728
 729 #ifdef __cplusplus
 730 }
 731 #endif
 732
 733 #endif