src/mesa/drivers/dri/i965/intel_mipmap_tree.h

   1 /*
   2  * Copyright 2006 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 /** @file intel_mipmap_tree.h
  27  *
  28  * This file defines the structure that wraps a BO and describes how the
  29  * mipmap levels and slices of a texture are laid out.
  30  *
  31  * The hardware has a fixed layout of a texture depending on parameters such
  32  * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
  33  * mipmap levels.  The individual level/layer slices are each 2D rectangles of
  34  * pixels at some x/y offset from the start of the drm_intel_bo.
  35  *
  36  * Original OpenGL allowed texture miplevels to be specified in arbitrary
  37  * order, and a texture may change size over time.  Thus, each
  38  * intel_texture_image has a reference to a miptree that contains the pixel
  39  * data sized appropriately for it, which will later be referenced by/copied
  40  * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
  41  * that there's a single miptree for the complete texture.
  42  */
  43
  44 #ifndef INTEL_MIPMAP_TREE_H
  45 #define INTEL_MIPMAP_TREE_H
  46
  47 #include <assert.h>
  48
  49 #include "main/mtypes.h"
  50 #include "isl/isl.h"
  51 #include "intel_bufmgr.h"
  52 #include "intel_resolve_map.h"
  53 #include <GL/internal/dri_interface.h>
  54
  55 #ifdef __cplusplus
  56 extern "C" {
  57 #endif
  58
  59 struct brw_context;
  60 struct intel_renderbuffer;
  61
  62 struct intel_resolve_map;
  63 struct intel_texture_image;
  64
  65 /**
  66  * This bit extends the set of GL_MAP_*_BIT enums.
  67  *
  68  * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
  69  * depthstencil-split-to-separate-stencil miptree, we'll normally make a
  70  * temporary and recreate the kind of data requested by Mesa core, since we're
  71  * satisfying some glGetTexImage() request or something.
  72  *
  73  * However, occasionally you want to actually map the miptree's current data
  74  * without transcoding back.  This flag to intel_miptree_map() gets you that.
  75  */
  76 #define BRW_MAP_DIRECT_BIT      0x80000000
  77
  78 struct intel_miptree_map {
  79    /** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */
  80    GLbitfield mode;
  81    /** Region of interest for the map. */
  82    int x, y, w, h;
  83    /** Possibly malloced temporary buffer for the mapping. */
  84    void *buffer;
  85    /** Possible pointer to a temporary linear miptree for the mapping. */
  86    struct intel_mipmap_tree *linear_mt;
  87    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  88    void *ptr;
  89    /** Stride of the mapping. */
  90    int stride;
  91 };
  92
  93 /**
  94  * Describes the location of each texture image within a miptree.
  95  */
  96 struct intel_mipmap_level
  97 {
  98    /** Offset to this miptree level, used in computing x_offset. */
  99    GLuint level_x;
 100    /** Offset to this miptree level, used in computing y_offset. */
 101    GLuint level_y;
 102
 103    /**
 104     * \brief Number of 2D slices in this miplevel.
 105     *
 106     * The exact semantics of depth varies according to the texture target:
 107     *    - For GL_TEXTURE_CUBE_MAP, depth is 6.
 108     *    - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
 109     *      identical for all miplevels in the texture.
 110     *    - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
 111     *      value, like width and height, varies with miplevel.
 112     *    - For other texture types, depth is 1.
 113     *    - Additionally, for UMS and CMS miptrees, depth is multiplied by
 114     *      sample count.
 115     */
 116    GLuint depth;
 117
 118    /**
 119     * \brief Is HiZ enabled for this level?
 120     *
 121     * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
 122     * allocated and (2) the HiZ memory for the slices in this level reside at
 123     * \c mt->hiz_mt->level[l].
 124     */
 125    bool has_hiz;
 126
 127    /**
 128     * \brief List of 2D images in this mipmap level.
 129     *
 130     * This may be a list of cube faces, array slices in 2D array texture, or
 131     * layers in a 3D texture. The list's length is \c depth.
 132     */
 133    struct intel_mipmap_slice {
 134       /**
 135        * \name Offset to slice
 136        * \{
 137        *
 138        * Hardware formats are so diverse that that there is no unified way to
 139        * compute the slice offsets, so we store them in this table.
 140        *
 141        * The (x, y) offset to slice \c s at level \c l relative the miptrees
 142        * base address is
 143        * \code
 144        *     x = mt->level[l].slice[s].x_offset
 145        *     y = mt->level[l].slice[s].y_offset
 146        *
 147        * On some hardware generations, we program these offsets into
 148        * RENDER_SURFACE_STATE.XOffset and RENDER_SURFACE_STATE.YOffset.
 149        */
 150       GLuint x_offset;
 151       GLuint y_offset;
 152       /** \} */
 153
 154       /**
 155        * Mapping information. Persistent for the duration of
 156        * intel_miptree_map/unmap on this slice.
 157        */
 158       struct intel_miptree_map *map;
 159    } *slice;
 160 };
 161
 162 /**
 163  * Enum for keeping track of the different MSAA layouts supported by Gen7.
 164  */
 165 enum intel_msaa_layout
 166 {
 167    /**
 168     * Ordinary surface with no MSAA.
 169     */
 170    INTEL_MSAA_LAYOUT_NONE,
 171
 172    /**
 173     * Interleaved Multisample Surface.  The additional samples are
 174     * accommodated by scaling up the width and the height of the surface so
 175     * that all the samples corresponding to a pixel are located at nearby
 176     * memory locations.
 177     *
 178     * @see PRM section "Interleaved Multisampled Surfaces"
 179     */
 180    INTEL_MSAA_LAYOUT_IMS,
 181
 182    /**
 183     * Uncompressed Multisample Surface.  The surface is stored as a 2D array,
 184     * with array slice n containing all pixel data for sample n.
 185     *
 186     * @see PRM section "Uncompressed Multisampled Surfaces"
 187     */
 188    INTEL_MSAA_LAYOUT_UMS,
 189
 190    /**
 191     * Compressed Multisample Surface.  The surface is stored as in
 192     * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
 193     * (Multisample Control Surface) buffer.  Each pixel in the MCS buffer
 194     * indicates the mapping from sample number to array slice.  This allows
 195     * the common case (where all samples constituting a pixel have the same
 196     * color value) to be stored efficiently by just using a single array
 197     * slice.
 198     *
 199     * @see PRM section "Compressed Multisampled Surfaces"
 200     */
 201    INTEL_MSAA_LAYOUT_CMS,
 202 };
 203
 204 enum miptree_array_layout {
 205    /* Each array slice contains all miplevels packed together.
 206     *
 207     * Gen hardware usually wants multilevel miptrees configured this way.
 208     *
 209     * A 2D Array texture with 2 slices and multiple LODs using
 210     * ALL_LOD_IN_EACH_SLICE would look somewhat like this:
 211     *
 212     *   +----------+
 213     *   |          |
 214     *   |          |
 215     *   +----------+
 216     *   +---+ +-+
 217     *   |   | +-+
 218     *   +---+ *
 219     *   +----------+
 220     *   |          |
 221     *   |          |
 222     *   +----------+
 223     *   +---+ +-+
 224     *   |   | +-+
 225     *   +---+ *
 226     */
 227    ALL_LOD_IN_EACH_SLICE,
 228
 229    /* Each LOD contains all slices of that LOD packed together.
 230     *
 231     * In some situations, Gen7+ hardware can use the array_spacing_lod0
 232     * feature to save space when the surface only contains LOD 0.
 233     *
 234     * Gen6 uses this for separate stencil and hiz since gen6 does not support
 235     * multiple LODs for separate stencil and hiz.
 236     *
 237     * A 2D Array texture with 2 slices and multiple LODs using
 238     * ALL_SLICES_AT_EACH_LOD would look somewhat like this:
 239     *
 240     *   +----------+
 241     *   |          |
 242     *   |          |
 243     *   +----------+
 244     *   |          |
 245     *   |          |
 246     *   +----------+
 247     *   +---+ +-+
 248     *   |   | +-+
 249     *   +---+ +-+
 250     *   |   | :
 251     *   +---+
 252     */
 253    ALL_SLICES_AT_EACH_LOD,
 254 };
 255
 256 enum intel_aux_disable {
 257    INTEL_AUX_DISABLE_NONE = 0,
 258    INTEL_AUX_DISABLE_HIZ  = 1 << 1,
 259    INTEL_AUX_DISABLE_MCS  = 1 << 2,
 260    INTEL_AUX_DISABLE_ALL  = INTEL_AUX_DISABLE_HIZ |
 261                             INTEL_AUX_DISABLE_MCS
 262 };
 263
 264 /**
 265  * Miptree aux buffer. These buffers are associated with a miptree, but the
 266  * format is managed by the hardware.
 267  *
 268  * For Gen7+, we always give the hardware the start of the buffer, and let it
 269  * handle all accesses to the buffer. Therefore we don't need the full miptree
 270  * layout structure for this buffer.
 271  */
 272 struct intel_miptree_aux_buffer
 273 {
 274    /**
 275     * Buffer object containing the pixel data.
 276     *
 277     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 278     * @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
 279     */
 280    drm_intel_bo *bo;
 281
 282    /**
 283     * Offset into bo where the surface starts.
 284     *
 285     * @see intel_mipmap_aux_buffer::bo
 286     *
 287     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 288     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 289     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 290     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 291     */
 292    uint32_t offset;
 293
 294    /*
 295     * Size of the MCS surface.
 296     *
 297     * This is needed when doing any gtt mapped operations on the buffer (which
 298     * will be Y-tiled). It is possible that it will not be the same as bo->size
 299     * when the drm allocator rounds up the requested size.
 300     */
 301    size_t size;
 302
 303    /**
 304     * Pitch in bytes.
 305     *
 306     * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
 307     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
 308     */
 309    uint32_t pitch;
 310
 311    /**
 312     * The distance in rows between array slices.
 313     *
 314     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch
 315     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
 316     */
 317    uint32_t qpitch;
 318 };
 319 /**
 320  * The HiZ buffer requires extra attributes on earlier GENs. This is easily
 321  * contained within an intel_mipmap_tree. To make sure we do not abuse this, we
 322  * keep the hiz datastructure separate.
 323  */
 324 struct intel_miptree_hiz_buffer
 325 {
 326    struct intel_miptree_aux_buffer aux_base;
 327
 328    /**
 329     * Hiz miptree. Used only by Gen6.
 330     */
 331    struct intel_mipmap_tree *mt;
 332 };
 333
 334 /* Tile resource modes */
 335 enum intel_miptree_tr_mode {
 336    INTEL_MIPTREE_TRMODE_NONE,
 337    INTEL_MIPTREE_TRMODE_YF,
 338    INTEL_MIPTREE_TRMODE_YS
 339 };
 340
 341 struct intel_mipmap_tree
 342 {
 343    /**
 344     * Buffer object containing the surface.
 345     *
 346     * @see intel_mipmap_tree::offset
 347     * @see RENDER_SURFACE_STATE.SurfaceBaseAddress
 348     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 349     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 350     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 351     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 352     */
 353    drm_intel_bo *bo;
 354
 355    /**
 356     * Pitch in bytes.
 357     *
 358     * @see RENDER_SURFACE_STATE.SurfacePitch
 359     * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
 360     * @see 3DSTATE_DEPTH_BUFFER.SurfacePitch
 361     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
 362     * @see 3DSTATE_STENCIL_BUFFER.SurfacePitch
 363     */
 364    uint32_t pitch;
 365
 366    /**
 367     * One of the I915_TILING_* flags.
 368     *
 369     * @see RENDER_SURFACE_STATE.TileMode
 370     * @see 3DSTATE_DEPTH_BUFFER.TileMode
 371     */
 372    uint32_t tiling;
 373
 374    /**
 375     * @see RENDER_SURFACE_STATE.TiledResourceMode
 376     * @see 3DSTATE_DEPTH_BUFFER.TiledResourceMode
 377     */
 378    enum intel_miptree_tr_mode tr_mode;
 379
 380    /**
 381     * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
 382     *
 383     * @see RENDER_SURFACE_STATE.SurfaceType
 384     * @see RENDER_SURFACE_STATE.SurfaceArray
 385     * @see 3DSTATE_DEPTH_BUFFER.SurfaceType
 386     */
 387    GLenum target;
 388
 389    /**
 390     * Generally, this is just the same as the gl_texture_image->TexFormat or
 391     * gl_renderbuffer->Format.
 392     *
 393     * However, for textures and renderbuffers with packed depth/stencil formats
 394     * on hardware where we want or need to use separate stencil, there will be
 395     * two miptrees for storing the data.  If the depthstencil texture or rb is
 396     * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be
 397     * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
 398     * MESA_FORMAT_Z24_UNORM_X8_UINT.
 399     *
 400     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
 401     * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
 402     *
 403     * @see RENDER_SURFACE_STATE.SurfaceFormat
 404     * @see 3DSTATE_DEPTH_BUFFER.SurfaceFormat
 405     */
 406    mesa_format format;
 407
 408    /**
 409     * This variable stores the value of ETC compressed texture format
 410     *
 411     * @see RENDER_SURFACE_STATE.SurfaceFormat
 412     */
 413    mesa_format etc_format;
 414
 415    /**
 416     * @name Surface Alignment
 417     * @{
 418     *
 419     * This defines the alignment of the upperleft pixel of each "slice" in the
 420     * surface. The alignment is in pixel coordinates relative to the surface's
 421     * most upperleft pixel, which is the pixel at (x=0, y=0, layer=0,
 422     * level=0).
 423     *
 424     * The hardware docs do not use the term "slice".  We use "slice" to mean
 425     * the pixels at a given miplevel and layer. For 2D surfaces, the layer is
 426     * the array slice; for 3D surfaces, the layer is the z offset.
 427     *
 428     * In the surface layout equations found in the hardware docs, the
 429     * horizontal and vertical surface alignments often appear as variables 'i'
 430     * and 'j'.
 431     */
 432
 433    /** @see RENDER_SURFACE_STATE.SurfaceHorizontalAlignment */
 434    uint32_t halign;
 435
 436    /** @see RENDER_SURFACE_STATE.SurfaceVerticalAlignment */
 437    uint32_t valign;
 438    /** @} */
 439
 440    GLuint first_level;
 441    GLuint last_level;
 442
 443    /**
 444     * Level zero image dimensions.  These dimensions correspond to the
 445     * physical layout of data in memory.  Accordingly, they account for the
 446     * extra width, height, and or depth that must be allocated in order to
 447     * accommodate multisample formats, and they account for the extra factor
 448     * of 6 in depth that must be allocated in order to accommodate cubemap
 449     * textures.
 450     */
 451    GLuint physical_width0, physical_height0, physical_depth0;
 452
 453    /** Bytes per pixel (or bytes per block if compressed) */
 454    GLuint cpp;
 455
 456    /**
 457     * @see RENDER_SURFACE_STATE.NumberOfMultisamples
 458     * @see 3DSTATE_MULTISAMPLE.NumberOfMultisamples
 459     */
 460    GLuint num_samples;
 461
 462    bool compressed;
 463
 464    /**
 465     * @name Level zero image dimensions
 466     * @{
 467     *
 468     * These dimensions correspond to the
 469     * logical width, height, and depth of the texture as seen by client code.
 470     * Accordingly, they do not account for the extra width, height, and/or
 471     * depth that must be allocated in order to accommodate multisample
 472     * formats, nor do they account for the extra factor of 6 in depth that
 473     * must be allocated in order to accommodate cubemap textures.
 474     */
 475
 476    /**
 477     * @see RENDER_SURFACE_STATE.Width
 478     * @see 3DSTATE_DEPTH_BUFFER.Width
 479     */
 480    uint32_t logical_width0;
 481
 482    /**
 483     * @see RENDER_SURFACE_STATE.Height
 484     * @see 3DSTATE_DEPTH_BUFFER.Height
 485     */
 486    uint32_t logical_height0;
 487
 488    /**
 489     * @see RENDER_SURFACE_STATE.Depth
 490     * @see 3DSTATE_DEPTH_BUFFER.Depth
 491     */
 492    uint32_t logical_depth0;
 493    /** @} */
 494
 495    /**
 496     * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
 497     * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
 498     */
 499    enum miptree_array_layout array_layout;
 500
 501    /**
 502     * The distance in between array slices.
 503     *
 504     * The value is the one that is sent in the surface state. The actual
 505     * meaning depends on certain criteria. Usually it is simply the number of
 506     * uncompressed rows between each slice. However on Gen9+ for compressed
 507     * surfaces it is the number of blocks. For 1D array surfaces that have the
 508     * mipmap tree stored horizontally it is the number of pixels between each
 509     * slice.
 510     *
 511     * @see RENDER_SURFACE_STATE.SurfaceQPitch
 512     * @see 3DSTATE_DEPTH_BUFFER.SurfaceQPitch
 513     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
 514     * @see 3DSTATE_STENCIL_BUFFER.SurfaceQPitch
 515     */
 516    uint32_t qpitch;
 517
 518    /**
 519     * MSAA layout used by this buffer.
 520     *
 521     * @see RENDER_SURFACE_STATE.MultisampledSurfaceStorageFormat
 522     */
 523    enum intel_msaa_layout msaa_layout;
 524
 525    /* Derived from the above:
 526     */
 527    GLuint total_width;
 528    GLuint total_height;
 529
 530    /**
 531     * The depth value used during the most recent fast depth clear performed
 532     * on the surface. This field is invalid only if surface has never
 533     * underwent a fast depth clear.
 534     *
 535     * @see 3DSTATE_CLEAR_PARAMS.DepthClearValue
 536     */
 537    uint32_t depth_clear_value;
 538
 539    /* Includes image offset tables: */
 540    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 541
 542    /**
 543     * Offset into bo where the surface starts.
 544     *
 545     * @see intel_mipmap_tree::bo
 546     *
 547     * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
 548     * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
 549     * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
 550     * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
 551     */
 552    uint32_t offset;
 553
 554    /**
 555     * \brief HiZ aux buffer
 556     *
 557     * To allocate the hiz buffer, use intel_miptree_alloc_hiz().
 558     *
 559     * To determine if hiz is enabled, do not check this pointer. Instead, use
 560     * intel_miptree_slice_has_hiz().
 561     */
 562    struct intel_miptree_hiz_buffer *hiz_buf;
 563
 564    /**
 565     * \brief Maps of miptree slices to needed resolves.
 566     *
 567     * hiz_map is used only when the miptree has a child HiZ miptree.
 568     *
 569     * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
 570     * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
 571     * mt->hiz_mt->hiz_map, is unused.
 572     *
 573     *
 574     * color_resolve_map is used only when the miptree uses fast clear (Gen7+)
 575     * lossless compression (Gen9+). It should be noted that absence in the
 576     * map means implicitly RESOLVED state. If item is found it always
 577     * indicates state other than RESOLVED.
 578     */
 579    struct exec_list hiz_map; /* List of intel_resolve_map. */
 580    struct exec_list color_resolve_map; /* List of intel_resolve_map. */
 581
 582    /**
 583     * \brief Stencil miptree for depthstencil textures.
 584     *
 585     * This miptree is used for depthstencil textures and renderbuffers that
 586     * require separate stencil.  It always has the true copy of the stencil
 587     * bits, regardless of mt->format.
 588     *
 589     * \see 3DSTATE_STENCIL_BUFFER
 590     * \see intel_miptree_map_depthstencil()
 591     * \see intel_miptree_unmap_depthstencil()
 592     */
 593    struct intel_mipmap_tree *stencil_mt;
 594
 595    /**
 596     * \brief Stencil texturing miptree for sampling from a stencil texture
 597     *
 598     * Some hardware doesn't support sampling from the stencil texture as
 599     * required by the GL_ARB_stencil_texturing extenion. To workaround this we
 600     * blit the texture into a new texture that can be sampled.
 601     *
 602     * \see intel_update_r8stencil()
 603     */
 604    struct intel_mipmap_tree *r8stencil_mt;
 605    bool r8stencil_needs_update;
 606
 607    /**
 608     * \brief MCS auxiliary buffer.
 609     *
 610     * This buffer contains the "multisample control surface", which stores
 611     * the necessary information to implement compressed MSAA
 612     * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
 613     *
 614     * NULL if no MCS buffer is in use for this surface.
 615     */
 616    struct intel_miptree_aux_buffer *mcs_buf;
 617
 618    /**
 619     * Planes 1 and 2 in case this is a planar surface.
 620     */
 621    struct intel_mipmap_tree *plane[2];
 622
 623    /**
 624     * The SURFACE_STATE bits associated with the last fast color clear to this
 625     * color mipmap tree, if any.
 626     *
 627     * Prior to GEN9 there is a single bit for RGBA clear values which gives you
 628     * the option of 2^4 clear colors. Each bit determines if the color channel
 629     * is fully saturated or unsaturated (Cherryview does add a 32b value per
 630     * channel, but it is globally applied instead of being part of the render
 631     * surface state). Starting with GEN9, the surface state accepts a 32b value
 632     * for each color channel.
 633     *
 634     * @see RENDER_SURFACE_STATE.RedClearColor
 635     * @see RENDER_SURFACE_STATE.GreenClearColor
 636     * @see RENDER_SURFACE_STATE.BlueClearColor
 637     * @see RENDER_SURFACE_STATE.AlphaClearColor
 638     */
 639    union {
 640       uint32_t fast_clear_color_value;
 641       union gl_color_union gen9_fast_clear_color;
 642    };
 643
 644    /**
 645     * Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS
 646     * buffer. This is useful for sharing the miptree bo with an external client
 647     * that doesn't understand auxiliary buffers.
 648     */
 649    enum intel_aux_disable aux_disable;
 650
 651    /**
 652     * Fast clear and lossless compression are always disabled for this
 653     * miptree.
 654     */
 655    bool no_ccs;
 656
 657    /**
 658     * Tells if the underlying buffer is to be also consumed by entities other
 659     * than the driver. This allows logic to turn off features such as lossless
 660     * compression which is not currently understood by client applications.
 661     */
 662    bool is_scanout;
 663
 664    /* These are also refcounted:
 665     */
 666    GLuint refcount;
 667 };
 668
 669 bool
 670 intel_miptree_is_lossless_compressed(const struct brw_context *brw,
 671                                      const struct intel_mipmap_tree *mt);
 672
 673 bool
 674 intel_tiling_supports_non_msrt_mcs(const struct brw_context *brw,
 675                                    unsigned tiling);
 676
 677 bool
 678 intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw,
 679                                            const struct intel_mipmap_tree *mt);
 680
 681 bool
 682 intel_miptree_supports_lossless_compressed(struct brw_context *brw,
 683                                            const struct intel_mipmap_tree *mt);
 684
 685 bool
 686 intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
 687                                  struct intel_mipmap_tree *mt,
 688                                  bool is_lossless_compressed);
 689
 690 enum {
 691    MIPTREE_LAYOUT_ACCELERATED_UPLOAD       = 1 << 0,
 692    MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD   = 1 << 1,
 693    MIPTREE_LAYOUT_FOR_BO                   = 1 << 2,
 694    MIPTREE_LAYOUT_DISABLE_AUX              = 1 << 3,
 695    MIPTREE_LAYOUT_FORCE_HALIGN16           = 1 << 4,
 696
 697    MIPTREE_LAYOUT_TILING_Y                 = 1 << 5,
 698    MIPTREE_LAYOUT_TILING_NONE              = 1 << 6,
 699    MIPTREE_LAYOUT_TILING_ANY               = MIPTREE_LAYOUT_TILING_Y |
 700                                              MIPTREE_LAYOUT_TILING_NONE,
 701
 702    MIPTREE_LAYOUT_FOR_SCANOUT              = 1 << 7,
 703 };
 704
 705 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
 706                                                GLenum target,
 707                                                mesa_format format,
 708                                                GLuint first_level,
 709                                                GLuint last_level,
 710                                                GLuint width0,
 711                                                GLuint height0,
 712                                                GLuint depth0,
 713                                                GLuint num_samples,
 714                                                uint32_t flags);
 715
 716 struct intel_mipmap_tree *
 717 intel_miptree_create_for_bo(struct brw_context *brw,
 718                             drm_intel_bo *bo,
 719                             mesa_format format,
 720                             uint32_t offset,
 721                             uint32_t width,
 722                             uint32_t height,
 723                             uint32_t depth,
 724                             int pitch,
 725                             uint32_t layout_flags);
 726
 727 void
 728 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
 729                                          struct intel_renderbuffer *irb,
 730                                          drm_intel_bo *bo,
 731                                          uint32_t width, uint32_t height,
 732                                          uint32_t pitch);
 733
 734 /**
 735  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 736  * The miptree has the following properties:
 737  *     - The target is GL_TEXTURE_2D.
 738  *     - There are no levels other than the base level 0.
 739  *     - Depth is 1.
 740  */
 741 struct intel_mipmap_tree*
 742 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
 743                                       mesa_format format,
 744                                       uint32_t width,
 745                                       uint32_t height,
 746                                       uint32_t num_samples);
 747
 748 mesa_format
 749 intel_depth_format_for_depthstencil_format(mesa_format format);
 750
 751 mesa_format
 752 intel_lower_compressed_format(struct brw_context *brw, mesa_format format);
 753
 754 /** \brief Assert that the level and layer are valid for the miptree. */
 755 static inline void
 756 intel_miptree_check_level_layer(const struct intel_mipmap_tree *mt,
 757                                 uint32_t level,
 758                                 uint32_t layer)
 759 {
 760    (void) mt;
 761    (void) level;
 762    (void) layer;
 763
 764    assert(level >= mt->first_level);
 765    assert(level <= mt->last_level);
 766    assert(layer < mt->level[level].depth);
 767 }
 768
 769 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 770                              struct intel_mipmap_tree *src);
 771
 772 void intel_miptree_release(struct intel_mipmap_tree **mt);
 773
 774 /* Check if an image fits an existing mipmap tree layout
 775  */
 776 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 777                                     struct gl_texture_image *image);
 778
 779 void
 780 intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt,
 781                                GLuint level, GLuint slice,
 782                                GLuint *x, GLuint *y);
 783
 784 enum isl_surf_dim
 785 get_isl_surf_dim(GLenum target);
 786
 787 enum isl_dim_layout
 788 get_isl_dim_layout(const struct gen_device_info *devinfo, uint32_t tiling,
 789                    GLenum target);
 790
 791 enum isl_tiling
 792 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree *mt);
 793
 794 void
 795 intel_miptree_get_isl_surf(struct brw_context *brw,
 796                            const struct intel_mipmap_tree *mt,
 797                            struct isl_surf *surf);
 798 void
 799 intel_miptree_get_aux_isl_surf(struct brw_context *brw,
 800                                const struct intel_mipmap_tree *mt,
 801                                struct isl_surf *surf,
 802                                enum isl_aux_usage *usage);
 803
 804 union isl_color_value
 805 intel_miptree_get_isl_clear_color(struct brw_context *brw,
 806                                   const struct intel_mipmap_tree *mt);
 807
 808 void
 809 intel_get_image_dims(struct gl_texture_image *image,
 810                      int *width, int *height, int *depth);
 811
 812 void
 813 intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
 814                      uint32_t *mask_x, uint32_t *mask_y);
 815
 816 void
 817 intel_get_tile_dims(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
 818                     uint32_t *tile_w, uint32_t *tile_h);
 819
 820 uint32_t
 821 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
 822                                GLuint level, GLuint slice,
 823                                uint32_t *tile_x,
 824                                uint32_t *tile_y);
 825 uint32_t
 826 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
 827                                  uint32_t x, uint32_t y);
 828
 829 void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
 830                                   GLuint level,
 831                                   GLuint x, GLuint y, GLuint d);
 832
 833 void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
 834                                     GLuint level,
 835                                     GLuint img, GLuint x, GLuint y);
 836
 837 void
 838 intel_miptree_copy_teximage(struct brw_context *brw,
 839                             struct intel_texture_image *intelImage,
 840                             struct intel_mipmap_tree *dst_mt, bool invalidate);
 841
 842 /**
 843  * \name Miptree HiZ functions
 844  * \{
 845  *
 846  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 847  * functions on a miptree without HiZ. In that case, each function is a no-op.
 848  */
 849
 850 bool
 851 intel_miptree_wants_hiz_buffer(struct brw_context *brw,
 852                                struct intel_mipmap_tree *mt);
 853
 854 /**
 855  * \brief Allocate the miptree's embedded HiZ miptree.
 856  * \see intel_mipmap_tree:hiz_mt
 857  * \return false if allocation failed
 858  */
 859 bool
 860 intel_miptree_alloc_hiz(struct brw_context *brw,
 861                         struct intel_mipmap_tree *mt);
 862
 863 bool
 864 intel_miptree_level_has_hiz(struct intel_mipmap_tree *mt, uint32_t level);
 865
 866 void
 867 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt,
 868                                           uint32_t level,
 869                                           uint32_t depth);
 870 void
 871 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt,
 872                                             uint32_t level,
 873                                             uint32_t depth);
 874
 875 void
 876 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree *mt,
 877                                                 uint32_t level);
 878
 879 /**
 880  * \return false if no resolve was needed
 881  */
 882 bool
 883 intel_miptree_slice_resolve_hiz(struct brw_context *brw,
 884                                 struct intel_mipmap_tree *mt,
 885                                 unsigned int level,
 886                                 unsigned int depth);
 887
 888 /**
 889  * \return false if no resolve was needed
 890  */
 891 bool
 892 intel_miptree_slice_resolve_depth(struct brw_context *brw,
 893                                   struct intel_mipmap_tree *mt,
 894                                   unsigned int level,
 895                                   unsigned int depth);
 896
 897 /**
 898  * \return false if no resolve was needed
 899  */
 900 bool
 901 intel_miptree_all_slices_resolve_hiz(struct brw_context *brw,
 902                                      struct intel_mipmap_tree *mt);
 903
 904 /**
 905  * \return false if no resolve was needed
 906  */
 907 bool
 908 intel_miptree_all_slices_resolve_depth(struct brw_context *brw,
 909                                        struct intel_mipmap_tree *mt);
 910
 911 /**\}*/
 912
 913 enum intel_fast_clear_state
 914 intel_miptree_get_fast_clear_state(const struct intel_mipmap_tree *mt,
 915                                    unsigned level, unsigned layer);
 916
 917 void
 918 intel_miptree_set_fast_clear_state(const struct brw_context *brw,
 919                                    struct intel_mipmap_tree *mt,
 920                                    unsigned level,
 921                                    unsigned first_layer,
 922                                    unsigned num_layers,
 923                                    enum intel_fast_clear_state new_state);
 924
 925 bool
 926 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree *mt,
 927                                    unsigned start_level, unsigned num_levels,
 928                                    unsigned start_layer, unsigned num_layers);
 929
 930 /**
 931  * Update the fast clear state for a miptree to indicate that it has been used
 932  * for rendering.
 933  */
 934 void
 935 intel_miptree_used_for_rendering(const struct brw_context *brw,
 936                                  struct intel_mipmap_tree *mt, unsigned level,
 937                                  unsigned start_layer, unsigned num_layers);
 938
 939 /**
 940  * Flag values telling color resolve pass which special types of buffers
 941  * can be ignored.
 942  *
 943  * INTEL_MIPTREE_IGNORE_CCS_E:   Lossless compressed (single-sample
 944  *                               compression scheme since gen9)
 945  */
 946 #define INTEL_MIPTREE_IGNORE_CCS_E (1 << 0)
 947
 948 bool
 949 intel_miptree_resolve_color(struct brw_context *brw,
 950                             struct intel_mipmap_tree *mt, unsigned level,
 951                             unsigned start_layer, unsigned num_layers,
 952                             int flags);
 953
 954 void
 955 intel_miptree_all_slices_resolve_color(struct brw_context *brw,
 956                                        struct intel_mipmap_tree *mt,
 957                                        int flags);
 958
 959 void
 960 intel_miptree_make_shareable(struct brw_context *brw,
 961                              struct intel_mipmap_tree *mt);
 962
 963 void
 964 intel_miptree_updownsample(struct brw_context *brw,
 965                            struct intel_mipmap_tree *src,
 966                            struct intel_mipmap_tree *dst);
 967
 968 void
 969 intel_update_r8stencil(struct brw_context *brw,
 970                        struct intel_mipmap_tree *mt);
 971
 972 /**
 973  * Horizontal distance from one slice to the next in the two-dimensional
 974  * miptree layout.
 975  */
 976 unsigned
 977 brw_miptree_get_horizontal_slice_pitch(const struct brw_context *brw,
 978                                        const struct intel_mipmap_tree *mt,
 979                                        unsigned level);
 980
 981 /**
 982  * Vertical distance from one slice to the next in the two-dimensional miptree
 983  * layout.
 984  */
 985 unsigned
 986 brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw,
 987                                      const struct intel_mipmap_tree *mt,
 988                                      unsigned level);
 989
 990 void
 991 brw_miptree_layout(struct brw_context *brw,
 992                    struct intel_mipmap_tree *mt,
 993                    uint32_t layout_flags);
 994
 995 void
 996 intel_miptree_map(struct brw_context *brw,
 997                   struct intel_mipmap_tree *mt,
 998                   unsigned int level,
 999                   unsigned int slice,
1000                   unsigned int x,
1001                   unsigned int y,
1002                   unsigned int w,
1003                   unsigned int h,
1004                   GLbitfield mode,
1005                   void **out_ptr,
1006                   ptrdiff_t *out_stride);
1007
1008 void
1009 intel_miptree_unmap(struct brw_context *brw,
1010                     struct intel_mipmap_tree *mt,
1011                     unsigned int level,
1012                     unsigned int slice);
1013
1014 void
1015 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
1016                unsigned int level, unsigned int layer, enum blorp_hiz_op op);
1017
1018 bool
1019 intel_miptree_sample_with_hiz(struct brw_context *brw,
1020                               struct intel_mipmap_tree *mt);
1021
1022 #ifdef __cplusplus
1023 }
1024 #endif
1025
1026 #endif